Circuit board layout method

Abstract

This application provides a circuit board layout method that can be applied to the field of circuit board layout technology. The layout method includes: determining the initial position information of each component based on the connection relationships between the components to be laid out and the attribute parameters of each component; the initial position information includes the initial two-dimensional position of the component relative to the circuit board and the initial confidence level of the component's placement on each layer of the circuit board; adjusting the initial position information with the goal of optimal layout rationality to obtain target position information; the layout rationality is determined based on a first evaluation index characterizing the amount of wiring, a second evaluation index characterizing the uniformity of component layout, a third evaluation index characterizing the degree of wiring intersection, and a fourth evaluation index characterizing the layout confidence level; determining the layer to be laid out for each component based on the target confidence level of each component's placement on each layer; and determining a layout scheme for the circuit board based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically to a method for laying out a circuit board. Background Technology

[0002] As the physical core of modern electronic systems, the design quality of circuit boards directly determines the performance, reliability, and manufacturing cost of electronic products. With the continuous increase in the complexity and signal speed of integrated circuits, single-layer circuit boards are no longer sufficient to meet the requirements of high-density interconnection and signal integrity. Therefore, complex electronic systems such as server motherboards, high-speed communication interface cards, and high-performance computing modules commonly employ multi-layer board structures.

[0003] However, the relevant circuit board layout methods usually assume that all components are located on the same plane, which cannot support the layout requirements of multi-layer circuit boards. Summary of the Invention

[0004] In view of the above problems, this application provides a circuit board layout method.

[0005] According to a first aspect of this application, a method for laying out a circuit board is provided, comprising: determining initial position information of each component based on the connection relationship between components to be laid out and attribute parameters of each component, wherein the initial position information includes the initial two-dimensional position of the component relative to the circuit board and the initial confidence level of the component in each layer of the circuit board; adjusting the initial position information with the goal of optimal layout rationality to obtain target position information, wherein the target position information includes the target two-dimensional position relative to the circuit board and the target confidence level of the component in each layer, wherein the layout rationality is determined based on at least one of the following evaluation indicators: a first evaluation indicator for characterizing the amount of wiring, a second evaluation indicator for characterizing the uniformity of component layout, a third evaluation indicator for characterizing the degree of wiring intersection, and a fourth evaluation indicator for characterizing layout confidence; determining the layer to be laid out for each component based on the target confidence level of the component in each layer; and determining a layout scheme for the circuit board based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out.

[0006] A second aspect of this application provides a circuit board layout apparatus, comprising: an initial determination module, configured to determine initial position information of each component based on the connection relationship between components to be laid out and attribute parameters of each component, the initial position information including the initial two-dimensional position of the component relative to the circuit board and the initial confidence level of the component in each layer; a target determination module, configured to adjust the initial position information with the goal of optimal layout rationality to obtain target position information, the target position information including the target two-dimensional position relative to the circuit board and the target confidence level of the component in each layer, the layout rationality being determined based on at least one of the following evaluation indicators: a first evaluation indicator characterizing the amount of wiring, a second evaluation indicator characterizing the uniformity of component layout, a third evaluation indicator characterizing the degree of wiring intersection, and a fourth evaluation indicator characterizing the layout confidence level; a layer determination module, configured to determine the layer to be laid out for each component based on the target confidence level of the component in each layer; and a layout determination module, configured to determine a layout scheme for the circuit board based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out.

[0007] A third aspect of this application provides an electronic device comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0008] A fourth aspect of this application also provides a computer-readable storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implement the steps of the above-described method.

[0009] The fifth aspect of this application also provides a computer program product, including a computer program or instructions that, when executed by a processor, implement the steps of the above-described method. Attached Figure Description

[0010] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments of this application with reference to the accompanying drawings.

[0011] Figure 1 An application scenario diagram of a circuit board layout method according to an embodiment of this application is shown.

[0012] Figure 2 A flowchart illustrating a circuit board layout method according to an embodiment of this application is shown.

[0013] Figure 3A A schematic diagram of a cross-layer mesh according to an embodiment of this application is shown.

[0014] Figure 3BA schematic diagram of a cross-layer network wiring method according to an embodiment of this application is shown.

[0015] Figure 4A A schematic diagram illustrating the wiring space conflict of two wire networks located on different layers according to an embodiment of this application is shown.

[0016] Figure 4B A schematic diagram illustrating a wiring space conflict where two net pins are located on the same layer according to an embodiment of this application is shown.

[0017] Figure 4C A schematic diagram of wiring space conflicts across pin layers with one and only one net according to an embodiment of this application is shown.

[0018] Figure 4D A schematic diagram illustrating a wiring space conflict where both nets span two layers, according to an embodiment of this application, are shown.

[0019] Figure 5 A flowchart illustrating the determination of a layout scheme according to an embodiment of this application is shown.

[0020] Figure 6 A structural block diagram of a circuit board layout apparatus according to an embodiment of this application is shown.

[0021] Figure 7 A block diagram of an electronic device suitable for implementing a circuit board layout method according to an embodiment of this application is shown. Detailed Implementation

[0022] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0025] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0026] As a platform for electronic systems, printed circuit boards (PCBs) often adopt a multi-layer structure in practice. Components are concentrated on the top and bottom layers, while the remaining inner layers are mainly used for signal routing, power distribution, and ground plane construction.

[0027] In multilayer boards, the placement strategy directly determines the channel distribution of critical signals across different layers, affecting overall routing congestion. Therefore, improving the intelligence level of the placement stage and rationally planning the placement of components on the top / bottom layers are core aspects of ensuring the feasibility of multilayer board routing and signal integrity. However, related placement methods only model single-layer PCB layouts, assuming all components are located on the same plane, thus failing to support the layout requirements of multilayer boards.

[0028] Embodiments of this application provide a circuit board layout method, comprising: determining initial position information of each component based on the connection relationship between the components to be laid out and the attribute parameters of each component, wherein the initial position information includes the initial two-dimensional position of the component relative to the circuit board and the initial confidence level of the component in each layer; adjusting the initial position information with the goal of optimal layout rationality to obtain target position information, wherein the target position information includes the target two-dimensional position relative to the circuit board and the target confidence level of the component in each layer of the circuit board, and the layout rationality is determined based on at least one of the following evaluation indicators: a first evaluation indicator for characterizing the amount of wiring, a second evaluation indicator for characterizing the uniformity of component layout, a third evaluation indicator for characterizing the degree of wiring intersection, and a fourth evaluation indicator for characterizing the layout confidence level; determining the layer to be laid out for each component based on the target confidence level of each component in each layer; and determining a layout scheme for the circuit board based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out.

[0029] The embodiments of this application represent the layer assignment decision of components with confidence levels, thus making the originally discrete layer selection problem continuous, reducing the optimization difficulty in the layout process, and improving layout efficiency. Furthermore, by using evaluation metrics based on four dimensions—routing quantity, component layout uniformity, routing crossover degree, and layout confidence—not only can the optimization of the two-dimensional position of components and the confidence level of their placement on each layer be solved under a unified optimization objective, but the final target confidence level also converges into a clear and discrete layer assignment scheme. This ensures that the layout scheme meets process requirements and improves the layout quality of multilayer circuit boards.

[0030] Figure 1 An application scenario diagram of a circuit board layout method according to an embodiment of this application is shown.

[0031] like Figure 1 As shown, the application scenario according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 serves as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0032] Users can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0033] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with displays and support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0034] Server 105 can be a server that provides various services, such as a backend management server that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103 (this is just an example). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0035] It should be noted that the circuit board layout method provided in this application embodiment can generally be executed by server 105. Correspondingly, the circuit board layout device provided in this application embodiment can generally be disposed in server 105. The circuit board layout method provided in this application embodiment can also be executed by a server or server cluster that is different from server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or server 105. Correspondingly, the circuit board layout device provided in this application embodiment can also be disposed in a server or server cluster that is different from server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or server 105.

[0036] It should be understood that Figure 1 The number of first terminal devices, second terminal devices, third terminal devices, networks, and servers shown in the diagram is merely illustrative. Depending on implementation needs, any number of first terminal devices, second terminal devices, third terminal devices, networks, and servers can be included.

[0037] The following will be based on Figure 1 The described scene, through Figures 2-6 The layout method of the circuit board according to the embodiments of the application will be described in detail.

[0038] Figure 2 A flowchart illustrating a circuit board layout method according to an embodiment of this application is shown.

[0039] like Figure 2 As shown, the circuit board layout method includes operations S210 to S240.

[0040] In operation S210, the initial position information of each element is determined based on the connection relationship between the elements to be laid out and the attribute parameters of each element.

[0041] In operation S220, with the goal of achieving optimal layout rationality, the initial position information is adjusted to obtain the target position information.

[0042] In operation S230, based on the target confidence level of each component's placement on each layer, the layer to be placed for each component is determined.

[0043] In operation S240, a layout scheme for the circuit board is determined based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out.

[0044] In embodiments of this application, the initial position information includes the initial two-dimensional position of the component relative to the circuit board and the initial confidence level of its placement on each layer; the target position information includes the target two-dimensional position relative to the circuit board and the target confidence level of its placement on each layer. Because the component... Floor Since these are discrete variables, optimization becomes difficult. Therefore, random variables are introduced. Used to represent elements Confidence levels at each layer.

[0045] Taking the example of components only placed on the top and bottom layers of a circuit board, random variables It follows a binomial distribution, and the confidence scores for the top layer (denoted as 0) and the bottom layer (denoted as 1) are defined as follows: , ,in, For components The probability of selecting the top layer is a parameter that can be continuously optimized.

[0046] To improve layout efficiency and quality, initial position information for each element can be generated based on the connection relationships between the elements to be laid out and the attribute parameters of each element. Optimization can then be performed based on this initial position information. Let each element be denoted as... Each component The attribute can include width ,high In addition to electrical and packaging properties, etc. In some embodiments, neural networks can be used to process the connection relationships between components and the attribute parameters of each component to determine the initial position information.

[0047] element The two-dimensional position relative to the circuit board can be defined as ( , This allows us to obtain the x-coordinate vectors of each component. y-coordinate vector Layout layer vectors and the probability vectors laid out at the top layer. .

[0048] After obtaining initial position information that can initially match the connection relationships between each component and the attribute parameters of each component, the initial position information can be optimized based on evaluation indicators to further improve the quality of the layout scheme.

[0049] In embodiments of this application, layout rationality is determined based on at least one of the following evaluation metrics: a first evaluation metric characterizing the amount of wiring, a second evaluation metric characterizing the uniformity of component layout, a third evaluation metric characterizing the degree of wiring intersection, and a fourth evaluation metric characterizing layout confidence. The initial position information can be optimized with the goal of minimizing the metric values ​​to obtain target position information that meets the requirements for circuit board layout quality.

[0050] The first evaluation index value can be determined based on the total length of the cabling. The second evaluation index value can be determined based on the difference between the actual component occupancy and the average component occupancy in each layout space. The third evaluation index value can be determined based on the degree of cabling space conflict between different cabling nets. The fourth evaluation index value can be determined based on the cross-entropy of the confidence level of component layout in each layer, so as to improve the clarity of confidence level through the fourth evaluation index value.

[0051] After optimizing and obtaining the target location information, the target confidence level of each component can be discretized to determine the layer to be laid out for each component. For example, in Greater than the preset value In the case of, determine That is, to determine the components The layer to be laid out is the top layer, and vice versa. In the case of, determine That is, to determine the components The layer to be laid out is the bottom layer.

[0052] After determining the layer to be laid out for each component, the layout scheme of the circuit board can be obtained by combining the target two-dimensional position of each component relative to the circuit board, and the layout scheme can be used to realize the layout of the circuit board.

[0053] According to embodiments of this application, by representing the layer assignment decision of components with confidence levels, the originally discrete layer selection problem is made continuous, reducing the optimization difficulty in the placement process and improving placement efficiency. Furthermore, by using evaluation metrics based on four dimensions—routing quantity, component placement uniformity, routing crossover degree, and placement confidence—not only can the optimization of the two-dimensional position of components and the confidence level of their placement on each layer be solved under a unified optimization objective, but the final target confidence level also converges, resulting in clearly discrete component layers to be placed. This ensures that the placement scheme meets process requirements and improves the placement quality of multilayer circuit boards.

[0054] According to an embodiment of this application, the initial position information of each element is determined based on the connection relationship between the elements to be laid out and the attribute parameters of each element, including: using a graph neural network to process the connection relationship graph constructed based on the connection relationship between the elements and the attribute parameters of each element to obtain the initial confidence of each element in each layer; and randomly initializing the two-dimensional position of each element to obtain the initial two-dimensional position.

[0055] The connections between components can be electrical connections. In some embodiments, electrical connections can be represented using a netlist to construct a connection diagram G of the components based on the netlist information. A netlist can be denoted as... Each wire mesh It consists of several pins, and the set of pins it contains is denoted as . In the embodiments of this application, it can be assumed that each net contains only two pins; for nets containing multiple pins, they can be decomposed into several two-pin nets to facilitate subsequent calculations.

[0056] Online Let the two pins it connects to be... and For each pin Its attributes include offset coordinates relative to the center of its constituent element. Components Belonging to the network .

[0057] In the connection graph G, the set of nodes This corresponds to all components on the circuit board. (See the connection diagram.) In, for each wire mesh Add an undirected edge This yields a set of edges that reflects the electrical connections between components. .

[0058] Each node in the connection diagram corresponds to a component. The feature vector can be obtained by extracting the attribute parameters of each component. The feature vector is shown in the following formula (1):

[0059] (1);

[0060] in Representing components Height and width, Indicating the connection relationship of components in the diagram The importance of a node can be calculated using node degree or node importance value, reflecting its centrality within the circuit structure. This indicates key network density metrics related to components, such as the proportion of high-current power supply networks, the proportion of high-frequency signal networks, and the proportion of differential signals. This indicates the electrical properties of the component, such as voltage regulation, filtering, input / output driving, clock driving, and other electrical properties. This indicates component package type characteristics such as surface mount, square flat no-lead package, ball grid array package, through-hole, module, and other component package characteristics. This indicates the role of a component in the system, such as a critical path device, a high heat load device, or a master / clock-related device. This represents mechanical constraints, such as three-dimensional feature vectors, indicating whether there are reinforced holes (0 / 1), whether they are confined to boundary regions (0 / 1), and whether there are mechanical assembly clearance requirements (0 / 1). Indicates thermal characteristics, such as 0 / 1 indicating whether it is a high heat source device. This indicates the signal quality level; for example, 0 / 1 indicates whether a fixed-length network is required. Indicator element eigenvectors.

[0061] After determining the eigenvectors of each element, an initial eigenma matrix including the eigenvectors of all elements can be obtained. As shown in equation (2):

[0062] (2).

[0063] Before using graph neural networks to process the connection graph, the adjacency matrix A of the connection graph can be normalized first. The normalization process is shown in equation (3) below:

[0064] (3);

[0065] in, The normalized adjacency matrix, Let the node degree matrix be... It is an identity matrix used to introduce self-joins.

[0066] When processing the connection graph, the graph neural network adopts a layer-by-layer propagation method. The feature matrix update process of its (l+1)th layer is shown in the following equation (4):

[0067] (4);

[0068] in, , For the first The learnable weight matrix of the layer.

[0069] When it spreads to the first After the layers are completed, the final node feature matrix can be obtained. Taking a circuit board with two layers as an example, the final node feature matrix is ​​input into a multi-layer neural network to obtain a matrix of dimensions. The output value is shown in equation (5) below:

[0070] (5);

[0071] in, Indicates the output value. This represents a multi-layer neural network.

[0072] Based on the output values, the initial confidence level of each component in each layer can be determined. For each component... The initial confidence level of the top layer is shown in equation (6):

[0073] (6);

[0074] in, Indicator element The initial confidence level at the top level, logits[i,0] represents the output value that is consistent with the element. The corresponding sub-output value at the top level, logits[i,1] represents the output value that is related to the element. The corresponding sub-output value located at the bottom layer. Correspondingly, the component... The initial confidence level at the bottom layer is shown in equation (7):

[0075] (7).

[0076] The two-dimensional position of each component can be obtained by randomly initializing the circuit board boundary as a constraint, so that the initial two-dimensional position of the component does not exceed the range of the circuit board.

[0077] According to embodiments of this application, by utilizing graph neural networks to determine the initial position information of each element, the difficulty of optimizing the position information can be reduced, the optimization efficiency can be improved, and thus the accuracy of the layout scheme and the efficiency of the layout scheme generation can be improved.

[0078] According to an embodiment of this application, the graph neural network is trained in the following manner: using an initial graph neural network, the sample connection relationship graph constructed based on the connection relationship between each sample element in the sample circuit board and the attribute parameters of each sample element is processed to obtain the sample confidence of each sample element in each layer of the sample circuit board; based on the sample confidence of each element and the actual layout layer in the sample circuit board, the initial graph neural network is adjusted to obtain the graph neural network.

[0079] To enable the graph neural network model to generalize across design scenarios, multiple real circuit boards designed by engineers are introduced as sample circuit boards during the training phase. Each sample circuit board corresponds to a design instance. After constructing the connection graph and extracting features, the sample connection graph corresponding to the sample circuit board can be obtained. ,in Indicates the index of different sample circuit boards. This represents the total number of training samples.

[0080] During training, forward propagation is performed on the connection graph of each sample, and the corresponding prediction error is calculated. The overall loss used to train the graph neural network is... The overall loss function is determined as shown in equation (8):

[0081] (8);

[0082] in, This represents the elements obtained from the forward propagation of the initial graph neural network. The probability of samples in the upper layer, Indicates the components in the sample circuit board The actual layout layer, Design examples The number of components it contains.

[0083] When adjusting the initial graph neural network using the loss value of the overall loss function, the parameters of the initial graph neural network and the initial multilayer neural network can be updated using the gradient descent method to achieve the mapping learning from element features to element levels.

[0084] According to embodiments of this application, by adjusting the parameters of the initial graph neural network using real sample circuit boards, the resulting graph neural network has the ability to map component attributes to component layout levels, thereby enabling the initial confidence level determined by the graph neural network to have high accuracy.

[0085] According to an embodiment of this application, target position information is obtained by iterative adjustment; wherein, performing one adjustment includes: based on an optimization objective function constructed using evaluation metrics, determining the current round position adjustment amount by performing gradient calculation on the optimization objective function; and adjusting the current round position information using the current round position adjustment amount to obtain the next round position information.

[0086] In embodiments of this application, the optimization objective can be constructed as a differentiable optimization objective function for the two-dimensional position and layering probability of the element. The initial two-dimensional position information is adjusted by iterative gradient descent on the objective function until the change in the objective function value between two adjacent rounds is less than a preset change threshold and meets the sampling criteria (all components must meet the following requirements). or ,in As a hyperparameter, the value used in this application is... This yields target location information, including the target's two-dimensional location and target probability.

[0087] During the optimization process, the optimization variables can be defined in the following vector form: In each round of adjustment, gradient descent is performed first, and the gradient descent update process is shown in equation (9) below:

[0088] (9);

[0089] in, For learning rate, This indicates the initial position information of the current round. This represents the gradient of the objective function with respect to the initial position information of the current round. This indicates the initial position information for the next round.

[0090] After performing gradient descent, calculate the change in the objective function value between two adjacent optimization rounds. As shown in equation (10):

[0091] (10);

[0092] in, This represents the value of the objective function in the previous round of optimization. This represents the value of the objective function in the current round of optimization.

[0093] After obtaining the changes in the objective function between two adjacent rounds of optimization, the [function name] can be determined. Is it less than the preset change threshold? This allows us to determine whether the iterative adjustment process can be terminated and to identify the current position information as the target position information.

[0094] According to embodiments of this application, the initial position information is adjusted using gradient descent to obtain target position information. This allows the target position information to more accurately reflect the optimal layout of components on the circuit board, thereby effectively improving layout efficiency and quality. During the iterative adjustment process, the objective function comprehensively considers multiple key dimensions such as wiring quantity, component layout uniformity, wiring crossover degree, and layout confidence, ensuring the global optimality of the layout scheme. Furthermore, by introducing the gradient descent method, the adjustment process of position information becomes smoother and more efficient, avoiding the local optima problem that may occur in traditional methods. The obtained target position information not only includes the precise two-dimensional coordinates of the components but also clarifies the layers to be laid out for each component, thus enabling the acquisition of a high-quality layout scheme.

[0095] In embodiments of this application, the optimization objective function may include an entropy regularization term and other evaluation terms. The entropy regularization term is constructed based on a fourth evaluation metric used to characterize layout confidence, and the other evaluation terms are constructed based on at least one of a first evaluation metric used to characterize routing quantity, a second evaluation metric used to characterize component layout uniformity, and a third evaluation metric used to characterize routing crossover degree. The optimization objective function can be shown in the following equation (11):

[0096] (11);

[0097] in, The first evaluation item is constructed based on the first evaluation indicator. This is a second evaluation item constructed based on the second evaluation indicator. This is a third evaluation item constructed based on the third evaluation indicator. For entropy regularization, Assigning weights to the first, second, and third evaluation items. is the weighting coefficient of the entropy regularization term.

[0098] According to an embodiment of this application, the layout method further includes: using a reinforcement learning method to adjust the weight coefficients of the entropy regularization term at least once as the initial position information is adjusted; wherein performing one adjustment includes: evaluating the current round position information based on other evaluation terms to obtain a current round evaluation result for the current round position information; using the current round policy network to process the current round evaluation result and the historical round evaluation results to determine the current round adjustment magnitude for the current round weight coefficients, wherein the historical round evaluation result is obtained by evaluating the historical round position information based on other evaluation terms, and the historical round position information includes the previous round position information and the initial position information; and adjusting the current round weight coefficients based on the current round adjustment magnitude to obtain the next round weight coefficients.

[0099] Because a fixed or empirically set α often leads to premature solidification of layer assignments when exploration is insufficient, or ambiguity when convergence is expected, the overall layout remains at a suboptimal solution. When hyperparameters... When the value is too small, the component Confidence (probability) of top-level layout It may not be able to meet the discretization standard; and when When the value is too large, the layer assignment will often become fixed too early when the exploration is insufficient, which will weaken the optimization effect of other loss items and lead to a decline in the overall layout quality.

[0100] Therefore, to avoid suboptimal results caused by manual parameter tuning, reinforcement learning methods can be used to simultaneously adjust the weight coefficients of the entropy regularization term during the iterative adjustment of the initial position information to obtain a relatively stable discretization result. This is to avoid suboptimal results caused by manually adjusting α.

[0101] Before adjusting the weighting coefficients, the current round's position information can be evaluated based on other evaluation items to obtain the current round's evaluation result. The current round's evaluation result can include the current round's first evaluation indicator value, current round's second evaluation indicator value, and current round's third evaluation indicator value. The historical round's evaluation result can include the historical round's first evaluation indicator value, historical round's second evaluation indicator value, and historical round's third evaluation indicator value. The historical round can include the previous round and the first round.

[0102] In some embodiments, the current round evaluation results and the historical round evaluation results can be processed to obtain the current round state vector, and then the current round state vector can be input into the current round policy network to determine the adjustment magnitude of the current round.

[0103] The state vector can include the degree of improvement state, which can compare the current round's first, second, and third evaluation index values ​​with the first, second, and third evaluation index values ​​of the first round, respectively, to determine the degree of improvement of the three evaluation indexes in the current round compared to the first round. The degree of improvement state can be represented by the following formula (12):

[0104] (12);

[0105] Where k represents the current round, , , These represent the values ​​of the first, second, and third evaluation indicators for the current round, respectively. , , These represent the values ​​of the first evaluation metric, the second evaluation metric, and the third evaluation metric in the first round, respectively. This feature reflects the overall improvement of the current optimization step relative to the initial state and can be used to assess whether the optimization has stagnated or degenerated. Indicates the degree of improvement.

[0106] The state vector can include the trend state, which can be determined by comparing the current round's first, second, and third evaluation index values ​​with the previous round's first, second, and third evaluation index values, respectively, to determine the direction and relative magnitude of the loss term's change between adjacent rounds. This trend state can be used to judge the instantaneous trend of the current optimization process. The trend state can be represented by the following equation (13):

[0107] (13);

[0108] in, , , , , These represent the values ​​of the first, second, and third evaluation indicators from the previous round, respectively. It indicates the trend or state of change.

[0109] The state vector can also include sampleable scaled states, if the element satisfy or , considering components Sampling criteria have been met. Sampling ratio status. It can be determined using the following formula (14):

[0110] (14);

[0111] in, express In the The values ​​taken before subgradient descent.

[0112] The state vector may also include the trend state of the sampled scale. The trend state of the sampled scale can be determined by the following equation (15):

[0113] (15);

[0114] In addition, the state vector also includes polarization state. Polarization state It can be determined by the following formula (16):

[0115] (16).

[0116] Combining the above states, the current round state vector is shown in equation (17):

[0117] (17);

[0118] in, This indicates the current state of the round.

[0119] After obtaining the current round state vector, the current round state vector can be input into the current round policy network, and the first multilayer perceptron of the current round policy network can be used. Will Mapped to high-dimensional latent vectors The mapping process is shown in equation (18):

[0120] (18).

[0121] After mapping, the latent vectors The second multilayer perceptron of the input policy network in the current round The resulting logits are 5-dimensional values, which are then converted by the SoftMax activation function into the current round probability distribution relative to each preset adjustment range, as shown in equations (19) to (20):

[0122] (19);

[0123] (20);

[0124] in, This represents the probability distribution for the current round.

[0125] The preset adjustment range can be achieved using discrete variable actions. The values ​​and meanings are as follows: This indicates a significant reduction in the weighting coefficient of the current round. , This indicates a slight reduction in the weighting coefficient of the current round. , This indicates that the weight coefficients of the current round are maintained. constant, This indicates a slight increase in the weighting coefficient of the current round. , This indicates a significant increase in the weighting coefficient of the current round. .

[0126] In the embodiments of this application, the weight coefficient of the entropy regularization term is dynamically adjusted by the reinforcement learning method, thereby realizing adaptive control of the circuit board layout optimization process. This effectively solves the contradiction between exploration and convergence caused by fixed parameter settings in traditional methods. Specifically, when the optimization process is detected to be trapped in a local optimum, the policy network tends to choose a large adjustment action (a=±2) to break through the current state; while in the near convergence stage, it uses more fine-tuning actions (a=±1) to finely optimize the layout quality.

[0127] The process of adjusting the weight coefficients for the current round can be shown in the following equation (21):

[0128] (twenty one);

[0129] in, This is a hyperparameter that indicates the adjustment step size; its value is typically 1. Indicates the weight coefficient for the current round. This indicates the weighting coefficient for the next round.

[0130] According to embodiments of this application, regularization weights are adjusted through reinforcement learning to avoid premature solidification of initial confidence and gradual increase in discreteness in the later stages, thereby obtaining a stable and high-quality layer to be laid out.

[0131] According to an embodiment of this application, the layout method further includes: determining the current round reward value for the current round policy network based on the current round evaluation result and the previous round evaluation result; and adjusting the parameters of the current round policy network based on the current round reward value to obtain the next round policy network.

[0132] During the initial location information adjustment process, the parameters of the policy network are also adjusted accordingly. The parameters of the policy network in the first round can be randomly initialized, denoted as... For the current round of the policy network The trajectory obtained by sampling is shown in equation (22):

[0133] (twenty two);

[0134] in, This represents the state vector for the first round. This indicates the magnitude of the first round of adjustments. This indicates the first round of instant rewards. This represents the state vector in round T. This indicates the adjustment range for round T. This indicates the instant reward for round T. Indicates a terminated state. This indicates the final reward.

[0135] In some embodiments, during the initialization of the iteration step number Then, using the current round's policy network. By repeating the following steps, the trajectory can be sampled: The first step can be to determine the current round state vector using the method defined above. The second sampling action The third step is to update the weight parameters. And based on the selected action Perform adaptive updates; the fourth step involves processing the current wheel position information. The subgradient descent operation obtains the position information for the next round and constructs the state vector for the next round. Step 5: Calculate the reward (instant reward) The sixth step is to determine whether to terminate. If... The final reward will be calculated according to the reward rules. And end sampling; otherwise, let Then return to step one and continue execution.

[0136] After obtaining the trajectory, the reward value for the current round's position information can be determined based on the current round's evaluation result and the previous round's evaluation result. The current round's reward value can be obtained based on a reward function, which in this application consists of two parts. The first part is the immediate reward obtained for each gradient optimization step, used to reflect the differences in evaluation metrics between adjacent rounds.

[0137] Set the current round evaluation results As shown in equation (23):

[0138] (twenty three).

[0139] The immediate reward value for the current round is calculated using the following formula (24):

[0140] (twenty four);

[0141] Among them, when The ratio of values Hours, indicating the action used right The adjustments yielded benefits, and compared to The greater the improvement, the greater the reward. Conversely, a negative reward is given for poor performance.

[0142] The second part of the reward function is based on the execution of the complete optimization process, and on whether the sampling criteria are met (all elements meet: or A reward or penalty will be given. If the sampling criteria are not met after the final gradient descent, a final penalty will be imposed. As shown in equation (25):

[0143] (25);

[0144] in, A sufficiently large positive number is used to ensure that in the th... Next adjustment Cumulative returns after This highlights the key indicator of "meeting the sampling criteria" through a penalty mechanism. The reward value for the current round can be obtained by estimating the cumulative return using the future rewards of the current policy network, as shown in equation (26):

[0145] (26);

[0146] in, This is the discount factor, which typically takes the value of... .

[0147] After obtaining the reward value for the current round, the parameters of the policy network for the current round are updated according to the policy gradient criterion, as shown in equation (27):

[0148] (27);

[0149] in, This is a hyperparameter.

[0150] According to embodiments of this application, by using a reward mechanism to update the parameters of the policy network, the policy network is guided to focus on short-term optimization effects through immediate rewards, while the long-term optimization goals are ensured through final rewards, thereby improving the accuracy of the policy network's parameters and thus improving the accuracy of the layout scheme.

[0151] According to an embodiment of this application, the index value of the first evaluation index of the current round is determined in the following manner: the cross-layer line length of the current round is determined based on the confidence of the current round of the components to which each pin belongs in each wiring net is laid out in each layer and the interlayer spacing of the circuit board; the planar line length of the current round is determined based on the two-dimensional position of each pin in each wiring net relative to the current round pin of the circuit board; and the index value of the first evaluation index of the current round is determined based on the cross-layer line length of the current round and the planar line length of the current round.

[0152] In multilayer boards, wire mesh The three-dimensional semi-perimeter length can be expressed as the sum of the spans in the x, y, and z directions. Since the layer assignment variable is a random variable, the embodiments of this application use the sum of the expected values ​​of the three-dimensional semi-perimeter length (HPWL) of each net as the first evaluation index, which is defined as follows (28):

[0153] (28);

[0154] (29);

[0155] in, This represents the value of the first evaluation indicator. and They represent wire meshes respectively. The span in the x and y directions, Indicates wire mesh The mathematical expectation of the interlayer distance in the z-direction. Indicates wire mesh The length of the three-dimensional semi-perimeter line.

[0156] Net The line lengths in the x and y directions are defined as shown in equations (30) and (31) respectively:

[0157] (30);

[0158] (31);

[0159] in, and Indicates wire mesh The two pins in , Pins Coordinates in the x and y directions, , Pins Coordinates in the x and y directions, pin The two-dimensional position of the pin is determined by the two-dimensional position of the component and the pin offset, and its calculation method is shown in the following formula (32):

[0160] (32);

[0161] in, For the two-dimensional position of the pin, This refers to the two-dimensional position of the component to which the pin belongs. This is the pin offset.

[0162] Net The discrete distance across layers is determined by the layer in which the pins are located. Taking a component placement only on the top and bottom layers as an example, the interlayer spacing is equal to the board thickness T. Net The cross-layer length in the z-direction is defined as shown in equation (33):

[0163] (33);

[0164] in, Pin indication The layer where the component is located, Pin indication The layer in which the component resides, where the pins When the layer containing the component is the top layer When the layer is the bottom layer pin Similarly.

[0165] Figure 3A A schematic diagram of a cross-layer mesh according to an embodiment of this application is shown.

[0166] like Figure 3A As shown, the component belonging to pin A in the cross-layer net is located on the top layer, and the component belonging to pin B is located on the bottom layer.

[0167] Figure 3B A schematic diagram of a cross-layer network wiring method according to an embodiment of this application is shown.

[0168] like Figure 3B As shown, the routing method for cross-layer nets is to drill a hole from pin A at the top layer to point H at the bottom layer, connect pin A to point H, and then connect point H and pin B at the bottom layer.

[0169] Due to the layer vector of the layout As random variables, in the embodiments of this application, Finding its expected value, we get the following equation (34):

[0170] (34);

[0171] in, The confidence level of the component to which the pin belongs, placed at the top level.

[0172] By substituting the current round's position information into the first evaluation index defined above, we can obtain the index value of the first evaluation index for the current round.

[0173] According to the embodiments of this application, by accurately calculating the first evaluation index, the impact of different layout schemes on the wire length can be evaluated more scientifically, thereby providing a more reliable basis for layout scheme optimization, improving the quality and efficiency of circuit board layout, and meeting the stringent requirements of complex electronic systems for circuit board performance.

[0174] According to an embodiment of this application, the index value of the second evaluation index for the current round is determined as follows: based on the size of each component and the initial two-dimensional position of the current round, the size and two-dimensional position of each layout space in each layer of the circuit board, and the confidence level of each component in the current round of the layer, the actual component occupancy of each layout space in the current round of the layer is determined; based on the difference between the actual component occupancy of each layout space in the current round and the average component occupancy, the index value of the second evaluation index for the current round is determined, and the average component occupancy is determined based on the ratio of the total area of ​​all components to the number of layout spaces.

[0175] The second evaluation metric aims to promote a more uniform distribution of components within the layout area. To measure the uniformity between the top and bottom layers, the embodiments of this application divide each layer into several rectangular areas as layout spaces and calculate the occupancy of each rectangular area.

[0176] Top-level rectangle Actual component occupancy The mathematical expectation is defined as follows (35):

[0177] (35);

[0178] in, and Representing components exist shaft and axial direction and The overlap length of 1 is defined as shown in equations (36) and (37) respectively:

[0179] (36);

[0180] (37);

[0181] in, and Represents a rectangle Width and height, , These are the coordinates of the center of rectangle B1.

[0182] Similarly, the top-level rectangle Actual component occupancy The mathematical expectation is defined as follows (38):

[0183] (38);

[0184] in, and Representing components exist shaft and axial direction and The overlap length of 2.

[0185] Based on the occupancy of all rectangular boxes, the overall expected density index of the layout can be defined as the second evaluation index, as shown in the following formula (39):

[0186] (39);

[0187] in, This represents the total number of rectangles. For components area, This represents the overall expected density. The third evaluation metric is used to measure the deviation between the expected occupancy of each rectangular area and the average component occupancy, thereby promoting a more uniform distribution of components at the top and bottom layers during the optimization process.

[0188] By substituting the current round's position information into the second evaluation index defined above, we can obtain the index value of the second evaluation index for the current round.

[0189] According to embodiments of this application, by optimizing the initial position information of components using a second evaluation index, the uniformity of component distribution in the layout scheme can be evaluated more comprehensively, avoiding excessively dense or sparse components in local areas, meeting the stringent requirements of complex electronic systems for circuit board performance, and improving the efficiency and quality of circuit board design.

[0190] According to an embodiment of this application, the index value of the third evaluation index for the current round is determined as follows: for any two routing nets, based on the current round confidence of the components to which each pin in each routing net is located in each layer, the current round routing probability of the two routing nets being in each relative position relationship is determined; based on the current round pin position information of each pin in the two routing nets, the current round routing spatial conflict degree of the two routing nets being in each relative position relationship is determined; based on the current round routing probability of any two routing nets being in each relative position relationship and the current round routing spatial conflict degree, the index value of the third evaluation index for the current round is determined.

[0191] The third evaluation metric measures the overall separation of all nets in the potential routing area in the three-dimensional layout space. It is used to guide nets to form sufficient space during the optimization process, thereby improving routing feasibility.

[0192] Online Let its two pins be denoted as and The pin coordinate matrix is ​​defined as shown in equation (40):

[0193] (40);

[0194] Among them, due to and All are determined by the confidence level of the corresponding components. Decision, matrix There will be four possible values, each corresponding to a different layer combination. Taking a component placed only on the top and bottom layers as an example, when both pins are located on the top layer, the pin coordinate matrix... As shown in equation (41):

[0195] (41).

[0196] The probability that both pins are located on the top layer. As shown in equation (42):

[0197] (42).

[0198] pin At the top level, At the lowest level, the pin coordinate matrix As shown in equation (43):

[0199] (43).

[0200] pin At the top level, Probability at the bottom layer As shown in equation (44):

[0201] (44).

[0202] pin At the bottom level, At the top level, the pin coordinate matrix As shown in equation (45):

[0203] (45).

[0204] The probability that pin p1 is at the bottom layer and p2 is at the top layer. As shown in equation (46):

[0205] (46).

[0206] When both pins are located at the bottom layer, the pin coordinate matrix As shown in equation (47):

[0207] (47).

[0208] The probability that both pins are located on the bottom layer. As shown in equation (48):

[0209] (48).

[0210] Online and Let the random values ​​of its pin coordinate matrix be respectively ,in This indicates four possible relative positional relationships. The relative positional relationships of two routing nets include nets located on different layers (no conflict), the pins of the two nets located on the same layer, one and only one net having pins spanning two layers, and both nets spanning two layers.

[0211] when or When two cabling networks are located at the top and bottom layers respectively, their potential cabling areas are naturally isolated. Therefore, the relative positional relationship between the two cabling networks is defined as the degree of cabling space conflict when the networks are located on different layers. As shown in equation (49):

[0212] (49).

[0213] when or When the pins of both nets are located on the top layer or both on the bottom layer, the definition can be referenced from the relevant two-dimensional net separation terms. Its physical meaning is the degree of intersection of net trajectories. The relative positional relationship between two routing nets represents the degree of routing space conflict when the nets are located on different layers. As shown in equation (50):

[0214] (50);

[0215] in, and These are optimization variables.

[0216] If the wire mesh Pin cross-layer, i.e. or And the wire mesh The pins are located on the same layer, that is... or The degree of wiring space conflict corresponding to the relative positional relationship can be equivalently simplified to the following formula (51):

[0217] (51).

[0218] when and The pins all span the top and bottom layers, that is... or and or Then the degree of wiring space conflict can be decomposed into the sum of two "same-layer separations", defined as follows (52):

[0219] (52).

[0220] Based on the aforementioned four relative positional relationships, the embodiments of this application will use a wire mesh. and The separation cost between them is expanded to their expected value. Specifically defined as follows (53):

[0221] (53);

[0222] in, and These represent the pin coordinate matrix values ​​for the two wire meshes under four possible relative positional relationships.

[0223] The expected value obtained by extending the above separation cost is summed over all wire pairs to obtain the global wire separation loss as the third evaluation index, as shown in the following equation (54):

[0224] (54);

[0225] in, This represents the global net separation loss.

[0226] According to embodiments of this application, by optimizing the circuit board layout using a third evaluation metric, the potential conflicts and separation between nets can be measured more accurately in three-dimensional space. Through continuous iterative optimization, the distribution of components on the top and bottom layers will be more uniform, meeting the stringent requirements of complex electronic systems for circuit board performance and improving the efficiency and quality of circuit board design.

[0227] Figure 4A A schematic diagram illustrating the wiring space conflict of two wire networks located on different layers according to an embodiment of this application is shown.

[0228] like Figure 4A As shown, the two wire meshes are located at the top and bottom layers respectively, and the wiring spaces of the two wire meshes do not conflict.

[0229] Figure 4B A schematic diagram illustrating a wiring space conflict where two net pins are located on the same layer according to an embodiment of this application is shown.

[0230] like Figure 4B As shown, both wire networks are located on the top layer, and the degree of conflict in the wiring space is calculated based on the dashed lines.

[0231] Figure 4C A schematic diagram of wiring space conflicts across pin layers with one and only one net according to an embodiment of this application is shown.

[0232] like Figure 4C As shown, one wire spans multiple layers, while the other wire is located on the top layer. The degree of spatial conflict in the wiring is calculated based on the dotted lines.

[0233] Figure 4D A schematic diagram illustrating a wiring space conflict where both nets span two layers, according to an embodiment of this application, are shown.

[0234] like Figure 4D As shown, both nets span multiple layers, and the degree of spatial conflict in the wiring is calculated based on the dashed lines.

[0235] When calculating the gradient of the objective function, both the first and second evaluation terms are the two-dimensional positions of the components. and confidence level Differentiable functions. For the third evaluation term, regarding the confidence level... The gradient is easy to calculate, and its effect on the two-dimensional position of the element is relatively simple. The gradient can be reduced to the calculation of the pin gradient using the chain rule. According to the definition of the third evaluation term, the gradient calculation under different relative positions can be reduced to the case where "both net pins are located at the top layer or both at the bottom layer". Therefore, the gradient solution process for this relative position is given.

[0236] When calculating the gradient, the optimal solution can be obtained by solving the optimization problem shown in equation (55). With scalar :

[0237] (55).

[0238] Then you can ask for the wire mesh. The gradient of each pin. (Based on pin...) For example, the gradient solution process is shown in equation (56) below:

[0239] (56);

[0240] in, For indicator functions, For matrix The first line.

[0241] pin The coordinate gradient is from The first two components constitute it, that is, its... and The directional component. Similarly, the wire mesh can be calculated. Another pin The gradient, and the wire mesh The pin gradient can also be obtained using the same method.

[0242] According to embodiments of this application, a layout scheme for the circuit board is determined based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out, including: under the constraints of no overlap between components and no component exceeding the circuit board boundary, with the goal of minimizing the total wiring length and the difference between the maximum wiring net length and the minimum wiring net length, adjusting the target two-dimensional position of each component and the rotation angle relative to a preset direction to obtain the two-dimensional position to be laid out of each component and the target rotation angle relative to the preset direction; and determining the layout scheme based on the two-dimensional position to be laid out of each component relative to the circuit board, the layer to be laid out, and the target rotation angle relative to the preset direction.

[0243] Determining the layer to be laid out for each component using gradient descent Next, legalization needs to be performed to obtain the final layout that satisfies manufacturing constraints. The optimization variables in the legalization phase include... ,in The definition is as stated above. The definition is shown in equation (57):

[0244] (57);

[0245] in, Indicator element The counterclockwise rotation angle, This indicates the counterclockwise rotation angle of each component.

[0246] Because after the iterative optimization is completed, each element's The expression has converged to 0 or 1, therefore the length terms are all definite values ​​during the legalization phase. The legalization phase solves the optimization problem as shown in equation (58):

[0247] (58);

[0248] in, To balance minimizing the total cabling length and the difference between the maximum and minimum cabling net lengths, a hyperparameter is used. [] indicates mathematical expectation.

[0249] In the embodiments of this application, the legalization constraints include the constraints that there is no overlap between components and that each component does not exceed the boundary of the circuit board, ensuring that the final layout scheme meets the component layout requirements of the circuit board.

[0250] After obtaining the two-dimensional position of each component relative to the circuit board, the layer to be laid out, and the target rotation angle relative to the preset direction, a layout scheme can be obtained accordingly, and then the circuit board can be laid out based on the layout scheme.

[0251] According to embodiments of this application, after determining the layers to be laid out for each component, the target two-dimensional positions of the components and their rotation angles relative to a preset direction are further adjusted to minimize the total wiring length and the difference between the maximum and minimum wiring net lengths, under the constraints of no overlap between components and no component exceeding the circuit board boundary. This ensures that the final layout scheme fully meets the component layout requirements of the circuit board. This not only guarantees the correctness of physical isolation and electrical connections between components but also optimizes the overall performance of the circuit board.

[0252] According to an embodiment of this application, a layout scheme is determined based on the two-dimensional position of each component relative to the circuit board, the layer to be laid out, and the target rotation angle relative to a preset direction. The scheme includes: obtaining the two-dimensional position of each component's layer to be laid out; checking and identifying all target components whose distance from adjacent components or the circuit board boundary is less than the preset component safety spacing rule; and for each target component, performing a position translation once on the two-dimensional plane of the layer to be laid out of the target component, along a direction away from the adjacent components or the circuit board boundary, until the safety spacing rule is met.

[0253] According to the embodiments of this application, by performing spacing checks and fine-tuning through post-implemented component safety spacing rules, it can be ensured that the optimized layout scheme fully meets the minimum physical spacing requirements for component installation and soldering, reducing the risk of manufacturing defects such as short circuits, assembly interference, or poor heat dissipation caused by insufficient spacing, thereby significantly improving the reliability of the final layout scheme.

[0254] Figure 5 A flowchart illustrating the determination of a layout scheme according to an embodiment of this application is shown.

[0255] like Figure 5 As shown, determining the layout scheme includes operations S510 to S550.

[0256] During operation S510, the initial two-dimensional positions of each element are randomly initialized.

[0257] When operating the S520, a graph neural network is used to determine the initial confidence level of each component's placement in each layer.

[0258] In operation S530, by performing gradient calculation on the optimization objective function, the initial two-dimensional position and initial confidence of each element are iteratively adjusted to obtain the target two-dimensional position and target confidence of each element, and the layer to be laid out for each element is determined based on the target confidence.

[0259] In operation S540, under the condition of satisfying the constraints, with the goal of minimizing the total wiring length and the difference between the maximum wiring net length and the minimum wiring net length, the target two-dimensional position of each component and the rotation angle relative to the preset direction are adjusted to obtain the two-dimensional position to be laid out of each component and the target rotation angle relative to the preset direction.

[0260] In operation of S550, a layout scheme is determined based on the two-dimensional position of each component relative to the circuit board, the layer to be laid out, and the target rotation angle relative to the preset direction.

[0261] Based on the above-described circuit board layout method, this application also provides a circuit board layout apparatus. The following will be combined with... Figure 6 The device is described in detail.

[0262] Figure 6 A structural block diagram of a circuit board layout apparatus according to an embodiment of this application is shown.

[0263] like Figure 6 As shown, the circuit board layout device 600 of this embodiment includes an initial determination module 610, a target determination module 620, a layer determination module 630, and a layout determination module 640.

[0264] The initial determination module 610 is used to determine the initial position information of each component based on the connection relationship between the components to be laid out and the attribute parameters of each component. The initial position information includes the initial two-dimensional position of the component relative to the circuit board and the initial confidence level of the component laid out on each layer of the circuit board. In one embodiment, the initial determination module 610 can be used to perform the operation S210 described above, which will not be repeated here.

[0265] The target determination module 620 is used to adjust the initial position information with the goal of achieving optimal layout rationality, thereby obtaining target position information. The target position information includes the target two-dimensional position relative to the circuit board and the target confidence level of the layout on each layer. Layout rationality is determined based on at least one of the following evaluation metrics: a first evaluation metric characterizing the amount of wiring, a second evaluation metric characterizing the uniformity of component layout, a third evaluation metric characterizing the degree of wiring intersection, and a fourth evaluation metric characterizing the layout confidence level. In one embodiment, the target determination module 620 can be used to perform the operation S220 described above, which will not be repeated here.

[0266] The layer determination module 630 is used to determine the layer to be laid out for each element based on the target confidence level of each element's placement in each layer. In one embodiment, the layer determination module 630 can be used to perform the operation S230 described above, which will not be repeated here.

[0267] The layout determination module 640 is used to determine a layout scheme for the circuit board based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out. In one embodiment, the layout determination module 640 can be used to perform the operation S240 described above, which will not be repeated here.

[0268] According to an embodiment of this application, the initial determination module 610 includes an initial confidence determination submodule and an initial two-dimensional determination submodule.

[0269] The initial confidence determination submodule is used to process the connection graph constructed based on the connection relationships between elements and the attribute parameters of each element using a graph neural network, so as to obtain the initial confidence of each element in each layer.

[0270] The initial two-dimensional determination submodule is used to randomly initialize the two-dimensional positions of each element to obtain the initial two-dimensional positions.

[0271] According to an embodiment of this application, the circuit board layout device 600 further includes an iterative adjustment module.

[0272] The iterative adjustment module is used to obtain the target position information through iterative adjustments. Each adjustment includes: based on an optimization objective function constructed using evaluation metrics, calculating the gradient of the optimization objective function to determine the current round position adjustment amount; and using the current round position adjustment amount, adjusting the current round position information to obtain the position information for the next round.

[0273] According to embodiments of this application, the optimization objective function includes an entropy regularization term and other evaluation terms. The entropy regularization term is constructed based on a fourth evaluation metric used to characterize layout confidence. The other evaluation terms are constructed based on at least one of a first evaluation metric used to characterize routing quantity, a second evaluation metric used to characterize component layout uniformity, and a third evaluation metric used to characterize routing crossover degree. The iterative adjustment module also includes a coefficient adjustment submodule.

[0274] The coefficient adjustment submodule is used to perform at least one adjustment on the weight coefficients of the entropy regularization term using reinforcement learning methods, based on the adjustment of the initial position information. Each adjustment includes: evaluating the current round position information based on other evaluation terms to obtain the current round evaluation result; processing the current round evaluation result and the historical round evaluation results using the current round policy network to determine the adjustment magnitude for the current round weight coefficients; the historical round evaluation result is obtained by evaluating the historical round position information based on other evaluation terms, including the previous round position information and the initial position information; and adjusting the current round weight coefficients based on the current round adjustment magnitude to obtain the weight coefficients for the next round.

[0275] According to embodiments of this application, the iterative adjustment module further includes a network adjustment submodule.

[0276] The network adjustment submodule is used to determine the current round reward value based on the current round evaluation results and the previous round evaluation results; and to adjust the parameters of the current round policy network based on the current round reward value to obtain the next round policy network.

[0277] According to an embodiment of this application, the iterative adjustment module further includes a cross-layer line length determination submodule, a planar line length determination submodule, and a first evaluation determination submodule.

[0278] The cross-layer line length determination submodule is used to determine the cross-layer line length of the current round based on the current round confidence of the components to which each pin belongs in each wiring net is located in each layer and the board layer spacing.

[0279] The planar line length determination submodule is used to determine the current wheel planar line length based on the two-dimensional position of each pin in each wiring net relative to the current wheel pin of the circuit board.

[0280] The first evaluation determination submodule is used to determine the index value of the first evaluation index for the current wheel based on the current wheel cross-layer line length and the current wheel plane line length.

[0281] According to embodiments of this application, the iterative adjustment module further includes an actual occupancy determination submodule and a second evaluation determination submodule.

[0282] The actual occupancy determination submodule is used to determine the actual component occupancy of each layout space in a layer based on the size of each component and the initial two-dimensional position of the current wheel, the size and two-dimensional position of each layout space in each layer of the circuit board, and the confidence level of each component's layout in the current wheel of the layer.

[0283] The second evaluation determination submodule is used to determine the index value of the second evaluation index for the current round based on the difference between the actual component occupancy and the average component occupancy of each layout space in the current round. The average component occupancy is determined based on the ratio of the total area of ​​all components to the number of layout spaces.

[0284] According to embodiments of this application, the iterative adjustment module includes a relation probability determination submodule, a relation conflict determination submodule, and a third evaluation determination submodule.

[0285] The relation probability determination submodule is used to determine the current round routing probability of two routing nets as having a relative positional relationship, based on the current round confidence of the components to which each pin in each routing net is located in each layer.

[0286] The relationship conflict determination submodule is used to determine the degree of current round routing space conflict between two routing nets based on the current round pin position information of each pin in the two routing nets for their relative positional relationship.

[0287] The third evaluation determination submodule is used to determine the index value of the third evaluation index for the current round based on the relative positional relationship between any two wiring nets and the degree of spatial conflict in the current round wiring.

[0288] According to an embodiment of this application, the layout determination module 640 includes a target adjustment submodule and a scheme determination submodule.

[0289] The scheme adjustment submodule is used to adjust the target two-dimensional position and rotation angle relative to a preset direction of each component under the constraints of no overlap between components and no component exceeding the circuit board boundary, with the goal of minimizing the total wiring length and the difference between the maximum and minimum wiring net lengths. This results in the desired two-dimensional position of each component and the target rotation angle relative to the preset direction.

[0290] The scheme determination submodule is used to determine the layout scheme based on the two-dimensional position of each component relative to the circuit board, the layer to be laid out, and the target rotation angle relative to the preset direction.

[0291] According to an embodiment of this application, the graph neural network is trained in the following manner: using an initial graph neural network, the sample connection relationship graph constructed based on the connection relationship between each sample element in the sample circuit board and the attribute parameters of each sample element is processed to obtain the sample confidence of each sample element in each layer of the sample circuit board; based on the sample confidence of each element and the actual layout layer in the sample circuit board, the initial graph neural network is adjusted to obtain the graph neural network.

[0292] According to embodiments of this application, any plurality of modules among the initial determination module 610, target determination module 620, layer determination module 630, and layout determination module 640 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of this application, at least one of the initial determination module 610, target determination module 620, layer determination module 630, and layout determination module 640 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the initial determination module 610, target determination module 620, layer determination module 630, and layout determination module 640 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0293] Figure 7 A block diagram of an electronic device suitable for implementing a circuit board layout method according to an embodiment of this application is shown.

[0294] like Figure 7As shown, an electronic device 700 according to an embodiment of this application includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage portion 708 into a random access memory (RAM) 703. The processor 701 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 701 may also include onboard memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of this application.

[0295] RAM 703 stores various programs and data required for the operation of electronic device 700. Processor 701, ROM 702, and RAM 703 are interconnected via bus 704. Processor 701 executes various operations of the method flow according to embodiments of this application by executing programs in ROM 702 and / or RAM 703. It should be noted that programs may also be stored in one or more memories other than ROM 702 and RAM 703. Processor 701 may also execute various operations of the method flow according to embodiments of this application by executing programs stored in one or more memories.

[0296] According to embodiments of this application, the electronic device 700 may further include an input / output (I / O) interface 705, which is also connected to a bus 704. The electronic device 700 may also include one or more of the following components connected to the input / output (I / O) interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the input / output (I / O) interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0297] This application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0298] According to embodiments of this application, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this application, the computer-readable storage medium may include ROM 702 and / or RAM 703 and / or one or more memories other than ROM 702 and RAM 703 described above.

[0299] Embodiments of this application also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the methods provided in the embodiments of this application.

[0300] When the computer program is executed by the processor 701, it performs the functions defined in the system / apparatus of this application embodiment. According to the embodiments of this application, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0301] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 709, and / or installed from a removable medium 711. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0302] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 709, and / or installed from the removable medium 711. When the computer program is executed by the processor 701, it performs the functions defined in the system of this application embodiment. According to the embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0303] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0304] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0305] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0306] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A circuit board layout method, characterized in that, The method includes: Based on the connection relationships between the components to be laid out and the attribute parameters of each component, the initial position information of each component is determined. The initial position information includes the initial two-dimensional position of the component relative to the circuit board and the initial confidence level of the component laid out on each layer of the circuit board. With the goal of achieving optimal layout rationality, the initial position information is adjusted to obtain target position information. The target position information includes the target two-dimensional position relative to the circuit board and the target confidence level of the layout in each layer. The layout rationality is determined based on at least one of the following evaluation indicators: a first evaluation indicator for characterizing the amount of wiring, a second evaluation indicator for characterizing the uniformity of component layout, a third evaluation indicator for characterizing the degree of wiring intersection, and a fourth evaluation indicator for characterizing layout confidence. Based on the target confidence level of each of the components being laid out in each of the layers, the layers to be laid out for each of the components are determined; Based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out, a layout scheme for the circuit board is determined.

2. The layout method according to claim 1, characterized in that, The determination of the initial position information of each element based on the connection relationships between the elements to be laid out and the attribute parameters of each element includes: Using a graph neural network, the connection graph constructed based on the connection relationships between the elements and the attribute parameters of the elements is processed to obtain the initial confidence of the elements in each layer. The two-dimensional positions of each element are randomly initialized to obtain the initial two-dimensional positions.

3. The layout method according to claim 1, characterized in that, It also includes obtaining the target location information through iterative adjustments; wherein performing one adjustment includes: Based on the optimization objective function constructed using the evaluation index, the current wheel position adjustment amount for adjusting the current wheel position information is determined by performing gradient calculation on the optimization objective function. The current wheel position information is adjusted using the current wheel position adjustment amount to obtain the position information for the next wheel.

4. The layout method according to claim 3, characterized in that, The optimization objective function includes an entropy regularization term and other evaluation terms. The entropy regularization term is constructed based on a fourth evaluation metric used to characterize layout confidence. The other evaluation terms are constructed based on at least one of a first evaluation metric used to characterize routing quantity, a second evaluation metric used to characterize component layout uniformity, and a third evaluation metric used to characterize routing crossover degree. The method further includes: Using reinforcement learning methods, the weight coefficients of the entropy regularization term are adjusted at least once as the initial position information is adjusted; wherein performing one adjustment includes: Based on the other evaluation items, the current wheel position information is evaluated to obtain the current wheel evaluation result for the current wheel position information; Using the current round policy network, the current round evaluation results and the historical round evaluation results are processed to determine the current round adjustment range for the current round weight coefficient. The historical round evaluation results are obtained by evaluating the historical round position information based on the other evaluation items. The historical round position information includes the previous round position information and the initial position information. Based on the adjustment range of the current round, the weight coefficient of the current round is adjusted to obtain the weight coefficient of the next round.

5. The layout method according to claim 4, characterized in that, The method further includes: Based on the current round's evaluation results and the previous round's evaluation results, determine the current round's reward value for the current round's policy network; and Based on the current round reward value, the parameters of the current round policy network are adjusted to obtain the next round policy network.

6. The layout method according to claim 3, characterized in that, The value of the first evaluation indicator in the current round is determined as follows: Based on the current round confidence of the components to which each pin belongs in each wiring net is located in each layer and the circuit board layer spacing, determine the current round cross-layer line length; The length of the current wheel plane is determined based on the two-dimensional position of each pin in each of the wiring nets relative to the current wheel pin of the circuit board; Based on the current wheel's cross-layer line length and the current wheel's plane line length, determine the index value of the current wheel's first evaluation index.

7. The layout method according to claim 3, characterized in that, The values ​​of the second evaluation indicator in the current round are determined as follows: Based on the dimensions of each component and the initial two-dimensional position of the current wheel, the dimensions and two-dimensional positions of each layout space in each layer of the circuit board, and the confidence level of each component's current wheel layout in the layer, the actual component occupancy of the current wheel in each layout space of the layer is determined. Based on the difference between the actual component occupancy and the average component occupancy of each layout space in the current round, the index value of the second evaluation index for the current round is determined, wherein the average component occupancy is determined based on the ratio of the total area of ​​all components to the number of layout spaces.

8. The layout method according to claim 3, characterized in that, The values ​​of the third evaluation indicator in the current round are determined as follows: For any two routing nets, based on the current round confidence of the components to which each pin in each routing net is located in each layer, determine the current round routing probability of the two routing nets being in their relative positional relationship. Based on the current wheel pin position information of each pin in the two wiring nets, the degree of current wheel wiring space conflict of the two wiring nets in their relative positional relationship is determined; Based on the current round routing probability and the current round routing spatial conflict degree of any two routing nets with their relative positional relationship, determine the index value of the third evaluation index for the current round.

9. The layout method according to claim 1, characterized in that, The step of determining a layout scheme for the circuit board based on the target two-dimensional position of each component relative to the circuit board and the layer to be laid out includes: Under the constraints of no overlap between the components and no component exceeding the circuit board boundary, with the goal of minimizing the total wiring length and the difference between the maximum and minimum wiring net lengths, the target two-dimensional position and rotation angle relative to the preset direction of each component are adjusted to obtain the two-dimensional position to be laid out of each component and the target rotation angle relative to the preset direction. The layout scheme is determined based on the two-dimensional position of each component relative to the circuit board, the layer to be laid out, and the target rotation angle relative to a preset direction.

10. The layout method according to claim 2, characterized in that, The graph neural network is trained in the following way: Using an initial graph neural network, the sample connection graph constructed based on the connection relationship between each sample element in the sample circuit board and the attribute parameters of each sample element is processed to obtain the sample confidence of each sample element in each layer of the sample circuit board. Based on the sample confidence of each component and the actual layout layer in the sample circuit board, the initial graph neural network is adjusted to obtain the graph neural network.

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