A digital delay shutdown relay drive system

Abstract

This invention relates to the field of electronic circuit control technology, specifically to a digital delay-off relay drive system. It addresses the technical problems of existing relay delay-off schemes, such as the difficulty in balancing digital setting and hardware reliability, and the poor turn-off performance caused by the simplistic back EMF handling methods. The technical solution includes: a power supply status detection module, a digital delay setting module, a back EMF segmented control module, and a coil drive and freewheeling control module. It achieves precise delay-off through pure digital logic circuits, dynamically switches the controllable freewheeling path according to the back EMF attenuation range, and realizes the linkage between delay logic and freewheeling control. This invention offers advantages such as high delay accuracy, strong anti-interference capability, the ability to balance back EMF suppression and rapid contact release, and high operational reliability, making it suitable for industrial control, power electronics, and other fields.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit control technology, and more specifically, to a digital delay-off relay drive system. Background Technology

[0002] Electromagnetic relays, as a commonly used switching element, are widely used in industrial control, automotive electronics, smart homes, and power management systems. In many application scenarios, when the main power supply is suddenly interrupted due to a fault or normal shutdown, the system often requires that the relay contacts not open immediately, but rather maintain a settable delay before separating, in order to ensure the preservation of critical data, safe reset of mechanisms, or execution of emergency communications.

[0003] There are currently two common solutions for implementing relay delayed shutdown.

[0004] The first type of solution uses a microcontroller and a software timer. The microcontroller monitors the power supply voltage, and when a power failure is detected, the software starts the timer. After the delay, the relay drive circuit is turned off through the I / O port. The main problem with this solution is that the microcontroller itself is at risk of reset or unstable operation during power drop, and the software runtime sequence is easily interfered with, which leads to a decrease in delay accuracy and reliability. Especially in the critical range of slow power supply voltage drop, the microcontroller may repeatedly reset, causing the relay contacts to malfunction.

[0005] The second type of solution uses an analog delay-off circuit composed of a resistor-capacitor delay circuit and a transistor. It uses the time constant of the capacitor to store charge to achieve the delay. The structure is relatively simple. However, the analog resistor-capacitor delay circuit is significantly affected by temperature, capacitor aging and voltage fluctuations. The delay time is inconsistent and it is difficult to achieve precise digital setting. In addition, this solution usually only uses a single freewheeling diode to deal with the back electromotive force generated when the relay coil is de-energized, which results in slow coil current decay and excessively long relay contact release time. It cannot meet the requirements in situations where fast and reliable turn-off is required.

[0006] More importantly, the relay coil generates a back electromotive force spike of hundreds or even thousands of volts at the moment of power failure. If not handled properly, it will not only damage the drive switch, but also accelerate the contact erosion due to excessive arc energy. The existing technology has relatively simple methods for handling back electromotive force, and does not take into account the difference in the attenuation characteristics of back electromotive force energy in different voltage ranges. It lacks a segmented freewheeling management mechanism that can take into account rapid energy discharge, switch stress control and contact protection.

[0007] Therefore, a digital delay-off relay drive system is proposed. Summary of the Invention

[0008] The purpose of this invention is to provide a digital delay-off relay drive system to solve the technical problems of existing relay delay-off schemes, which make it difficult to balance digital setting and hardware reliability, and the poor off-off performance caused by the single back EMF processing method.

[0009] To address the aforementioned technical problems, the present invention aims to provide a digital delay-off relay drive system, comprising: The power status detection module is used to continuously monitor the main power supply voltage and output a power-off indication signal when the main power supply voltage is lower than the preset voltage threshold. The digital delay setting module is used to generate a delay time setting value based on the mechanical position of the external DIP switch, and after receiving the power-off indication signal, it starts a delay count based on pure digital logic circuit. When the count value reaches the delay time setting value, it outputs a shutdown trigger signal. The back EMF segmented control module includes a voltage divider network, a multi-channel voltage comparator, and a freewheeling path switching logic circuit. The voltage divider network samples the back EMF voltage generated by the relay coil at the moment of power failure and outputs multiple voltage divider signals with different ratios. The multi-channel voltage comparator compares each voltage divider signal with the corresponding reference voltage threshold to generate a segmented state signal characterizing the current decay interval of the back EMF voltage. The freewheeling path switching logic circuit selects the controllable freewheeling path corresponding to the current decay interval based on the segmented state signal and the counting state of the digital delay setting module during the delay counting period and when the shutdown trigger signal is not output. The coil drive and freewheeling control module includes a normal drive path and multiple controllable freewheeling paths. The normal drive path is turned on when the main power supply voltage is higher than the preset voltage threshold, providing the rated pull-in voltage to the relay coil. The controllable freewheeling paths are selected by the back electromotive force segmentation control module when the main power supply voltage is lower than the preset voltage threshold. The coil drive and freewheeling control module is also used to turn off all controllable freewheeling paths when the turn-off trigger signal is received, so that the relay contacts are separated.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This digital delay-off relay drive system uses pure digital logic circuits to realize delay setting and counting, avoiding the influence of temperature drift and parameter dispersion of analog devices. It has high delay accuracy, and at the same time, it does not require the participation of MCU and software program. It has strong anti-electromagnetic interference capability, is suitable for harsh industrial operating environments, and solves the problems of unreliable delay and inconvenient adjustment of existing solutions. 2. In this digital delay turn-off relay drive system, by adopting a back EMF segmented control scheme, the controllable freewheeling path with different impedances is dynamically switched according to the real-time decay range of the back EMF. During the peak stage of the back EMF, a high-impedance path is used to suppress the peak voltage and avoid overvoltage damage to the switching device. During the middle and later stages of the back EMF decay, a low-impedance path is used to accelerate the discharge of the coil current. This solves the conflicting requirements of device protection and rapid contact release and reduces the risk of contact arcing and burning. 3. In this digital delay-off relay drive system, during the delay counting period, the coil current is maintained by dynamically selected freewheeling paths to ensure that the relay reliably engages during the delay phase after the main power supply fails. After the delay count reaches the set value, all freewheeling paths are immediately shut off, realizing rapid energy discharge of the coil and reliable separation of the contacts. This solves the technical problem that existing solutions cannot simultaneously achieve accurate delay maintenance and rapid and reliable shutdown. Attached Figure Description

[0011] Figure 1 This is an overall system block diagram of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] Examples, such as Figure 1 As shown, this embodiment provides a digital delay-off relay drive system, including: The power status detection module is used to continuously monitor the main power supply voltage and output a power-off indication signal when the main power supply voltage is lower than the preset voltage threshold. The digital delay setting module is used to generate a delay time setting value based on the mechanical position of the external DIP switch, and after receiving the power-off indication signal, it starts a delay count based on pure digital logic circuit. When the count value reaches the delay time setting value, it outputs a shutdown trigger signal. The back EMF segmented control module includes a voltage divider network, a multi-channel voltage comparator, and a freewheeling path switching logic circuit. The voltage divider network samples the back EMF voltage generated by the relay coil at the moment of power failure and outputs multiple voltage divider signals with different ratios. The multi-channel voltage comparator compares each voltage divider signal with the corresponding reference voltage threshold to generate a segmented state signal characterizing the current decay interval of the back EMF voltage. The freewheeling path switching logic circuit selects the controllable freewheeling path corresponding to the current decay interval based on the segmented state signal and the counting state of the digital delay setting module during the delay counting period and when the shutdown trigger signal is not output. The coil drive and freewheeling control module includes a normal drive path and multiple controllable freewheeling paths. The normal drive path is turned on when the main power supply voltage is higher than the preset voltage threshold, providing the rated pull-in voltage to the relay coil. The controllable freewheeling paths are selected by the back electromotive force segmentation control module when the main power supply voltage is lower than the preset voltage threshold. The coil drive and freewheeling control module is also used to turn off all controllable freewheeling paths when the turn-off trigger signal is received, so that the relay contacts are separated.

[0014] It should be noted that the application object of this embodiment is a DC electromagnetic relay with a rated voltage of 24V, a relay coil inductance of 100mH, a coil internal resistance of 100Ω, a rated contact load of 220VAC / 10A, and a rated input voltage of 24VDC for the main power supply. Furthermore, each module is disclosed.

[0015] Since the core trigger condition for relay delayed turn-off is the main power supply failure, it is necessary to accurately and reliably identify the main power supply failure state to avoid false triggering caused by voltage fluctuations. Simultaneously, a trigger signal should be output quickly at the moment of power failure to provide accurate timing for subsequent delay and freewheeling control. Therefore, a power supply status detection module is proposed. This module samples the main power supply voltage through a resistor divider network, compares the sampled voltage with a reference voltage, determines whether the main power supply is in a normal power supply state, and outputs the corresponding level signal. The specific implementation method is as follows: The input terminal of the power status detection module is connected to the positive terminal of the main power supply input and continuously samples the main power supply voltage. The preset voltage threshold is set to 18V. When the main power supply voltage is lower than 18V, the module outputs a high-level valid power-off indication signal; when the main power supply voltage is higher than 18V, the module outputs a low level, and the system is in normal working condition. Through the above technical means, the operating status of the main power supply can be monitored in real time, and a valid trigger signal can be output within 100us after the main power supply fails, providing an accurate start time for the subsequent delayed shutdown action.

[0016] In order to solve the problems of low accuracy, large temperature drift, and poor anti-interference ability of existing analog RC delay circuits, while achieving flexible setting of wide-range delays without the participation of software programs and improving the operation reliability of the system in an industrial environment, a digital delay setting module is proposed. The module generates a binary delay setting value through the mechanical position coding of a DIP switch. After receiving a power-off indication signal, it starts a digital counter to count standard clock pulses. When the count value is equal to the set value, it outputs a turn-off trigger signal. The whole process is completed by a pure hardware digital logic circuit. The specific implementation method is as follows: The module obtains the delay time set by the user through an external 4-bit DIP switch and generates a corresponding 16-bit binary delay setting value. After receiving the power-off indication signal output by the power status detection module, it immediately starts the internal digital counter to start delay counting. When the count value of the counter is exactly the same as the delay setting value set by the DIP switch, it outputs a turn-off trigger signal with a high-level validity. Through the above technical means, the influence of parameter discreteness and temperature drift of analog devices is avoided, the delay accuracy is high, the anti-interference ability is strong, and the delay time can be flexibly adjusted through the DIP switch without modifying the hardware circuit.

[0017] In order to solve the contradiction that the existing fixed freewheeling circuit cannot balance the suppression of back EMF spikes and the rapid release of contacts, while realizing the linkage of freewheeling control and delay logic and ensuring the reliable attraction of the relay during the delay stage, a back EMF segmented control module is proposed. The back EMF voltage after the relay coil is powered off gradually decreases as the coil current decays. The back EMF voltage is sampled in real time through a voltage division network. Its implementation principle is as follows: multiple voltage comparators are used to identify the attenuation interval where the back EMF is currently located, and then a logic circuit combines the delay counting state to dynamically select a freewheeling circuit with a corresponding impedance. Only during the delay counting period is the freewheeling circuit allowed to conduct. The specific implementation method is as follows: The voltage divider network inside the back EMF segmented control module is connected in parallel across the relay coil. It collects the back EMF voltage generated at the moment the coil is de-energized in real time and outputs three voltage divider signals with different ratios. These three voltage divider signals are input to three corresponding voltage comparators. Each voltage comparator compares the voltage divider signal with the corresponding reference voltage threshold and outputs three segmented status signals, representing the high, medium, and low attenuation ranges of the back EMF. The freewheeling path switching logic circuit receives the segmented status signals, the counting status signal from the digital delay setting module, and the shutdown trigger signal. Only when the system is in the delay counting period and no shutdown trigger signal is output will the controllable freewheeling path of the corresponding attenuation range be selected according to the segmented status signal. Once the shutdown trigger signal is valid, all controllable freewheeling paths are immediately locked to the shutdown state. Through the above technical means, the fine control of the back EMF attenuation process is achieved, taking into account the requirements of peak voltage suppression and rapid coil current discharge. At the same time, through linkage with the delay logic, reliable relay engagement during the delay phase is ensured, and rapid contact separation can be achieved after the delay ends.

[0018] To achieve reliable relay operation during normal operation, maintain coil current during the delay phase after main power failure, and ensure rapid turn-off after the delay, a coil drive and freewheeling control module is proposed to dynamically switch the freewheeling path. The normal drive path is activated when the main power is normal, providing the coil with the rated pull-in voltage to ensure reliable relay engagement. Multiple controllable freewheeling paths are connected in parallel with the coil and dynamically selected by the back-EMF segmented control module after main power failure to maintain coil current. Upon receiving a turn-off trigger signal, all freewheeling paths are simultaneously turned off, cutting off the coil's freewheeling circuit and achieving rapid contact separation. The specific implementation method is as follows: The normal drive path input of the coil drive and freewheeling control module is connected to the main power supply, and the output is connected to the high end of the relay coil. When the main power supply voltage is higher than a preset threshold, the normal drive path is activated, outputting a 24V rated pull-in voltage to the coil. The module integrates three controllable freewheeling paths, all connected in parallel across the relay coil. The control terminal of each freewheeling path is connected to the output of the back EMF segmented control module. After the main power supply fails, the back EMF segmented control module dynamically selects the corresponding freewheeling path based on the back EMF decay range. The coil drive and freewheeling control module is then deactivated. The control input terminal is connected to the turn-off trigger signal output terminal of the digital delay setting module. When a valid turn-off trigger signal is received, regardless of the output state of the back EMF segmented control module, all three controllable freewheeling circuits are immediately turned off, cutting off all freewheeling circuits of the coil and causing the relay contacts to separate quickly. Through the above technical means, reliable control of the entire process of the relay's normal drive, delay holding, and rapid turn-off is achieved. Combined with segmented freewheeling control, reliable relay engagement during the delay stage is ensured, and rapid contact separation is achieved after the delay ends, reducing the risk of contact arcing and burning.

[0019] To accurately identify the three core intervals in the back electromotive force (EMF) decay process using three independent voltage comparators, and to provide accurate state information for the dynamic switching of the freewheeling path, the three-interval division balances control accuracy and circuit complexity, and is compatible with the back EMF decay characteristics of most DC relays. Therefore, the multi-voltage comparator in the back EMF segmented control module includes a first voltage comparator, a second voltage comparator, and a third voltage comparator. The reference voltage threshold of the first voltage comparator corresponds to the high voltage interval of the back EMF peak voltage, the reference voltage threshold of the second voltage comparator corresponds to the medium voltage interval of the back EMF peak voltage, and the reference voltage threshold of the third voltage comparator corresponds to the low voltage interval of the back EMF peak voltage. The implementation principle is as follows: the output terminal of each voltage comparator is connected to the input port of the freewheeling path switching logic circuit. Based on the parameters of the relay coil and the withstand voltage value of the switching transistor, the thresholds for the high, medium, and low voltage intervals are set. The three voltage comparators correspond to the three intervals respectively, and output the state signal of the interval in which the back EMF is located in real time. The specific implementation method is as follows: All three voltage comparators employ high-speed open-drain output voltage comparators with a response time of less than 1µs, ensuring rapid response when back EMF spikes occur. The non-inverting input of the first voltage comparator is connected to a 37.5% voltage divider signal output from a voltage divider network, and the inverting input is connected to a first reference voltage threshold of 11.25V, corresponding to the threshold of 30V in the high-voltage range of the back EMF. When the back EMF voltage is ≥30V, the first voltage comparator outputs a high-level active segmented state signal. The non-inverting input of the second voltage comparator is connected to an 18.75% voltage divider signal output from a voltage divider network, and the inverting input is connected to a second reference voltage threshold of 1.875V, corresponding to the threshold of 10V in the medium-voltage range of the back EMF. When 10V ≤ back EMF voltage < 30V, the second voltage comparator outputs a high level. The system provides valid segmented status signals. The non-inverting input of the third voltage comparator is connected to the 6.25% ratio voltage divider signal output by the voltage divider network, while the inverting input is connected to the third reference voltage threshold of 0.3125V, corresponding to the threshold of 5V in the low voltage range of the back EMF. When 5V ≤ back EMF voltage < 10V, the third voltage comparator outputs a high-level valid segmented status signal. The outputs of all three voltage comparators are directly connected to the input ports of the freewheeling path switching logic circuit, providing real-time interval status signals for the logic circuit. Through the above techniques, the three core intervals in the back EMF decay process can be accurately identified. The system has a fast response speed and high identification accuracy, providing a reliable status basis for the dynamic switching of the freewheeling path. The three-interval division balances control accuracy and circuit complexity, making it highly practical.

[0020] To address the core requirements of different back EMF decay ranges, corresponding impedance-matched freewheeling paths are used. High-impedance paths suppress spikes in the high-voltage range, medium-impedance paths balance energy consumption and discharge speed in the medium-voltage range, and low-impedance paths maximize current discharge in the low-voltage range. Simultaneously, interlocking logic ensures that only one freewheeling path is active at a time, avoiding short-circuit risks. Therefore, during the delay counting period and without an output turn-off trigger signal, the freewheeling path switching logic circuit executes the following logic based on the segmented status signal: when the segmented status signal indicates that the back EMF voltage is in the high-voltage range, the first controllable freewheeling path is selected. The first controllable freewheeling path consists of a first resistor and a first switching transistor connected in series; when the segmented status signal indicates that the back EMF voltage is in the medium-voltage range, the first controllable freewheeling path is selected. The second controllable freewheeling path consists of a second resistor and a second switch connected in series, and its equivalent impedance is lower than that of the first controllable freewheeling path. When the segmented status signal indicates that the back electromotive force voltage is in the low voltage range, the third controllable freewheeling path is selected. The third controllable freewheeling path consists of a freewheeling diode and a third switch connected in series, and its equivalent impedance is lower than that of the second controllable freewheeling path. The principle of implementation is as follows: the higher the impedance of the freewheeling path, the lower the back electromotive force peak voltage, but the slower the coil current discharge speed; the lower the impedance, the faster the discharge speed, but the higher the peak voltage. By segmenting and switching paths with different impedances, the optimal impedance parameters are matched in different attenuation ranges, taking into account both peak suppression and fast discharge requirements. The specific implementation method is as follows: The freewheeling path switching logic circuit is built using combinational logic gates with built-in interlocking logic to ensure that only one valid control signal is output at a time. The path switching logic is only executed when the delay count is valid and the shutdown trigger signal is invalid. When the first voltage comparator outputs a high level, indicating that the back EMF is in the high voltage range, the logic circuit outputs the first controllable freewheeling path, selecting the first controllable freewheeling path. The first resistor of the first controllable freewheeling path has a resistance of 100Ω and a power of 5W. The first switching transistor is an N-channel MOSFET with an on-resistance of 10mΩ, and the equivalent impedance of the path is approximately 100.1Ω, the highest among the three paths. This limits the back EMF spike voltage to below 50V, lower than the 60V withstand voltage of the switching transistor, while rapidly dissipating the magnetic field energy of the coil. When the second voltage comparator outputs a high level and the first voltage comparator outputs a low level, indicating that the back EMF is in the medium voltage range, the logic circuit outputs the second controllable freewheeling path, selecting the second controllable freewheeling path. The second resistor of the second controllable freewheeling path... With a resistance of 30Ω and a power of 3W, the second switching transistor is an N-channel MOSFET, and its equivalent impedance is approximately 30.1Ω, lower than that of the first path. This allows for faster coil current discharge while ensuring the back EMF voltage remains within a safe range. When the third voltage comparator outputs a high level, and the first and second voltage comparators output low levels, indicating a low back EMF range, the logic circuit outputs a third control signal to select the third controllable freewheeling path. This third controllable freewheeling path uses a fast recovery Schottky diode connected in series with the N-channel MOSFET. The diode's forward voltage drop is 0.4V, and its equivalent impedance is significantly lower than the first two paths, maximizing the speed of coil current discharge and shortening contact release time. Through these techniques, a three-stage impedance-matched freewheeling path resolves the contradiction between back EMF spike suppression and rapid contact release. Compared to the traditional single freewheeling diode solution, this shortens contact release time while limiting the back EMF spike voltage within a safe range, effectively protecting the driving switching devices.

[0021] Considering that the delay function is implemented through pure hardware digital logic circuits, requiring no software intervention, it has strong anti-interference capabilities and high delay accuracy. Furthermore, the delay parameters can be flexibly set via DIP switches to adapt to different application scenarios. Therefore, the digital delay setting module includes an external DIP switch, an oscillator, a frequency divider, and a digital comparator. The mechanical contact positions of the external DIP switch are encoded as multi-bit binary delay setting values. The oscillator starts oscillating when the power-off indication signal is valid and provides clock pulses to the frequency divider. The frequency divider divides and counts the clock pulses. The digital comparator compares the divided count value bit by bit with the multi-bit binary delay setting value. When the two are equal, the shutdown trigger signal is output. The specific implementation method is as follows: The external DIP switches are 4-bit decimal BCD code switches, which can be set to decimal values ​​from 0000 to 9999. Their mechanical contact positions are encoded with 16-bit binary delay settings. The common terminal of the DIP switches is grounded, and the output is connected to the auxiliary power supply via a pull-up resistor. The auxiliary power supply is powered by a supercapacitor, providing a stable operating power supply to the digital logic circuits after the main power supply fails. The oscillator is a high-precision RC oscillator, constructed from an inverter and low-temperature drift resistors and capacitors. The oscillation frequency is set to 1kHz, and the clock period is 1ms. The oscillator's enable terminal is connected to a power-off indicator signal. When the power-off indicator signal is invalid, the oscillator is in a stopped state, reducing system power consumption. When the power-off indicator signal is valid, the oscillator immediately starts oscillating, providing a stable clock pulse to the counter divider. The counter divider uses a 16-bit binary synchronous counter, composed of four cascaded 4-bit synchronous counters. The clock input terminal of the counter is connected to the oscillator. The output of the oscillator has a reset terminal connected to the inverted output of the power-off indicator signal. When the main power supply is normal, the counter is in a reset state with a count value of 0. Upon receiving the power-off indicator signal, the reset is canceled, and the counter begins to increment the clock pulse count. The digital comparator uses a 16-bit binary digital comparator, which is composed of four cascaded 4-bit digital comparators. The A group input of the comparator is connected to the 16-bit binary delay setting value output by the DIP switch, and the B group input is connected to the 16-bit parallel counting output of the counter divider. The A=B output of the comparator is the shutdown trigger signal output. When the counter count value is exactly equal to the delay setting value set by the DIP switch, a high-level valid shutdown trigger signal is output. Through the above technical means, pure hardware digital logic is implemented without software intervention, which has strong anti-electromagnetic interference capability, improves delay accuracy, and allows for flexible adjustment of the delay time via the DIP switch. It is simple to operate and highly adaptable.

[0022] After prolonged use, relay contacts may become stuck, welded, or experience abnormal coil energy dissipation, preventing proper contact separation after the shutdown trigger signal is issued. This can lead to load uncontrollable accidents. Existing solutions typically lack contact status detection functionality, failing to detect anomalies promptly. Therefore, a contact status feedback module is proposed. This module includes an isolation detection circuit and a logic latch. The input of the isolation detection circuit is connected in parallel across the relay contacts to detect the voltage difference and output the isolated contact status level. The logic latch, upon receiving the shutdown trigger signal and after a preset delay, latches the contact status level. When the latched level indicates that the relay contacts have not successfully separated, an alarm signal is output. The principle is as follows: when the electrical contacts are closed, the voltage difference across them is close to 0V; when they are separated, the voltage difference equals the load supply voltage. By detecting the voltage difference across the contacts, the contact status can be determined. The isolation detection circuit avoids interference from the high-voltage circuit to the low-voltage control circuit. The logic latch latches the contact status after the shutdown action is completed, identifies anomalies, and outputs an alarm. The specific implementation is as follows: The isolation detection circuit uses a linear optocoupler. A current-limiting resistor is connected in series with the primary side of the optocoupler and then connected in parallel across the relay contacts. One end of the relay contact is connected to a 220VAC load power supply, and the other end is connected to the load, with the other end of the load connected to ground. When the contacts are closed, the voltage difference across the contacts is 0V, there is no current in the primary side of the optocoupler, and the secondary side outputs a high level. When the contacts are open, the voltage difference across the contacts is 220VAC, current flows through the primary side of the optocoupler, and the secondary side outputs a low level. The output of the secondary side of the optocoupler is connected to an RC low-pass filter circuit with a cutoff frequency of 1kHz to filter out interference signals generated by contact bounce. The filtered signal is the isolated contact state level. The logic latch uses a D flip-flop. The D input of the D flip-flop is connected to the contact state level, and the clock input is connected to the turn-off trigger signal after an RC delay circuit. The output has a preset delay time of 100ms. That is, after the shutdown trigger signal is issued, it waits 100ms for the relay contacts to complete the release action before triggering the D flip-flop to latch the current contact state level. The inverted output of the D flip-flop is connected to the alarm circuit. When the latched contact state level is high, it indicates that the contacts are still in the closed state and have not successfully separated. The inverted output of the D flip-flop outputs a high-level valid alarm signal. The alarm signal can drive an LED indicator or a buzzer, or it can be uploaded to the upper-level control system. Through the above technical means, complete isolation between the high-voltage circuit and the low-voltage control circuit is achieved, with strong anti-interference ability. It can accurately detect the actual working state of the relay contacts, promptly identify abnormal situations such as contact adhesion and failure to separate, and output alarms, thereby improving the system's operational safety and fault early warning capability.

[0023] Considering that the inductance and internal resistance of the relay coil change with usage time and temperature, and the on-resistance of the switching transistor increases with aging, these changes will alter the decay rate of the back electromotive force. Existing solutions lack monitoring of these parameters, making it impossible to predict device aging and performance degradation in advance. Repairs can only be performed after a fault occurs, posing a downtime risk. Therefore, a status recording module is proposed. This module collects the duration of segmented status signals output from multiple voltage comparators and compares the duration with a preset reference duration range. When the duration exceeds the reference duration range, abnormal event information is recorded. The principle is as follows: the decay rate of the back electromotive force after the relay coil is de-energized is directly related to the coil inductance, internal resistance, and freewheeling path impedance. By collecting the duration of each segmented status signal and comparing it with the calibrated reference duration range, the performance status of the device can be determined, and abnormal events can be recorded. The specific implementation method is as follows: The status recording module includes a timing unit, a reference duration storage unit, a comparison unit, and a non-volatile storage unit. The timing unit uses a 16-bit counter, with its clock input connected to the 1kHz oscillator output of the digital delay setting module. The trigger input of the timing unit is connected to the outputs of three voltage comparators, recording the duration of the high, medium, and low voltage segment status signals in milliseconds (ms). The reference duration storage unit uses an EEPROM to store preset reference duration ranges for each segment status signal. These reference duration ranges are obtained based on newly calibrated relay and driver parameters. In this embodiment, the reference duration range for the high voltage range is 0.5ms-2ms, for the medium voltage range it is 2ms-5ms, and for the low voltage range it is 5ms-10ms. The comparison unit uses a digital comparator to record the time from the timing unit. The duration of each segment is compared with the upper and lower thresholds in the reference duration storage unit. When the duration is less than the lower limit or greater than the upper limit, an abnormal trigger signal is output. The non-volatile storage unit uses ferroelectric RAM. When an abnormal trigger signal is received, it records the abnormal event information, including the time of the abnormality, the segmented channel of the abnormality, the actual duration, and the reference duration range. It also records the current delay setting value and the voltage value when the main power supply fails. The recorded information can be uploaded to the upper-level control system through the serial communication interface. Through the above technical means, the performance status of the relay coil and the drive switch can be monitored in real time, the aging and performance degradation of the devices can be predicted in advance, predictive maintenance can be achieved, and downtime losses caused by sudden failures can be avoided. At the same time, the abnormal event recording provides complete data support for fault analysis, improving the maintainability and traceability of the system.

[0024] Since the rated voltage required for relay activation is much higher than the holding voltage after activation, applying the rated activation voltage for an extended period will cause severe coil overheating, excessive power consumption, and shorten the relay's lifespan. Therefore, the coil drive and freewheeling control module also includes a PWM buck holding submodule during normal operation. During the holding phase after relay activation, this submodule outputs a pulse width modulation signal with an adjustable duty cycle to the relay coil, maintaining the average coil voltage above the relay's minimum holding voltage but below the rated activation voltage. The principle is as follows: after the relay activates, the pulse width modulation signal controls the switching of the drive transistor, reducing the average voltage across the coil and maintaining it above the minimum holding voltage. This ensures reliable relay activation while reducing coil power consumption and overheating. The specific implementation method is as follows: The PWM buck holding submodule includes a PWM generator, a dead-time control circuit, and a pull-in state judgment circuit. The PWM generator is built using a 555 timer and outputs a pulse width modulation signal with a frequency of 20kHz. The duty cycle adjustment range is 10%–50%. The engagement status determination circuit determines whether the relay has completed engagement by detecting the coil current or setting a fixed delay. In this embodiment, a fixed delay of 100ms is used, meaning that the relay is determined to be engaged 100ms after the normal drive path outputs the rated engagement voltage, and the PWM buck holding submodule is activated. The dead-time control circuit avoids the risk of short circuits caused by the upper and lower transistors shooting through the drive switching transistor, ensuring the safety of the drive circuit. In this embodiment, the minimum holding voltage of the relay is 10V. Therefore, the duty cycle of the PWM signal is set to 42%, so that the average voltage across the coil is maintained at around 10V. This ensures reliable relay engagement and reduces the coil power consumption from 5.76W during engagement to 1W during the holding phase. Through the above technical means, the power consumption and heat generation during the relay holding phase are reduced, while the coil power consumption is also reduced, effectively extending the relay's service life. At the same time, it avoids parameter drift caused by long-term high-temperature operation of the coil and improves the system's operational stability.

[0025] Considering the use of a push-pull drive structure, which improves the response speed and driving capability of the normal drive path and ensures rapid and reliable relay engagement; and the use of a parallel controllable freewheeling path structure to achieve independent control of each path, coupled with segmented logic for dynamic switching, the normal drive path in the coil drive and freewheeling control module includes a push-pull drive structure composed of complementary switching transistors. Multiple controllable freewheeling paths are formed by multiple switching transistors connected in series with power resistors or freewheeling diodes of different resistance values ​​to create multiple parallel branches. The control terminals of each switching transistor are connected to the output control terminal of the freewheeling path switching logic circuit. The implementation principle is as follows: the complementary push-pull drive structure enables rapid current injection and extraction, improving the coil charging speed and ensuring rapid relay engagement; multiple parallel controllable freewheeling paths can be controlled by independent switching transistors to achieve flexible switching between different impedance paths. The specific implementation method is as follows: The push-pull drive structure of the normal drive path consists of an N-channel MOSFET Q1 and a P-channel MOSFET Q2. The drain of Q1 is connected to the positive terminal of the main power supply, and the source of Q1 is connected to the source of Q2, both connected to the high end of the relay coil. The drain of Q2 is connected to system ground. The gates of Q1 and Q2 are connected to the drive control circuit. When the main power supply is normal, Q1 is turned on and Q2 is turned off, and the main power supply voltage is directly applied to the two ends of the coil to provide the rated pull-in voltage. When the main power supply fails, both Q1 and Q2 are turned off, cutting off the normal drive path. The three controllable freewheeling paths are in parallel, with one end connected to the high end of the relay coil and the other end connected to the low end of the coil. The first controllable freewheeling path is 100... The first controllable freewheeling circuit consists of a 30Ω power resistor connected in series with an N-channel MOSFET, and the second controllable freewheeling circuit consists of a 30Ω power resistor connected in series with an N-channel MOSFET. The third controllable freewheeling circuit consists of a fast recovery Schottky diode connected in series with an N-channel MOSFET. The gates of the three MOSFETs are connected to the three output control terminals of the freewheeling circuit switching logic circuit, respectively. The logic circuit independently controls the on / off state of each path. Through the above technical means, the fast response speed and strong driving capability of the push-pull drive structure are utilized to ensure that the relay is quickly and reliably engaged. The parallel controllable freewheeling circuit structure is simple and flexible in control, and can realize the rapid switching of different impedance paths. Combined with the segmented control logic, it achieves the optimal freewheeling effect.

[0026] Considering that ordinary comparators often exhibit frequent output switching when the main power supply voltage fluctuates near a critical value, leading to false triggering of the system, a hysteresis comparator can effectively avoid malfunctions caused by voltage fluctuations and improve the system's anti-interference capability. Therefore, the power status detection module includes a series voltage divider resistor network and a hysteresis comparator. The series voltage divider resistor network samples the main power supply voltage, and the hysteresis comparator compares the sampled voltage with an internal reference voltage. Its positive threshold voltage is greater than the negative threshold voltage. The output is connected to the start input pin of the digital delay setting module and the path switching control pin of the coil drive and freewheeling control module. Its implementation principle is as follows: the main power supply voltage is accurately sampled through the series voltage divider resistor network, and the hysteresis comparator sets two threshold voltages, positive and negative. Only when the main power supply voltage is lower than the negative threshold is a power-off indication signal output; only when the main power supply voltage recovers to above the positive threshold is the power-off indication signal canceled. The hysteresis window effectively avoids output jitter caused by voltage fluctuations. The specific implementation method is as follows: The series voltage divider resistor network consists of high-precision, low-temperature drift metal film resistors R1 and R2 connected in series. One end of R1 is connected to the positive terminal of the main power supply input, and the other end is connected to one end of R2. The other end of R2 is connected to system ground. The connection node of R1 and R2 is the sampling voltage output terminal, which is connected to the non-inverting input terminal of the hysteresis comparator. The hysteresis comparator is built using a high-precision operational amplifier. The inverting input terminal is connected to a 2.5V low-temperature drift bandgap reference voltage source, and the output terminal is connected to the non-inverting input terminal via a hysteresis feedback resistor R3. The hysteresis window is set by the resistance ratio of R3 to R1 and R2. In this embodiment, the rated voltage of the main power supply is 24V, and the negative threshold voltage is set to 18V, i.e., the main power supply voltage is low. At 18V, the hysteresis comparator outputs a high-level valid power-off indication signal; the positive threshold voltage is 20V, that is, when the main power supply voltage recovers to above 20V, the hysteresis comparator outputs a low level, canceling the power-off indication signal, and the hysteresis window is 2V; the output of the hysteresis comparator is connected to the start input pin of the digital delay setting module and the path switching control pin of the coil drive and freewheeling control module, respectively, to provide a unified trigger signal for the two modules. Through the above technical means, the system false triggering caused by the fluctuation of the main power supply voltage near the critical value is effectively avoided. It has strong anti-interference ability, high sampling accuracy, fast response speed, and can provide a stable and reliable trigger signal for subsequent modules.

[0027] Because different application scenarios have significantly different time requirements for relay delay shutdown, a wide range of delay settings is needed. At the same time, decimal DIP switches are used for user convenience, eliminating the need for binary conversion. Therefore, the delay time setting range of the digital delay setting module covers hundreds of milliseconds to hundreds of seconds. The external DIP switches are multi-bit decimal DIP switches, and the counter divider is a multi-stage binary serial counter divider. Its implementation principle is as follows: by adjusting the oscillator frequency and the number of bits in the counter divider, a wide range of delay coverage is achieved. Decimal BCD code DIP switches are used to directly convert the user-set decimal values ​​into binary codes for use by the digital comparator. The specific implementation method is as follows: The oscillator's oscillation frequency is set to 1kHz. The counter divider uses a 16-bit multi-stage binary serial counter divider with a maximum count value of 65535. Therefore, the maximum delay time is 65535ms, or approximately 65 seconds, and the minimum delay time is 100ms, covering a setting range from hundreds of milliseconds to hundreds of seconds. The external DIP switch uses a 4-bit decimal BCD code DIP switch, allowing users to directly set the delay time from 0.1 seconds to 65 seconds. For example, setting the DIP switch to 0500 corresponds to a delay time of 500ms; setting it to 1000 corresponds to a delay time of 1 second; and setting it to 30000 corresponds to a delay time of 30 seconds. No binary conversion is required, making the operation simple and intuitive. Through the above technical means, a wide range of delay settings from hundreds of milliseconds to hundreds of seconds is achieved, adapting to the delay requirements of most industrial control scenarios. At the same time, the use of decimal DIP switches makes user operation simple and intuitive, requiring no professional knowledge to complete parameter settings.

[0028] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A digital delay-off relay drive system, characterized in that, include: The power status detection module is used to continuously monitor the main power supply voltage and output a power-off indication signal when the main power supply voltage is lower than the preset voltage threshold. The digital delay setting module is used to generate a delay time setting value based on the mechanical position of the external DIP switch, and after receiving the power-off indication signal, it starts a delay count based on pure digital logic circuit. When the count value reaches the delay time setting value, it outputs a shutdown trigger signal. The back EMF segmented control module includes a voltage divider network, a multi-channel voltage comparator, and a freewheeling path switching logic circuit. The voltage divider network samples the back EMF voltage generated by the relay coil at the moment of power failure and outputs multiple voltage divider signals with different ratios. The multi-channel voltage comparator compares each voltage divider signal with the corresponding reference voltage threshold to generate a segmented state signal characterizing the current decay interval of the back EMF voltage. The freewheeling path switching logic circuit selects the controllable freewheeling path corresponding to the current decay interval based on the segmented state signal and the counting state of the digital delay setting module during the delay counting period and when the shutdown trigger signal is not output. The coil drive and freewheeling control module includes a normal drive path and multiple controllable freewheeling paths. The normal drive path is turned on when the main power supply voltage is higher than the preset voltage threshold, providing the rated pull-in voltage to the relay coil. The controllable freewheeling paths are selected by the back electromotive force segmentation control module when the main power supply voltage is lower than the preset voltage threshold. The coil drive and freewheeling control module is also used to turn off all controllable freewheeling paths when the turn-off trigger signal is received, so that the relay contacts are separated.

2. The digital delay-off relay drive system according to claim 1, characterized in that, The multi-channel voltage comparator in the back EMF segmented control module includes a first voltage comparator, a second voltage comparator, and a third voltage comparator. The reference voltage threshold of the first voltage comparator corresponds to the high voltage range of the back EMF peak voltage, the reference voltage threshold of the second voltage comparator corresponds to the medium voltage range of the back EMF peak voltage, and the reference voltage threshold of the third voltage comparator corresponds to the low voltage range of the back EMF peak voltage. The output terminal of each voltage comparator is connected to the input port of the freewheeling path switching logic circuit.

3. The digital delay-off relay drive system according to claim 2, characterized in that: When the continuous flow path switching logic circuit does not output the shutdown trigger signal during the delay counting period, it executes the following logic based on the segmented status signal: When the segmented status signal indicates that the back electromotive force voltage is in the high voltage range, the first controllable freewheeling path is selected. The first controllable freewheeling path consists of a first resistor and a first switching transistor connected in series. When the segmented status signal indicates that the back electromotive force voltage is in the medium voltage range, the second controllable freewheeling path is selected. The second controllable freewheeling path is composed of a second resistor and a second switch connected in series, and its equivalent impedance is lower than that of the first controllable freewheeling path. When the segmented status signal indicates that the back electromotive force voltage is in the low voltage range, the third controllable freewheeling path is selected. The third controllable freewheeling path is composed of a freewheeling diode and a third switching transistor connected in series, and its equivalent impedance is lower than that of the second controllable freewheeling path.

4. The digital delay-off relay drive system according to claim 1, characterized in that, The digital delay setting module includes an external DIP switch, an oscillator, a frequency divider, and a digital comparator. The mechanical contact positions of the external DIP switch are encoded as multi-bit binary delay setting values. The oscillator starts oscillating when the power-off indication signal is valid and provides clock pulses to the frequency divider. The frequency divider divides and counts the clock pulses. The digital comparator compares the divided count value with the multi-bit binary delay setting value bit by bit. When the two are equal, the shutdown trigger signal is output.

5. The digital delay-off relay drive system according to claim 1, characterized in that, It also includes a contact status feedback module, which includes an isolation detection circuit and a logic latch. The input of the isolation detection circuit is connected in parallel across the relay contact to detect the voltage difference across the contact and output the isolated contact status level. After receiving the shutdown trigger signal and after a preset delay, the logic latch latches the contact status level. When the latched level indicates that the relay contact has not successfully separated, it outputs an alarm signal.

6. The digital delay-off relay drive system according to claim 1, characterized in that, It also includes a status recording module, which collects the duration of the segmented status signals output by the multi-channel voltage comparator and compares the duration with a preset reference duration range. When the duration exceeds the reference duration range, it records abnormal event information.

7. The digital delay-off relay drive system according to claim 1, characterized in that, The coil drive and freewheeling control module also includes a PWM buck holding submodule during normal operation. During the holding phase after the relay is energized, the PWM buck holding submodule outputs a pulse width modulation signal with an adjustable duty cycle to the relay coil, so that the average coil voltage is maintained above the minimum holding voltage of the relay and below the rated energizing voltage.

8. The digital delay-off relay drive system according to claim 1, characterized in that, The normal drive path in the coil drive and freewheeling control module includes a push-pull drive structure composed of complementary switching transistors. The multiple controllable freewheeling paths are formed by multiple switching transistors connected in series with power resistors or freewheeling diodes of different resistance values ​​to form multiple parallel branches. The control terminal of each switching transistor is connected to the output control terminal of the freewheeling path switching logic circuit.

9. The digital delay-off relay drive system according to claim 1, characterized in that, The power status detection module includes a series voltage divider resistor network and a hysteresis comparator. The series voltage divider resistor network samples the main power supply voltage. The hysteresis comparator compares the sampled voltage with an internal reference voltage. Its positive threshold voltage is greater than its negative threshold voltage. The output terminal is connected to the start input pin of the digital delay setting module and the path switching control pin of the coil drive and freewheeling control module.

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