Low voltage ride through control method and system for grid-connected inverter with asymmetrical fault

Abstract

This invention belongs to the field of low-voltage ride-through control technology for grid-connected inverters. It provides a method and system for low-voltage ride-through control of grid-connected inverters applicable to asymmetrical faults. The invention involves modeling the grid-connected inverter equipment and introducing a virtual impedance control loop into the reactive power-voltage loop of the grid-connected inverter. Using the positive and negative sequence separation method, it constructs equivalent circuit diagrams for both positive and negative sequences. Based on the negative sequence equivalent circuit diagram, it analyzes the impact of virtual impedance on current limiting and the voltage at the positive and negative sequence grid connection points. During asymmetrical faults, it designs the impedance ratio of the virtual impedance to limit the maximum output phase current of the grid-connected inverter within a set current limit, thus limiting the output overcurrent of the grid-connected inverter. It provides phasor diagrams of the positive and negative sequence networks under asymmetrical faults, sets the positive and negative sequence voltage amplitudes, and calculates the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection points. Finally, it provides the maximum voltage support range of the grid-connected inverter during asymmetrical faults.

Description

Technical Field

[0001] This invention belongs to the field of low voltage ride-through control technology for grid-connected inverters, and particularly relates to a low voltage ride-through control method and system applicable to grid-connected inverters with asymmetrical faults. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] During the large-scale grid connection of renewable energy, the inherent volatility and randomness of its output power not only pose challenges to the stable operation of the power grid, but also seriously threaten the reliable grid connection of renewable energy due to asymmetrical faults occurring within the grid. Grid connection standards explicitly require that grid-connected inverters possess low-voltage ride-through capability during asymmetrical faults. Therefore, researching control strategies for inverters under asymmetrical faults and improving their low-voltage ride-through performance is particularly important.

[0004] Compared to grid-connected inverters, grid-connected inverters have become the preferred solution in modern power systems due to their higher reliability and stability. Currently, current limiting strategies for grid-connected inverters are mainly divided into two categories. The first is direct current limiting, which limits the amplitude and phase of the output current by adjusting the reference value of the inner current loop. However, this method causes the inverter to lose its voltage source characteristics, making it difficult to maintain frequency and voltage support during faults. The second is indirect current limiting, mainly including power setpoint modulation current limiting, voltage-type current limiting, and virtual impedance current limiting. Among them, power setpoint modulation current limiting achieves current constraint by dynamically adjusting the power setpoint, which can effectively support the grid voltage and directly meet the reactive current supply demand. However, how to maintain the voltage source characteristics of the grid-connected inverter and ensure the speed and accuracy of current limiting under this method still requires further research. Voltage-type current limiting restricts the output current amplitude within an allowable range during a fault by adjusting the phase angle of the output current. However, this method relies on a phase-locked loop to track the grid voltage phase, causing the inverter to become a controlled current source during a fault, which may lead to stability problems under weak grid conditions.

[0005] Virtual impedance current limiting methods have become a research hotspot in the field of grid-connected equipment current limiting due to their ability to maximize the voltage source characteristics of grid-connected inverters. However, existing virtual impedance current limiting control strategies mostly focus on a single objective—limiting overcurrent—without fully considering the impact of virtual impedance insertion on the grid connection point voltage. In fact, the voltage support provided by grid-connected inverters not only helps maintain system voltage stability during faults but also accelerates the recovery of grid voltage after fault clearance, thereby enhancing system rigidity. Especially in the more complex and prevalent asymmetric fault scenarios, existing research rarely explores the impact of positive-sequence and negative-sequence virtual impedances on the grid connection point voltage. This limitation makes it difficult to simultaneously achieve overcurrent suppression and dual support for positive and negative-sequence voltages through virtual impedance control during asymmetric faults, thus hindering the precise adjustment of the positive and negative-sequence voltages at the grid connection point. Summary of the Invention

[0006] To address at least one of the technical problems mentioned above, this invention provides a low-voltage ride-through control method and system for inverters with asymmetrical fault grids, which can accurately control the positive and negative sequence voltages at the grid connection point.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A first aspect of the present invention provides a low-voltage ride-through control method applicable to asymmetrical fault grid-connected inverters, comprising the following steps: Model the grid-type inverter equipment and introduce a virtual impedance control loop into the reactive-voltage loop of the grid-type inverter to simulate the stator impedance in the virtual synchronous generator; Using the positive and negative sequence separation method, we construct the positive and negative sequence equivalent circuit diagrams. Based on the negative sequence equivalent circuit diagram, we analyze the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltages. During asymmetric faults, the impedance ratio of the virtual impedance is designed to limit the maximum phase current of the grid-connected inverter output within the set current limit, thereby limiting the overcurrent output of the grid-connected inverter. The phasor diagram of the positive and negative sequence network under asymmetric fault is given. The positive and negative sequence voltage amplitudes are set, and the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection point are calculated respectively. By combining the values ​​of positive and negative sequence virtual impedances, the maximum voltage support range of the grid-connected inverter during asymmetric faults can be obtained, so as to realize positive and negative sequence voltage control at the grid connection point.

[0008] Furthermore, the control loop that introduces virtual impedance into the reactive power-voltage loop of the grid-connected inverter specifically involves: activating the virtual impedance when a fault occurs. The activation method is to modify the reference voltage value before the voltage-current dual closed loop, satisfying the following: , In the formula, , These are the reference values ​​for the d-axis and q-axis voltages of the voltage loop, respectively. and These are the d-axis and q-axis components of the virtual internal potential, respectively. , These are the d-axis and q-axis current components, respectively. For virtual resistance, This is a virtual reactance.

[0009] Furthermore, the analysis of the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltage based on the negative sequence equivalent circuit diagram includes: extending the virtual impedance to positive and negative sequence virtual impedance, combining the equivalent positive and negative sequence network to calculate the value of positive and negative sequence output current, and then obtaining the positive and negative sequence voltage at the grid connection point.

[0010] Furthermore, the formulas for calculating the positive and negative sequence voltages at the grid connection point are as follows: , , in, , These are the positive-sequence and negative-sequence grid connection point voltages, respectively. , These are the positive-sequence and negative-sequence grid-side voltages, respectively. , These represent the positive-sequence and negative-sequence output currents, respectively. Z is the internal electromotive force of the inverter. g For line impedance, , These are the positive-sequence and negative-sequence virtual impedances, respectively.

[0011] Furthermore, the positive and negative sequence virtual impedances that limit the output overcurrent of a grid-connected inverter are expressed as: , , in, and These are the positive-sequence virtual resistance and virtual reactance, respectively. and These are the negative-sequence virtual resistance and virtual reactance, respectively. and These are the positive and negative sequence virtual impedance gain coefficients, respectively. and These are the ratios of positive and negative sequence virtual resistance to virtual reactance, respectively. This indicates the maximum phase current amplitude output by the inverter. This represents the overcurrent threshold that triggers the virtual impedance.

[0012] Furthermore, the phasor diagram of the positive and negative sequence network under asymmetric fault is given. Based on the set positive and negative sequence voltage amplitudes, the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection point are calculated, including: Based on the phasor diagrams of the positive and negative sequence networks, the relationships between the positive and negative sequence voltages at the grid connection point and the line impedance, the positive and negative sequence virtual impedances, and the line impedance are derived. The amplitudes of the positive and negative sequence voltages are set to be equal to the positive and negative sequence voltages at the grid connection point, thereby obtaining the amplitudes of the corresponding positive and negative sequence virtual impedances, and further obtaining the values ​​of the positive and negative sequence virtual resistances and virtual reactances.

[0013] Furthermore, the maximum voltage support range of the grid-connected inverter during asymmetric faults includes both the positive-sequence voltage support range and the negative-sequence voltage support range.

[0014] A second aspect of the present invention provides a low-voltage ride-through control system applicable to asymmetric fault grid-type inverters, comprising: Impedance simulation module, which is used for modeling grid-connected inverter equipment and introducing a virtual impedance control loop into the reactive-voltage loop of the grid-connected inverter to simulate the stator impedance in a virtual synchronous generator; The virtual impedance analysis module is used to construct positive and negative sequence equivalent circuit diagrams using the positive and negative sequence separation method, and analyze the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltages based on the negative sequence equivalent circuit diagram. The current limiting module is used to design the impedance ratio of the virtual impedance during asymmetrical faults, limiting the maximum phase current of the grid-connected inverter output within the set current limit, thus limiting the overcurrent of the grid-connected inverter output. The impedance calculation module is used to provide the phasor diagram of the positive and negative sequence networks under asymmetrical faults, set the positive and negative sequence voltage amplitudes, and calculate the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection point. The control strategy output module is used to combine the values ​​of positive and negative sequence virtual impedances to obtain the maximum voltage support range of the grid-connected inverter during asymmetrical faults, so as to realize positive and negative sequence voltage control at the grid connection point.

[0015] A third aspect of the present invention provides a computer-readable storage medium.

[0016] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the low-voltage ride-through control method for asymmetric fault grid-type inverters as described above.

[0017] A fourth aspect of the present invention provides a computer device.

[0018] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the low-voltage ride-through control method for asymmetric fault grid-type inverters as described above.

[0019] Compared with the prior art, the beneficial effects of the present invention are: This invention limits the maximum phase current output of a grid-connected inverter to within a current threshold by designing the impedance ratio of the virtual impedance during asymmetrical faults, thereby suppressing overcurrent output of the grid-connected inverter. Simultaneously, this scheme provides voltage support for the grid-connected inverter during asymmetrical faults and can precisely control the positive and negative sequence voltages at the grid connection point.

[0020] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0021] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0022] Figure 1 This is a flowchart of a low-voltage ride-through control method for asymmetrical fault grid-type inverters provided in an embodiment of the present invention; Figure 2 This is an architecture diagram of the precise voltage support system for asymmetric fault low-voltage ride-through in grid-type inverters, as described in an embodiment of the present invention. Figure 3 The positive and negative order equivalent networks of the system under asymmetric faults in this embodiment of the invention are shown below; where (a) is the positive order equivalent network of the system under asymmetric faults and (b) is the negative order equivalent network of the system under asymmetric faults. Figure 4 The diagrams show the phasor relationships of the positive-order and negative-order networks according to an embodiment of the present invention; wherein, (a) is the phasor relationship diagram of the positive-order network and (b) is the phasor relationship diagram of the negative-order network. Figure 5 This is a diagram showing the tuning range of the positive sequence voltage boundary value according to an embodiment of the present invention; wherein, (a) is φ< When the positive sequence voltage is not supported, the range of the positive sequence voltage cannot cover the grid-side positive sequence voltage; (b) is φ> At that time, the support range of the positive sequence voltage can cover the grid-side positive sequence voltage; Figure 6 This is a diagram showing the tuning range of the negative sequence voltage boundary value according to an embodiment of the present invention; Figure 7The diagram shows the changes in output current and positive and negative sequence voltage at the grid connection point of the grid-connected inverter when an asymmetrical fault occurs in an embodiment of the present invention; (a) is the three-phase current waveform output by the grid-connected inverter, and (b) is the output waveform of the positive and negative sequence voltage at the grid connection point of the grid-connected inverter. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] Example 1 like Figure 1 As shown, this embodiment provides a low-voltage ride-through control method for inverters with asymmetrical fault grids, including the following steps: Step 1: Model the grid-connected inverter equipment and introduce a virtual impedance control loop into the reactive-voltage loop of the grid-connected inverter to simulate the stator impedance in the virtual synchronous generator; In this embodiment, the grid-type inverter equipment is modeled using a three-phase three-wire structure and controlled by a virtual synchronous generator (VSG).

[0027] Figure 2 This is a control system structure diagram of a grid-connected inverter, in which... This represents the output voltage of the converter. Indicates the output current. and These represent the equivalent resistance and inductance from the converter port to the grid connection point, respectively. , and These represent the filter resistor, filter inductor, and filter capacitor, respectively.

[0028] VSG control provides inertia and damping to the power grid by simulating the rotor motion equations of a synchronous generator. Its control structure includes a power outer loop, a voltage control inner loop, and a current control inner loop. The power outer loop comprises active power-frequency control and reactive power-voltage control, and its basic equations are as follows: (1), in, This represents the magnitude of the virtual internal potential. The phase angle representing the virtual internal potential. It is the damping coefficient that suppresses oscillations. It is virtual inertia. , , and These represent the actual and reference values ​​of active power and reactive power, respectively. Represents the rated voltage. and These represent the virtual rated speed and the actual speed of the VSG, respectively. This is the reactive voltage droop coefficient.

[0029] A control loop with virtual impedance is introduced into the reactive power-voltage loop of the grid-connected inverter, specifically as follows: When a fault occurs, a virtual impedance is applied. The method for applying the impedance is to modify the reference voltage value before the voltage-current double closed loop, satisfying the following formula: (2), In the formula, , These are the reference values ​​for the d-axis and q-axis voltages of the voltage loop, respectively. and These are the d-axis and q-axis components of the virtual internal potential, respectively. , These are the d-axis and q-axis current components, respectively. For virtual resistance, This is a virtual reactance.

[0030] Step 2: Using the positive and negative sequence separation method, construct the positive and negative sequence equivalent circuit diagram. Based on the positive and negative sequence equivalent circuit diagram, analyze the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltage. Specifically, the steps include the following: Step 201: Use the positive and negative sequence separation method to construct the positive and negative sequence equivalent circuit diagram; like Figure 3 As shown, Figure 3 Figures (a) and (b) show the positive and negative sequence equivalent networks of the system under asymmetrical faults. Since the grid-type inverter in this method adopts a three-phase three-wire structure without a neutral point, there is no zero-sequence component when the system experiences a fault. The three-phase voltage and three-phase current are converted to voltage and current in the positive and negative sequence reference frames using the symmetrical component method.

[0031] Step 202: Based on the positive and negative sequence equivalent circuit diagram, analyze the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltage; In this embodiment, the step of analyzing the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltage based on the negative sequence equivalent circuit diagram includes: extending the virtual impedance to positive and negative sequence virtual impedance, combining the equivalent positive and negative sequence network to calculate the value of positive and negative sequence output current, and then obtaining the positive and negative sequence voltage at the grid connection point.

[0032] like Figure 3 Figures (a) and (b) show the equivalent positive and negative sequence voltage networks of the system under asymmetrical faults. Therefore, the formulas for calculating the positive and negative sequence voltages at the grid connection point are: (3), (4), in, , These represent the positive-sequence and negative-sequence output currents, respectively. , These are the positive-sequence and negative-sequence grid connection point voltages, respectively. , These are the positive-sequence and negative-sequence grid-side voltages, respectively. This is the internal electromotive force of the inverter. For line impedance, , These are the positive-sequence and negative-sequence virtual impedances, respectively.

[0033] As can be seen from the above formula, the injected positive-sequence and negative-sequence virtual impedances can suppress positive-sequence and negative-sequence currents, respectively. However, excessive injection of positive-sequence virtual impedance will cause a significant voltage drop at the positive-sequence grid connection point. Conversely, excessive injection of negative-sequence virtual impedance will lead to an increase in the negative-sequence grid connection point voltage.

[0034] When an asymmetrical fault occurs, in order to keep the system operating within a safe range, the virtual impedance should not be too small, otherwise it will not be able to effectively suppress overcurrent; nor should it be too large, so as not to affect the voltage support effect.

[0035] Step 3: Design the impedance ratio of the virtual impedance during asymmetric faults to limit the maximum phase current of the grid-connected inverter output within the set current limit, thereby limiting the overcurrent output of the grid-connected inverter. Under symmetrical fault conditions, the virtual impedance value is determined based on the threshold current and the maximum current limit: (5), in, This indicates the maximum phase current amplitude output by the inverter. The overcurrent threshold representing the triggering virtual impedance, This represents the virtual impedance gain coefficient, which is applied when the inverter output current exceeds... At that time, the virtual impedance should be activated. It is the ratio of virtual resistance to virtual reactance.

[0036] Under asymmetrical faults, this is extended to positive and negative sequence virtual impedances: (6), (7), In the formula, and These are the positive-sequence virtual resistance and virtual reactance, respectively. and These are the negative-sequence virtual resistance and virtual reactance, respectively. and These are the positive and negative sequence virtual impedance gain coefficients, respectively. and These represent the ratios of positive and negative sequence virtual resistance to virtual reactance, respectively.

[0037] By introducing positive and negative sequence virtual impedances, the relationship between the inverter's equivalent port voltage reference value, internal potential reference value, and output current in the dq rotating coordinate system can be derived: (8), In the formula, , These are the reference values ​​for the positive sequence voltages along the d and q axes of the voltage loop, respectively. , These are the negative sequence voltage reference values ​​for the d-axis and q-axis of the voltage loop, respectively. and These are the d-axis and q-axis components of the positive-sequence virtual internal potential, respectively. and These are the d-axis and q-axis components of the negative-sequence virtual internal potential, respectively. , These are the positive sequence current components along the d and q axes, respectively. , These are the negative sequence current components along the d and q axes, respectively.

[0038] Step 4: Provide the phasor diagram of the positive and negative sequence networks under asymmetrical faults. Based on the set positive and negative sequence voltage amplitudes, calculate the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection point. Specifically, the steps include the following: Step 401: Based on the relationship between the positive and negative sequence voltages at the grid connection point and the line impedance, the positive and negative sequence virtual impedances and the line impedance, and combined with the geometric relationship in the phasor diagram, the phasor diagrams of the positive and negative sequence networks are obtained. according to Figure 3 As shown in (a), the phase of the positive-sequence grid-connected voltage lags behind the phase of the inverter's internal electromotive force and leads the phase of the positive-sequence grid-side voltage; according to Figure 3As shown in (b), the phase of the negative sequence grid connection point voltage leads the phase of the negative sequence grid-side voltage. Since the amplitudes of the positive sequence current and the negative sequence current remain unchanged, the voltage drop amplitudes across the positive sequence and negative sequence line impedances remain unchanged. Therefore, the changes in voltage drop across the positive sequence and negative sequence line impedances can be represented by a circle, thus obtaining the complete phasor relationship diagrams of the positive sequence and negative sequence networks. Figure 4 In the diagrams (a) and (b), the phasor relationships of the positive-order and negative-order networks are shown respectively.

[0039] Step 402: Set the positive sequence and negative sequence voltage amplitudes respectively, and make them equal to the positive sequence and negative sequence voltages at the grid connection point, so as to obtain the amplitudes of the corresponding positive sequence and negative sequence virtual impedances, and then obtain the values ​​of the positive and negative sequence virtual resistance and virtual reactance.

[0040] definition and Let be the voltage drops across the positive-sequence and negative-sequence virtual impedances, respectively, and define them respectively. and This represents the voltage drop across the positive and negative sequence line impedances.

[0041] Will and Set the positive and negative sequence voltage values ​​respectively. and According to the phasor diagram, we can obtain: , , in, φ + for The angle between the voltage drop and the total impedance can be obtained from the geometric relationships of the phasor diagram. φ + The expression: , , , in, for The angle between the voltage drop and the total impedance.

[0042] Furthermore, the values ​​of the positive-sequence and negative-sequence virtual resistances can be derived: , , Furthermore, by setting the positive and negative sequence virtual impedance values ​​according to the above formula, the positive and negative sequence voltage values ​​at the grid connection point can be controlled to the set values ​​during asymmetrical faults, thus achieving the goal of precise control of the positive and negative sequence grid connection point voltages.

[0043] Step 5: Combine the values ​​of positive and negative sequence virtual impedances to obtain the maximum voltage support range of the grid-connected inverter during asymmetrical faults, so as to realize positive and negative sequence voltage control at the grid connection point.

[0044] Depend on Figure 4 It can be concluded that, due to the impedance characteristics presented by the virtual impedance and the grid-side impedance, the supported range of positive and negative sequence voltages is limited, that is, the set value of the positive and negative sequence voltages is limited. and The settings are within a range; furthermore, the support range of positive and negative sequence voltages differs for different types and severity of asymmetrical faults. In this embodiment, the boundary values ​​of the positive and negative sequence voltages under virtual impedance control are set to determine the support range of the positive and negative sequence voltages.

[0045] Figure 5 This is a schematic diagram for setting the boundary values ​​of the positive sequence voltage. Assuming the equivalent impedance of the line is inductive after the positive sequence virtual impedance is applied, the output current is... After the positive-sequence virtual impedance is applied, when the equivalent impedance of the line is resistive, the output current is... . φ This is the line impedance angle. Therefore, the setting value for the positive sequence voltage support range falls into two categories. Figure 5 (a) is φ< At that time, the support range of the positive sequence voltage cannot cover the grid-side positive sequence voltage. At this time, the maximum and minimum values ​​of the positive sequence voltage are shown in the figure. , ; Figure 5 (b) is φ> At that time, the support range of the positive sequence voltage can cover the grid-side positive sequence voltage. At this time, the minimum value of the positive sequence voltage is shown in the figure. The maximum value is , The larger value in the range. In summary, the final setting value for the positive sequence voltage support range can be written as: , Figure 6 This is a schematic diagram for setting the boundary values ​​of the negative sequence voltage. Assuming the negative sequence virtual impedance is applied and the equivalent impedance of the line is inductive, the output current is... After the negative-sequence virtual impedance is applied, when the equivalent impedance of the line is resistive, the output current is... At this moment, regardless of φ What value should be chosen so that the negative sequence voltage support range can always cover the grid-side negative sequence voltage? The final setting value for the negative sequence voltage support range can be written as: , To verify the effectiveness of the precise voltage support method for low-voltage ride-through during asymmetrical faults in grid-connected inverters proposed in this invention, a two-phase asymmetrical fault (phases a and b) occurs at t1=1s, drops to 0.3pu, and is cleared at t2=2s. The simulation model is then configured to... and The values ​​are 0.75 pu and 0.1 pu, respectively. Observe the output three-phase current and the positive and negative sequence voltage support at the grid connection point.

[0046] First, based on the conclusion of step 5, it can be concluded that the positive sequence voltage of this grid-type inverter supports a range of 0.60-0.85 pu, and the negative sequence voltage supports a range of 0.08-0.15 pu.

[0047] Figure 7 In Figure (a), the three-phase current waveform of the grid-connected inverter is shown. It can be seen that when a fault occurs, the current is limited to less than 1.5 pu, thus achieving current limiting. Figure 7 In Figure (b), the output waveforms of the positive and negative sequence voltages at the grid connection point of the grid-connected inverter are shown. It can be seen that when a fault occurs, the positive and negative sequence voltages are controlled to 0.75pu and 0.1pu, respectively, which means that precise control of the positive and negative sequence voltages is achieved.

[0048] Example 2 This embodiment provides a low-voltage ride-through control system applicable to asymmetric fault grid-type inverters, including: Impedance simulation module, which is used for modeling grid-connected inverter equipment and introducing a virtual impedance control loop into the reactive-voltage loop of the grid-connected inverter to simulate the stator impedance in a virtual synchronous generator; The virtual impedance analysis module is used to construct positive and negative sequence equivalent circuit diagrams using the positive and negative sequence separation method, and analyze the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltages based on the negative sequence equivalent circuit diagram. The current limiting module is used to design the impedance ratio of the virtual impedance during asymmetrical faults, limiting the maximum phase current of the grid-connected inverter output within the set current limit, thus limiting the overcurrent of the grid-connected inverter output. The impedance calculation module is used to provide the phasor diagram of the positive and negative sequence networks under asymmetrical faults, set the positive and negative sequence voltage amplitudes, and calculate the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection point. The control strategy output module is used to combine the values ​​of positive and negative sequence virtual impedances to obtain the maximum voltage support range of the grid-connected inverter during asymmetrical faults, so as to realize positive and negative sequence voltage control at the grid connection point.

[0049] It should be noted that the specific implementation of the low voltage ride-through control system for grid-connected inverters with asymmetric faults in this embodiment of the invention is similar to the specific implementation of the low voltage ride-through control method for grid-connected inverters with asymmetric faults in this embodiment of the invention. For details, please refer to the description in the method section. To reduce redundancy, it will not be repeated here.

[0050] Example 3 This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in the low-voltage ride-through control method for asymmetric fault grid-type inverters as described above.

[0051] Example 4 This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps in the low voltage ride-through control method for asymmetric fault grid-type inverters as described above.

[0052] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0053] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0054] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0055] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0056] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-voltage ride-through control method applicable to asymmetrical fault grid-type inverters, characterized in that, Includes the following steps: Model the grid-type inverter equipment and introduce a virtual impedance control loop into the reactive-voltage loop of the grid-type inverter to simulate the stator impedance in the virtual synchronous generator; Using the positive and negative sequence separation method, we construct the positive and negative sequence equivalent circuit diagrams. Based on the negative sequence equivalent circuit diagram, we analyze the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltages. During asymmetric faults, the impedance ratio of the virtual impedance is designed to limit the maximum phase current of the grid-connected inverter output within the set current limit, thereby limiting the overcurrent output of the grid-connected inverter. The phasor diagram of the positive and negative sequence network under asymmetric fault is given. The positive and negative sequence voltage amplitudes are set, and the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection point are calculated respectively. By combining the values ​​of positive and negative sequence virtual impedances, the maximum voltage support range of the grid-connected inverter during asymmetrical faults can be obtained, so as to realize positive and negative sequence voltage control at the grid connection point. By setting the positive and negative sequence virtual impedance values, the positive and negative sequence voltage values ​​at the grid connection point are controlled to the set values ​​during asymmetrical faults, thus achieving the goal of precise control of the positive and negative sequence grid connection point voltages. The calculation process for the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection point includes: Based on the relationship between the positive and negative sequence voltages at the grid connection point and the line impedance, as well as the positive and negative sequence virtual impedances and the line impedance, and combined with the geometric relationship in the phasor diagram, the phasor diagrams of the positive and negative sequence networks are derived. Set the amplitudes of the positive-sequence and negative-sequence voltages respectively, and make them equal to the positive-sequence and negative-sequence voltages at the grid connection point. Then, obtain the amplitudes of the corresponding positive-sequence and negative-sequence virtual impedances, and consequently, the values ​​of the positive-sequence and negative-sequence virtual resistances and reactances. The calculation formula is as follows: ， ， ， ， ， ， ， in, and These are the values ​​of the positive-sequence and negative-sequence virtual resistors. and These are positive-sequence virtual reactance and negative-sequence virtual reactance, respectively. and Set the positive and negative sequence voltage values ​​respectively. and , φ + for The angle between the voltage drop and the total impedance. for The angle between the voltage drop and the total impedance. , These represent the positive-sequence and negative-sequence output currents, respectively. This is the internal electromotive force of the inverter. For line impedance, This is the positive sequence grid-side voltage; Specifically, by combining the values ​​of positive and negative sequence virtual impedances, the maximum voltage support range of the grid-connected inverter during asymmetrical faults is obtained, in order to achieve positive and negative sequence voltage control at the grid connection point, including: The calculation process for the setting value of the positive sequence voltage support range includes: Assuming the positive-sequence virtual impedance is applied, and the equivalent impedance of the line is inductive, the output current is... After the positive-sequence virtual impedance is applied, when the equivalent impedance of the line is resistive, the output current is... , φ The setting value for the positive sequence voltage support range, which is the line impedance angle, falls into two categories. φ< At that time, the support range of the positive sequence voltage cannot cover the grid-side positive sequence voltage. At this time, the maximum and minimum values ​​of the positive sequence voltage are... , , φ> At that time, the support range of the positive sequence voltage can cover the grid-side positive sequence voltage. At this time, the minimum value of the positive sequence voltage is The maximum value is , The largest value in the middle, ， The calculation process for the setting value of the negative sequence voltage support range includes: Assuming the negative-sequence virtual impedance is applied, and the equivalent impedance of the line is inductive, the output current is... After the negative-sequence virtual impedance is applied, when the equivalent impedance of the line is resistive, the output current is... At this time, regardless of φ What value should be chosen so that the negative sequence voltage support range can always cover the grid-side negative sequence voltage? The setting value for the negative sequence voltage support range is written as: 。 2. The low-voltage ride-through control method for asymmetric fault grid-type inverters as described in claim 1, characterized in that, The control loop that introduces virtual impedance into the reactive power-voltage loop of the grid-connected inverter specifically involves: activating the virtual impedance when a fault occurs. The activation method is to modify the reference voltage value before the voltage-current dual closed loop, satisfying the following: ， In the formula, , These are the reference values ​​for the d-axis and q-axis voltages of the voltage loop, respectively. and These are the d-axis and q-axis components of the virtual internal potential, respectively. , These are the d-axis and q-axis current components, respectively. For virtual resistance, This is a virtual reactance.

3. The low-voltage ride-through control method for asymmetric fault grid-type inverters as described in claim 1, characterized in that, The analysis of the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltage based on the negative sequence equivalent circuit diagram includes: extending the virtual impedance to positive and negative sequence virtual impedance, combining the equivalent positive and negative sequence network to calculate the value of positive and negative sequence output current, and then obtaining the positive and negative sequence voltage at the grid connection point.

4. The low-voltage ride-through control method for asymmetrical fault grid-type inverters as described in claim 3, characterized in that, The formulas for calculating the positive and negative sequence voltages at the grid connection point are: ， ， in, , These are the positive-sequence and negative-sequence grid connection point voltages, respectively. , These are the positive-sequence and negative-sequence grid-side voltages, respectively. , These represent the positive-sequence and negative-sequence output currents, respectively. Z is the internal electromotive force of the inverter. g For line impedance, , These are the positive-sequence and negative-sequence virtual impedances, respectively.

5. The low-voltage ride-through control method for asymmetrical fault grid-type inverters as described in claim 1, characterized in that, The positive and negative sequence virtual impedances for limiting overcurrent at the output of a grid-connected inverter are expressed as follows: ， ， in, and These are the positive-sequence virtual resistance and virtual reactance, respectively. and These are the negative-sequence virtual resistance and virtual reactance, respectively. and These are the positive and negative sequence virtual impedance gain coefficients, respectively. and These are the ratios of positive and negative sequence virtual resistance to virtual reactance, respectively. This indicates the maximum phase current amplitude output by the inverter. This represents the overcurrent threshold that triggers the virtual impedance.

6. A low-voltage ride-through control system for inverters with asymmetrical fault grids, characterized in that, The method for implementing the low-voltage ride-through control of an inverter with an asymmetric fault grid as described in any one of claims 1-5 includes: Impedance simulation module, which is used for modeling grid-connected inverter equipment and introducing a virtual impedance control loop into the reactive-voltage loop of the grid-connected inverter to simulate the stator impedance in a virtual synchronous generator; The virtual impedance analysis module is used to construct positive and negative sequence equivalent circuit diagrams using the positive and negative sequence separation method, and analyze the impact of virtual impedance on current limiting and positive and negative sequence grid connection point voltages based on the negative sequence equivalent circuit diagram. The current limiting module is used to design the impedance ratio of the virtual impedance during asymmetrical faults, limiting the maximum phase current of the grid-connected inverter output within the set current limit, thus limiting the overcurrent of the grid-connected inverter output. The impedance calculation module is used to provide the phasor diagram of the positive and negative sequence networks under asymmetrical faults, set the positive and negative sequence voltage amplitudes, and calculate the values ​​of the positive and negative sequence virtual impedances required to support the positive and negative sequence voltages at the grid connection point. The control strategy output module is used to combine the values ​​of positive and negative sequence virtual impedances to obtain the maximum voltage support range of the grid-connected inverter during asymmetrical faults, so as to realize positive and negative sequence voltage control at the grid connection point.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the steps in the applicable low-voltage ride-through control method for asymmetric fault grid-type inverters as described in any one of claims 1-5.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the applicable low-voltage ride-through control method for asymmetric fault grid-type inverters as described in any one of claims 1-5.

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