Phase interpolator linearity calibration system, method and chip

Abstract

The present application relates to a kind of phase interpolator linearity calibration system, method and chip.The phase interpolator linearity calibration system includes phase interpolator, amplitude detection unit and loop filter;Phase interpolator is connected first clock signal end, second clock signal end, digital control end, for generating differential clock signal according to the first clock signal received, second clock signal and digital control code;Amplitude detection unit is connected the output end of phase interpolator, for generating amplitude detection signal according to differential clock signal;Loop filter is connected between the output end of amplitude detection unit and the phase calibration control end of phase interpolator, for generating phase calibration control voltage according to amplitude detection signal, and phase calibration control voltage is used to control the transmission characteristic of phase interpolator.The present application technical scheme can calibrate the weight that influences phase interpolator, and the linearity between the phase of differential clock signal output by phase interpolator and digital control code can be effectively calibrated.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a phase interpolator linearity calibration system, method, and chip. Background Technology

[0002] Phase interpolators are key modules in digital or analog mixed-signal circuits, generating a controllable intermediate phase between two input clock signals. The main working principle of a phase interpolator is to adjust the weight ratio of the two input clock signals to achieve continuously adjustable output phase. For example, if 0° and 90° clocks are input, the phase interpolator can output any phase between 0° and 90°. It is primarily used in high-speed digital interfaces and clock management systems, including serializer / deserializers (SerDes), memory interfaces, and optical communication systems. In SerDes, phase interpolators dynamically adjust the sampling clock phase to align with the center of the data eye diagram; in memory interfaces, they compensate for process, voltage, and temperature (PVT) deviations to ensure signal synchronization; in optical communication, they assist coherent receivers in recovering the phase of the optical signal. Furthermore, artificial intelligence (AI) chips and 3D integrated circuits (3D ICs) also utilize phase interpolators to optimize cross-module timing.

[0003] Nonlinearity in phase interpolators refers to the deviation between their output phase and the ideal linear interpolation. That is, when the control code changes uniformly, the actual output phase is not strictly evenly distributed, but exhibits curved or abrupt characteristics. In high-speed systems, nonlinearity significantly reduces the accuracy of phase interpolators. For example, in the Clock Data Recovery (CDR) stage of SerDes, nonlinearity may cause the sampling clock to deviate from the center of the data eye diagram, increasing the bit error rate. In All Digital Phase-Locked Loops (ADPLLs), nonlinearity introduces additional phase jitter, deteriorating the timing stability of the clock signal. In multi-channel parallel systems, nonlinearity can also cause phase inconsistencies between channels, disrupting signal synchronization. Summary of the Invention

[0004] To address the nonlinearity problem of phase interpolators in existing technologies, this invention provides a phase interpolator linearity calibration system, method, and chip.

[0005] The phase interpolator linearity calibration system provided by this invention generates an amplitude detection signal based on the differential clock signal generated by the phase interpolator through an amplitude detection unit. This signal reflects the output amplitude deviation caused by nonlinearity. A loop filter then generates a phase calibration control voltage based on this amplitude detection signal. This phase calibration control voltage is used to control the transmission characteristics of the phase interpolator, thereby calibrating the weights affecting the phase interpolator and effectively calibrating the linearity between the phase of the differential clock signal output by the phase interpolator and the digital control code.

[0006] To achieve the above objectives, the first aspect of the present invention provides a phase interpolator linearity calibration system, comprising: a phase interpolator, an amplitude detection unit, and a loop filter; The phase interpolator is connected to a first clock signal terminal, a second clock signal terminal, and a digital control terminal, and is used to generate a differential clock signal based on the received first clock signal, second clock signal, and digital control code. The amplitude detection unit is connected to the output of the phase interpolator and is used to generate an amplitude detection signal based on the differential clock signal. The loop filter is connected between the output of the amplitude detection unit and the phase calibration control terminal of the phase interpolator, and is used to generate a phase calibration control voltage based on the amplitude detection signal. The phase calibration control voltage is used to control the transmission characteristics of the phase interpolator to calibrate the linearity between the phase of the differential clock signal output by the phase interpolator and the digital control code.

[0007] In one possible implementation of the first aspect, the amplitude detection unit includes a signal detection path and a reference path; the input of the signal detection path is connected to the output of the phase interpolator to receive the differential clock signal, and the output of the signal detection path is connected to the first input of the loop filter; the signal detection path is used to generate a detection voltage signal based on the differential clock signal; the input of the reference path is connected to a reference voltage input to receive a reference voltage signal, and the output of the reference path is connected to the second input of the loop filter; the reference path is used to generate a reference voltage signal based on the reference voltage signal; the amplitude detection signal is generated based on the comparison result between the detection voltage signal and the reference voltage signal.

[0008] By setting up a signal detection path and a reference path, the amplitude detection signal can be generated based on the comparison between the detected voltage signal and the reference voltage signal. This enables real-time comparison of the instantaneous output state of the phase interpolator with a stable reference, thereby accurately and reliably generating an amplitude detection signal characterizing its nonlinear deviation, providing precise error input for closed-loop calibration.

[0009] In one possible implementation of the first aspect, the signal detection path includes a first differential pair, the two gates of the first differential pair forming the input terminal of the signal detection path for receiving the differential clock signal; the source of the first differential pair is connected to a first tail current source.

[0010] By employing a first differential pair to receive the differential clock signal and using a first tail current source to provide bias, a highly linear and common-mode interference-resistant input stage is constructed for the signal detection path. This ensures that the detected voltage signal can effectively reflect the amplitude information of the differential clock signal, providing the original signal for subsequent comparison stages and improving the accuracy and reliability of the entire detection link.

[0011] In one possible implementation of the first aspect, the reference path includes a second differential pair, both gates of which are connected to the reference voltage input terminal for receiving the reference voltage signal; the source of the second differential pair is connected to a second tail current source.

[0012] A reference path is formed by using a second differential pair to receive the reference voltage signal and providing bias through a second tail current source. The structure where both gates of the second differential pair are connected to the reference voltage input allows for stable handling of common-mode voltage, generating a low-noise, highly stable reference voltage signal. The symmetry of this design with the signal detection path ensures the accuracy of the comparison reference, thereby improving the precision of the amplitude detection signal.

[0013] In one possible implementation of the first aspect, the loop filter includes an operational amplifier, an integrating resistor, and an integrating capacitor; the signal detection path includes a first resistor; the reference path includes a second resistor; the inverting input of the operational amplifier serves as the first input of the loop filter and is connected to the common source node of the first differential pair via the integrating resistor and the first resistor; the non-inverting input of the operational amplifier serves as the second input of the loop filter and is connected to the common source node of the second differential pair via the second resistor; and the integrating capacitor is connected between the output of the operational amplifier and the inverting input of the operational amplifier.

[0014] An integrator, consisting of an operational amplifier, integrating resistors, and integrating capacitors, is used as a loop filter. The specific circuit connections are defined: the inverting input of the operational amplifier is connected to the common-source node of the first differential pair via the integrating resistor and a first resistor; the non-inverting input is connected to the common-source node of the second differential pair via a second resistor. This integrator structure can filter and integrate the amplitude detection signal, generating a smooth phase calibration control voltage, ensuring the stability and accuracy of phase calibration.

[0015] In one possible implementation of the first aspect, the signal detection path further includes a first capacitor, and the reference path further includes a second capacitor; one end of the first capacitor is connected between the first resistor and the integrating resistor, and the other end of the first capacitor is grounded; one end of the second capacitor is connected between the second resistor and the non-inverting input terminal, and the other end of the second capacitor is grounded.

[0016] By setting a first capacitor in the signal detection path and a second capacitor in the reference path, the first capacitor and the first resistor form a low-pass filter network, and the second capacitor and the second resistor also form a low-pass filter network. This can effectively filter out high-frequency noise and harmonic components in the differential clock signal, making the phase calibration control voltage reaching the loop filter purer and reducing the interference of noise on the phase calibration control voltage, thereby improving the noise immunity and robustness of the entire calibration system.

[0017] In one possible implementation of the first aspect, the phase interpolator includes multiple current units connected in parallel; each current unit includes a switching transistor, a digital selection switch, a main tail current source, and a calibration current source; the control terminal of the switching transistor is connected to either the first clock signal terminal or the second clock signal terminal to receive the first clock signal or the second clock signal; the digital selection switch is connected to the current output terminal of the switching transistor to control the on / off state of the current unit; the main tail current source and the calibration current source are connected in parallel and then connected to the digital selection switch; the control terminal of the calibration current source is connected to the phase calibration control terminal to receive the phase calibration control voltage.

[0018] By incorporating multiple parallel current units—comprising switching transistors, digital selection switches, main and tail current sources, and calibration current sources—within the phase interpolator, and designing the control terminal of the calibration current source to receive the phase calibration control voltage, the phase calibration control voltage can directly adjust the current of the calibration current source in each current unit. This allows for continuous and precise adjustment of the phase interpolator's transmission characteristics, providing a crucial and operable electrical adjustment mechanism for achieving high-precision linearity calibration.

[0019] In a second aspect, the present invention provides a phase interpolator linearity calibration method, applicable to a phase interpolator linearity calibration system as described in the first aspect and any possible implementation thereof, the method comprising: A differential clock signal is generated by a phase interpolator based on the received first clock signal, second clock signal, and digital control code. An amplitude detection signal is generated by the amplitude detection unit based on the differential clock signal; A phase calibration control voltage is generated based on the amplitude detection signal by a loop filter. The phase calibration control voltage is used to control the transmission characteristics of the phase interpolator in order to calibrate the linearity between the phase of the differential clock signal output by the phase interpolator and the digital control code.

[0020] In one possible implementation of the second aspect, generating the amplitude detection signal based on the differential clock signal includes: A detection voltage signal is generated based on the differential clock signal through a signal detection path; A reference voltage signal is generated based on the reference voltage signal through a reference reference path; The amplitude detection signal is generated based on the comparison result between the detected voltage signal and the reference voltage signal.

[0021] This allows for the accurate and reliable extraction of error components that are only related to the nonlinearity of the phase interpolator. This provides a high-precision, low-noise error input for phase calibration.

[0022] Thirdly, the present invention provides a chip including a phase interpolator linearity calibration system as described in the first aspect and any possible implementation thereof.

[0023] The chip provided by this invention integrates a phase interpolator linearity calibration system as described in the first aspect and any possible implementation thereof, enabling the built-in phase interpolator to achieve closed-loop, automatic linearity calibration. This improves the performance of the chip's internal clock management or high-speed data interface. Specifically, it ensures a highly linear relationship between the phase of the clock signal output by the phase interpolator and the digital control code, thereby reducing clock timing errors and data error rates, and enhancing adaptability to process variations, voltage fluctuations, and temperature changes. This results in superior signal integrity, timing stability, and overall reliability when performing high-speed, high-performance computation and communication.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows: The phase interpolator linearity calibration system provided by this invention constructs a closed-loop feedback architecture comprising a phase interpolator, an amplitude detection unit, and a loop filter. The amplitude detection unit generates an amplitude detection signal based on the differential clock signal generated by the phase interpolator. This signal reflects the output amplitude deviation caused by nonlinearity. The loop filter then generates a phase calibration control voltage based on this amplitude detection signal. This phase calibration control voltage is used to control the transmission characteristics of the phase interpolator, thereby calibrating the weights affecting the phase interpolator and effectively calibrating the linearity between the phase of the differential clock signal output by the phase interpolator and the digital control code. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This demonstrates the theoretical principle of uniform phase segmentation by a phase interpolator; Figure 2 A circuit diagram of a conventional phase interpolator is shown. Figure 3 This illustrates the phenomenon of non-uniform phase segmentation by the phase interpolator in the physical implementation; Figure 4 According to some embodiments of the present invention, an architecture for a phase interpolator linearity calibration system is shown; Figure 5 According to some embodiments of the present invention, a circuit diagram of an amplitude detection unit and a loop filter is shown; Figure 6 According to some embodiments of the present invention, a circuit diagram of a current source in a phase interpolator is shown; Figure 7 According to some embodiments of the present invention, a flowchart of a bit interpolator linearity calibration method is shown; Figure 8 According to some embodiments of the present invention, a chip architecture is shown. Detailed Implementation

[0027] Illustrative embodiments of the present invention include, but are not limited to, a phase interpolator linearity calibration system, method, and chip.

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] To facilitate understanding of the technical solution of this invention, the following first combines... Figures 1 to 3 The problems with the existing technology are explained in detail.

[0030] An ideal phase interpolator should generate a clock with a specific phase. .in, It is the angular frequency of the input clock of the phase interpolator. Let clk1 be the phase difference between the generated clock and the reference clock. Using the law of sines to decompose clk1, we can obtain... Therefore, given a pair of quadrature clocks, their weighted sum can be used to obtain a clock with any phase difference between them. The coefficients for the I and Q paths are respectively... and sin( t) and cos( t) is a pair of quadrature input clocks with a 90-degree phase difference. Typically, the input sin( The path of the clock (t) is called the I-path, which takes the input cos( The clock path is called the Q-path. The I-path and Q-path refer to the two input clock channels of the phase interpolator. The I-path typically corresponds to a 0° phase clock, and the Q-path corresponds to a 90° phase clock. An ideal phase interpolator should achieve a uniform division of the clock phase, such as... Figure 1 As shown, Figure 1 The quarter-circle in the diagram is marked with multiple equally spaced output clocks. Each output clock is obtained by weighted summation of the I-channel clock and the Q-channel clock. The weighting coefficients of the I-channel clock and the Q-channel clock (hereinafter also referred to as weight values) correspond to the cosine and sine values ​​of the corresponding phases, respectively, achieving uniform phase division from 0° to 90°.

[0031] However, in actual circuit design, it is difficult to generate a set of... and The physical quantities are used as weights for the I-channel clock and Q-channel clock. Traditional circuit design, such as... Figure 2 As shown, an integer number of clock cycles are generated using a current-to-analog converter (DAC) for summation. Figure 2 It consists of two sets of slices, each with M=16. Figure 2 The left side shows 16 slices with 0° clock information. Figure 2 The right side shows 16 slices with 90° clock information. If n slices are opened on the left, then (Mn) slices are opened on the right, and the two are combined across the load resistor to form a new clock with a phase of n*0° + (16-n)*90°. Therefore, the simplification of the PI mathematical model in existing practical circuit implementations results in the non-ideal characteristic that the phase shift corresponding to each scale of the PI is different. Figure 3 As shown, in practical digital phase converters, the phase shift per cycle is smaller closer to the I / Q clock, while it is larger further away from the I / Q clock. This is the core reason for the nonlinearity of the phase interpolator.

[0032] As mentioned earlier, existing phase interpolators cannot accurately reproduce the ideal weight values ​​due to their circuit implementation, resulting in non-uniformly distributed output phases when the control code changes uniformly, leading to nonlinear deviations.

[0033] In view of this, embodiments of the present invention provide a phase interpolator linearity calibration system. Specifically, the phase interpolator linearity calibration system provided by the present invention generates an amplitude detection signal based on the differential clock signal generated by the phase interpolator through an amplitude detection unit. This signal reflects the output amplitude deviation caused by nonlinearity. A loop filter then generates a phase calibration control voltage based on the amplitude detection signal, and uses this phase calibration control voltage to control the transmission characteristics of the phase interpolator. This allows for the calibration of the weights affecting the phase interpolator, effectively calibrating the linearity between the phase of the differential clock signal output by the phase interpolator and the digital control code.

[0034] Figure 4 According to some embodiments of the present invention, an architecture of a phase interpolator linearity calibration system 100 is shown, with reference to Figure 4 The present invention provides a phase interpolator linearity calibration system 100, comprising a phase interpolator 10, an amplitude detection unit 30, and a loop filter 20. The phase interpolator 10 is connected to a first clock signal terminal 40, a second clock signal terminal 50, and a digital control terminal 60, and is used to generate a differential clock signal based on the received first clock signal, second clock signal, and digital control code. The amplitude detection unit 30 is connected to the output terminal 11 of the phase interpolator 10 and is used to generate an amplitude detection signal based on the differential clock signal. The loop filter 20 is connected between the output terminal of the amplitude detection unit 30 and the phase calibration control terminal 12 of the phase interpolator 10, and is used to generate a phase calibration control voltage based on the amplitude detection signal. The phase calibration control voltage is used to control the transmission characteristics of the phase interpolator 10 to calibrate the linearity between the phase of the differential clock signal output by the phase interpolator 10 and the digital control code.

[0035] Figure 5 According to some embodiments of the present invention, a circuit diagram of an amplitude detection unit 30 and a loop filter 20 is shown. (See reference) Figure 5The amplitude detection unit 30 includes a signal detection path 31 and a reference path 32. The input terminal 311 of the signal detection path 31 is connected to the output terminal 11 of the phase interpolator 10 to receive a differential clock signal. The output terminal 312 of the signal detection path 31 is connected to the first input terminal 211 of the loop filter 20. The signal detection path 31 is used to generate a detection voltage signal based on the differential clock signal. The input terminal 321 of the reference path 32 is connected to a reference voltage input terminal (not shown in the figure) to receive a reference voltage signal Vref. The output terminal 322 of the reference path 32 is connected to the second input terminal 212 of the loop filter 20. The reference path 32 is used to generate a reference voltage signal based on the reference voltage signal. The amplitude detection signal is generated based on the comparison result between the detection voltage signal and the reference voltage signal. By setting the signal detection path 31 and the reference path 32, the amplitude detection signal can be generated based on the comparison result between the detection voltage signal and the reference voltage signal. The instantaneous output state of the phase interpolator 10 is compared with a stable reference in real time, thereby accurately and reliably generating an amplitude detection signal that characterizes its nonlinear deviation, providing a precise error input for closed-loop calibration.

[0036] refer to Figure 5 The signal detection path 31 includes a first differential pair 313. The two gates of the first differential pair 313 form the input terminal 311 of the signal detection path 31, used to receive the differential clock signal. The source of the first differential pair 313 is connected to a first tail current source 314. By using the first differential pair 313 to receive the differential clock signal and the first tail current source 314 to provide bias, a highly linear and common-mode interference resistant input stage is formed for the signal detection path 31. This ensures that the detected voltage signal can effectively reflect the amplitude information of the differential clock signal, providing the original signal for the subsequent comparison stage and improving the accuracy and reliability of the entire detection link.

[0037] The reference path 32 includes a second differential pair 323, both gates of which are connected to a reference voltage input (not shown) to receive the reference voltage signal Vref; the source of the second differential pair 323 is connected to a second tail current source 324. By using the second differential pair 323 to receive the reference voltage signal and the second tail current source 324 to provide bias, the reference path 32 is formed. The structure of both gates of the second differential pair 323 being connected to the reference voltage input allows it to stably handle common-mode voltage, generating a low-noise, highly stable reference voltage signal. The symmetry of this design with the signal detection path 31 ensures the accuracy of the comparison reference, thereby improving the accuracy of the amplitude detection signal.

[0038] exist Figure 5In the illustrated embodiment, the loop filter 20 includes an operational amplifier 21, an integrating resistor R0, and an integrating capacitor C0. The signal detection path 31 includes a first resistor R1, and the reference path 32 includes a second resistor R2. The inverting input terminal 213 of the operational amplifier 21 serves as the first input terminal of the loop filter 20 and is connected to the common source node 315 of the first differential pair 313 through the integrating resistor R0 and the first resistor R1. The non-inverting input terminal 214 of the operational amplifier 21 serves as the second input terminal of the loop filter 20 and is connected to the common source node 325 of the second differential pair 323 through the second resistor R2. The integrating capacitor C0 is connected between the output terminal 215 of the operational amplifier 21 and the inverting input terminal 213 of the operational amplifier 21. An integrator, consisting of operational amplifier 21, integrating resistor R0, and integrating capacitor C0, serves as a loop filter 20. The circuit connections are clearly defined: the inverting input 213 of operational amplifier 21 is connected to the common-source node 315 of the first differential pair 313 via integrating resistor R0 and a first resistor R1; the non-inverting input 214 is connected to the common-source node 325 of the second differential pair 323 via a second resistor R2. This integrator structure filters and integrates the amplitude detection signal, generating a smooth phase calibration control voltage, ensuring the stability and accuracy of phase calibration.

[0039] refer to Figure 5 The signal detection path 31 also includes a first capacitor C1, and the reference path 32 includes a second capacitor C2. One end of the first capacitor C1 is connected between the first resistor R1 and the integrating resistor R0, and the other end of the first capacitor C1 is grounded. One end of the second capacitor C2 is connected between the second resistor R2 and the non-inverting input terminal 214, and the other end of the second capacitor C2 is grounded. By setting the first capacitor C1 in the signal detection path 31 and the second capacitor C2 in the reference path 32, the first capacitor C1 and the first resistor R1 form a low-pass filter network, and the second capacitor C2 and the second resistor R2 also form a low-pass filter network. This can effectively filter out high-frequency noise and harmonic components in the differential clock signal, making the phase calibration control voltage reaching the loop filter 20 purer, reducing the interference of noise on the phase calibration control voltage, and thus improving the noise immunity and robustness of the entire calibration system.

[0040] In some embodiments, the phase interpolator 10 includes a plurality of current units 13 connected in parallel. Figure 6 According to some embodiments of the present invention, a circuit diagram of a current unit 13 is shown, with reference to... Figure 6The current unit 13 includes a switching transistor 131, a digital selection switch 132, a main tail current source 133, and a calibration current source 134. The control terminal of the switching transistor 131 is connected to either a first clock signal terminal 40 or a second clock signal terminal 50 to receive the first or second clock signal. The digital selection switch 132 is connected to the current output terminal of the switching transistor 131 to control the on / off state of the current unit 13. The main tail current source 133 and the calibration current source 134 are connected in parallel and then connected to the digital selection switch 132. The control terminal (not shown) of the calibration current source 134 is connected to the phase calibration control terminal to receive the phase calibration control voltage. By setting multiple parallel current units 13 consisting of the switching transistor 131, the digital selection switch 132, the main tail current source 133, and the calibration current source 134 inside the phase interpolator 10, and designing the control terminal of the calibration current source 134 to receive the phase calibration control voltage, the current unit 133 is configured to receive the phase calibration control voltage. This allows the phase calibration control voltage to directly adjust the current of the calibration current source 134 in each current unit 13, thereby continuously and precisely adjusting the transmission characteristics of the phase interpolator 10, providing a key and operable electrical adjustment mechanism for achieving high-precision linearity calibration.

[0041] In summary, the phase interpolator linearity calibration system 100 provided by this invention constructs a feedback loop including a phase interpolator 10, an amplitude detection unit 30, and a loop filter 20. The amplitude detection unit 30 generates an amplitude detection signal based on the differential clock signal generated by the phase interpolator 10. This signal reflects the output amplitude deviation caused by nonlinearity. The loop filter 20 then generates a phase calibration control voltage based on this amplitude detection signal. This phase calibration control voltage is used to control the transmission characteristics of the phase interpolator 10, thereby calibrating the weights affecting the phase interpolator 10 and effectively calibrating the linearity between the phase of the differential clock signal output by the phase interpolator 10 and the digital control code.

[0042] This invention also provides a method for calibrating the linearity of a phase interpolator, applicable to, for example... Figure 4 The phase interpolator linearity calibration system 100 is shown. Figure 7 According to some embodiments of the present invention, a flowchart of a phase interpolator linearity calibration method is shown, with reference to... Figure 7 The present invention provides a method for calibrating the linearity of a phase interpolator, comprising the following steps S11 to S13: Step S11: Generate a differential clock signal using the phase interpolator 10 based on the received first clock signal, second clock signal, and digital control code.

[0043] After decoding, the digital control code generates multiple gating signals. These gating signals are respectively connected to the control terminals of the digital selection switches 132 of multiple parallel current units in the phase interpolator 10. The first clock signal and the second clock signal are a pair of quadrature clock signals, respectively connected to the control terminals of the switching transistors 131 of different current units. When the digital control code changes, the phase interpolator 10 generates differential clock signals with different intermediate phases by changing the proportion of current units turned on by the gating signals.

[0044] Step S12: Generate an amplitude detection signal based on the differential clock signal using the amplitude detection unit 30.

[0045] In signal detection path 31, the first differential pair 313 converts the differential clock signal into a voltage signal at the common-source node 315 of the first differential pair 313. The common-source node 315 of the first differential pair 313 is connected to the inverting input of the operational amplifier in loop filter 20 through a first resistor R1. In reference path 32, the second differential pair 323 converts the reference voltage signal into a voltage signal at the common-source node 325 of the second differential pair 323. The common-source node 325 of the second differential pair 323 is connected to the non-inverting input of the operational amplifier through a second resistor R2. The voltage difference received by the inverting and non-inverting inputs of the operational amplifier constitutes the amplitude detection signal.

[0046] Step S13: The loop filter 20 generates a phase calibration control voltage based on the amplitude detection signal. The phase calibration control voltage is used to control the transmission characteristics of the phase interpolator 10 to calibrate the linearity between the phase of the differential clock signal output by the phase interpolator 10 and the digital control code.

[0047] The operational amplifier, integrating resistor, and integrating capacitor in the loop filter 20 together form an integrator, which continuously integrates the amplitude detection signal and outputs a smoothly varying phase calibration control voltage. This phase calibration control voltage is applied to the control terminal of the calibration current source 134 in each current unit of the phase interpolator 10. The output current value of the calibration current source 134 changes linearly with the phase calibration control voltage, thereby continuously adjusting the total tail current of its current unit, and thus finely adjusting the overall transmission characteristics of the phase interpolator 10 to compensate for nonlinear deviations.

[0048] This invention provides a phase interpolator linearity calibration method that constructs a complete closed-loop calibration process, enabling dynamic and automatic calibration of the linearity between the phase of the differential clock signal output by the phase interpolator 10 and the digital control code. When the technical solution of this invention is applied to a CDR circuit, it can ensure that the sampling clock is accurately aligned with the center of the data eye diagram, thereby significantly reducing the bit error rate. When the technical solution of this invention is applied to multi-channel systems such as memory interfaces, it can calibrate and match the phase of each channel, ensuring signal synchronization and avoiding data conflicts. When the technical solution of this invention is applied to an all-digital phase-locked loop (ADPLL), it can eliminate deterministic phase jitter introduced by nonlinearity, thereby outputting a more stable clock signal and improving the overall timing performance of the system.

[0049] It is understood that the execution order of steps S11 to S13 above is only an illustration. In other embodiments, other execution orders may be used, and some steps may be split or combined. This is not limited here.

[0050] In some embodiments, generating an amplitude detection signal based on a differential clock signal includes: generating a detection voltage signal based on the differential clock signal via a signal detection path 31; generating a reference voltage signal based on a reference voltage signal via a reference reference path 32; and generating an amplitude detection signal based on a comparison between the detection voltage signal and the reference voltage signal. This enables accurate and reliable extraction of error components that are only nonlinearly related to the phase interpolator 10. This provides a high-precision, low-noise error input for phase calibration.

[0051] The present invention also provides a chip, such as Figure 8 As shown, the chip includes the components described above. Figure 4 The phase interpolator linearity calibration system 100 in the illustrated embodiment.

[0052] The chip provided by this invention integrates a phase interpolator linearity calibration system 100, as described in the first aspect and any possible implementation thereof, enabling the built-in phase interpolator 10 to achieve closed-loop, automatic linearity calibration. This improves the performance of the chip's internal clock management or high-speed data interface. Specifically, it ensures a highly linear relationship between the phase of the clock signal output by the phase interpolator 10 and the digital control code, thereby reducing clock timing errors and data error rates, and enhancing adaptability to process variations, voltage fluctuations, and temperature changes. This results in superior signal integrity, timing stability, and overall reliability when performing high-speed, high-performance computation and communication.

[0053] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0054] It should be noted that the units / modules mentioned in the various device embodiments of the present invention are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problem proposed by the present invention. Furthermore, to highlight the innovative aspects of the present invention, the above-described device embodiments of the present invention have not introduced units / modules that are not closely related to solving the technical problem proposed by the present invention. This does not mean that the above-described device embodiments do not contain other units / modules.

[0055] It should be noted that in the examples and description of this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0056] Although the invention has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A phase interpolator linearity calibration system, characterized in that, include: Phase interpolator, amplitude detection unit, and loop filter; The phase interpolator is connected to a first clock signal terminal, a second clock signal terminal, and a digital control terminal, and is used to generate a differential clock signal based on the received first clock signal, second clock signal, and digital control code. The amplitude detection unit is connected to the output of the phase interpolator and is used to generate an amplitude detection signal based on the differential clock signal. The loop filter is connected between the output of the amplitude detection unit and the phase calibration control terminal of the phase interpolator, and is used to generate a phase calibration control voltage according to the amplitude detection signal. The phase calibration control voltage is used to control the transmission characteristics of the phase interpolator to calibrate the linearity between the phase of the differential clock signal output by the phase interpolator and the digital control code. The phase interpolator includes multiple parallel current units; each current unit includes a switching transistor, a digital selection switch, a main tail current source, and a calibration current source; the control terminal of the switching transistor is connected to the first clock signal terminal or the second clock signal terminal, and is used to receive the first clock signal or the second clock signal. The digital selection switch is connected to the current output terminal of the switching transistor and is used to control the on / off state of the current unit. The main tail current source and the calibration current source are connected in parallel and then connected to the digital selection switch; the control terminal of the calibration current source is connected to the phase calibration control terminal to receive the phase calibration control voltage.

2. The phase interpolator linearity calibration system according to claim 1, characterized in that, The amplitude detection unit includes a signal detection path and a reference path. The input of the signal detection path is connected to the output of the phase interpolator to receive the differential clock signal, and the output of the signal detection path is connected to the first input of the loop filter. The signal detection path is used to generate a detection voltage signal based on the differential clock signal. The input of the reference path is connected to the reference voltage input to receive the reference voltage signal, and the output of the reference path is connected to the second input of the loop filter. The reference path is used to generate a reference voltage signal based on the reference voltage signal. The amplitude detection signal is generated based on the comparison result between the detected voltage signal and the reference voltage signal.

3. The phase interpolator linearity calibration system according to claim 2, characterized in that, The signal detection path includes a first differential pair, the two gates of the first differential pair constitute the input terminal of the signal detection path for receiving the differential clock signal; the source of the first differential pair is connected to a first tail current source.

4. The phase interpolator linearity calibration system according to claim 3, characterized in that, The reference path includes a second differential pair, both gates of which are connected to the reference voltage input terminal to receive the reference voltage signal; the source of the second differential pair is connected to a second tail current source.

5. The phase interpolator linearity calibration system according to claim 4, characterized in that, The loop filter includes an operational amplifier, an integrating resistor, and an integrating capacitor. The signal detection path includes a first resistor, and the reference path includes a second resistor. The inverting input of the operational amplifier serves as the first input of the loop filter and is connected to the common source node of the first differential pair through the integrating resistor and the first resistor. The non-inverting input of the operational amplifier serves as the second input of the loop filter and is connected to the common source node of the second differential pair through the second resistor. The integrating capacitor is connected between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier.

6. The phase interpolator linearity calibration system according to claim 5, characterized in that, The signal detection path further includes a first capacitor, and the reference path further includes a second capacitor; one end of the first capacitor is connected between the first resistor and the integrating resistor, and the other end of the first capacitor is grounded; one end of the second capacitor is connected between the second resistor and the non-inverting input terminal, and the other end of the second capacitor is grounded.

7. A method for calibrating the linearity of a phase interpolator, characterized in that, The method, applied to the phase interpolator linearity calibration system as described in any one of claims 1 to 6, comprises: A differential clock signal is generated by a phase interpolator based on the received first clock signal, second clock signal, and digital control code. An amplitude detection signal is generated by the amplitude detection unit based on the differential clock signal; A phase calibration control voltage is generated based on the amplitude detection signal by a loop filter. The phase calibration control voltage is used to control the transmission characteristics of the phase interpolator in order to calibrate the linearity between the phase of the differential clock signal output by the phase interpolator and the digital control code.

8. The phase interpolator linearity calibration method according to claim 7, characterized in that, The step of generating an amplitude detection signal based on the differential clock signal includes: A detection voltage signal is generated based on the differential clock signal through a signal detection path; A reference voltage signal is generated based on the reference voltage signal through a reference reference path; The amplitude detection signal is generated based on the comparison result between the detected voltage signal and the reference voltage signal.

9. A chip, characterized in that, Includes a phase interpolator linearity calibration system as described in any one of claims 1 to 6.

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