System on chip and method therefor, electronic device and storage medium

Abstract

At least one embodiment of the present disclosure provides a system on chip and a method therefor, an electronic device, and a storage medium. The system on chip includes a first group of high-speed interface subsystems including two or more high-speed interface subsystems, a first external interface for connecting to a first reference resistor, and a first connection control device configured to multiplex the first external interface by at least two of the first group of high-speed interface subsystems to separately connect a high-speed interface subsystem requiring resistance calibration among the at least two high-speed interface subsystems to the first external interface, wherein the first group of high-speed interface subsystems is located on a first die of the system on chip. The system on chip can reliably reduce the number of external interfaces of high-speed interface subsystems of the system on chip including a die for connecting a reference resistor.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuits, and more specifically, to systems-on-a-chip and methods, electronic devices, and storage media for use therein. Background Technology

[0002] A System on Chip (SOC), also known as a system-on-a-chip or SOC chip, is a highly integrated integrated circuit that integrates the core functions of an electronic system, such as a central processing unit (CPU), a graphics processing unit (GPU), memory, and various control and interface modules, into a single chip. With its advantages of high performance, small size, and low power consumption, it is widely used in various electronic products such as mobile phones, autonomous vehicles, and Internet of Things devices.

[0003] As the complexity of SOC chips increases, high-speed interface subsystems employing various types of high-speed interface technologies (such as PCIe, Universal Chip Interconnect (UCIe), Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI), Double Data Rate (DDR), etc.) are widely used to achieve efficient communication between various functional modules within the SOC chip and / or between the SOC chip and external devices. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a system-on-a-chip (SoC), characterized in that the SoC includes: a first set of high-speed interface subsystems, the first set of high-speed interface subsystems including two or more high-speed interface subsystems; a first external interface for connection to a first reference resistor; and a first connection control device configured to: multiplex at least two of the first set of high-speed interface subsystems to the first external interface, so as to individually connect the high-speed interface subsystems requiring resistance calibration in the at least two high-speed interface subsystems to the first external interface, wherein the first set of high-speed interface subsystems is located on a first die of the SoC.

[0005] For example, in at least one embodiment of this disclosure, the first connection control device is a multiplexer switch, wherein the multiplexer switch is configured to: in response to the need to perform a first resistance calibration on a first high-speed interface subsystem in at least two high-speed interface subsystems, select one of the multiplexers corresponding to the first high-speed interface subsystem to the first external interface.

[0006] For example, in at least one embodiment of this disclosure, the first connection control device is a plurality of single-channel selector switches, which are configured to correspond one-to-one with each of the at least two high-speed interface subsystems. The plurality of single-channel selector switches are configured to: in response to the need to perform a first resistance calibration on the first high-speed interface subsystem of the at least two high-speed interface subsystems, close the single-channel selector switch of the plurality of single-channel selector switches corresponding to the first high-speed interface subsystem, and open the remaining single-channel selector switches of the plurality of single-channel selector switches.

[0007] For example, in at least one embodiment of this disclosure, a plurality of single-channel selection switches are located on a first die of the system-on-chip.

[0008] For example, in at least one embodiment of this disclosure, the first connection control device is further configured to: continue performing the first resistance calibration in response to the need to perform a second resistance calibration on the second high-speed interface subsystem in at least two high-speed interface subsystems during the first resistance calibration of the first high-speed interface subsystem in at least two high-speed interface subsystems; and connect the second high-speed interface subsystem to the first external interface separately in response to the completion of the first resistance calibration.

[0009] For example, in at least one embodiment of this disclosure, the system-on-chip further includes: a copying unit configured to: in response to the need to perform a second resistance calibration on a second high-speed interface subsystem in at least two high-speed interface subsystems during a first resistance calibration on a first high-speed interface subsystem in at least two high-speed interface subsystems, compare the operating configuration parameters of the first high-speed interface subsystem and the second high-speed interface subsystem, the operating configuration parameters including at least one of function, location, and operating speed; and in response to the comparison result satisfying a consistency condition, copy the result of the first resistance calibration to the second high-speed interface subsystem.

[0010] For example, in at least one embodiment of this disclosure, the system-on-chip includes a packaging layer, and at least two high-speed interface subsystems are merged and connected to a first external interface within the packaging layer.

[0011] For example, in at least one embodiment of this disclosure, the system-on-chip further includes: a second set of high-speed interface subsystems, the second set of high-speed interface subsystems including two or more high-speed interface subsystems; a second external interface for connection to a second reference resistor; and a second connection control device configured to: multiplex at least two of the second set of high-speed interface subsystems to the second external interface to individually connect the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems to the second external interface, wherein the second set of high-speed interface subsystems is located on a second die of the system-on-chip.

[0012] For example, in at least one embodiment of this disclosure, the first set of high-speed interface subsystems and the second set of high-speed interface subsystems are UCIe subsystems, and each of the first set of high-speed interface subsystems and each of the second set of high-speed interface subsystems are connected in a one-to-one correspondence.

[0013] For example, in at least one embodiment of this disclosure, a first set of high-speed interface subsystems is located on a first die of the system-on-a-chip, and a second set of high-speed interface subsystems is located on a second die of the system-on-a-chip.

[0014] At least one embodiment of this disclosure provides a method for a system-on-a-chip (SoC), characterized in that the SoC includes a first set of high-speed interface subsystems, a first external interface, and a first connection control device. The first set of high-speed interface subsystems includes two or more high-speed interface subsystems, and the first external interface is used to connect to a first reference resistor. The method includes: the first connection control device causing at least two of the first set of high-speed interface subsystems to multiplex the first external interface, so as to individually connect the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems to the first external interface, wherein the first set of high-speed interface subsystems is located on a first die of the SoC.

[0015] For example, in at least one embodiment of this disclosure, the first connection control device is a plurality of single-channel selector switches, which are configured one-to-one with each of at least two high-speed interface subsystems. The method includes: in response to the need to perform a first resistance calibration on the first high-speed interface subsystem of the at least two high-speed interface subsystems, the plurality of single-channel selector switches close the single-channel selector switch corresponding to the first high-speed interface subsystem and open the remaining single-channel selector switches.

[0016] For example, in at least one embodiment of this disclosure, the system-on-chip includes a copying unit, and the method further includes: the copying unit performing the following operations: in response to the need to perform a second resistance calibration on a second high-speed interface subsystem in at least two high-speed interface subsystems during a first resistance calibration on a first high-speed interface subsystem in at least two high-speed interface subsystems, comparing the operating configuration parameters of the first high-speed interface subsystem and the second high-speed interface subsystem, the operating configuration parameters including at least one of function, location, and operating speed; and in response to the comparison result satisfying a consistency condition, copying the result of the first resistance calibration to the second high-speed interface subsystem.

[0017] For example, in at least one embodiment of this disclosure, the system-on-chip includes a packaging layer, and at least two high-speed interface subsystems are merged and connected to a first external interface within the packaging layer.

[0018] For example, in at least one embodiment of this disclosure, the system-on-chip further includes a second set of high-speed interface subsystems, a second external interface, and a second connection control device, wherein the second set of high-speed interface subsystems includes two or more high-speed interface subsystems, the second external interface is used to connect to a second reference resistor, and the method further includes: the second connection control device causing at least two of the second set of high-speed interface subsystems to multiplex the second external interface, so as to individually connect the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems to the second external interface, wherein the second set of high-speed interface subsystems is located on a second die of the system-on-chip.

[0019] At least one embodiment of this disclosure provides an electronic device, wherein the electronic device includes at least one processing unit and a memory; wherein the memory stores computer-readable instructions and is communicatively connected to at least one processing unit; the at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the method described above.

[0020] At least one embodiment of this disclosure provides a computer-readable storage medium storing computer-readable instructions that, when executed by a processor, implement the method described above. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Clearly, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure.

[0022] Figure 1 A schematic diagram of an exemplary system-on-a-chip structure is shown;

[0023] Figure 2 A schematic diagram of the connection structure between an on-chip system and a reference resistor according to at least one embodiment of the present disclosure is shown;

[0024] Figure 3A A schematic diagram of the connection structure of another on-chip system with a reference resistor according to at least one embodiment of the present disclosure is shown;

[0025] Figure 3B A schematic diagram of the connection structure between another on-chip system and a reference resistor according to at least one embodiment of the present disclosure is shown;

[0026] Figure 3C A schematic diagram of the connection structure between another on-chip system and a reference resistor according to at least one embodiment of the present disclosure is shown;

[0027] Figure 4 A flowchart of a method for a system-on-a-chip according to at least one embodiment of the present disclosure is shown;

[0028] Figure 5 A schematic diagram illustrating an example application scenario according to at least one embodiment of the present disclosure is shown;

[0029] Figure 6 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0030] Figure 7 A schematic diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0031] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0032] To enable those skilled in the art to better understand this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of this disclosure to the specific shapes, hardware, connections, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can utilize the concepts of this disclosure to construct further embodiments not mentioned herein by reading this specification.

[0034] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0035] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0036] First, the abbreviations and related terms involved in this application are defined and explained.

[0037] A high-speed interface subsystem refers to a collection of hardware units that employ high-speed interface technologies (such as PCIe, UCIe, USB, HDMI, DDR, etc.). For example, this collection of hardware units can include interface controllers, physical layer circuits, transmission links, protocol stacks, etc. Exemplary high-speed interface subsystems include PCIe subsystems and UCIe subsystems.

[0038] The external interface of a SOC chip (hereinafter referred to as the external interface) refers to the channel on the SOC chip used to achieve physical connection, signal transmission and data interaction with external hardware devices, modules or systems. Its physical carrier is usually the chip pins and pads, and it can also be extended to a board-level interface form through package pins.

[0039] It is understood that the terms defined above are merely exemplary definitions in specific application scenarios to better understand this application, and this disclosure is not limited thereto.

[0040] Figure 1 A schematic diagram of an exemplary system-on-a-chip structure is shown.

[0041] See Figure 1 The system-on-a-chip 100 includes multiple high-speed interface subsystems (shown as four high-speed interface subsystems). These high-speed interface subsystems can be connected to different external interfaces of the system-on-a-chip 100 (shown as four pins 104 in the figure) to achieve physical connection, signal transmission and data interaction with external hardware devices, modules or systems of the system-on-a-chip 100.

[0042] The inventors of this disclosure recognized during their research that the number of high-speed interfaces in current systems-on-a-chip (SoCs) is enormous, making external interfaces extremely valuable. Therefore, given the limited number of external interfaces, it is necessary to rationally plan their usage to meet the needs of the SoC. Furthermore, high-speed interface subsystems typically require external reference resistors for calibration of resistors within the SoC, necessitating the use of external interfaces to connect to these reference resistors.

[0043] However, when a system-on-a-chip (SoC) has multiple or even large-scale high-speed interface subsystems, the number of pins occupied by the external resistors of each high-speed interface subsystem is considerable, further reducing the number of external interfaces available to the SoC. For example, in Figure 1In the described exemplary structure, the use of four high-speed interface subsystems necessitates four external interfaces for resistance calibration, which puts pressure on the design of other functional modules that also require external interfaces. Furthermore, the four external interfaces corresponding to the four high-speed interface subsystems will complicate the routing layout, as excessive routing not only increases the difficulty of layout but also affects signal quality. Moreover, when routing resistance is critical, calibration accuracy will also be affected.

[0044] Furthermore, the inventors of this disclosure have recognized that with the development of system-on-chip (SoC) manufacturing technology, it has become possible to integrate multiple high-speed interface subsystems onto a single die. However, due to differences in the production environment (temperature, doping, etc.) of different dies, variations in process corners and performance exist between them. Therefore, different dies cannot reuse the same external reference resistor. For example, the external reference resistor for die 0 can only be used for calibration of the high-speed interface subsystem of die 0, and the external reference resistor for die 1 can only be used for calibration of the high-speed interface subsystem of die 1. Exemplarily, reusing a single reference resistor across the high-speed interface subsystems of the entire SoC, or grouping the high-speed interface subsystems of the entire SoC based on proximity or I / O capabilities and reusing a single reference resistor within a group, will make it impossible to reliably calibrate the high-speed interface subsystems of the SoC, including the dies.

[0045] In view of this, at least one embodiment of the present disclosure provides a system-on-a-chip and a method, electronic device and storage medium therefor, which can reliably reduce the number of external interfaces used by the high-speed interface subsystem of the system-on-a-chip, including the die, to connect to a reference resistor.

[0046] Figure 2 A schematic diagram of the connection structure between an on-chip system and a reference resistor according to at least one embodiment of the present disclosure is shown.

[0047] See Figure 2 The system-on-a-chip 200 includes a first high-speed interface subsystem 202, a first external interface 204, and a first connection control device 206.

[0048] exist Figure 2 In this context, the first set of high-speed interface subsystems 202 is located on die 0 of the system-on-chip 200 (e.g., the first die described in the context). That is, the first set of high-speed interface subsystems 202 is located on the same die of the system-on-chip 200.

[0049] For example, as described above, the exemplary mechanism of multiple high-speed interface subsystems reusing a single external interface for the entire on-chip does not take into account how multiple high-speed interface subsystems can reliably reuse a single external interface for on-chip systems including dies that are supported as technology advances, in order to reduce the number of external interfaces (such as pins) used by the high-speed interface subsystems of the on-chip to connect reference resistors.

[0050] The following is combined Figure 2 Describe how a group of high-speed interface subsystems within the same die or divided by die can reuse a single external interface.

[0051] See also Figure 2 The first set of high-speed interface subsystems 202 located in die 0 includes two or more high-speed interface subsystems. See, for example... Figure 2 The first high-speed interface subsystem 202 includes four high-speed interface subsystems.

[0052] In some embodiments, each high-speed interface subsystem in the first set of high-speed interface subsystems 202 can be capable of using the same reference resistor (e.g., Figure 2 The high-speed interface subsystem performs resistance calibration using a first reference resistor 208. In some embodiments, each high-speed interface subsystem in the first set of high-speed interface subsystems 202 may be a high-speed interface subsystem located on the same die of the system-on-chip 200. In some embodiments, the first set of high-speed interface subsystems 202 may include one or more of the following: PCIe subsystem, UCIe subsystem, USB subsystem, HDMI subsystem, DDR subsystem, etc.

[0053] See also Figure 2 The first external interface 204 is used to connect to the first reference resistor 208.

[0054] Here, the first external interface 204 can be connected to the first reference resistor 208 so that the high-speed interface subsystem that needs to calibrate its resistance can be connected to the reference resistor via the external interface.

[0055] It is understood that the reference resistor described in this article can be any resistor used as a reference to correct deviations in the internal resistance of an on-chip system. Generally, the reference resistor can be a precision resistor with extremely high accuracy, extremely low temperature coefficient, and excellent long-term stability. Its resistance value maintains minimal deviation and drift under specified operating conditions such as temperature, humidity, and voltage. The selection of the reference resistor can be determined based on the actual design requirements.

[0056] See also Figure 2The first connection control device 206 is configured to multiplex the first external interface 204 in at least two of the first high-speed interface subsystems 202, so as to connect the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems to the first external interface individually.

[0057] It should be noted that, although Figure 2 The following describes the reuse of all (four) high-speed interface subsystems in the first high-speed interface subsystem 202 to the first external interface 204. However, this disclosure is not limited thereto. Additionally or alternatively, some (e.g., two or three) of the high-speed interface subsystems in the first high-speed interface subsystem 202 may be reused to the first external interface 204.

[0058] For example, as mentioned above, in Figure 1 In the illustrated system-on-a-chip 100, using N (e.g., 4) high-speed interface subsystems requires N (e.g., 4) external interfaces for resistance calibration. In contrast, in this embodiment, the first connection control device 206 allows at least two of the first group of high-speed interface subsystems 202 to multiplex the first external interface 204, thereby reducing the number of external interfaces required.

[0059] Here, reuse means that each of at least two of the first high-speed interface subsystems 202 can occupy the first external interface 204 in a time-sharing manner or not at the same time, so that the high-speed interface subsystem that needs to be calibrated has exclusive access to the first reference resistor 208.

[0060] Additionally, when it is necessary to perform another resistance calibration on another high-speed interface subsystem that requires resistance calibration in the at least two high-speed interface subsystems, the other high-speed interface subsystem can be connected separately to the first external interface.

[0061] As described above, the system-on-a-chip according to at least one embodiment of the present disclosure provides a mechanism at the die level that allows multiple high-speed interface subsystems within a die to reuse a single external interface. For example, the system-on-a-chip according to at least one embodiment of the present disclosure can use a connection control device to enable at least two of a group of high-speed interface subsystems on the same die to reuse a single external interface to achieve resistor calibration of the at least two high-speed interface subsystems, without having to provide an external interface for each high-speed interface subsystem (e.g., as shown in the image). Figure 1 As shown in the figure, this allows for a reliable reduction in the number of external interfaces used by the high-speed interface subsystem of a system-on-a-chip (SoC) to connect to reference resistors, for SoCs including dies.

[0062] Additionally, due to the reduction in the number of external interfaces, the number of internal traces of the on-chip system (such as the traces between the first connection control device 206 and the first external interface 204) is also reduced accordingly. This optimizes the trace layout, reduces the design difficulty, and also enhances signal quality and improves system operating efficiency.

[0063] The following describes some exemplary additional aspects of a system-on-a-chip according to at least one embodiment of the present disclosure.

[0064] For example, in at least one embodiment of this disclosure, the first connection control device may be a multiplexer switch. This multiplexer switch may be configured to select one of the multiplexer switches corresponding to the first high-speed interface subsystem to the first external interface in response to the need for a first resistance calibration of the first high-speed interface subsystem in at least two high-speed interface subsystems.

[0065] For example, Figure 3A A schematic diagram of the connection structure of another system-on-chip according to at least one embodiment of the present disclosure with a reference resistor is shown. Figure 3A The system-on-chip 300 shown can be used with the referenced Figure 2 The structure of the described system-on-chip 200 is similar, the difference being... Figure 3A The multiplexer 306 is shown as... Figure 2 An example of the first connection control device 206 in the example.

[0066] See Figure 3A The multiplexer 306 may include terminals P1 to P4 connected to the high-speed interface subsystem, and terminal P5 connected to the first external interface 204. When a high-speed interface subsystem ( Figure 3A When performing resistance calibration (shown as filled with slashes), the multiplexer 306 can connect the terminal corresponding to the high-speed interface subsystem (i.e., P2) to P5 to select the high-speed interface subsystem to the first external interface 204.

[0067] As described above, the system-on-a-chip according to at least one embodiment of the present disclosure can use a multiplexing switch (e.g., a multiplexer) to enable separate connection between a high-speed interface subsystem requiring resistance calibration and an external interface, thereby reducing the number of components and space occupied on the system-on-a-chip and reducing the amount of wiring.

[0068] The above embodiments describe the use of multiplexers to establish separate connections between a high-speed interface subsystem requiring resistance calibration and an external interface. However, the embodiments of this disclosure are not limited thereto. For example, in at least one embodiment of this disclosure, the first connection control device may be a plurality of single-channel switches, each corresponding to one of at least two high-speed interface subsystems. The plurality of single-channel switches may be configured to close the single-channel switch corresponding to the first high-speed interface subsystem and open the remaining single-channel switches in response to the need for a first resistance calibration of the first high-speed interface subsystem.

[0069] For example, Figure 3B A schematic diagram of the connection structure between another on-chip system and a reference resistor according to at least one embodiment of the present disclosure is shown. Figure 3B The system-on-chip 350 shown can be used with the referenced Figure 2 The structure of the described system-on-chip 200 is similar, the difference being... Figure 3B Multiple single-channel selector switches 356 are shown as Figure 2 An example of the first connection control device 206 in the example.

[0070] See Figure 3B Multiple single-channel selection switches 356 may include single-channel selection switches S1 to S4, each corresponding to a specific high-speed interface subsystem. When it is necessary to select a specific high-speed interface subsystem (… Figure 3B When performing resistance calibration (shown as slashes in the middle), the single-channel selection switch corresponding to the high-speed interface subsystem (i.e., S2) can be closed, and the remaining single-channel selection switches (i.e., S1, S3, and S4) among the multiple single-channel selection switches can be opened.

[0071] As described above, the system-on-chip according to at least one embodiment of this disclosure can achieve separate connections between a high-speed interface subsystem requiring resistance calibration and an external interface through multiple single-channel selection switches. In this embodiment, since each switch can be set independently, the number of switches can be increased or decreased as needed, and / or switches can be set for specific high-speed interface subsystems without redesigning the entire control logic, resulting in strong scalability and flexibility.

[0072] In other respects, the first connection control device 206 may include both a multiplexer switch 306 and a plurality of single-channel selectors 356, or the first connection control device 206 may include other similar selectors, provided that they enable at least two of a set of high-speed interface subsystems to multiplex a single external interface to connect a high-speed interface subsystem that requires resistance calibration to a single external interface so that the high-speed interface subsystem has exclusive access to the reference resistor.

[0073] For example, in at least one embodiment of this disclosure, a plurality of single-channel selection switches may be located on the first die of the system-on-chip.

[0074] For example, Figure 3B Multiple single-channel selector switches S1 to S4 can be located on the same die of the system-on-a-chip. Since the control systems of the same die are usually consistent, the closing and opening of multiple single-channel selector switches can be conveniently and accurately implemented. Of course, the embodiments of this disclosure are not limited thereto. In some embodiments, multiple single-channel selector switches can be located on different dies, and the closing and opening of multiple single-channel selector switches can be implemented collaboratively by other control elements (e.g., processors on the SOC).

[0075] For example, in at least one embodiment of this disclosure, the first set of high-speed interface subsystems may be located on the first die of the system-on-a-chip. For example, Figure 2 , Figure 3A , Figure 3B and Figure 3C Each high-speed interface subsystem in the first group of high-speed interface subsystems 202 can be located on the same die of the system-on-a-chip. Since the control system of the same die is consistent, the resistor calibration of each high-speed interface subsystem can be conveniently and accurately coordinated. Of course, the embodiments of this disclosure are not limited thereto. In some embodiments, each high-speed interface subsystem in the first group of high-speed interface subsystems 202 can be located on a different die, and the resistor calibration of each high-speed interface subsystem can be coordinated by other control elements (e.g., a processor on the SOC).

[0076] As described above, the first connection control device 206 can enable at least two multiplexed single external interfaces in a set of high-speed interface subsystems to connect a high-speed interface subsystem requiring resistance calibration to a single external interface, so that the high-speed interface subsystem has exclusive access to the reference resistor, thereby achieving resistance calibration of the high-speed interface subsystem. The inventors of this disclosure also recognized in their research that, since resistance calibration of high-speed interface subsystems takes time, in some cases, such as in the first set of high-speed interface subsystems 202, when resistance calibration is performed on one high-speed interface subsystem, there may be a need to calibrate the resistance of another high-speed interface subsystem; that is, at the same time, there may be two or more high-speed interface subsystems requiring resistance calibration using the same reference resistor.

[0077] In view of this, for example, in at least one embodiment of this disclosure, the first connection control device may also be configured to: continue performing the first resistance calibration in response to the need to perform a second resistance calibration on the second high-speed interface subsystem in at least two high-speed interface subsystems during the first resistance calibration of the first high-speed interface subsystem in at least two high-speed interface subsystems; and connect the second high-speed interface subsystem to the first external interface separately in response to the completion of the first resistance calibration.

[0078] As described above, the on-chip system according to at least one embodiment of the present disclosure can wait for the previous high-speed interface subsystem to complete the resistance calibration before switching to another high-speed interface subsystem that needs to perform resistance calibration, thereby satisfying the need for two or more high-speed interface subsystems to perform resistance calibration simultaneously using the same reference resistor.

[0079] In the above embodiments, since the other high-speed interface subsystem that needs to be calibrated can only be calibrated after the resistance calibration of the previous high-speed interface subsystem is completed, the resistance calibration of the other high-speed interface subsystem will be delayed due to waiting, thereby reducing the efficiency of resistance calibration, or even causing the resistance calibration request to time out.

[0080] In view of this, for example, in at least one embodiment of this disclosure, the system-on-chip may further include a copying unit. The copying unit may be configured to copy the result of the first resistance calibration to the second high-speed interface subsystem in response to the need for a second resistance calibration of the second high-speed interface subsystem in the at least two high-speed interface subsystems during a first resistance calibration of the first high-speed interface subsystem in the at least two high-speed interface subsystems.

[0081] In some embodiments, the replication unit may be implemented by any element on the system-on-chip (e.g., the system-on-chip processor and / or memory) capable of storing and / or transmitting the results of resistance calibration (i.e., data).

[0082] As described above, the on-chip system according to at least one embodiment of the present disclosure can, when other high-speed interface subsystems request a reference resistor, copy the resistance calibration result of the high-speed interface subsystem currently performing resistance calibration to the other high-speed interface subsystems requesting the reference resistor if a high-speed interface subsystem is currently performing resistance calibration. This eliminates the need for other high-speed interface subsystems to perform resistance calibration, saves resistance calibration time, and improves the efficiency of resistance calibration.

[0083] Furthermore, the inventors of this disclosure recognize that even for multiple high-speed interface subsystems within the same die, each high-speed interface subsystem may have different functions, locations, and operating speeds. Therefore, when high calibration accuracy is required, the replication unit can reuse calibration results only when it determines that the multiple high-speed interface subsystems within the same die are relatively consistent.

[0084] In view of this, for example, in at least one embodiment of this disclosure, the system-on-chip may further include a copying unit. The copying unit may be configured to: in response to the need for a second resistance calibration of a second high-speed interface subsystem in at least two high-speed interface subsystems during a first resistance calibration of a first high-speed interface subsystem in at least two high-speed interface subsystems, compare the operating configuration parameters of the first high-speed interface subsystem and the second high-speed interface subsystem, the operating configuration parameters including at least one of function, location, and operating speed; and in response to the comparison result satisfying a consistency condition, copy the result of the first resistance calibration to the second high-speed interface subsystem.

[0085] As described above, the on-chip system according to at least one embodiment of the present disclosure can reuse calibration results only when it is determined that multiple high-speed interface subsystems in the same die are relatively consistent, thereby improving calibration accuracy.

[0086] In some examples, consistency criteria include, for example, that the high-speed interface subsystems being compared have the same, similar, or related functions, are located within a predetermined distance range (e.g., 1 mm, 3 mm, etc.), and have the same or similar operating speeds. Here, "similar" can mean, for example, a difference not exceeding 50%, 30%, 20%, 10%, 5%, etc.

[0087] The inventors of this disclosure also recognize that connections between external interfaces and the internal systems on a single chip require long paths. For example, Figure 3C A schematic diagram of the connection structure between another on-chip system and a reference resistor according to at least one embodiment of the present disclosure is shown. Figure 3C The system-on-chip 380 shown can be used with the referenced Figure 2 The structure of the described system-on-chip 200 is similar. See also Figure 3C The on-chip system 380 needs to traverse a long path through multiple bumps (such as U bump and C4 bump) and multiple dielectric layers (such as interposer 382 and package layer 384) to connect the high-speed interface subsystem of die 0 to the first external interface 204.

[0088] Additionally, in Figure 3C In the middle, the intermediate layer 382 can be interconnected with the high-speed interface subsystem and the package layer 384 in die 0 using U bump and C4 bump.

[0089] However, as mentioned above, resistor calibration is highly sensitive to the parasitic resistance of the traces. To achieve pin multiplexing, additional connections are required within the on-chip system, which increases parasitic resistance and leads to deviations in calibration results. Therefore, a suitable connection mechanism is needed to reduce the parasitic resistance introduced by these additional connections.

[0090] In view of this, for example, in at least one embodiment of this disclosure, the system-on-chip includes a packaging layer, and the at least two high-speed interface subsystems are combined and connected to the first external interface in the packaging layer.

[0091] In this embodiment, for example, Figure 3C As shown, multiple high-speed interface subsystems are merged in the encapsulation layer 384 and connected to the first external interface 204. The main reasons for merging in the encapsulation layer 384 are: firstly, the trace resistance of the interposer layer 382 is relatively large, and if the above-mentioned merging and connection to the first external interface 204 is implemented in the interposer layer 382, ​​it will lead to more parasitic resistance; secondly, the traces in the interposer layer 382 are relatively dense, and its routing is difficult.

[0092] As described above, the on-chip system according to at least one embodiment of the present disclosure can reduce the parasitic resistance introduced by additional connections, and additionally, can reduce the difficulty of wiring the additional connections.

[0093] It is worth noting that, although Figure 3C Multiple single-channel selector switches 356 are shown; however, this disclosure is not limited thereto. Figure 3C The multiple single-channel selector switches 356 shown are only one example of the first connection control device 206.

[0094] See Figure 2 , Figure 3A , Figure 3B and Figure 3C This describes a system-on-a-chip (SoC) including a first set of high-speed interface subsystems, a first external interface, and a first connection control device. For ease of description, see [link to documentation]. Figure 2 , Figure 3A , Figure 3B and Figure 3C The structure of the first high-speed interface subsystem, the first external interface, and the first connection control device described herein can be simply referred to as the "first resistance calibration subsystem." Additionally, this system-on-a-chip may also include other resistance calibration subsystems with the same or similar structures, i.e., multiple identical or similar resistance calibration subsystems. For example, other resistance calibration subsystems may be related to those described in [reference needed]. Figure 2 , Figure 3A , Figure 3B and Figure 3CThe first described resistance calibration subsystem has a similar structure so that for each resistance calibration subsystem, at least two multiplexed single external interfaces from a set of high-speed interface subsystems can be implemented, such that when resistance calibration is required for a particular high-speed interface subsystem, that high-speed interface subsystem is individually connected to a single external interface.

[0095] For example, in at least one embodiment of this disclosure, the system-on-chip may further include: a second set of high-speed interface subsystems, the second set of high-speed interface subsystems including two or more high-speed interface subsystems; a second external interface for connection to a second reference resistor; and a second connection control device configured to: multiplex at least two of the second set of high-speed interface subsystems to the second external interface, so as to individually connect the high-speed interface subsystems requiring resistance calibration in the at least two high-speed interface subsystems to the second external interface. For example, the second set of high-speed interface subsystems may be located on a second die of the system-on-chip.

[0096] As described above, the system-on-a-chip according to at least one embodiment of the present disclosure can divide the high-speed interface subsystem of the system-on-a-chip into two or more groups of high-speed interface subsystems (e.g., a first group of high-speed interface subsystems, a second group of high-speed interface subsystems) according to the die, and map them to the above-mentioned resistance calibration subsystem respectively, so that for at least two high-speed interface subsystems in each group of high-speed interface subsystems, only a single external interface is needed to perform resistance calibration on at least two high-speed interface subsystems in a single die.

[0097] It should be noted that, depending on the requirements of resistance calibration, the first reference resistor and the second reference resistor can be the same two resistors or two different resistors.

[0098] As described above, the high-speed interface subsystem may include one or more of the following: PCIe subsystem, UCIe subsystem, USB subsystem, HDMI subsystem, DDR subsystem, etc. For example, when the high-speed interface subsystem is a PCIe subsystem, it can connect to devices outside the system-on-a-chip. However, the inventors of this disclosure also recognized in their research that UCIe, as an interconnect standard for chiplet heterogeneous integration, has significant technical characteristics and advantages compared to PCIe, which is commonly used for inter-device connections, in terms of adapting to chiplet interconnects within the package, multi-protocol compatibility, and energy efficiency. For example, UCIe has the technical advantages of high bandwidth, low latency, and adaptation to heterogeneous integration. Therefore, systems-on-a-chip that include UCIe subsystems are widely applicable to many application areas such as AI and high-performance computing, data centers, automotive electronics, and wireless communications.

[0099] In view of this, for example, in at least one embodiment of this disclosure, the first set of high-speed interface subsystems and the second set of high-speed interface subsystems can be UCIe subsystems, and each of the first set of high-speed interface subsystems and each of the second set of high-speed interface subsystems can be connected in a one-to-one correspondence.

[0100] As described above, the system-on-a-chip according to at least one embodiment of the present disclosure can achieve resistor calibration for at least one high-speed interface subsystem in each group of high-speed interface subsystems in the application scenario of UCIe connection within the system-on-a-chip, requiring only a single external interface. For chipplet type chips, the resulting reduction in the occupation of external interfaces will significantly increase the number of available external interfaces for this type of chip and improve the support of this type of chip for other functions.

[0101] Additionally, in a system-on-a-chip, UCIe connectivity can include die-to-die UCIe connections. A single die can have a consistent control system to control the unified control of the components within the die.

[0102] Therefore, the system-on-chip according to at least one embodiment of the present disclosure can support a reduction in the occupancy of external interfaces in scenarios of die-to-die UCIe connections.

[0103] See above Figure 2 , Figure 3A , Figure 3B and Figure 3C A system-on-a-chip (SoC) and additional aspects thereof according to at least one embodiment of the present disclosure are described. Accordingly, at least one embodiment of the present disclosure provides a method for or for operating a system-on-a-chip.

[0104] The system-on-a-chip (SoC) may include a first set of high-speed interface subsystems, a first external interface, and a first connection control device. The first set of high-speed interface subsystems may include two or more high-speed interface subsystems. The first external interface is used to connect to a first reference resistor. In this respect, the SoC may, for example, be compatible with... Figure 2 The described system-on-chip 200 is the same as or similar to it.

[0105] Figure 4 A flowchart of a method for a system-on-a-chip according to at least one embodiment of the present disclosure is shown.

[0106] See Figure 4 The method 400 includes step S410.

[0107] In step S410, at least two of the first high-speed interface subsystems in the first group are multiplexed to use the first external interface, so that the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems are individually connected to the first external interface. The first group of high-speed interface subsystems is located on the first die of the system-on-a-chip.

[0108] In some embodiments, step S410 may be performed by, for example, a person. Figure 2 The first connection control device 206 is used to implement this.

[0109] As described above, the method for a system-on-a-chip according to at least one embodiment of this disclosure can achieve resistor calibration of at least two high-speed interface subsystems on the same die by multiplexing a single external interface through a connection control device, without having to provide an external interface for each high-speed interface subsystem (e.g., as shown in the image). Figure 1 As shown in the figure, this allows for a reliable reduction in the number of external interfaces used by the high-speed interface subsystem of a system-on-a-chip (SoC) to connect to reference resistors, for SoCs including dies.

[0110] The following describes some exemplary additional aspects of a method for a system-on-a-chip according to at least one embodiment of the present disclosure.

[0111] For example, in at least one embodiment of this disclosure, the first connection control device may be a plurality of single-channel selector switches, which may be configured one-to-one with each of the at least two high-speed interface subsystems. The method may include: in response to the need to perform a first resistance calibration on the first high-speed interface subsystem of the at least two high-speed interface subsystems, the plurality of single-channel selector switches close the single-channel selector switch corresponding to the first high-speed interface subsystem and open the remaining single-channel selector switches.

[0112] For example, in at least one embodiment of this disclosure, a plurality of single-channel selection switches may be located on the first die of the system-on-chip.

[0113] For example, in at least one embodiment of this disclosure, the system-on-chip may include a copying unit, and the method may further include: the copying unit performing the following operations: in response to the need to perform a second resistance calibration on a second high-speed interface subsystem in at least two high-speed interface subsystems during a first resistance calibration on a first high-speed interface subsystem in at least two high-speed interface subsystems, comparing the operating configuration parameters of the first high-speed interface subsystem and the second high-speed interface subsystem, the operating configuration parameters including at least one of function, location, and operating speed; and in response to the comparison result satisfying a consistency condition, copying the result of the first resistance calibration to the second high-speed interface subsystem.

[0114] For example, in at least one embodiment of this disclosure, the system-on-chip includes a packaging layer, and at least two high-speed interface subsystems are merged and connected to a first external interface within the packaging layer.

[0115] For example, in at least one embodiment of this disclosure, the system-on-chip may further include a second set of high-speed interface subsystems, a second external interface, and a second connection control device, wherein the second set of high-speed interface subsystems includes two or more high-speed interface subsystems, and the second external interface is used to connect to a second reference resistor. In this case, the method may further include: the second connection control device causing at least two of the second set of high-speed interface subsystems to multiplex the second external interface, so as to individually connect the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems to the second external interface, wherein the second set of high-speed interface subsystems is located on a second die of the system-on-chip.

[0116] For example, in at least one embodiment of this disclosure, the first set of high-speed interface subsystems and the second set of high-speed interface subsystems can be UCIe subsystems, and each of the first set of high-speed interface subsystems and each of the second set of high-speed interface subsystems can be connected in a one-to-one correspondence.

[0117] For example, in at least one embodiment of this disclosure, the first set of high-speed interface subsystems may be located on the first die of the system-on-a-chip, and the second set of high-speed interface subsystems may be located on the second die of the system-on-a-chip.

[0118] Further aspects of the method for a system-on-a-chip according to at least one embodiment of this disclosure can be referred to above. Figure 2 , Figure 3A , Figure 3B and Figure 3C A system-on-chip according to at least one embodiment of the present disclosure and its additional aspects are described herein, and will not be repeated here.

[0119] The following describes the above combination with example application scenarios. Figure 2 , Figure 3A , Figure 3B and Figure 3C as well as Figure 4 One or more exemplary aspects are described. It is understood that the example application scenarios described below are merely examples and not limitations, intended to exemplify the above combination in specific application scenarios. Figure 2 , Figure 3A , Figure 3B and Figure 3C as well as Figure 4 One or more aspects, and the aspects described below in conjunction with example application scenarios can be combined with the above. Figure 2 , Figure 3A , Figure 3B and Figure 3C as well as Figure 4 One or more aspects are combined.

[0120] Figure 5 A schematic diagram of an example application scenario according to at least one embodiment of the present disclosure is shown. This example application scenario 500 illustrates an exemplary structure for connecting an on-chip system to a reference resistor on which a die-to-die UCIe connection is implemented.

[0121] See Figure 5 This example application scenario 500 may include a system-on-chip 550 and reference resistors 0 and 1. For example, system-on-chip 550 may be a more detailed example of system-on-chip 200, 300 and 350 described above, and reference resistors 0 and 1 may be examples of reference resistors (such as a first reference resistor and a second reference resistor) described above.

[0122] The System-on-Chip 550 may include die 0 and die 1. Die 0 includes four UCIe subsystems, namely UCIe01, UCIe02, UCIe03, and UCIe04. Die 1 includes four UCIe subsystems, namely UCIe11, UCIe12, UCIe13, and UCIe14.

[0123] The UCIe subsystems of die 0 and die 1 can be interconnected to communicate. For example, UCIe01, UCIe02, UCIe03 and UCIe04 of die 0 can be interconnected with UCIe11, UCIe12, UCIe13 and UCIe14 of die 1 respectively to communicate.

[0124] Each UCIe subsystem of die 0 and die 1 has a control switch on the path or route to the external interface. For example, the control switch could be an example of the single-channel selector switch described above.

[0125] For example, the control switches S01 to S04, which are connected to the external interface 504 of die 0, control the connection and disconnection of die 0's UCIe01 to UCIe04 with reference resistor 0, respectively. Similarly, the control switches S11 to S14, which are connected to the external interface 506 of die 1, control the connection and disconnection of die 1's UCIe11 to UCIe14 with reference resistor 1, respectively.

[0126] Taking UCIe01 to UCIe04 of die 0 as examples, when only subsystem UCIe01 requests a reference resistor, control switch S01 can be closed, and control switches S02 to S04 can be opened, allowing UCIe01 to exclusively use reference resistor 0 for resistance calibration. Similarly, when only subsystem UCIe02 requests a reference resistor, control switch S02 can be closed, and control switches S01, S03, and S04 can be opened, allowing UCIe02 to exclusively use reference resistor 0 for resistance calibration. UCIe11 to UCIe14 of die 1 can exclusively use reference resistor 1 in the same way as UCIe01 to UCIe04 of die 0, and will not be elaborated further here.

[0127] Additionally, since the control system on the same die is usually consistent, while the control systems on different dies are usually not consistent, in order to conveniently and accurately realize the closing and opening of multiple selector switches, the control switches can be set on the corresponding dies (for example, control switches S01 to S04 can be set on die 0, and control switches S11 to S14 can be set on die 1), and resistor multiplexing can be performed only for the UCIe subsystem on the same die. Therefore, see [link to relevant documentation] Figure 5 In the described die-to-die UCIe connection, two reference resistors can be used to support the resistor multiplexing of the UCIe subsystems on the two dies respectively.

[0128] It is worth noting that, see Figure 5 The System-on-Chip 550 and reference resistors 0 and 1 described herein are merely exemplary and are not intended to limit the scope of this disclosure. For example, the System-on-Chip 550 may contain more or fewer dies, and each die may include more or fewer UCIe subsystems. As another example, control switches may be located outside the die instead of on it, as long as they enable the closing and opening of the high-speed interface subsystem and the external interface. As yet another example, for die 0 or die 1, some (but not all) of its UCIe subsystems may correspond to one external interface. In one example, for die 0, UCIe01 to UCIe02 may correspond to one external interface, and UCIe03 to UCIe04 may correspond to one external interface, or UCIe03 and UCIe04 may each correspond to one external interface.

[0129] For example, the UCIe subsystem of the system-on-chip 550 can be replaced by a subsystem of other high-speed interface technologies, thereby changing the structure of the system-on-chip 550 accordingly. For instance, when using PCIe technology, the UCIe subsystem can be modified into a PCIe subsystem, and additionally, the PCIe subsystem can be connected to devices external to the system-on-chip 550.

[0130] Figure 6A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0131] like Figure 6 As shown, the electronic device 600 includes at least one processing unit 620 and a memory 610. The memory 610 stores computer-readable instructions and is communicatively connected to the processing unit 620. The processing unit 620 executes the computer-readable instructions stored in the memory 610 to implement a method according to at least one embodiment of the present disclosure and its additional aspects.

[0132] For example, the memory 610 and the processing unit 620 can communicate with each other directly or indirectly. For example, in some examples, such as... Figure 6 As shown, the electronic device 600 may also include a system bus 630, through which the memory 610 and the processing unit 620 can communicate with each other. For example, the processing unit 620 can access the memory 610 through the system bus 630. For example, in other examples, components such as the memory 610 and the processing unit 620 can communicate through a network on-chip (NOC) connection.

[0133] For example, the processing unit 620 can control other components in the electronic device 600 to perform desired functions. The processing unit 620 can be an artificial intelligence processor.

[0134] For example, memory 610 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0135] For example, one or more computer-readable instructions can be stored on memory 610, and processing unit 620 can execute computer-readable instructions to perform various functions. Various application programs and various data, such as instruction processing code and various data used and / or generated by the application programs, can also be stored in the computer-readable storage medium.

[0136] For example, some computer instructions stored in memory 610 can perform one or more steps in accordance with the method described above when executed by processing unit 620.

[0137] For example, such as Figure 6As shown, the electronic device 600 may further include an input interface 640 that allows external devices to communicate with the electronic device 600. For example, the input interface 640 may be used to receive instructions from external computer devices, users, etc. The electronic device 600 may also include an output interface 650 that enables the electronic device 600 to connect to one or more external devices. For example, the electronic device 600 can communicate via the output interface 650, etc.

[0138] It should be noted that the electronic device 600 according to at least one embodiment of the present disclosure is exemplary and not restrictive. Depending on the actual application needs, the electronic device 600 may also include other conventional components or structures. For example, in order to realize the necessary functions of the electronic device, those skilled in the art can set other conventional components or structures according to the specific application scenario. The embodiments of the present disclosure do not limit this.

[0139] At least one embodiment of this disclosure also provides a computer-readable storage medium. Figure 7 A schematic diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure is shown.

[0140] For example, such as Figure 7 As shown, the computer-readable storage medium 700 stores computer-readable instructions 710, which, when executed by a computer, can implement the method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0141] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 700. Some of the computer-readable instructions stored on the computer-readable storage medium 700 may be, for example, instructions for implementing one or more steps in the methods described above.

[0142] For example, a computer-readable storage medium may include the storage component of a tablet computer, a hard disk of a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical disc read-only memory (CD-ROM), flash memory, or any combination of the above computer-readable storage media, or other suitable storage media. For example, computer-readable storage medium 700 may include the memory 610 in the electronic device 600 described above.

[0143] In addition to the exemplary descriptions above, the following points should be noted regarding this disclosure:

[0144] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0145] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0146] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A system-on-a-chip, characterized in that, The on-chip system includes: The first group of high-speed interface subsystems includes two or more high-speed interface subsystems; The first external interface is used to connect to the first reference resistor; and The first connection control device is configured to: At least two of the first set of high-speed interface subsystems reuse the first external interface, so that the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems can be individually connected to the first external interface, wherein the first set of high-speed interface subsystems is located on the first die of the system-on-a-chip.

2. The system-on-a-chip according to claim 1, characterized in that, The first connection control device is a multiplexer switch. The multiplexer switch is configured as follows: In response to the need to perform a first resistance calibration on the first high-speed interface subsystem of the at least two high-speed interface subsystems, one of the multiplexer switches corresponding to the first high-speed interface subsystem is selected to the first external interface.

3. The system-on-a-chip according to claim 1, characterized in that, The first connection control device consists of multiple single-channel selection switches, each of which is configured in a one-to-one correspondence with each of the at least two high-speed interface subsystems. The plurality of single-channel selection switches are configured as follows: In response to the need to perform a first resistance calibration on the first high-speed interface subsystem of the at least two high-speed interface subsystems, the single-channel selection switch corresponding to the first high-speed interface subsystem among the plurality of single-channel selection switches is closed, and the remaining single-channel selection switches among the plurality of single-channel selection switches are opened.

4. The system-on-a-chip according to claim 3, characterized in that, The plurality of single-channel selection switches are located on the first die of the system-on-a-chip.

5. The system-on-a-chip according to claim 1, characterized in that, The first connection control device is further configured to: In response to the need to perform a second resistance calibration on the second high-speed interface subsystem of the at least two high-speed interface subsystems during the first resistance calibration of the first high-speed interface subsystem of the at least two high-speed interface subsystems, the first resistance calibration continues. as well as In response to the completion of the first resistor calibration, the second high-speed interface subsystem is connected separately to the first external interface.

6. The system-on-a-chip according to claim 1, characterized in that, The on-chip system also includes: The replication unit is configured as follows: In response to the need for a second resistance calibration of a second high-speed interface subsystem in the at least two high-speed interface subsystems during a first resistance calibration of a first high-speed interface subsystem in the at least two high-speed interface subsystems, a comparison is made of the operating configuration parameters of the first high-speed interface subsystem and the second high-speed interface subsystem, the operating configuration parameters including at least one of function, location, and operating speed; and In response to the comparison result satisfying the consistency condition, the result of the first resistor calibration is copied to the second high-speed interface subsystem.

7. The system-on-a-chip according to claim 1, characterized in that, The system-on-a-chip includes a packaging layer, and the at least two high-speed interface subsystems are combined and connected to the first external interface in the packaging layer.

8. The system-on-a-chip according to any one of claims 1-7, characterized in that, The on-chip system also includes: The second high-speed interface subsystem includes two or more high-speed interface subsystems. The second external interface is used to connect to the second reference resistor; and The second connection control device is configured as follows: At least two of the second set of high-speed interface subsystems are multiplexed to the second external interface, so that the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems are individually connected to the second external interface, wherein the second set of high-speed interface subsystems is located on the second die of the system-on-a-chip.

9. The system-on-a-chip according to claim 8, characterized in that, The first set of high-speed interface subsystems and the second set of high-speed interface subsystems are UCIe subsystems, and Each of the first set of high-speed interface subsystems is connected in a one-to-one correspondence with each of the second set of high-speed interface subsystems.

10. A method for a system-on-a-chip, characterized in that, The system-on-a-chip includes a first set of high-speed interface subsystems, a first external interface, and a first connection control device. The first set of high-speed interface subsystems includes two or more high-speed interface subsystems. The first external interface is used to connect to a first reference resistor. The method includes: The first connection control device enables at least two of the first set of high-speed interface subsystems to reuse the first external interface, so as to connect the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems to the first external interface individually, wherein the first set of high-speed interface subsystems is located on the first die of the system-on-a-chip.

11. The method according to claim 10, characterized in that, The first connection control device comprises multiple single-channel selection switches, each of which is configured in a one-to-one correspondence with each of the at least two high-speed interface subsystems. The method includes: In response to the need to perform a first resistance calibration on the first high-speed interface subsystem of the at least two high-speed interface subsystems, the plurality of single-channel selector switches close the single-channel selector switch corresponding to the first high-speed interface subsystem and open the remaining single-channel selector switches.

12. The method according to claim 10, characterized in that, The on-chip system includes a replication unit, and the method further includes: The copying unit performs the following operations: In response to the need for a second resistance calibration of a second high-speed interface subsystem in the at least two high-speed interface subsystems during a first resistance calibration of a first high-speed interface subsystem in the at least two high-speed interface subsystems, a comparison is made of the operating configuration parameters of the first high-speed interface subsystem and the second high-speed interface subsystem, the operating configuration parameters including at least one of function, location, and operating speed; and In response to the comparison result satisfying the consistency condition, the result of the first resistor calibration is copied to the second high-speed interface subsystem.

13. The method according to claim 10, characterized in that, The system-on-a-chip includes a packaging layer, and the at least two high-speed interface subsystems are combined and connected to the first external interface in the packaging layer.

14. The method according to any one of claims 10-13, characterized in that, The system-on-a-chip further includes a second set of high-speed interface subsystems, a second external interface, and a second connection control device, wherein the second set of high-speed interface subsystems includes two or more high-speed interface subsystems, and the second external interface is used to connect to a second reference resistor. The method further includes: The second connection control device enables at least two of the second set of high-speed interface subsystems to multiplex the second external interface, so as to connect the high-speed interface subsystems that require resistance calibration in the at least two high-speed interface subsystems to the second external interface individually, wherein the second set of high-speed interface subsystems is located on the second die of the system-on-a-chip.

15. An electronic device, characterized in that, The electronic device includes at least one processing unit and a memory; wherein... The memory stores computer-readable instructions and is communicatively connected to the at least one processing unit; The at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the method according to any one of claims 10-14.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-readable instructions that, when executed by a processor, implement the method according to any one of claims 10-14.

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