Semiconductor device and electronic system including the same

Abstract

A semiconductor device includes a cell array region, a connection region including a first region and a second region, a stack structure including a gate stack structure and an insulating stack structure, a channel structure passing through the gate stack structure, and a gate contact in the second region and electrically connected to at least a portion of a gate electrode in the first region. The gate stack structure includes the gate electrode and an interlayer insulating layer. The insulating stack structure includes a sacrificial insulating layer and the interlayer insulating layer. Each gate contact includes a conductive portion and a side insulating layer. The conductive portion includes a penetration portion and a connection portion that horizontally extends to have an area larger than that of the penetration portion. The penetration portion of a first contact among the gate contacts includes first and second portions on respective first and second surfaces of the connection portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and the benefit thereof to Korean Patent Application No. 10-2024-0191831, filed with the Korean Intellectual Property Office on December 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device and an electronic system including the semiconductor device, and more specifically, to a semiconductor device having an improved structure and an electronic system including the semiconductor device. Background Technology

[0004] In electronic systems that implement data storage, semiconductor devices capable of storing high-capacity data are required. Therefore, methods for increasing the data storage capacity of semiconductor devices are being investigated. For example, as a method for increasing the data storage capacity of semiconductor devices, a semiconductor device comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0005] This disclosure provides a semiconductor device capable of improving performance and reliability, as well as an electronic system including the semiconductor device.

[0006] A semiconductor device according to an embodiment includes a cell array region and a connection region including a first region and a second region. The semiconductor device includes a stacked structure, a channel structure, and a plurality of gate contacts. The stacked structure includes a gate stacked structure and an insulating stacked structure. The gate stacked structure is located in the cell array region and the first region, and includes a plurality of gate electrodes and a plurality of interlayer insulating layers. The insulating stacked structure is located in the second region, and includes a plurality of sacrificial insulating layers and a plurality of interlayer insulating layers. The channel structure passes through the gate stacked structure in the cell array region. The plurality of gate contacts are located in the second region and are electrically connected to at least a portion of the plurality of gate electrodes in the first region, respectively. Each of the plurality of gate contacts includes a conductive portion and a side insulating layer. The conductive portion includes a through portion and a connection portion, the through portion passing through the insulating stacked structure, and the connection portion extending horizontally to have an area larger than the area of ​​the through portion. The side insulating layer is on at least a portion of the side surface of the conductive portion. The plurality of gate contacts includes a first contact. The connection portion has a first surface and a second surface opposite to each other. The through portion of the first contact includes a first portion located on the first surface of the connection portion and a second portion located on the second surface of the connection portion.

[0007] A semiconductor device according to an embodiment includes a stacked structure, a channel structure, and a plurality of gate contacts. The stacked structure includes a gate stack structure comprising a plurality of gate electrodes and a plurality of interlayer insulating layers. A channel structure extends through the gate stack structure. The plurality of gate contacts each extend through at least a portion of the plurality of gate electrodes and are electrically connected thereto. Each of the plurality of gate contacts includes a conductive portion and a side insulating layer. The conductive portion includes a through-hole portion extending through the stacked structure and a connection portion extending horizontally to have an area larger than the area of ​​the through-hole portion. The side insulating layer is located on a side surface of the conductive portion. The plurality of gate contacts includes a first contact. The connection portion has a first surface and a second surface opposite to each other. The through-hole portion of the first contact includes a first portion located on the first surface of the connection portion and a second portion located on the second surface of the connection portion. The side insulating layer of the first contact is on a side surface of the first portion and spaced apart from the second portion.

[0008] An electronic system according to an embodiment includes a main substrate, a semiconductor device on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate. The semiconductor device includes a cell array region and a connection region, the connection region including a first region and a second region. The semiconductor device includes a stacked structure, a channel structure, and a plurality of gate contacts. The stacked structure includes a gate stacked structure and an insulating stacked structure. The gate stacked structure is located in the cell array region and the first region, and includes a plurality of gate electrodes and a plurality of interlayer insulating layers. The insulating stacked structure is located in the second region, and includes a plurality of sacrificial insulating layers and a plurality of interlayer insulating layers. The channel structure passes through the gate stacked structure in the cell array region. The plurality of gate contacts are located in the second region and are respectively electrically connected to at least a portion of the plurality of gate electrodes in the first region. Each of the plurality of gate contacts includes a conductive portion and a side insulating layer. The conductive portion includes a through portion and a connection portion, the through portion passing through the insulating stacked structure, and the connection portion extending horizontally to have an area larger than the area of ​​the through portion. The side insulating layer is on at least a portion of the side surface of the conductive portion. The plurality of gate contacts include a first contact. The connection portion has a first surface and a second surface opposite to each other. The penetrating portion of the first contact member includes a first portion located on a first surface of the connecting portion and a second portion located on a second surface of the connecting portion.

[0009] According to an embodiment, a first through-hole portion with a gate contact can be formed using a first etching process including a partial etching process according to a binary system, which simplifies the process of forming the gate contact and reduces the area of ​​the connection region. The gate contact can be disposed in an insulating stack structure, positioned in a space separated from the through-hole dummy structure, and the first through-hole portion can be stably formed. The gate contact may include a horizontally extending connection portion and can be easily electrically connected to a gate electrode included in the gate stack structure. In the first contact of the gate contact, the through portion may include a first portion on a first surface of the connection portion and a second portion on a second surface of the connection portion, and the first contact can be used to improve the performance of the semiconductor device. Thus, the performance and reliability of the semiconductor device can be improved. Attached Figure Description

[0010] Figure 1 This is a schematic partial cross-sectional view of a semiconductor device according to an example embodiment.

[0011] Figure 2 It is shown that it includes Figure 1 An enlarged cross-sectional view of an example of a channel structure in a semiconductor device.

[0012] Figure 3 It is shown schematically. Figure 1 A plan view of a portion of the semiconductor device shown.

[0013] Figure 4 It is shown Figure 3 A magnified plan view of part D in the diagram.

[0014] Figure 5 It is along Figure 3 The cross-sectional view taken from line E-E' in the diagram.

[0015] Figures 6 to 16 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0016] Figure 17 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0017] Figure 18 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0018] Figure 19 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0019] Figure 20 This is a cross-sectional view of a semiconductor device according to a modified example embodiment.

[0020] Figure 21This is a schematic plan view of a semiconductor device according to an example embodiment.

[0021] Figure 22 yes Figure 21 The diagram shows a cross-sectional view of the semiconductor device.

[0022] Figure 23 This is a cross-sectional view of a semiconductor device according to a modified example embodiment.

[0023] Figure 24 This is a cross-sectional view of a semiconductor device according to a modified example embodiment.

[0024] Figure 25 This is a cross-sectional view of a semiconductor device according to a modified example embodiment.

[0025] Figure 26 This is a schematic plan view of a semiconductor device according to an example embodiment.

[0026] Figure 27 This is a schematic plan view of a semiconductor device according to an example embodiment.

[0027] Figure 28 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment.

[0028] Figure 29 It is shown that it includes Figure 28 A plan view of the upper surface of the first stacked portion in the semiconductor device shown.

[0029] Figure 30 It is shown that it includes Figure 28 A plan view of the upper surface of the second stacked portion in the semiconductor device shown.

[0030] Figure 31 Conceptually showing including Figure 28 The separation structure in the first stacked portion and the second stacked portion of the semiconductor device shown.

[0031] Figure 32 A conceptual illustration shows a discrete structure in a plurality of gate stack portions included in a semiconductor device according to an example embodiment.

[0032] Figure 33 A conceptual illustration shows a discrete structure in a plurality of gate stack portions included in a semiconductor device according to an example embodiment.

[0033] Figure 34 This is a schematic plan view of a portion of a semiconductor device according to an example embodiment.

[0034] Figure 35This is a schematic partial cross-sectional view of a semiconductor device according to an example embodiment.

[0035] Figure 36 This is a schematic partial cross-sectional view of a semiconductor device according to a modified example embodiment.

[0036] Figure 37 An electronic system including a semiconductor device is illustrated according to an example embodiment.

[0037] Figure 38 This is a perspective view schematically illustrating an electronic system including semiconductor devices according to an example embodiment.

[0038] Figure 39 This is a schematic cross-sectional view of a semiconductor package according to an example embodiment.

[0039] Figure 40 This is a schematic cross-sectional view of a semiconductor package according to an example embodiment. Detailed Implementation

[0040] To those skilled in the art, embodiments of this disclosure will be described more fully below with reference to the accompanying drawings to facilitate its practice. This disclosure may be implemented in various different forms and is not limited to the embodiments provided herein. The same reference numerals always denote the same elements.

[0041] For clarity of description, irrelevant parts have been omitted, and throughout the specification, the same or similar parts are indicated by the same reference numerals.

[0042] Furthermore, since the dimensions and / or thicknesses of the parts, areas, components, units, layers, films, substrates, etc. shown in the accompanying drawings may be arbitrarily shown for better understanding and ease of explanation, this disclosure is not limited to the dimensions and / or thicknesses shown. In the accompanying drawings, the thicknesses of parts, areas, components, units, layers, films, substrates, etc., may be enlarged or exaggerated for ease of explanation and / or simple illustration.

[0043] It should be understood that when a component, such as a part, region, member, unit, layer, film, substrate, etc., is referred to as being "on" or "above" another component, it may be directly on the other component or there may be intermediate components. Conversely, when a component is referred to as being "directly on" another component, there are no intermediate components. Furthermore, when a component is referred to as being "on" or "above" a reference component, the component may be positioned on or below the reference component, and it does not necessarily have to be "on" or "above" the reference component in the opposite direction of gravity.

[0044] Furthermore, throughout the specification, unless explicitly stated otherwise, the words “comprising,” “including,” or “containing,” as well as variations such as “including…,” “containing…,” or “containing…”, shall be understood to imply the inclusion of other components rather than the exclusion of any other components.

[0045] Furthermore, throughout the specification, the phrases “in a plane,” “in a plane,” “in a plan view,” or “in a plan view” can indicate the view of a portion as seen from above or at the top, and the phrases “in a section” or “in a section view” can indicate the view of a section taken along the vertical direction as seen from the side.

[0046] It should be understood that when a component is referred to as being “connected” or “coupled” to or “on” another component, it may be directly connected to or coupled to or on the other component, or there may be intermediate components. Conversely, when a component is referred to as being “directly connected” or “directly coupled” to another component, or referred to as being “in contact” with or “in contact with” another component (or any form of using the word “in contact”), there are no intermediate components at the point of contact.

[0047] As used in this article, the term "area" refers to a planar area.

[0048] The following is for reference Figures 1 to 16 The following will describe in detail the semiconductor device and its manufacturing method according to the embodiments.

[0049] Figure 1 This is a schematic partial cross-sectional view of the semiconductor device 10 according to an embodiment. Figure 2 It is shown that it includes Figure 1 An enlarged cross-sectional view of an example of the channel structure CH in the semiconductor device 10 shown. Figure 1 It shows along Figure 3 The portions intercepted by lines A-A', B-B', and C-C' in the diagram. For clarity, in... Figure 1 The location of the source contact 174 and the input / output connection wiring 176 is conceptually shown in the diagram.

[0050] Reference Figure 1 and Figure 2 The semiconductor device 10 according to an embodiment may include a cell region 100 and a circuit region 200. The cell region includes a memory cell structure, and the circuit region includes a peripheral circuit structure configured to control the operation of the memory cell structure. For example, the circuit region 200 and the cell region 100 may respectively correspond to... Figure 37 The electronic system 1000 shown illustrates a first structure 1100F and a second structure 1100S for the semiconductor device 1100. For example, the circuit region 200 and the cell region 100 may respectively include... Figure 39The semiconductor chip 2200 shown is a portion of the first structure 3100 and the second structure 3200.

[0051] The circuit region 200 may include a peripheral circuit structure located on the first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH located on the second substrate 110, serving as a memory cell structure. The circuit region 200 may include a circuit wiring portion 290, and the cell region 100 may include a through contact 170 and a cell wiring portion 190 electrically connected to the memory cell structure.

[0052] In this embodiment, cell region 100 may be disposed on circuit region 200. Therefore, it is not necessary to separately ensure the area corresponding to circuit region 200 from cell region 100. Thus, the area of ​​semiconductor device 10 can be reduced. However, the embodiment is not limited to this, and circuit region 200 may be configured to be adjacent to cell region 100. Various other modified embodiments are possible.

[0053] Circuit region 200 may include a first substrate 210, and a surface of the first substrate 210. Figure 1 The circuit elements 220 and circuit wiring portions 290 on the upper surface of the circuit.

[0054] The first substrate 210 may be a semiconductor substrate comprising a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate comprising or formed of a semiconductor material, or a semiconductor substrate in which a semiconductor layer is on a base substrate. For example, the first substrate 210 may include single-crystal or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc., or may be formed from single-crystal or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc.

[0055] The circuit elements 220 on the first substrate 210 may include any of a variety of circuit elements that control the operation of the memory cell structure in the control unit region 100. For example, the circuit elements 220 may constitute a peripheral circuit structure, such as the decoder circuit 1110 (see reference 1110). Figure 37 Page buffer 1120 (reference) Figure 37 ), Logic circuit 1130 (reference) Figure 37 )wait.

[0056] Circuit element 220 may include, for example, multiple transistors, but the embodiments are not limited thereto. For example, circuit element 220 may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, inductors, etc.

[0057] Circuit wiring portions 290 on the first substrate 210 can be electrically connected to circuit elements 220. In an embodiment, the circuit wiring portions 290 may include a plurality of wiring layers 296 spaced apart from each other with an insulating layer 292 inserted therebetween, and electrically connected via contact vias 294 to form desired paths. The wiring layers 296 or contact vias 294 may include any of a variety of conductive materials, and the insulating layer 292 may include any of a variety of insulating materials. For example, the insulating layer 292 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, or be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0058] Cell region 100 may include cell array region 102 and connection region 104. In cell array region 102 and connection region 104, a stacked structure including gate stacked structure 120 and insulating stacked structure 120s may be formed on the second substrate 110. In cell array region 102, channel structure CH may pass through gate stacked structure 120. A structure connecting the gate electrode 130 and / or channel structure CH included in gate stacked structure 120 to circuit region 200 or external circuitry may be provided in cell array region 102 and / or connection region 104.

[0059] The gate stack structure 120, the insulating stack structure 120s, or the stack structure may include a first surface 120a and a second surface 120b opposite to each other. The first surface 120a of the gate stack structure 120, the insulating stack structure 120s, or the stack structure may be a surface adjacent to the channel pad 144 or the cell wiring portion 190 (e.g., the first wiring portion). Figure 1 The upper surface of the gate stack structure 120, the insulating stack structure 120s, or the second surface 120b of the stack structure may be a surface opposite to the channel pad 144 or the cell wiring portion 190 (e.g., the first wiring portion). Figure 1 (the lower surface of the middle).

[0060] In an embodiment, the second substrate 110 may include a semiconductor layer comprising a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate comprising or formed of a semiconductor material, or a semiconductor substrate in which the semiconductor layer is on a base substrate. For example, the second substrate 110 may include silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc., or may be formed of silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. A p-type dopant or an n-type dopant may be doped into the semiconductor layer included in the second substrate 110. For example, a p-type dopant may include boron (B), gallium (Ga), etc., or an n-type dopant may include phosphorus (P), arsenic (As), etc. However, the embodiments are not limited to the material of the second substrate 110, the conductivity type of the dopant doped into the semiconductor layer, etc.

[0061] In the cell array region 102, a gate stack structure 120 and a channel structure CH can be disposed. The gate stack structure 120 may include a cell insulating layer 132 (e.g., an interlayer insulating layer 132m) and a gate electrode 130 alternately stacked on the surface (e.g., the upper surface) of the second substrate 110. The channel structure CH may extend longitudinally through the gate stack structure 120 in a direction that intersects (e.g., perpendicularly) to the second substrate 110 (e.g., vertical direction) (Z-axis direction in the figure).

[0062] In this embodiment, horizontal conductive layers 112 and 114 may be disposed in the cell array region 102 between the second substrate 110 and the gate stack structure 120. Horizontal conductive layers 112 and 114 can electrically connect the channel structure CH and the second substrate 110. Horizontal conductive layers 112 and 114 can directly connect the channel structure CH and the second substrate 110. Horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 and / or a second horizontal conductive layer 114 sequentially located on the second substrate 110. The first horizontal conductive layer 112 may serve as part of the common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 may serve as a common source line together with the second substrate 110.

[0063] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may comprise a semiconductor material (e.g., polysilicon). For example, the first horizontal conductive layer 112 may comprise a polysilicon layer containing dopants. However, embodiments are not limited thereto; the second horizontal conductive layer 114 may comprise a material different from the material of the first horizontal conductive layer 112 (e.g., an insulating material) or be formed of a material different from the material of the first horizontal conductive layer 112 (e.g., an insulating material), or the second horizontal conductive layer 114 may be omitted.

[0064] A gate stack structure 120, in which interlayer insulating layers 132m and gate electrodes 130 are alternately stacked, can be disposed on a second substrate 110 (e.g., on a first horizontal conductive layer 112 and a second horizontal conductive layer 114 disposed on the second substrate 110). The gate electrode 130 may include a gate electrode electrically connected to a string select contact 172 (e.g., a first gate electrode 1301 and a second gate electrode 1302 (see reference)). Figure 5 )) and the gate electrodes electrically connected to the gate contact 180 (e.g., the third gate electrode 1303 to the tenth gate electrode 1310 (see reference) Figure 5 For example, the gate electrode (e.g., the first gate electrode 1301 and the second gate electrode 1302) electrically connected to the string select contact 172 can be a string select electrode. The gate electrode 130 may also include a dummy gate electrode, a ground select electrode, etc.

[0065] The gate electrode 130 may comprise any of a variety of conductive materials. For example, the gate electrode 130 may comprise a metallic material (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), polycrystalline silicon, metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or combinations thereof, or may be formed of a metallic material (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), polycrystalline silicon, metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or combinations thereof. Figure 2 As shown in the enlarged portion, a portion of an insulating material or a barrier layer 156 formed of an insulating material (e.g., a first barrier layer 156a) may be disposed outside the gate electrode 130. The interlayer insulating layer 132m may comprise any of a variety of insulating materials. For example, the interlayer insulating layer 132m may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric-constant material having a dielectric constant lower than that of silicon oxide, or a combination thereof.

[0066] In an embodiment, a channel structure CH may be disposed in the cell array region 102. The channel structure CH may extend to pass through the gate stack structure 120 in the thickness direction of the semiconductor device 10 (e.g., the Z-axis direction in the figure).

[0067] The channel structure CH may include a channel layer 140 and a gate dielectric layer 150 located on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may also include a core insulating layer 142 inside the channel layer 140. In some embodiments, the core insulating layer 142 may be omitted. The channel structure CH may also include channel pads 144 on the channel layer 140 and / or the core insulating layer 142. The gate dielectric layer 150 between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154, and a barrier layer 156 sequentially located on the channel layer 140.

[0068] Each channel structure CH can form a memory cell string, and multiple channel structures CH can be spaced apart from each other while forming rows and columns in a planar view. For example, multiple channel structures CH can be configured in any shape of various shapes such as a grid shape, a zigzag shape, etc., formed in a planar view. The channel structure CH can be cylindrical. For example, in a cross-sectional view, the channel structure CH can have sloping side surfaces, such that the width of the channel structure CH decreases towards the second substrate 110 due to the high aspect ratio. However, the embodiments are not limited to this, and various modifications can be made to the arrangement, structure, shape, etc. of the channel structures CH.

[0069] The channel layer 140 may include a semiconductor material (e.g., polysilicon). The core insulating layer 142 may include any of a variety of insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, or may be formed of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0070] The tunneling layer 152 may include an insulating material (e.g., silicon oxide, silicon oxynitride, etc.) capable of tunneling charges. The charge storage layer 154 may serve as a data storage region and may include polysilicon, silicon nitride, etc. The barrier layer 156 may include an insulating material capable of preventing unwanted charges from flowing into the gate electrode 130. For example, the barrier layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high-dielectric-constant material having a higher dielectric constant than silicon oxide, or a combination thereof, or may be formed of silicon oxide, silicon nitride, silicon oxynitride, a high-dielectric-constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In an embodiment, the barrier layer 156 may include a first barrier layer 156a and a second barrier layer 156b, the first barrier layer including a portion extending horizontally on the gate electrode 130, and the second barrier layer extending vertically between the first barrier layer 156a and the charge storage layer 154. The second barrier layer 156b may contact the first barrier layer 156a and the charge storage layer 154.

[0071] However, the materials, stacking structure, etc. of the channel layer 140, the core insulating layer 142, and the gate dielectric layer 150 can be modified in various ways, and the embodiments are not limited thereto.

[0072] The channel pad 144 may cover the upper surface of the core insulating layer 142 and is configured to be electrically connected to the channel layer 140. The channel pad 144 may contact the upper surface of the core insulating layer 142 and the side surface of the channel layer 140. The channel pad 144 may include a conductive material (e.g., doped polysilicon), but the embodiments are not limited thereto.

[0073] In an embodiment, the gate stack structure 120 may include a plurality of gate stack portions 121 and 122 stacked sequentially. Therefore, the number of stacked gate electrodes 130 can be increased, and thus the number of memory cells can be increased in a stable structure. Figure 1 The diagram illustrates a gate stack structure 120 including a first gate stack portion 121 and a second gate stack portion 122. In some embodiments, the gate stack structure 120 may include one gate stack portion or three or more gate stack portions.

[0074] When multiple gate stack portions 121 and 122 are provided as described above, the channel structure CH may include multiple channel portions CH1 and CH2 passing through the multiple gate stack portions 121 and 122, respectively. The multiple channel portions CH1 and CH2 may be connected to each other. In a cross-sectional view, each of the multiple channel portions CH1 and CH2 may have a sloping side surface, such that the width of each of the multiple channel portions CH1 and CH2 decreases towards the second substrate 110 due to a high aspect ratio. Bending portions resulting from the width difference of the multiple channel portions CH1 and CH2 may be provided at the boundary portions of the multiple channel portions CH1 and CH2. In some embodiments, the multiple channel portions CH1 and CH2 may have continuously extending sloping side surfaces without bending portions. Figure 2 In the illustration, as an example, each of the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of a plurality of channel portions CH1 and CH2 extends sequentially to have an integral structure. In some embodiments, the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of the plurality of channel portions CH1 and CH2 may be formed separately and electrically connected to each other. In some embodiments, individual channel pads may be additionally provided at the boundary portions of the plurality of channel portions CH1 and CH2. Therefore, the embodiments are not limited to the shape of the plurality of channel portions CH1 and CH2.

[0075] In an embodiment, the gate stack structure 120 may be divided into multiple portions by a separation structure 146 in a plan view. The separation structure 146 may extend to pass through or penetrate the gate stack structure 120 in the thickness direction of the semiconductor device 10 (e.g., the Z-axis direction in the figure). An upper separation region 148 may be disposed on the upper portion of the gate stack structure 120. In a plan view, the separation structure 146 and / or the upper separation region 148 may extend in a first direction (the X-axis direction in the figure). The plurality of separation structures 146 and / or the plurality of upper separation regions 148 may be spaced apart from each other at predetermined intervals in a second direction (the Y-axis direction in the figure).

[0076] The separation structure 146 or the upper separation region 148 may comprise any of a variety of insulating materials. For example, the separation structure 146 or the upper separation region 148 may comprise, or be formed of, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiments are not limited thereto, and various modifications may be made to the structure, shape, material, etc., of the separation structure 146 or the upper separation region 148.

[0077] A connection region 104, a through contact 170, and a cell wiring portion 190 may be provided to connect the gate stack structure 120 and the channel structure CH in the cell array region 102 to the circuit region 200 or external circuitry. The connection region 104 may be disposed on the periphery of the cell array region 102, and a portion of the through contact 170 and a portion of the cell wiring portion 190 may be disposed in the connection region 104.

[0078] The through-contact 170 may include a string select contact 172, a gate contact 180, a source contact 174, and input / output connection wiring 176. The string select contact 172 may be electrically connected to a portion of a plurality of gate electrodes 130 (e.g., a first gate electrode 1301 and a second gate electrode 1302). The gate contact 180 may be electrically connected to a portion of a plurality of gate electrodes 130 (e.g., a third gate electrode 1303 to a tenth gate electrode 1310). The source contact 174 may be electrically connected to horizontal conductive layers 112 and 114 and / or a second substrate 110.

[0079] Cell wiring portion 190 may include bit line 192, contact via 194, and connection wiring 196. Bit line 192 may extend in a second direction (Y-axis direction in the figure) intersecting (e.g., perpendicular to) the extension direction of gate electrode 130. Bit line 192 may be electrically connected to channel structure CH (e.g., channel pad 144) through contact via 194 (e.g., bit line contact via) passing through cell insulating layer 132. Contact via 194 may connect channel structure CH to bit line 192, or may connect string select contact 172, gate contact 180, source contact 174, or input / output connection wiring 176 to connection wiring 196. Connection wiring 196 may be electrically connected to bit line 192, string select contact 172, gate contact 180, source contact 174, or input / output connection wiring 176.

[0080] In an embodiment, the connection region 104 may include a first region 106 in which a gate stack structure 120 is disposed and a second region 108 in which an insulating stack structure 120s is disposed. The connection region 104 may also include regions other than the first region 106 and the second region 108.

[0081] In connection region 104, string select contact 172 may pass through gate stack structure 120 and may be electrically connected to a portion of a plurality of gate electrodes 130 (e.g., the first gate electrode 1301 and the second gate electrode 1302 serving as string gate electrodes). For example, string select contact 172 may pass through gate stack structure 120 in first region 106 and may be electrically connected to the first gate electrode 1301 and the second gate electrode 1302 serving as string gate electrodes.

[0082] In connection region 104, a plurality of gate contacts 180 may pass through insulating stack structure 120s and may be electrically connected to at least a portion of a plurality of gate electrodes 130 (e.g., the third gate electrode 1303 to the tenth gate electrode 1310 constituting a word line). For example, gate contacts 180 may pass through insulating stack structure 120s in second region 108 and be electrically connected to the third gate electrode 1303 to the tenth gate electrode 1310 constituting a word line. Gate contacts 180 may be electrically connected to the side surface of the gate electrode 130 disposed in first region 106. For example, each of the gate contacts 180 may contact the side surface of the corresponding gate electrode 130.

[0083] In the connection area 104, a penetration virtual structure DH can be further set (refer to...). Figure 3 The through-hole dummy structure DH can reduce the stress applied to the gate stack structure 120. For example, the through-hole dummy structure DH can be provided in the first region 106.

[0084] Please refer to later Figures 3 to 5The first region 106 and the second region 108, the string select contact 172, the gate contact 180, and the through-hole dummy structure DH are described in more detail.

[0085] In the connection region 104, the source contact 174 may pass through the cell insulating layer 132 and be electrically connected to the horizontal conductive layers 112 and 114 and / or the second substrate 110. The input / output connection wiring 176 may pass through the gate stack structure 120 or be disposed outside the gate stack structure 120 to be electrically connected to the circuit wiring portion 290 of the circuit region 200.

[0086] exist Figure 1 As an example, source contacts 174 and / or input / output connection wiring 176 are shown disposed in a region of connection region 104 in which cell insulating layer 132 is disposed but gate stack structure 120 and insulating stack structure 120s are not present. However, the embodiment is not limited to this, and source contacts 174 and / or input / output connection wiring 176 may be disposed in a second region 108 in which insulating stack structure 120s is disposed.

[0087] exist Figure 1 In the illustration, source contacts 174 and / or input / output connection wiring 176 are shown as having sloping side surfaces, such that the width of source contacts 174 and / or input / output connection wiring 176 decreases towards the second substrate 110 due to the aspect ratio, and in the cross-sectional view, bent portions are provided at the boundary portions of the plurality of gate stack portions 121 and 122. However, the embodiment is not limited thereto. In some embodiments, source contacts 174 and / or input / output connection wiring 176 may not include bent portions at the boundary portions of the plurality of gate stack portions 121 and 122. Various other modified embodiments are possible.

[0088] For clarity and to simplify the illustration, the cell wiring portion 190 is shown as an example comprising a single wiring layer disposed on the same plane as the bit line 192, and an insulating layer 132a disposed in an area outside the single wiring layer. However, the embodiments are not limited thereto. In some embodiments, for electrical connection to the bit line 192, the string select contact 172, the gate contact 180, the source contact 174, and / or the input / output connection wiring 176, the connection wiring 196 may include multiple wiring layers and may also include contact vias.

[0089] The unit wiring portion 190 can be electrically connected to the circuit wiring portion 290, so that the channel structure CH, the gate electrode 130, the horizontal conductive layers 112 and 114 and / or the second substrate 110 can be electrically connected to the circuit element 220 of the circuit region 200.

[0090] Reference Figures 3 to 5 as well as Figure 1 and Figure 2 The first region 106 and the second region 108 included in the connection region 104, as well as the string selection contact 172, the gate contact 180 and the through dummy structure DH disposed in the connection region 104, will be described in detail.

[0091] Figure 3 It is shown schematically. Figure 1 A plan view of a portion of the semiconductor device 10 shown. Figure 4 It is shown Figure 3 A magnified plan view of part D in the diagram. Figure 5 It is along Figure 3 The cross-sectional view taken from line E-E' in the diagram.

[0092] Reference Figures 1 to 5 In an embodiment, the connection region 104 may include a first region 106 in which a gate stack structure 120 is disposed and a second region 108 in which an insulating stack structure 120s is disposed.

[0093] In the first region 106, the gate stack structure 120 may be disposed on the second substrate 110 (e.g., on the horizontal conductive layers 112 and 114 disposed on the second substrate 110). Therefore, the gate stack structure 120 may be disposed in the cell array region 102 and the first region 106.

[0094] In the second region 108, the insulating stack structure 120s may be disposed on the second substrate 110 (e.g., on the horizontal conductive layers 112, 114 and / or the horizontal insulating layer 116 disposed on the second substrate 110).

[0095] The insulating stack structure 120s may include a plurality of unit insulating layers 132 (e.g., a plurality of interlayer insulating layers 132m) and a plurality of sacrificial insulating layers 130s that are stacked alternately on top of each other. In the insulating stack structure 120s, the plurality of sacrificial insulating layers 130s may be configured to correspond to a plurality of gate electrodes 130 respectively. The plurality of interlayer insulating layers 132m of the insulating stack structure 120s may be configured to correspond to interlayer insulating layers 132m of the gate stack structure 120 respectively. The sacrificial insulating layers 130s may include a material different from the material of the unit insulating layers 132 (e.g., interlayer insulating layers 132m). For example, the sacrificial insulating layers 130s may include silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride (SiONx), etc., or be formed of silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride (SiONx), etc., and may include a material different from the material of the unit insulating layers 132 (e.g., interlayer insulating layers 132m).

[0096] The multiple interlayer insulating layers 132m of the gate stack structure 120 and the multiple interlayer insulating layers 132m of the insulating stack structure 120s can be insulating layers formed by the same process. In the cell array region 102, the first region 106, and the second region 108, multiple interlayer insulating layers 132m and multiple sacrificial insulating layers 130s can be alternately stacked to form the insulating stack structure 120s. Subsequently, multiple sacrificial insulating layers 130s disposed in at least a portion of the cell array region 102 and the first region 106 can be selectively removed, and a gate electrode 130 can be formed in the portion where the sacrificial insulating layers 130s have been removed. Therefore, in at least a portion of the cell array region 102 and the first region 106, a gate stack structure 120 in which multiple interlayer insulating layers 132m and multiple gate electrodes 130 are alternately stacked can be provided. In the second region 108, the insulating stack structure 120s in which multiple interlayer insulating layers 132m and multiple sacrificial insulating layers 130s are alternately stacked can be retained.

[0097] The separation structure 146 may include a first separation structure 146a and a second separation structure 146b. The first separation structure 146a may extend in a first direction (the X-axis direction in the figure) to correspond to the cell array region 102, the first region 106, and the second region 108. The second separation structure 146b may be disposed between a plurality of first separation structures 146a (e.g., between two adjacent first separation structures 146a) and may extend to have a length smaller than that of the first separation structures 146a in the first direction. For example, the second separation structure 146b may be configured to correspond to a portion of the second region 108 disposed in a second direction (the Y-axis direction in the figure) and may be spaced apart from the second region 108 in the first direction. In the process of replacing the sacrificial insulating layer 130s with the gate electrode 130, the sacrificial insulating layer 130s may be retained in the portion spaced apart from the first separation structures 146a and the second separation structure 146b. The remaining portion of the sacrificial insulating layer 130s may constitute the second region 108.

[0098] For example, in the first direction (the X-axis direction in the figure), the first separation structure 146a can have a longer length than the upper separation region 148. Figure 4 As an example, the second separation structure 146b is shown to have a length less than that of the upper separation region 148, but the second separation structure 146b may have a length equal to or greater than that of the upper separation region 148.

[0099] The first region 106 may include a first region 106a and a second region 106b. In the first region 106a, the first separation structure 146a and the second separation structure 146b may be provided together. In the second region 106b, the first separation structure 146a may be provided without the second separation structure 146b.

[0100] The first region 106a can be positioned in the second direction (Y-axis direction in the figure) between the first separation structure 146a and the second separation structure 146b, between adjacent first separation structures 146a, or between adjacent second separation structures 146b. That is, in the second direction, two adjacent first regions 106a can be positioned with a first separation structure 146a or a second separation structure 146b inserted between them.

[0101] The second region 106b can be adjacent to two adjacent first separation structures 146a in the second direction (Y-axis direction in the figure), and the two second regions 106b adjacent to the two adjacent first separation structures 146a can be configured with a second region 108 inserted between them. For example, the two first regions 106 (that is, the two second regions 106b) can be adjacent to two adjacent first separation structures 146a in the second direction (Y-axis direction in the figure), and the two first regions 106 (that is, the two second regions 106b) adjacent to the two adjacent first separation structures 146a can be configured with a second region 108 inserted between them.

[0102] The second region 108 can be positioned between two adjacent first separation structures 146a in the second direction (Y-axis direction in the figure), and can be spaced apart from the second separation structure 146b in the first direction (X-axis direction in the figure). That is, the second region 108 can be spaced apart from the second separation structure 146b between two adjacent first separation structures 146a.

[0103] In the embodiment, a connection region 104 including a first region 106 and a second region 108 can be easily formed by using a first separation structure 146a and a second separation structure 146b with different lengths.

[0104] The string select contact 172 may be disposed in the first region 106 (e.g., first region 106a), and the gate contact 180 may be disposed in the second region 108. A through-dummy structure DH may be disposed in the first region 106 (e.g., first region 106a and / or second region 106b). For example, the through-dummy structure DH may be disposed around the string select contact 172 in the first region 106a, and may also be disposed in the second region 106b.

[0105] exist Figure 3 and Figure 5In the example shown, a through-dummy structure DH and a channel structure CH are formed using the same process and have the same structure, materials, etc., and the through-dummy structure DH has a planar shape and an area (e.g., planar area) identical to the planar shape and area of ​​the channel structure CH. The through-dummy structure DH may not be electrically connected to bit line 192. Therefore, the manufacturing process can be simplified. Furthermore, the through-dummy structure DH may have the same properties as the channel structure CH and can stably form the separation structure 146. However, the embodiments are not limited thereto. In some embodiments, the through-dummy structure DH may be formed using a different process than that used to form the channel structure CH, and may have a different structure, material, planar shape, area, etc., than the channel structure CH.

[0106] exist Figure 3 As an example, multiple through-dummy structures DH are shown configured to form a rectangular shape around the periphery of the string select contact 172 in a first region 106a and a Z-shaped shape in a second region 106b. However, the embodiments are not limited to this, and the arrangement of the through-dummy structures DH can be modified differently. In some embodiments, at least a portion of the through-dummy structures DH may be disposed across the edge of the gate electrode 130 and may reach or contact the separation structure 146. Various other modified embodiments are possible.

[0107] In this embodiment, the through-hole dummy structure DH can be disposed in the first region 106 (e.g., the first region 106a and / or the second region 106b), and the gate contact 180 can be disposed in the second region 108. Therefore, the through-hole dummy structure DH can be disposed independently in a space separate from the gate contact 180. That is, the through-hole dummy structure DH can be disposed in the first region 106 (e.g., the first region 106a and / or the second region 106b) to be separate from the gate contact 180 disposed in the second region 108. Therefore, the process for forming the gate contact 180 can be easily performed, and the stability of the gate contact 180 can be enhanced.

[0108] On the other hand, in comparative examples where the gate contact and the through-hole structure are adjacent to or overlap, during the process of forming the via for the gate contact, both the portion where the through-hole structure is provided and the portion where the through-hole structure is not provided can be removed together. Therefore, it may be difficult to form the via precisely at the desired location.

[0109] As described above, in the embodiments, the string select contact 172 may be disposed in the first region 106 (e.g., first region 106a) and may be distinct from the gate contact 180 disposed in the second region 108. Furthermore, the string select contact 172 may have a shape or structure different from that of the gate contact 180. The shape of the gate contact 180 will be described in detail, and the shape of the string select contact 172 will also be described in detail.

[0110] In this embodiment, a plurality of gate contacts 180 may be disposed in a second region 108 in which an insulating stack structure 120s is disposed, and may be electrically connected to at least a portion of a plurality of gate electrodes 130 disposed in a first region 106 (e.g., the third gate electrode 1303 to the tenth gate electrode 1310). For example, the side surface of the connection portion 180c of the gate contact 180 disposed in the second region 108 may be electrically connected to the side surface of the gate electrode 130 disposed in the first region 106. For example, the side surface of the connection portion 180c of the gate contact 180 disposed in the second region 108 may contact the side surface of the gate electrode 130 disposed in the first region 106.

[0111] Each of the plurality of gate contacts 180 may include a conductive portion 180a and a side insulating layer 180b. The conductive portion 180a may include a through portion 180p and a connection portion 180c. The through portion 180p may pass through the insulating stack structure 120s, and the connection portion 180c may extend horizontally to have an area larger than that of the through portion 180p. The side insulating layer 180b may be disposed on at least a portion of the side surface of the conductive portion 180a. In a plan view, the connection portion 180c may have a shape that protrudes from the through portion 180p.

[0112] The penetrating portion 180p may extend in the thickness direction (Z-axis direction in the figure) of the semiconductor device 10 to pass through the insulating stack structure 120s, and the connecting portion 180c may extend horizontally to have an area larger than that of the penetrating portion 180p. The penetrating portion 180p may be spaced apart from the first region 106, and the connecting portion 180c may extend horizontally to connect to (e.g., contact) the gate electrode 130 disposed in the first region 106. For example, the connecting portion 180c may extend horizontally to contact the side surface of the corresponding gate electrode 130. For example, the connecting portion 180c may have a flange shape.

[0113] For example, the conductive portion 180a may include or be formed of tungsten (W), copper (Cu), aluminum (Al), etc., and may also include a diffusion barrier layer. However, the embodiments are not limited to the material of the conductive portion 180a. For example, the side insulating layer 180b may include oxides (e.g., silicon oxide), oxynitrides (e.g., silicon oxynitride), low dielectric constant materials having a lower dielectric constant than silicon oxide, or combinations thereof, or may be formed of oxides (e.g., silicon oxide), oxynitrides (e.g., silicon oxynitride), low dielectric constant materials having a lower dielectric constant than silicon oxide, or combinations thereof. The side insulating layer 180b may include a single layer or multiple layers. However, the embodiments are not limited thereto, and the conductive portion 180a or the side insulating layer 180b may include any of the various materials.

[0114] Multiple gate contacts 180 (e.g., multiple connection portions 180c included in the multiple gate contacts 180) can be respectively connected to multiple gate electrodes 130. In the thickness direction (Z-axis direction in the figure) of the semiconductor device 10, the multiple gate electrodes 130 can be disposed at different heights or different levels, and the multiple connection portions 180c of the multiple gate contacts 180 can be disposed at different heights or different levels. At least a portion of the penetration portion 180p (e.g., a portion of the penetration portion 180p on the first surface of the connection portion 180c) can pass through a portion of the gate stack structure 120, such that the connection portion 180c of the gate contact 180 is electrically connected to the connecting gate electrode.

[0115] For example, a first gate contact 1801 (e.g., a connection portion 180c included in the first gate contact 1801) can be electrically connected to a third gate electrode 1303. An nth gate contact (e.g., a connection portion 180c included in the nth gate contact) can be electrically connected to a (n+2)th gate electrode. In the figures, as an example, gate electrodes 130 electrically connected to gate contacts 180 are shown to include third gate electrodes 1303 to tenth gate electrodes 1310. In this case, first gate contacts 1801 to eighth gate contacts 1808 can be electrically connected to third gate electrodes 1303 to tenth gate electrodes 1310, respectively. Therefore, a plurality of gate contacts 180 can be electrically connected to a plurality of gate electrodes 130, respectively.

[0116] Based on a gate contact 180, a plurality of gate electrodes 130 may include a connection gate electrode electrically connected to the gate contact 180, and may include a through gate electrode and / or a residual gate electrode. A through gate electrode may refer to a gate electrode 130 disposed above the connection gate electrode and penetrated by the gate contact 180. The through gate electrode may include a string select electrode. A residual gate electrode refers to a gate electrode 130 below the connection gate electrode. The residual gate electrode may or may not be penetrated by the gate contact 180.

[0117] In an embodiment, a plurality of vias PH may individually pass through an insulating stack structure 120s and be spaced apart from each other when the insulating stack structure 120s is inserted therebetween. Each of the gate contacts 180 may be disposed in a corresponding one of the vias PH. The side surface of the connection portion 180c of each gate contact 180 in each via PH may be connected to (e.g., contact) the side surface of the gate electrode 130. In some embodiments, a plurality of gate contacts 180 may be disposed in a plurality of vias PH spaced apart from each other, corresponding one-to-one with the plurality of gate contacts 180. In an embodiment, a portion of the via PH may have any of a variety of planar shapes such as circular, polygonal, elliptical, etc., but the embodiments are not limited to the planar shape of the via PH.

[0118] In an embodiment, the gate stack structure 120 may be disposed in the entire portion of the first region 106 (e.g., first region 106a and / or second region 106b), except for the separation structure 146 and the upper separation region 148. For example, in the first region 106 (e.g., first region 106a and / or second region 106b), the extension lengths of the plurality of gate electrodes 130 may be substantially the same. "Substantially the same" may mean having a difference within process tolerances (e.g., less than 10%). In an embodiment, the portion (e.g., pad area) in which the gate stack structure 120 is removed to have a stepped shape for electrical connection between the gate electrodes 130 and the gate contacts 180, or the insulating layer in that portion (e.g., pad insulating layer), may not be provided. That is, without the pad area or pad insulating layer, the plurality of gate electrodes 130 may be individually electrically connected to the plurality of gate contacts 180. Therefore, the process of electrically connecting the gate contacts 180 to the gate electrodes 130 can be simplified, and the area of ​​the connection region 104 can be reduced.

[0119] On the other hand, in a comparative example including a pad region, the process involves etching the gate stack structure (e.g., forming a portion of a stepped shape), forming a pad insulating layer covering the gate stack structure, and electrically connecting multiple gate contacts passing through a pad insulating layer to multiple gate electrodes. Therefore, the processes for forming the pad region and forming the gate contacts can be complex. In the pad region or pad insulating layer through which the multiple gate contacts pass, the spacing between the multiple gate contacts can be large to prevent misalignment of the gate contacts. Therefore, the area of ​​the connection region can be large.

[0120] In an embodiment, the plurality of connection portions 180c included in a plurality of gate contacts 180 adjacent to each other along a first direction (X-axis direction in the figure) can be configured such that at least one sacrificial insulating layer 130s is inserted therebetween in the thickness direction (Z-axis direction in the figure) of the semiconductor device 10. Thus, at least one sacrificial insulating layer 130s can be disposed between the plurality of connection portions 180c included in a plurality of gate contacts 180 adjacent to each other along the first direction, thereby improving physical and electrical stability.

[0121] This could be because the distance between the plurality of gate contacts 180 in the second direction (the Y-axis direction in the figure) can be greater than the distance between the plurality of gate contacts 180 in the first direction (the X-axis direction in the figure). However, the embodiments are not limited to this, and the distance between the plurality of gate contacts 180 in the second direction can be equal to or less than the distance between the plurality of gate contacts 180 in the first direction.

[0122] For example, in Figure 4 In the illustration, as an example, a first gate contact 1801, a third gate contact 1803, a fifth gate contact 1805, and a seventh gate contact 1807 are arranged in a first row in a second direction (the Y-axis direction in the figure), and a second gate contact 1802, a fourth gate contact 1804, a sixth gate contact 1806, and an eighth gate contact 1808 are arranged in a second row in the second direction. The first gate contact 1801, third gate contact 1803, fifth gate contact 1805, and seventh gate contact 1807 can be arranged sequentially in the first direction. The second gate contact 1802, fourth gate contact 1804, sixth gate contact 1806, and eighth gate contact 1808 can be arranged sequentially in the first direction. However, the embodiment is not limited to this. In the second direction, it may include a single row in which the gate contacts 180 are arranged, or it may each include three or more rows in which the gate contacts 180 are arranged. Various modifications can be made to the arrangement of the plurality of gate contacts 180.

[0123] exist Figure 4In the diagram, as an example, a first gate contact 1801, a third gate contact 1803, a fifth gate contact 1805, and a seventh gate contact 1807 are shown disposed at a first position in a second direction (the Y-axis direction in the figure), and are configured to have the same spacing in the first direction. Figure 4 In the example shown, the second gate contact 1802, the fourth gate contact 1804, the sixth gate contact 1806, and the eighth gate contact 1808 are disposed at a second position in a second direction and are arranged to have the same spacing in a first direction. However, the embodiment is not limited thereto. See also Figure 34 The embodiments will be described in detail later.

[0124] exist Figure 4 As an example, the diagram shows multiple connections 180c within a plurality of adjacent gate contacts 180 arranged along a first direction (X-axis direction in the figure) and a second direction (Y-axis direction in the figure) that do not overlap. However, the embodiment is not limited to this, and the multiple connections 180c within a plurality of adjacent gate contacts 180 arranged along the first and / or second directions can be configured to partially overlap. In this case, the multiple connections 180c can be electrically insulated from each other by an interlayer insulating layer 132m and / or a sacrificial insulating layer 130s between the multiple connections 180c. This reduces the distance between the multiple gate contacts 180 and the area of ​​the connection region 104.

[0125] In an embodiment, the plurality of gate contacts 180 may include a first contact 1810.

[0126] In the first contact 1810, the penetrating portion 180p may be included on the first surface of the connecting portion 180c. Figure 5 The first part 181p on the upper surface of the middle and the second surface of the connecting part 180c Figure 5 The second portion 182p is on the lower surface of the connecting portion 180c. The first surface and the second surface of the connecting portion 180c can be opposite each other. The first portion 181p and the second portion 182p of the penetrating portion 180p can be disposed on opposite surfaces and inserted into the connecting portion 180c. In the first contact 1810, the side insulating layer 180b can be disposed on the side surface of the first portion 181p and can be spaced apart from the second portion 182p. That is, the side insulating layer 180b can be disposed on the side surface of the first portion 181p and can be not disposed on the side surface of the second portion 182p.

[0127] The connecting portion 180c may be disposed between the first portion 181p and the second portion 182p, and may have an area (e.g., planar area) larger than the area (e.g., planar area) of the first portion 181p and the second portion 182p. For example, when viewed in cross-section, the horizontal width of the connecting portion 180c may be greater than the horizontal width of the first portion 181p and the horizontal width of the second portion 182p.

[0128] The first portion 181p may extend in the thickness direction (Z-axis direction in the figure) of the semiconductor device 10. The first portion 181p may extend from the first surface 120a of the stacked structure (e.g., the insulating stacked structure 120s). Figure 5 The upper surface of the middle part extends to the first surface of the connecting part 180c.

[0129] The second portion 182p may extend in the thickness direction (Z-axis direction in the figure) of the semiconductor device 10. The second portion 182p may extend from the second surface of the connection portion 180c to the second surface 120b of the stacked structure (e.g., the insulating stacked structure 120s).

[0130] The penetration portion 180p of the first contact 1810 may include a first portion 181p and a second portion 182p, and the first portion 181p and the second portion 182p of the penetration portion 180p may help improve the performance of the semiconductor device 10. In some embodiments, the first contact 1810 may be a first connecting contact electrically connected to a first wiring portion and a second wiring portion on opposite sides of a stacked structure, and may improve the degree of freedom of wiring included in the semiconductor device 10. In some embodiments, an extension portion 180e (refer to the second portion 182p) configured to release stress applied to the semiconductor device 10 may be provided in a portion of the penetration portion 180p (e.g., the second portion 182p). Figures 18 to 20 ). Reference Figures 18 to 20 This will be described in detail later.

[0131] In an embodiment, the first contact 1810 is electrically connected via a first portion 181p to a first wiring portion (e.g., cell wiring portion 190) on a first surface 120a of the stacked structure (e.g., an insulating stacked structure 120s), and via a second portion 182p to a second wiring portion (e.g., circuit wiring portion 290) on a second surface 120b of the stacked structure (e.g., an insulating stacked structure 120s). That is, the first contact 1810 can be a first connecting contact that is electrically connected to the first wiring portion and the second wiring portion on opposite sides of the stacked structure.

[0132] The first connection contact can pass through the entire insulating stack structure 120s and be electrically connected to the first wiring portion and the second wiring portion, and can be referred to as the cell gate contact.

[0133] When the first contact 1810 is the first connecting contact, a voltage or signal can be applied to the opposite side of the gate contact 180. This increases the freedom of wiring included in the semiconductor device 10.

[0134] For example, the conductive portion 180a of the first contact 1810 can be a base contact that includes a penetrating portion 180p and a connecting portion 180c but does not include an extension portion. When the first contact 1810 is a base contact, the manufacturing process can be simplified.

[0135] exist Figure 5 In the illustration, a plurality of gate contacts 180 are shown as an example, including a plurality of first contacts 1810, each of which is a first connecting contact and a base contact. However, the embodiment is not limited thereto. The plurality of gate contacts 180 may also include contacts having a structure or shape different from that of the first contacts 1810, or the first contacts 1810 may include second connecting contacts different from the first connecting contacts, extension contacts other than base contacts, etc. (See also...) Figures 17 to 20 This will be described in detail later.

[0136] exist Figure 5 As an example, a penetrating insulating portion 110i is shown passing through the second substrate 110 and / or the horizontal conductive layers 112 and 114, and a second portion 182p of the first contact 1810 passes through the penetrating insulating portion 110i to be electrically connected to the circuit region 200. The penetrating insulating portion 110i may include any of a variety of insulating materials. However, the embodiments are not limited thereto, and the electrical connection structure between the second portion 182p of the first contact 1810 and the circuit region 200 can be modified in various ways.

[0137] The side insulating layer 180b may be disposed on the side surface of the first portion 181p, but may not be disposed on the side surface of the connector 180c and the side surface of the second portion 182p. For example, the side insulating layer 180b may surround the side surface of the first portion 181p. The side insulating layer 180b may protect the portion of the insulating stack structure 120s surrounding the first portion 181p during the process of forming the connector 180c. However, the embodiment is not limited to this, and various modifications may be made to the position of the side insulating layer 180b, etc.

[0138] For example, the penetration portion 180p (e.g., the first portion 181p and / or the second portion 182p) may be cylindrical (e.g., a cylindrical shape with a planar shape or a circular or polygonal shape), and the side insulating layer 180b may be any of a variety of planar shapes such as annular, frame shape, etc., to surround the first portion 181p.

[0139] In the accompanying drawings, by way of example, the penetrating portion 180p (e.g., the first portion 181p and / or the second portion 182p) is shown in a cross-sectional view to have inclined side surfaces, such that the width of the penetrating portion 180p decreases toward the second substrate 110 due to the high aspect ratio. However, the embodiments are not limited to this, and the shape, structure, etc. of the penetrating portion 180p can be modified in various ways.

[0140] In an embodiment, the gate contact 180 can be formed by a process including a multi-part etching process using a binary system. For example, the process for forming the first contact 1810 may include a first etching process (see reference). Figures 7 to 10 The process for forming the side insulating layer 180b (refer to) Figure 13 The process for forming the through-hole PH connection (refer to) Figure 14 ), second etching process (refer to Figure 15 ) and the process for forming the conductive portion 180a (refer to Figure 16 In the first etching process, the first through-hole portion of the via PH can be formed in the portion where the first portion 181p will be formed. In the process of forming the side insulating layer 180b, the side insulating layer 180b can be formed on the side surface of the first through-hole portion of the via PH. In the process of forming the connection through-hole portion of the via PH, the connection through-hole portion of the via PH can be formed in the portion where the connection portion 180c will be provided. In the second etching process, the second through-hole portion of the via PH can be formed in the portion where the second portion 182p will be formed. The first etching process may include a multi-part etching process using a binary system.

[0141] By repeatedly performing the partial etching process according to the binary system as described above, multiple first through-hole portions with different depths can be formed with a small number of etching processes. For example, when the partial etching process according to the binary system is repeated four times, fifteen first through-hole portions with different depths can be formed. For example, when the partial etching process according to the binary system is repeated five times, thirty-one first through-hole portions with different depths can be formed. For example, when the partial etching process according to the binary system is repeated six times, sixty-three first through-hole portions with different depths can be formed. Therefore, the number of etching processes can be effectively reduced. The number of multiple partial etching processes can be modified differently depending on the number of gate electrodes 130, and in some embodiments, an additional etching process can be performed after the multiple partial etching processes to achieve a predetermined depth.

[0142] The process of forming the gate contact 180 (e.g., the first contact 1810) will be described in detail in the method of manufacturing the semiconductor device 10.

[0143] In an embodiment, the string select contact 172 may be arranged in a first region 106 (e.g., first region 106a). The string select contact 172 may include a conductive portion 172a passing through the gate stack structure 120 and a side insulating layer 172b disposed on a side surface of the conductive portion 172a. The conductive portion 172a may correspond to a first portion 181p of the first contact 1810, and the side insulating layer 172b may be disposed on the entire side surface of the conductive portion 172a. Therefore, the string select contact 172 may not include portions in which the side insulating layer 172b is not disposed (e.g., portions corresponding to the second portion 182p of the first contact 1810) and portions corresponding to horizontally extending portions (e.g., connection portions 180c of the gate contact 180).

[0144] The string select contact 172, or the conductive portion 172a therein, can extend downward from the first surface 120a toward the second surface 120b of the gate stack structure 120, and can pass through a portion of the gate stack structure 120 in the thickness direction (Z-axis direction in the figure) of the semiconductor device 10. For example, the string select contact 172, or the conductive portion 172a therein, can be electrically connected to the upper surface of the string select electrode (e.g., the first gate electrode 1301 or the second gate electrode 1302). For example, the string select contact 172, or the conductive portion 172a therein, can contact the upper surface of the string select electrode (e.g., the first gate electrode 1301 or the second gate electrode 1302). However, the embodiments are not limited thereto. Each string select contact 172 can be electrically connected to another portion (e.g., a side surface) of the string select electrode (e.g., the first gate electrode 1301 or the second gate electrode 1302). For example, each string select contact 172 can contact another portion of the string select electrode (e.g., the first gate electrode 1301 or the second gate electrode 1302).

[0145] For example, multiple string select contacts 172 can be respectively connected to multiple string select electrodes (e.g., the first gate electrode 1301 and the second gate electrode 1302). In the thickness direction (Z-axis direction in the figure) of the semiconductor device 10 (e.g., in the vertical direction), the multiple string select electrodes (e.g., the first gate electrode 1301 and the second gate electrode 1302) can be disposed at different heights or different levels, and the multiple string select contacts 172 can have different depths to reach the multiple string select electrodes respectively. For example, the first string select contact can be electrically connected to the first string select electrode (e.g., the first gate electrode 1301), and the second string select contact can be electrically connected to the second string select electrode (e.g., the second gate electrode 1302).

[0146] The accompanying drawings and description illustrate, by way of example, two string select gates and two string select contacts 172. However, the string select gates may include one, three or more string select gates, and the string select contacts 172 may include one or more string select contacts electrically connected to one, three or more string select gates, respectively.

[0147] In this embodiment, the process of forming the string select contact 172 may include an etching process for forming a via PH, a process for forming a side insulating layer 172b, and a process for forming a conductive portion 172a. In the etching process for forming the via PH, the via PH may be formed in the portion where the conductive portion 172a will be formed. In the process for forming the side insulating layer 172b, the side insulating layer 172b may be formed on the side surface of the via PH. That is, the process of forming the string select contact 172 may not include the process of forming the through-hole portion of the via PH and the second etching process.

[0148] In this embodiment, the via PH for which the string select contact 172 is to be configured can be formed using at least a portion of the first etching process for forming the gate contact 180, or using an additional etching process performed separately from the first etching process for forming the gate contact 180. For example, the additional etching process can be performed before or after the first etching process. The side insulating layer 172b of the string select contact 172 can be formed using at least a portion of the process for forming the side insulating layer 180b of the gate contact 180, or using an additional process performed separately from the process for forming the side insulating layer 180b of the gate contact 180. The conductive portion 172a of the string select contact 172 can be formed using at least a portion of the process for forming the conductive portion 180a of the gate contact 180, or using an additional process performed separately from the process for forming the conductive portion 180a of the gate contact 180.

[0149] According to an embodiment, a first etching process including a partial etching process according to a binary system can be used to form the first through-portion of the gate contact 180, which can simplify the process of forming the gate contact 180 and reduce the area of ​​the connection region 104. The gate contact 180 can be disposed in an insulating stack structure 120s to be disposed in a space separated from the through-hole dummy structure DH, and the first through-portion of the via PH can be stably formed. For example, if process errors may be undesirably caused in the process of forming the first through-portion of the via PH, the gate contact 180 can be disposed in the insulating stack structure 120s to prevent or minimize undesirable electrical short circuits. The gate contact 180 may include a horizontally extending connection portion 180c and can be easily electrically connected to the gate electrode 130 included in the gate stack structure 120. In the first contact 1810 of the gate contact 180, the through-portion 180p may include a first portion 181p and a second portion 182p on the first surface and the second surface of the connection portion 180c, respectively, and can be used to improve the performance of the semiconductor device 10. This can improve the performance and reliability of the semiconductor device 10.

[0150] In the following text, refer to Figures 6 to 16 The following describes in detail a method for manufacturing a semiconductor device according to an embodiment. To the extent that no element is described in detail below, it will be understood that the element is at least similar to a corresponding element already described elsewhere in this disclosure. Parts not described above will be described in detail.

[0151] Figures 6 to 16 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 6 and Figure 12 It shows the relationship with along Figure 3 The corresponding parts intercepted by lines A-A' and C-C' in the diagram. Figures 7 to 11 as well as Figures 13 to 16 It shows the corresponding Figure 3 The portion of line C-C' in the diagram. The following mainly describes the gate stack structure 120, the channel structure CH, the separation structure 146, and the gate contact 180 in the semiconductor device manufacturing method.

[0152] like Figure 6 As shown, a second substrate 110 and an insulating stack structure 120s can be formed on the circuit region 200, and a channel structure CH extending through the insulating stack structure 120s can be formed. For example, after forming a horizontal insulating layer 116 and a second horizontal conductive layer 114, the insulating stack structure 120s can be formed on the horizontal insulating layer 116 and the second horizontal conductive layer 114 on the second substrate 110. The channel structure CH can extend through the insulating stack structure 120s, the second horizontal conductive layer 114, and the horizontal insulating layer 116.

[0153] For example, a second substrate 110 may be formed on the circuit region 200, and a horizontal insulating layer 116, a second horizontal conductive layer 114, and an insulating stack structure 120s may be formed on the second substrate 110. The insulating stack structure 120s may be formed by alternately stacking an interlayer insulating layer 132m and a sacrificial insulating layer 130s.

[0154] A portion of the sacrificial insulating layer 130s can be processed by the gate electrode 130 (see reference). Figure 12 The horizontal insulating layer 116 can be replaced by the first horizontal conductive layer 112 (see reference 112). Furthermore, it can be formed to include a portion in which the gate electrode 130 will be disposed. Through subsequent processes, at least a portion of the horizontal insulating layer 116 can be replaced by the first horizontal conductive layer 112 (see reference 112). Figure 12 Instead, it can be formed to include a portion in which the first horizontal conductive layer 112 will be disposed.

[0155] The horizontal insulating layer 116 and / or the sacrificial insulating layer 130s may include or be formed of a material different from or from the material of the interlayer insulating layer 132m. For example, the interlayer insulating layer 132m may include at least one of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, etc., or may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, etc. The sacrificial insulating layer 130s may include or be formed of at least one of silicon, silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, or may include or be formed of a material different from or from the material of the interlayer insulating layer 132m.

[0156] Before forming the insulating stack structure 120s, a penetrating insulating portion 110i may be formed through the second substrate 110, the second horizontal conductive layer 114, and the horizontal insulating layer 116. The penetrating insulating portion 110i may be formed in which a gate contact 180 (see reference 120s) will be disposed. Figure 16 In the portion where the gate contact 180 (e.g., the first contact 1810) will be located. To form the penetrating insulating portion 110i, a penetrating portion may be formed in the portion where the gate contact 180 (e.g., the first contact 1810) will be located, and an insulating material may be filled in the penetrating portion. However, the embodiments are not limited to this, and the penetrating insulating portion 110i may include any material of various kinds and may be formed by any process of various kinds of processes.

[0157] In an embodiment, the insulating stack structure 120s may include a plurality of insulating stack portions 121s and 122s sequentially stacked on the second substrate 110, and the channel structure CH may include a plurality of channel portions passing through the plurality of insulating stack portions 121s and 122s respectively. However, the embodiment is not limited thereto.

[0158] In an embodiment, the insulating stack structure 120s may be disposed in the unit array region 102 and the connection region 104. In the connection region 104, the insulating stack structure 120s may be formed to include a connection with the first region 106 (see reference 104). Figure 12 ) and Zone 108 (refer to) Figure 12 The corresponding part.

[0159] A preliminary through-passage through the insulating stack structure 120s can be formed in the portion where the channel structure CH will be formed, and the channel structure CH can be formed in the preliminary through-passage. The process of forming the preliminary through-passage can be performed by any of a variety of etching processes (e.g., dry etching process). The gate dielectric layer 150 (see reference) can be formed sequentially. Figure 2 ), channel layer 140 (reference) Figure 2 ) and core insulation layer 142 (refer to) Figure 2 And it can form channel pads 144 (refer to) Figure 2 To form the channel structure CH. The process of forming the gate dielectric layer 150, channel layer 140, core insulating layer 142, or channel pad 144 can be performed using any of various processes (e.g., deposition processes, etc.). A portion of the gate dielectric layer 150 (e.g., the first barrier layer 156a (see reference)) Figure 2 It may not be formed, but it can be formed in subsequent processes.

[0160] In the process of forming the channel structure CH, the through-hole virtual structure DH can be formed simultaneously (see reference). Figure 5 However, the embodiments are not limited thereto.

[0161] In the embodiment, as an example, the first through portion P1 of the via formed after the formation of the channel structure CH is described (refer to...). Figure 10 However, the embodiments are not limited thereto. In some embodiments, before forming the first through portion P1, a preliminary through portion through the insulating stack structure 120s may be formed in the portion where the channel structure CH will be formed, and a channel sacrificial layer may be formed by filling the preliminary through portion with sacrificial material. After forming the first through portion P1, the channel sacrificial layer may be removed, and the channel structure CH may be formed.

[0162] Subsequently, as Figures 7 to 10 As shown, by performing the first etching process, a plurality of vias PH can be formed in the portion of the first portion 181p where a plurality of gate contacts 180 will be formed (see reference). Figure 15 The first through portion P1 of the multiple vias PH can be formed in the first etching process by using multiple part etching processes of the binary system (e.g., first to fourth part etching processes E1, E2, E3 and E4).

[0163] To ensure clarity and simplify the illustration, Figures 7 to 10 In the example shown, the gate electrode 130 (refer to) is shown. Figure 12 The number of sacrificial insulating layers replaced by 130s is ten (10), and the first to fourth part etching processes E1, E2, E3 and E4 are performed. For clarity, Figures 7 to 10 The positions of the first via PH1, third via PH3, fifth via PH5, and seventh via PH7, corresponding to the first gate contact, third gate contact, fifth gate contact, and seventh gate contact, are shown. However, the embodiments are not limited to this; the number of sacrificial insulating layers 130s can be modified differently, and the number of partial etching processes can be modified differently depending on the number of sacrificial insulating layers 130s.

[0164] In an embodiment, the location of the sacrificial insulating layer 130s where the gate electrode 130 will be replaced (e.g., a vertical or horizontal location) can be converted to a binary system. Accordingly, multiple partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4) can be performed to form multiple first to third portions P1 of multiple vias PH with different depths. Additional partial etching processes can also be performed after the first to fourth partial etching processes E1, E2, E3, and E4.

[0165] Multiple partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4) can be cyclic etching processes. In each partial etching process, a mask configured to expose a predetermined portion can be formed, a partial etching process according to a binary system can be performed, and the mask can be removed. In additional partial etching processes, a mask configured to expose a predetermined portion can be formed, an etching process according to a binary system or a sequential etching process can be performed, and the mask can be removed. The mask can include a photosensitive material or a photoresist layer or a hard mask layer formed of a photosensitive material. In the first to fourth partial etching processes E1, E2, E3, and E4 and / or the additional partial etching processes, the etching of the insulating stack structure 120s can be performed by any of a variety of etching processes (e.g., dry etching processes, etc.).

[0166] For example, in a multi-part etching process using a binary system (e.g., first to fourth part etching processes E1, E2, E3, and E4), 1, 2, 4, ..., 2 can be etched according to the binary system. (n-1) Each interlayer insulation layer is 132m or the sacrificial insulation layer is 130s.

[0167] For example, the position of the third sacrificial insulating layer corresponding to the third gate electrode electrically connected to the first gate contact (i.e., 3) can be converted to 11 according to the binary system, and the first through portion P1 of the first via PH1 can be formed by performing the first partial etching process E1 and the second partial etching process E2. For example, the position of the fifth sacrificial insulating layer corresponding to the fifth gate electrode electrically connected to the third gate contact (i.e., 5) can be converted to 101 according to the binary system, and the first through portion P1 of the third via PH3 can be formed by performing the first partial etching process E1 and the third partial etching process E3. For example, the position of the seventh sacrificial insulating layer corresponding to the seventh gate electrode electrically connected to the fifth gate contact (i.e., 7) can be converted to 111 according to the binary system, and the first through portion P1 of the fifth via PH5 can be formed by performing the first partial etching process E1, the second partial etching process E2, and the third partial etching process E3. For example, the position of the ninth sacrificial insulating layer corresponding to the ninth gate electrode that is electrically connected to the seventh gate contact can be converted to 1001 according to the binary system, and the first through portion P1 of the seventh via PH7 can be formed by performing the first part etching process E1 and the fourth part etching process E4.

[0168] In the following text, refer to Figures 7 to 10 The first through hole PH1, the third through hole PH3, the fifth through hole PH5, and the seventh through hole PH7 can be described in more detail.

[0169] like Figure 7As shown, in the first etching process E1, portions of multiple vias PH corresponding to the first etching process E1 can be selectively etched. For example, in the first etching process E1, an interlayer insulating layer 132m can be etched in the portions corresponding to the first via PH1, the third via PH3, the fifth via PH5, and the seventh via PH7.

[0170] Subsequently, as Figure 8 As shown, in the second etching process E2, portions of multiple vias PH corresponding to the second etching process E2 can be selectively etched. For example, in the second etching process E2, in the portions corresponding to the first via PH1 and the fifth via PH5, two interlayer insulating layers 132m and a sacrificial insulating layer 130s thereon can be etched.

[0171] Subsequently, as Figure 9 As shown, in the third etching process E3, the portions of multiple vias PH corresponding to the third etching process E3 can be selectively etched. For example, in the third etching process E3, in the portions corresponding to the third via PH3 and the fifth via PH5, four interlayer insulating layers 130m and the sacrificial insulating layer 130s thereon can be etched.

[0172] Subsequently, as Figure 10 As shown, in the fourth etching process E4, the portions of multiple vias PH corresponding to the fourth etching process E4 can be selectively etched. For example, in the fourth etching process E4, in the portion corresponding to the seventh via PH7, eight interlayer insulating layers 130m and the sacrificial insulating layer 130s thereon can be etched.

[0173] However, the embodiments are not limited to partial etching processes, and various modifications can be made to partial etching processes using binary systems.

[0174] Subsequently, as Figure 11 As shown, the protective insulating layer 180t and the penetrating sacrificial layer 180s can be formed in each of the plurality of first penetrating portions P1.

[0175] A protective insulating layer 180t may be disposed in each of the plurality of first through portions P1. For example, the protective insulating layer 180t may be formed on the inner surface and lower surface of each of the plurality of first through portions P1. The process of forming the protective insulating layer 180t may be performed by any of a variety of processes (e.g., deposition processes, etc.). However, the embodiments are not limited thereto.

[0176] After the protective insulating layer 180t is formed, a penetration sacrificial layer 180s can be formed on the protective insulating layer 180t in the first penetration portion P1. The penetration sacrificial layer 180s may include at least one of polysilicon, tungsten, titanium nitride, and carbon, or may be formed from at least one of polysilicon, tungsten, titanium nitride, and carbon. However, the embodiments are not limited thereto, and the penetration sacrificial layer 180s may include any of a variety of materials.

[0177] Subsequently, as Figure 12 As shown, a gate electrode 130 and a separation structure 146 can be formed. The separation structure 146 may include a first separation structure 146a (see reference). Figure 3 ) and the second separation structure 146b (refer to) Figure 3 In the plan view, the first separation structure 146a and the second separation structure 146b can have different lengths.

[0178] An opening for the separation structure can be formed in the region corresponding to the separation structure 146, passing through the insulating stack structure 120s. The sacrificial insulating layer 130s can be replaced by the gate electrode 130, and the opening for the separation structure can be filled with insulating material or the like to form the separation structure 146.

[0179] In an embodiment, openings for the separation structure can be formed by an etching process (e.g., dry etching). The sacrificial insulating layer 130s can be selectively removed via these openings by an etching process (e.g., wet etching). For example, a portion of the sacrificial insulating layer 130s in the cell array region 102 and the first region 106 of the connection region 104 can be selectively removed. Another portion of the sacrificial insulating layer 130s in the second region 108 of the connection region 104, spaced apart from the second separation structure 146b, may not be etched and may be retained.

[0180] The gate electrode 130 can be formed by filling the portion from which the sacrificial insulating layer 130s has been removed with a conductive material. As a result, the region where the sacrificial insulating layer 130s is disposed in the first region 106 of the cell array region 102 and the connection region 104 can be replaced by the gate electrode 130. In this case, the formation of the barrier layer 156 (see reference) can be further performed before the process of filling the conductive material constituting the gate electrode 130. Figure 2 Part of (e.g., the first barrier layer 156a (see reference)) Figure 2 The process is described. However, the embodiments are not limited to this.

[0181] In some embodiments, the opening for the separation structure may expose the horizontal insulating layer 116. During an etching process through the opening for the separation structure, at least a portion of the horizontal insulating layer 116 and at least a portion of the gate dielectric layer 150 may be removed, and material may be used to fill the first horizontal conductive layer 112. Thus, the first horizontal conductive layer 112 can be formed.

[0182] The separation structure 146 can be formed by filling the openings for the separation structure. The process of filling the openings for the separation structure can be performed by any of a variety of processes (e.g., deposition processes, etc.). In an embodiment, the first region 106 can be configured to be adjacent to the first separation structure 146a, and the second region 108 can be spaced apart from the second separation structure 146b between two adjacent first separation structures 146a.

[0183] In some embodiments, the upper separation region 148 may be formed in a portion of the gate stack structure 120. The upper separation region 148 can be formed by using a mask layer to form an opening for the separation pattern via an etching process and filling at least a portion of the opening for the separation pattern with an insulating material. The process of forming the opening for the separation pattern can be performed using any of a variety of etching processes (e.g., dry etching). The process of forming the insulating material in the opening for the separation pattern can be performed using any of a variety of processes (e.g., deposition processes, etc.). The order of the process of forming the opening for the separation pattern and the process of forming the insulating material in the opening for the separation pattern can be modified in various ways.

[0184] In this embodiment, as an example, an opening for the separation structure is described after the formation of the first through-hole P1, the protective insulating layer 180t, and the through-hole sacrificial layer 180s. However, the embodiment is not limited to this. The opening for the separation structure may be formed before the formation of the first through-hole P1, and a sacrificial layer may be formed in the opening for the separation structure. In this case, after removing the sacrificial layer from the opening for the separation structure, a replacement process utilizing the gate electrode 130, a replacement process utilizing the first horizontal conductive layer 112, etc., may be performed.

[0185] Subsequently, as Figure 13 As shown, the lower part of the protective insulating layer 180t on the lower surface of the first through portion P1 can be removed (refer to...). Figure 12 (That is, a portion of the protective insulating layer 180t on the upper surface of the gate electrode 130) to form the side insulating layer 180b. The lower portion of the protective insulating layer 180t can be removed by any of a variety of processes (e.g., etching processes, dry etching processes as an example).

[0186] Subsequently, as Figure 14As shown, a connection portion 180c can be formed (refer to...) Figure 16 The corresponding through-hole portion PC. For example, by performing a wet etching process via the first through-hole portion P1, the portion reached by the first through-hole portion P1 of the sacrificial insulating layer 130s can be removed. Through the wet etching process, a portion of the sacrificial insulating layer 130s can be etched in the horizontal direction, and a through-hole portion PC with an area larger than that of the first through-hole portion P1 can be formed. For example, when viewed in cross-section, the through-hole portion PC can be formed to have a horizontal width greater than that of the first through-hole portion P1. Thus, the through-hole portion PC can be formed using a simple process.

[0187] Subsequently, as Figure 15 As shown, by performing a second etching process, the second portion 182p (refer to) of the plurality of gate contacts 180 can be formed. Figure 16 Multiple second through-hole portions P2 are formed in the portion of the via PH. In a second etching process, the second through-hole portions P2 can be formed. The second through-hole portions P2 can extend from the second surface (connected to the through-hole portion PC) in the thickness direction (Z-axis direction in the figure) of the semiconductor device. Figure 15 The lower surface of the middle layer extends to the second surface 120b of the insulating stack structure 120s. Figure 15 (the lower surface of the middle).

[0188] In the second etching process, a mask having openings configured to expose predetermined portions is used to selectively etch the predetermined portions. The mask may comprise a photosensitive material or a photoresist layer formed of a photosensitive material or a hard mask layer. In the second etching process, the insulating stack structure 120s can be selectively etched using any of a variety of etching processes (e.g., dry etching). After the selective etching of the insulating stack structure 120s, the mask can be removed.

[0189] In some embodiments, during the second etching process, the second through-portion P2 may extend from the second surface connecting the through-portion PC and may pass through the second surface 120b of the insulating stack structure 120s, penetrate the insulating portion 110i, and the insulating layer of the circuit region 200. Therefore, the second through-portion P2 can connect the second surface connecting the through-portion PC and the wiring layer of the circuit wiring portion 290. However, the embodiments are not limited thereto. In some embodiments, the second through-portion P2 may not pass through the second surface 120b of the insulating stack structure 120s, penetrate the insulating portion 110i, and / or the insulating layer of the circuit region 200.

[0190] Subsequently, as Figure 16 As shown, the conductive portion 180a can be formed by filling the through-hole PH with a conductive material. This allows the gate contact 180 to be formed.

[0191] Subsequently, bit lines 192, including those connected to the channel structure CH, can be formed (see reference). Figure 1 Unit wiring section 190 (refer to) Figure 1 Therefore, it is possible to form Figure 1 The semiconductor device shown.

[0192] According to an embodiment, by using a first etching process including a partial etching process according to a binary system, a first through portion P1 of a via PH in which a first portion 181p of a gate contact 180 is disposed can be formed. Therefore, the process for forming the gate contact 180 can be simplified, and the area of ​​the connection region 104 can be reduced.

[0193] The gate contact 180 can be disposed within the insulating stack structure 120s and can stably form the first through-port P1 of the via PH. For example, if process errors may be undesirably introduced during the process of forming the first through-port P1 of the via PH, the gate contact 180 can be disposed within the insulating stack structure 120s to prevent or minimize undesirable electrical short circuits. The gate contact 180 can be disposed in a space separated from the through-port dummy structure DH, and the gate contact 180 can be stably formed.

[0194] Therefore, semiconductor devices can be stably formed through a simple manufacturing process.

[0195] In the above description, as an example, the processes of forming an opening for the separation structure, replacing a portion of the sacrificial insulating layer 130s with the gate electrode 130, and forming the separation structure 146 are described after the formation of the first through-hole portion P1. However, the embodiments are not limited thereto. In some embodiments, the first through-hole portion P1 may be formed after the processes of forming the opening for the separation structure, replacing a portion of the sacrificial insulating layer 130s with the gate electrode 130, and forming the separation structure 146 are performed. This reduces the number of processes. For example, the process of forming the through-sacrificial layer 180s may be omitted. Various other modified embodiments are possible.

[0196] In the following text, refer to Figures 17 to 36 The semiconductor device and its manufacturing method according to embodiments will be described in more detail below. Where an element is not described in detail below, it will be understood that the element is at least similar to a corresponding element described elsewhere in this disclosure. Parts not described above will be described in detail.

[0197] Figure 17 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 17 It shows the relationship with Figure 1 The part that corresponds to the part in the middle.

[0198] Reference Figure 17 In an embodiment, the gate contact 180 may include a first contact 1810 and a second contact 1820.

[0199] Reference Figures 1 to 16 The description of the first contact 1810 can be applied to the first contact 1810. The second contact 1820 may have a structure or shape different from that of the first contact 1810.

[0200] In the second contact 1820, the penetrating portion 180p may include a first surface disposed on the connecting portion 180c. Figure 17 The portion on the upper surface of the connecting portion 180c that corresponds to or is formed by the first portion 181p of the first contact 1810. The penetrating portion 180p may not include the second surface (which is provided on the connecting portion 180c opposite to the first surface of the connecting portion 180c). Figure 17 The portion corresponding to the second portion 182p of the first contact 1810 on the lower surface of the first contact 180c. That is, the penetrating portion 180p can be provided on the first surface of the connecting portion 180c, but may not be provided on the second surface of the connecting portion 180c opposite to the first surface of the connecting portion 180c. Therefore, the connecting portion 180c can be provided in the end of the penetrating portion 180p. In the second contact 1820, the side insulating layer 180b can be provided in the entire side surface of the penetrating portion 180p, and the side insulating layer 180b may not include the portion corresponding to the second portion 182p of the first contact 1810 where the side insulating layer 180b is not provided.

[0201] In an embodiment, the second contact 1820 may be electrically connected via a penetration portion 180p to a first wiring portion (e.g., cell wiring portion 190) on a first surface 120a of a stacked structure (e.g., an insulated stacked structure 120s). The second contact 1820 (e.g., the penetration portion 180p and the connecting portion 180c) may be spaced apart from and electrically insulated from the second surface 120b and / or the second wiring portion (e.g., circuit wiring portion 290) of the stacked structure (e.g., the insulated stacked structure 120s). That is, the second contact 1820 may be a second connecting contact. The second connecting contact may be electrically connected to one of the first and second wiring portions, but may not be electrically connected to the other of the first and second wiring portions.

[0202] For example, the process of forming the second contact 1820 may include a first etching process (see reference). Figures 7 to 10 The process for forming the side insulating layer 180b (refer to) Figure 13 The process for forming the through-hole PH connection (refer to) Figure 14) and the process for forming the conductive portion 180a (refer to Figure 16 In the first etching process, the first through-hole PH can be formed in the portion where the through-hole 180p will be formed. In the process of forming the side insulating layer 180b, the side insulating layer 180b can be formed on the side surface of the first through-hole PH. In the process of forming the connection through-hole PH, the connection through-hole PH can be formed in the portion where the connection 180c will be provided. The first etching process may include a multi-part etching process using a binary system.

[0203] In other words, a second through-hole PH can be formed in the portion where the second part 182p will be set (see reference). Figure 15 The second contact 1820 is formed in the case of the second etching process.

[0204] exist Figure 17 In the example shown, a gate contact 180 with a relatively high connection portion 180c at a first position (e.g., at a relatively high vertical level) is depicted as a second contact 1820, and a gate contact 180 with a relatively low connection portion 180c at a second position (e.g., at a relatively low vertical level) is depicted as a first contact 1810. Thus, in a second etching process configured to form the second portion 182p of the first contact 1810, the number of layers etched can be reduced. The second etching process can be easily performed, and the time of the second etching process can be reduced. However, the embodiment is not limited to this, and the arrangement of the first contact 1810 or the second contact 1820, or the position of the connection portion 180c in the first contact 1810 or the second contact 1820, can be modified in various ways.

[0205] In an embodiment, the plurality of gate contacts 180 may include a first contact 1810 and a second contact 1820, and the process of forming the plurality of gate contacts 180 can be easily performed, the process time of forming the plurality of gate contacts 180 can be reduced, and the degree of freedom of wiring can be improved.

[0206] Figure 18 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 18 It shows the relationship with Figure 5 The corresponding part.

[0207] Reference Figure 18In this embodiment, the first contact 1810 may be an extended contact. The extended contact may further include an extended portion 180e that extends horizontally from the second portion 182p and is spaced apart from and electrically insulated from the gate electrode 130 of the gate stack structure 120. The area (e.g., planar area) of the extended portion 180e may be smaller than the area (e.g., planar area) of the connection portion 180c, and the extended portion 180e may be spaced apart from and electrically insulated from the gate electrode 130 of the gate stack structure 120. For example, when viewed in cross-section, the horizontal width of the extended portion 180e may be smaller than the horizontal width of the connection portion 180c.

[0208] In some embodiments, the extension portion 180e can be configured to alleviate stress applied to the semiconductor device and reduce warping, cracking, etc., of the semiconductor device. For example, the process of forming the first contact 1810 may include a second etching process and an etching process for forming the extension through portion, in which the extension portion 180e will be formed after the second etching process.

[0209] In some embodiments, during the process of forming a first through-hole in which a first portion 181p of a first contact 1810 is disposed, another sacrificial insulating layer 130s (e.g., a lower sacrificial insulating layer) below the sacrificial insulating layer 130s in which a connection portion 180c is disposed may be undesirably etched due to process errors. For example, a pin hole may be formed. Therefore, during the process of forming the connection through-hole, a portion of the lower sacrificial insulating layer may be undesirably etched, and an extended through-hole may be formed. In this case, the area of ​​the extended through-hole in the lower sacrificial insulating layer may be smaller than the area of ​​the connection through-hole. Thus, when the conductive portion 180a is formed, the area of ​​the extended portion 180e may be smaller than the area of ​​the connection portion 180c. Therefore, the extended portion 180e may be spaced apart from the gate electrode 130 disposed in the first region 106. Therefore, if process errors, pin holes, etc., may occur, undesirable electrical short circuits can be prevented, and the process margin can be sufficient.

[0210] exist Figure 18In the example shown, an extension portion 180e is disposed at the end of a penetration portion 180p. A second portion 182p of the penetration portion 180p connects the connecting portion 180c and the extension portion 180e, and the first contact 1810 is electrically insulated from the second wiring portion (e.g., circuit wiring portion 290). That is, the first contact 1810 including the extension portion 180e can be a second connecting contact. The second connecting contact can be electrically connected to one of the first wiring portion and the second wiring portion, and may not be electrically connected to the other of the first wiring portion and the second wiring portion. In this case, the process of forming the first contact 1810 may not include a second etching process. However, the embodiment is not limited thereto. Reference will be made later. Figure 19 and Figure 20 Detailed description of the embodiments.

[0211] exist Figure 18 In the illustration, a first contact 1810 and a second contact 1820 of the extended contact are shown together, but the embodiment is not limited thereto. The first contact 1810 may also include a base contact, or the second contact 1820 may be omitted.

[0212] In some embodiments, the extended portion 180e can alleviate the stress applied to the semiconductor device and reduce warpage, cracking, etc. of the semiconductor device. In some embodiments, when process errors exist, the extended portion 180e can be formed with an area smaller than that of the connection portion 180c, and the process allowance can be sufficient.

[0213] Figure 19 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 19 It shows the relationship with Figure 5 The corresponding part.

[0214] Reference Figure 19 In an embodiment, the first contact 1810 may be an extended contact. The extended contact may further include an extended portion 180e that extends horizontally from the second portion 182p and is spaced apart from and electrically insulated from the gate electrode 130 of the gate stack structure 120. In an embodiment, the extended portion 180e can alleviate stress applied to the semiconductor device and can reduce warping, cracking, etc., of the semiconductor device.

[0215] In an embodiment, the second portion 182p may extend through the extension portion 180e. The second portion 182p may include a portion disposed on a first surface of the extension portion 180e and a portion disposed on a second surface of the extension portion 180e opposite to the first surface of the extension portion 180e.

[0216] For example, the first contact 1810 can be electrically connected via a first portion 181p to a first wiring portion (e.g., cell wiring portion 190) on a first surface 120a of a stacked structure (e.g., an insulated stacked structure 120s), and via a second portion 182p to a second wiring portion (e.g., circuit wiring portion 290) on a second surface 120b of the stacked structure (e.g., an insulated stacked structure 120s). That is, the first contact 1810 can be a first connecting contact electrically connected to the first and second wiring portions on opposite sides of the stacked structure.

[0217] In some embodiments, the extension portion 180e may include a plurality of extension portions 180e having the same area, and may be formed by a simple manufacturing process.

[0218] In some embodiments, such as Figure 20 As shown, the extension portion 180e may include multiple extension portions 180e with different areas. For example, the extension portion 180e may include a first extension portion 181e and a second extension portion 182e with an area smaller than that of the first extension portion 181e. For example, when viewed in cross-section, the horizontal width of the first extension portion 181e may be greater than the horizontal width of the second extension portion 182e. The areas of the first extension portion 181e and the second extension portion 182e may be different by any of various methods. For example, the areas of the first extension portion 181e and the second extension portion 182e may be adjusted by different compositions of the sacrificial insulating layer 130s. The sacrificial insulating layer 130s may include a first sacrificial insulating layer and a second sacrificial insulating layer. The first sacrificial insulating layer may be disposed in the layer corresponding to the first extension portion 181e. The second sacrificial insulating layer may be disposed in the layer corresponding to the second extension portion 182e and may have a composition different from that of the first sacrificial insulating layer. For example, when the sacrificial insulating layer 130s includes silicon nitride, the silicon content of the first sacrificial insulating layer may be less than the silicon content of the second sacrificial insulating layer, the nitrogen content of the first sacrificial insulating layer may be greater than the nitrogen content of the second sacrificial insulating layer, and / or the hydrogen content of the first sacrificial insulating layer may be greater than the hydrogen content of the second sacrificial insulating layer.

[0219] In some embodiments, the area of ​​the plurality of extension portions 180e may decrease in stages as the plurality of extension portions 180e extend downward, or the area of ​​the plurality of extension portions 180e may increase in stages as the plurality of extension portions 180e extend downward. Various other modified embodiments are possible.

[0220] In an embodiment, the gate contact 180 may include a reference. Figures 1 to 20The first contact 1810 described is (e.g., a base contact, an extension contact, a first connecting contact, or a second connecting contact), and also includes a second contact. Additionally, it may include a contact having a structure or shape different from that of the first contact, second contact, base contact, extension contact, first connecting contact, or second connecting contact.

[0221] Figure 21 This is a schematic plan view of a semiconductor device according to an embodiment. Figure 22 yes Figure 21 The diagram shows a cross-sectional view of the semiconductor device. Figure 21 It shows the corresponding Figure 4 Part of Figure 22 It shows the corresponding Figure 1 The part. In Figure 22 In the middle, the connecting area 104 includes along Figure 21 The portion intercepted by line E-E' in the middle.

[0222] Reference Figure 21 and Figure 22 In an embodiment, in the second region 108 of the connection region 104, the extended dummy structure 160 has the same or similar structure or shape as the gate contact 180.

[0223] The extended dummy structure 160 may include a dummy penetration 160p that passes through the insulating stack structure 120s, and a dummy extension 160e that extends horizontally to have an area larger than that of the dummy penetration 160p. For example, when viewed in cross-section, the horizontal width of the dummy extension 160e may be greater than the horizontal width of the dummy penetration 160p.

[0224] The dummy penetration 160p can extend to pass through the insulating stack structure 120s in the thickness direction (Z-axis direction in the figure) of the semiconductor device, and the dummy extension 160e can extend horizontally to have an area (e.g., planar area) larger than that of the dummy penetration 160p. For example, when viewed in cross-section, the dummy extension 160e can have a horizontal width larger than that of the dummy penetration 160p. For example, multiple dummy extensions 160e can be provided one-to-one with multiple sacrificial insulating layers 130s.

[0225] By extending the dummy structure 160, the stress applied to the semiconductor device can be reduced, and warping, cracking, etc., of the semiconductor device can be decreased. For example, in a semiconductor device, stress can be applied to the semiconductor device through regions of the gate stack structure 120 and the insulating stack structure 120s. The extended dummy structure 160 may include a material capable of reducing the stress applied to the semiconductor device, and / or the extended dummy structure 160 may be disposed at a location capable of reducing the stress applied to the semiconductor device. The extended dummy structure 160 may include a dummy penetration portion 160p through the insulating stack structure 120s and a dummy extension portion 160e extending from it, and may have sufficient volume. Therefore, the stress applied to the semiconductor device can be effectively reduced.

[0226] The extended dummy structure 160 may include at least one of an insulating material and a conductive material, or be formed of at least one of an insulating material and a conductive material. In some embodiments, the extended dummy structure 160 may be disposed in an insulating stack structure 120s, and the extended dummy structure 160 may include a conductive material (e.g., a metal). The conductive material (e.g., a metal) can effectively alleviate the stress applied to the semiconductor device. That is, since the extended dummy structure 160 may be disposed in the second region 108 in which the insulating stack structure 120s is disposed, the extended dummy structure 160 may include a conductive material (e.g., a metal) capable of effectively alleviating the stress applied to the semiconductor device. However, the embodiments are not limited thereto, and the extended dummy structure 160 may include an insulating material.

[0227] The extended dummy structure 160 may include, or be formed of, a material capable of reducing warpage in the semiconductor device. For example, a warpage-inducing material may induce warpage in a direction opposite to the warpage direction of the semiconductor device. The extended dummy structure 160 may include a compressive stress material or a tensile stress material. The compressive stress material may have a negative stress at room temperature and applies compressive stress when it is disposed on a substrate. The tensile stress material may have a positive stress at room temperature and applies tensile stress when it is disposed on a substrate.

[0228] For example, the extended dummy structure 160 may include at least one of oxides, nitrides, carbonitrides, carbon oxides, oxynitrides, carbonitrides, resins, and metals, or be formed from at least one of oxides, nitrides, carbonitrides, carbon oxides, oxynitrides, carbonitrides, resins, and metals. For example, the extended dummy structure 160 may include at least one of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, silicon carbonitride (SiCN), silicon carbon oxynitride (SiOC), silicon oxynitride (SiON), silicon carbonitride (SiOCN), resin, tungsten (W), copper (Cu), and aluminum (Al), or be formed from at least one of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, silicon carbonitride (SiCN), silicon carbon oxynitride (SiOC), silicon oxynitride (SiON), silicon carbonitride (SiOCN), resin, tungsten (W), copper (Cu), and aluminum (Al).

[0229] Silicon oxide, aluminum oxide, or hafnium oxide can be compressive stress materials. Silicon nitride, silicon carbonitride, or metals (e.g., tungsten (W), copper (Cu), aluminum (Al)) can be tensile stress materials. Depending on their composition, silicon carbide, silicon oxynitride, or silicon carbonitride can be either compressive or tensile stress materials. Resins are generally tensile stress materials, but depending on the material or composition, resins can be compressive stress materials.

[0230] The compressive or tensile stress of the extended virtual structure 160 can be adjusted by modifying its composition, manufacturing process, and process conditions.

[0231] In an embodiment, at least a portion of the process for forming the gate contact 180 may be used to form the extended dummy structure 160.

[0232] For example, in the first etching process (refer to...) Figures 7 to 10 ) and / or a second etching process (refer to Figure 15 In the first etching process, a through-hole portion corresponding to the dummy through-hole 160p can be formed. In the first etching process, a first through-hole portion of the via PH can be formed, wherein at least a portion of the through-hole 180p of the gate contact 180 is disposed. In the second etching process, a second through-hole portion of the via PH can be formed, wherein at least a portion of the through-hole 180p of the gate contact 180 is disposed. The process for forming the connecting through-hole portion of the via PH (see...) Figure 14 The process of forming an extended through portion corresponding to the extended portion 180e of the gate contact 180 (see reference). Figures 18 to 20 In the ), a virtual through portion can be formed in which a virtual extension portion 160e of an extended virtual structure 160 is set.

[0233] For example, when the extended dummy structure 160 includes a conductive material, in the process of forming the conductive portion 180a (refer to...) Figure 16 The extended dummy structure 160 can be formed by filling the penetrating portion and the dummy penetrating portion corresponding to the extended dummy structure 160 with conductive material. When the extended dummy structure 160 includes a material other than conductive material, the extended dummy structure 160 can be formed by filling the penetrating portion and the dummy penetrating portion corresponding to the extended dummy structure 160 with a material other than conductive material.

[0234] However, the embodiments are not limited thereto, and the extended dummy structure 160 can be formed by a process performed separately from the process of forming the gate contact 180.

[0235] To ensure clarity and simplify the illustration, Figure 21 As an example, an extended dummy structure 160 is shown disposed in the central portion of a second region 108 between a plurality of gate contacts 180 in a second direction (the Y-axis direction in the figure). However, the embodiment is not limited to this, and various modifications can be made to the position, arrangement, number, etc. of the extended dummy structure 160.

[0236] exist Figure 22 As an example, in the extended dummy structure 160, a dummy penetration portion 160p passes through the entirety of a plurality of sacrificial insulating layers 130s included in the insulating stack structure 120s, and a plurality of dummy extension portions 160e respectively correspond to a plurality of sacrificial insulating layers 130s. Thus, the extended dummy structure 160 can pass through the entire insulating stack structure 120s, and the extended dummy structure 160 can effectively reduce the stress applied to the semiconductor device. However, the embodiments are not limited thereto, and as... Figure 24 and Figure 25 As shown, an extended dummy structure 160 may be provided in a portion of the plurality of sacrificial insulation layers 130s included in the insulating stack structure 120s.

[0237] In this embodiment, by extending the dummy structure 160, the stress applied to the semiconductor device can be reduced, and warping, cracking, etc. of the semiconductor device can be reduced.

[0238] exist Figure 22 In the example shown, a dummy extension portion 160e includes multiple dummy extension portions 160e having the same area. However, the embodiments are not limited to this. Figures 23 to 25 As shown, the dummy extension portion 160e may include multiple dummy extension portions 160e with different areas.

[0239] For example, such as Figure 23As shown, the dummy extension 160e may include a first dummy extension 161e and a second dummy extension 162e with an area (e.g., planar area) smaller than that of the first dummy extension 161e. For example, when viewed in cross-section, the horizontal width of the first dummy extension 161e may be greater than the horizontal width of the second dummy extension 162e. The areas of the first dummy extension 161e and the second dummy extension 162e may be different from each other by any of various methods. For example, the areas of the first dummy extension 161e and the second dummy extension 162e may be adjusted by different compositions of the sacrificial insulating layer 130s. The sacrificial insulating layer 130s may include a first sacrificial insulating layer and a second sacrificial insulating layer. The first sacrificial insulating layer may be disposed in the layer corresponding to the first dummy extension 161e. The second sacrificial insulating layer may be disposed in the layer corresponding to the second dummy extension 162e and may have a composition different from that of the first sacrificial insulating layer. For example, when the sacrificial insulating layer 130s includes silicon nitride, the silicon content of the first sacrificial insulating layer may be less than the silicon content of the second sacrificial insulating layer, the nitrogen content of the first sacrificial insulating layer may be greater than the nitrogen content of the second sacrificial insulating layer, and / or the hydrogen content of the first sacrificial insulating layer may be greater than the hydrogen content of the second sacrificial insulating layer.

[0240] In some embodiments, such as Figure 24 As shown, the area of ​​the plurality of dummy extension portions 160e can decrease in stages as the plurality of extension portions 180e extend downward. In some embodiments, such as Figure 25 As shown, the area of ​​the plurality of dummy extension portions 160e can increase in stages as the plurality of extension portions 180e extend downward. Various other modified embodiments are possible.

[0241] Figure 26 This is a schematic plan view of a semiconductor device 10 according to an embodiment.

[0242] Reference Figure 26 In an embodiment, the semiconductor device 10 may include a plurality of memory regions 10m partitioned, separated, divided, or defined by the external region 12.

[0243] The memory region 10m can be a unit region of the semiconductor device 10. Figure 1 As an example, a semiconductor device 10 is shown including a plurality of memory regions 10m adjacent to each other in a first direction (X-axis direction in the figure) and a plurality of memory regions 10m adjacent to each other in a second direction (Y-axis direction in the figure). However, the embodiment is not limited thereto. The number, arrangement, etc. of the plurality of memory regions 10m can be modified in various ways.

[0244] The outer region 12 can be disposed outside the plurality of memory regions 10m, and can partition, separate, divide, or define the plurality of memory regions 10m. The outer region 12 may include at least one first outer region 12a and at least one second outer region 12b. The first outer region 12a may extend longitudinally in a first direction (the X-axis direction in the figure). The second outer region 12b may extend longitudinally in a second direction (the Y-axis direction in the figure). Therefore, the structure of the outer region 12 can be simplified. However, the embodiments are not limited thereto. In some embodiments, depending on the arrangement of the plurality of memory regions 10m, the first outer region 12a and / or the second outer region 12b may include curved portions, folded portions, curved portions, circular portions, etc.

[0245] The external region 12 may include portions between multiple memory regions 10m and portions between the multiple memory regions 10m and the edge of the semiconductor device 10. At least a portion of the external region 12 may be a dicing region, a scribe line, etc.

[0246] In an embodiment, an extended dummy structure 160 may be provided in the outer region 12 of the semiconductor device 10. For example, the extended dummy structure 160 may be provided in any of various locations. For example, in a plan view, the extended dummy structure 160 may be provided in a portion between multiple memory regions 10m and / or in a portion between the memory regions 10m and the edge of the semiconductor device 10. However, the embodiment is not limited to this. Therefore, various modifications can be made to the position, shape, arrangement, number, etc., of the extended dummy structure 160. For example, the extended dummy structure 160 may be provided in a portion of the memory regions 10m.

[0247] In the outer area 12 of the extended dummy structure 160, an insulating stack structure can be set, or an insulating structure can be set after the insulating stack structure is removed.

[0248] exist Figure 26 In the example shown, the expanded dummy structure 160 is configured to have a honeycomb structure. Thus, the expanded dummy structure 160 can be provided to have a high density. However, the embodiments are not limited to this, and the expanded dummy structure 160 can have any of a variety of arrangements.

[0249] In the embodiments, Figures 21 to 26 As an example, the extended dummy structure 160 is shown disposed in the second region 108 or the outer region 12. However, the embodiments are not limited thereto, and the extended dummy structure 160 can be disposed in any of various locations in portions other than the cell array region 102 or in portions where an insulating stack structure is disposed.

[0250] Figure 27 This is a schematic plan view of a semiconductor device according to an embodiment. Figure 27 It shows the relationship with Figure 3 The corresponding part.

[0251] Reference Figure 27 In an embodiment, the second separation structure 146b may include a plurality of separation portions 1460 extending in a first direction and spaced apart from each other in the first direction. When the second separation structure 146b includes a plurality of separation portions 1460, the sacrificial insulating layer 130s can be stably replaced with the gate electrode 130s in the first region 106. With the plurality of separation portions 1460, the gate stack structure 120 can have a relatively large area and can improve the structural stability during the process of replacing the sacrificial insulating layer 130s with the gate electrode 130.

[0252] Figure 28 This is a schematic cross-sectional view of a semiconductor device according to an embodiment. Figure 29 It is shown that it includes Figure 28 A plan view of the upper surface of the first stacked portion 121 in the semiconductor device shown. Figure 30 It is shown that it includes Figure 28 A plan view of the upper surface of the second stacked portion 122 in the semiconductor device shown. Figure 28 It shows the relationship with Figure 1 The part corresponding to the left side of the middle, Figure 29 and Figure 30 It shows the relationship with Figure 4 The part corresponding to the left side of the text. Figure 31 Conceptually showing including Figure 28 The separation structure 146 in the first stacked portion 121 and the second stacked portion 122 of the semiconductor device shown.

[0253] Reference Figures 28 to 31 In an embodiment, the second separation structure 146b may have different planar shapes in the plurality of gate stack portions (e.g., the first stack portion 121 and the second stack portion 122) included in the gate stack structure 120.

[0254] For example, such as Figure 29 As shown, in the first stacked portion 121, the second separation structure 146b may have a shape extending along the first direction. For example, as Figure 30 As shown, in the second stack portion 122, the second separation structure 146b may include a plurality of separation portions 1460 extending in the first direction and spaced apart in the first direction. The difference in planar shape between the second separation structure 146b of the first stack portion 121 and the second separation structure 146b of the second stack portion 122 can reduce the stress applied to the semiconductor device or can stably support the gate stack structure 120.

[0255] exist Figures 28 to 31 The diagram illustrates, by way of example, a first stacked portion 121 and a second stacked portion 122. However, the gate stack structure 120 may include three or more stacked portions, and the second separation structure 146b in the three or more stacked portions may have any of a variety of planar shapes. (See also...) Figure 32 and Figure 33 An example in which the gate stack structure 120 includes four stacked portions will be described.

[0256] Figure 32 A conceptual illustration shows a discrete structure 146 in a plurality of gate stack portions included in a semiconductor device according to an embodiment. Figure 33 A conceptual illustration shows a discrete structure 146 in a plurality of gate stack portions included in a semiconductor device according to an embodiment.

[0257] like Figure 32 and Figure 33 As shown, the gate stack structure 120 may include a first stack portion 121, a second stack portion 122, a third stack portion 123, and a fourth stack portion 124.

[0258] For example, such as Figure 32 As shown, the second separation structure 146b in the first stack portion 121 may have a shape extending in a first direction (the X-axis direction in the figure), and the second separation structure 146b in the second stack portion 122 may include a plurality of separation portions 1460 extending in the first direction and spaced apart in the first direction. The second separation structure 146b in the third stack portion 123 may have a shape extending in the first direction, and the second separation structure 146b in the fourth stack portion 124 may include a plurality of separation portions 1460 extending in the first direction and spaced apart in the first direction. In some embodiments, the second separation structure 146b in each of the first stack portion 121 and the third stack portion 123 may include a plurality of separation portions 1460, and the second separation structure 146b in each of the second stack portion 122 and the fourth stack portion 124 may have a shape extending in the first direction. In some embodiments, as Figure 33As shown, the second separation structure 146b in each of the first stack portion 121 and the second stack portion 122 may include a plurality of separation portions 1460, and the second separation structure 146b in each of the third stack portion 123 and the fourth stack portion 124 may have a shape extending along a first direction. In some embodiments, the second separation structure 146b in each of the first stack portion 121 and the second stack portion 122 may have a shape extending in a first direction, and the second separation structure 146b in each of the third stack portion 123 and the fourth stack portion 124 may include a plurality of separation portions 1460.

[0259] In some embodiments, the second separation structure 146b in at least one of the first to fourth stack portions 121, 122, 123, and 124 may include a plurality of separation portions 1460, and the second separation structure 146b in the other of the first to fourth stack portions 121, 122, 123, and 124 may have a shape extending in a first direction (the X-axis direction in the figures). In some embodiments, the second separation structure 146b in at least one of the first to fourth stack portions 121, 122, 123, and 124 may have a shape extending in a first direction, and the second separation structure 146b in the other of the first to fourth stack portions 121, 122, 123, and 124 may include a plurality of separation portions 1460. Various other modified embodiments are possible.

[0260] However, the embodiments are not limited to Figure 32 and Figure 33 The planar shape of the second separation structure 146b in the plurality of gate stack portions is shown, and the planar shape of the second separation structure 146b in the plurality of gate stack portions can be modified differently.

[0261] The difference in planar shape between the second separation structure 146b of the first stacked portion 121 and the second separation structure 146b of the second stacked portion 122 can reduce the stress applied to the semiconductor device or stably support the gate stacked structure 120.

[0262] Figure 34 This is a schematic plan view of a portion of a semiconductor device according to an embodiment. Figure 34 It shows the relationship with Figure 4 The corresponding part.

[0263] Reference Figure 34The multiple gate contacts 180 connected to the multiple gate electrodes 130 that overlap each other in the plan view can be disposed at different positions in the second direction (the Y-axis direction in the figure). For example, among the first gate contact 1801, third gate contact 1803, fifth gate contact 1805, and seventh gate contact 1807 disposed in the first row along the first direction, at least one can be disposed at a position different from the other in the second direction. For example, among the second gate contact 1802, fourth gate contact 1804, sixth gate contact 1806, and eighth gate contact 1808 disposed in the second row along the first direction, at least one can be disposed at a position different from the other in the second direction. This may be because the edge positions of the upper gate electrode and the lower gate electrode in the multiple gate electrodes 130 are different from each other due to process errors, etc.

[0264] For example, such as Figure 34 As shown, the distance between the edge 1307e of the seventh gate electrode located in the lower position and the adjacent first separation structure 146a can be greater than the distance between the edge 1301e of the first gate electrode located in the upper position and the adjacent first separation structure 146a. This distance can refer to the distance in the second direction (the Y-axis direction in the figure), for example, the minimum distance. In the second direction (the Y-axis direction in the figure), the seventh gate contact 1807 can be configured to be electrically connected to the seventh gate electrode, and the first gate contact 1801 can be configured to be electrically connected to the first gate electrode. Therefore, in the second direction, the distance between the center of the seventh gate contact 1807 and the adjacent first separation structure 146a can be greater than the distance between the center of the first gate contact 1801 and the adjacent first separation structure 146a. That is, in the second direction, the position of the seventh gate contact 1807 can be different from the position of the first gate contact 1801.

[0265] To understand this clearly, in Figure 34In the above description, the first gate contact 1801 and the seventh gate contact 1807 are described as examples, but the embodiments are not limited thereto. In the above description, as examples, the edge positions of the upper gate electrode and the lower gate electrode among the plurality of gate electrodes 130 are described as differing from each other due to process errors, but the embodiments are not limited thereto. The embodiments can be applied to any of various situations in which the edge positions of the plurality of gate electrodes 130 overlapping each other in a plan view are different from each other. In some embodiments, even when the edge positions of the plurality of gate electrodes 130 overlapping each other in a plan view can be the same, the plurality of gate contacts 180 connected to the plurality of gate electrodes 130 can be disposed at different positions in a second direction in the plan view. In this case, the connection portions 180c of the plurality of gate contacts 180 can have different areas, such that the plurality of gate contacts 180 are electrically connected to the plurality of gate electrodes 130 respectively.

[0266] In some embodiments, the spacing between the plurality of gate contacts 180 in a first direction (the X-axis direction in the figure) may have a first spacing and a second spacing that are different from each other. For example, in the first gate contact 1801, third gate contact 1803, fifth gate contact 1805, and seventh gate contact 1807 disposed in a first row along the first direction (the X-axis direction in the figure), the spacing between the plurality of gate contacts 180 may have a first spacing and a second spacing that are different from each other. For example, in the second gate contact 1802, fourth gate contact 1804, sixth gate contact 1806, and eighth gate contact 1808 disposed in a first row along the first direction, the spacing between the plurality of gate contacts 180 may have a first spacing and a second spacing that are different from each other. The spacing between the plurality of gate contacts 180 may refer to the spacing between the plurality of first portions included in the plurality of gate contacts 180 in the first direction (the X-axis direction in the figure).

[0267] exist Figure 34In the example shown, the spacing between the fourth gate contact 1804 and the sixth gate contact 1806 is greater than the spacing between the second gate contact 1802 and the fourth gate contact 1804, and the spacing between the sixth gate contact 1806 and the eighth gate contact 1808 is greater than the spacing between the fourth gate contact 1804 and the sixth gate contact 1806. For example, in a plan view, the connection portion 180c of the second gate contact 1802 and the connection portion 180c of the fourth gate contact 1804 may overlap each other. In a plan view, the connection portion 180c of the fourth gate contact 1804 and the connection portion 180c of the sixth gate contact 1806 may not overlap each other, and the connection portion 180c of the sixth gate contact 1806 and the connection portion 180c of the eighth gate contact 1808 may not overlap each other. However, the embodiments are not limited to this. Figure 34 The arrangement of the second gate contact 1802, the fourth gate contact 1804, the sixth gate contact 1806, and the eighth gate contact 1808 shown in the figure allows for various modifications to the position, arrangement, etc., of the multiple gate contacts 180.

[0268] As described above, in the embodiments, the positions of the plurality of gate contacts 180 can be modified differently in the first direction and / or the second direction.

[0269] Figure 35 This is a schematic partial cross-sectional view of the semiconductor device 20 according to an embodiment.

[0270] Reference Figure 35 The semiconductor device according to the embodiments can be a bonding structure bonded by a chip-to-chip (C2C) bonding process, a chip-to-wafer bonding process, or a wafer-to-wafer bonding process. For example, a lower chip including a circuit region 200a in which peripheral circuit structures are disposed on a first substrate 210 can be manufactured, an upper chip including a cell region 100a in which memory cell structures are disposed on an initial substrate can be manufactured, and the semiconductor device 20 can be manufactured by bonding the lower chip and the upper chip.

[0271] The circuit region 200a may include a first substrate 210, circuit elements 220, and circuit wiring portions 290. The circuit wiring portions 290 may include an insulating layer 292, contact vias 294, wiring layers 296, and bonding structures 298 disposed on the surface facing the cell region 100a. The area on the surface facing the cell region 100a, except for the bonding structures 298, may be covered by the bonding insulating layer.

[0272] Cell region 100a may include a stacked structure, a channel structure CH, a through contact 170, and a cell wiring portion 190. The stacked structure includes a gate stacked structure 120 and an insulating stacked structure 120s.

[0273] The unit wiring portion 190 may include a first unit wiring portion 190a disposed on a first surface 120a of the stacked structure and a second unit wiring portion 190b disposed on a second surface 120b of the stacked structure. For example, the first unit wiring portion 190a may include a horizontal conductive layer 199, a through-hole 199a, and a connection wiring 199b. The through-hole 199a may pass through an insulating layer 199c to be electrically connected to the horizontal conductive layer 199. The connection wiring 199b may be electrically connected to the through-hole 199a. For example, the second unit wiring portion 190b may include a bit line 192, a contact through-hole 194, a connection wiring 196, and a bonding structure 198 disposed on the surface facing the circuit region 200a. The area in the surface facing the circuit region 200a, except for the bonding structure 198, may be covered by a bonding insulating layer.

[0274] To clarify and simplify the illustration, the connecting wiring 199b of the first unit wiring portion 190a is shown as an example, comprising a single wiring layer, and an insulating layer 199d may be disposed in an area outside the single wiring layer. However, the embodiments are not limited thereto. In some embodiments, the connecting wiring 199b of the first unit wiring portion 190a may include multiple wiring layers and may also include contact vias.

[0275] In an embodiment, the first contact 1810 of the gate contact 180 can be electrically connected via a first portion to a first wiring portion (e.g., a first cell wiring portion 190a) on a first surface 120a of the stacked structure (e.g., an insulated stacked structure 120s), and via a second portion to a second wiring portion (e.g., a second cell wiring portion 190b) on a second surface 120b of the stacked structure (e.g., an insulated stacked structure 120s). That is, the first contact 1810 can be a first connecting contact that is electrically connected to the first wiring portion and the second wiring portion on opposite sides of the stacked structure. Figure 35 In this context, the first contact 1810 may be a base contact excluding the extended portion.

[0276] However, the embodiments are not limited thereto, and the first contact 1810 may include at least one of a first connecting contact, a second connecting contact, a base contact, and an extension contact, and / or the gate contact 180 may also include a second contact.

[0277] In an embodiment, the gate stack structure 120 can be sequentially stacked on... Figure 35 On the lower part of the first unit wiring portion 190a, and may have therein Figure 1The gate stack structure 120 shown is configured in a vertically flipped manner. The channel structure CH passing through the gate stack structure 120 may have the following characteristics: Figure 2 The channel structure CH shown is configured in a vertically flipped manner. Therefore, in the cross-sectional view, the channel structure CH can have sloping side surfaces, such that the width of the channel structure CH decreases with distance from the circuit region 200a. The channel pads and bit lines 192 at the upper part of the gate stack structure 120 can be adjacent to the circuit region 200a.

[0278] For example, the bonding structure 298 of circuit region 200a and / or the bonding structure 198 of unit region 100a may include aluminum, copper, tungsten, or an alloy including aluminum, copper, and tungsten. For example, the bonding structure 298 of circuit region 200a and the bonding structure 198 of unit region 100a may include copper, such that unit region 100a and circuit region 200a can be bonded to each other by copper-copper bonding (e.g., direct bonding).

[0279] In an embodiment, the channel structure CH may include a protruding portion CHP that protrudes from the first surface 120a of the gate stack structure 120. The gate dielectric layer 150 is not disposed in the protruding portion CHP, and the channel layer 140 disposed in the protruding portion CHP may be exposed to the outside. A horizontal conductive layer 199 may be electrically connected to the channel layer 140 in the protruding portion CHP. However, the embodiment is not limited thereto and may include horizontal conductive layers 112 and 114, such as... Figure 1 As shown. Various other modified embodiments are also possible.

[0280] In some embodiments, the semiconductor device may include input / output pads and input / output connection wiring electrically connected to the input / output pads. The input / output connection wiring may be electrically connected to a portion of the bonding structure 198 of cell region 100a. The input / output pads may, for example, be disposed on insulating layer 199d. In some embodiments, additional input / output pads electrically connected to circuit region 200a may be provided.

[0281] For example, circuit region 200a and unit region 100a can be respectively connected to the included Figure 37 The first structure 1100F and the second structure 1100S of the semiconductor device 1100 in the electronic system 1000 shown correspond to each other. For example, the circuit region 200a and the cell region 100a may respectively include Figure 40 The regions of the first structure 4100 and the second structure 4200 of the semiconductor chip 2200a shown.

[0282] In the above description and figures, as an example, it is described and shown that when the insulating stack structure 120s includes a plurality of insulating stack portions corresponding to a plurality of gate stack portions, a plurality of insulating stack portions are formed, and a plurality of through-holes in which a plurality of gate contacts 180 are respectively disposed. For example, when the insulating stack structure 120s includes a first insulating stack portion 121s and a second insulating stack portion 122s, the first insulating stack portion 121s and the second insulating stack portion 122s can be formed, and a plurality of through-holes in which a plurality of gate contacts 180 are respectively disposed. However, the embodiments are not limited thereto.

[0283] In some embodiments, such as Figure 36 As shown, when the insulating stack structure 120s includes multiple insulating stack portions, a partial process can be repeatedly performed. In the partial process, a portion corresponding to at least one of the multiple insulating stack portions can be formed, and thereafter, a process can be performed to form a portion with multiple through holes.

[0284] For example, when the insulating stack structure 120s includes a first insulating stack portion 121s and a second insulating stack portion 122s, the first insulating stack portion 121s can be formed and a portion of a plurality of through holes can be formed, and thereafter, the second insulating stack portion 122s can be formed and other portions of the plurality of through holes can be formed.

[0285] For example, after the first insulator stack portion 121s can be formed, a portion of the via in which a first connecting gate contact 1830 is disposed (e.g., the first connecting portion 1830c) and a portion of the via in which a second connecting gate contact 1840 is disposed (e.g., the second extension portion 1840e) are disposed. The first connecting gate contact 1830 may be a gate contact 180 including the connecting portion 180c in the first insulator stack portion 121s, and the second connecting gate contact 1840 may be a gate contact 180 including the connecting portion 180c in the second insulator stack portion 122s. The first connecting portion 1830c may include a first through portion, a side insulating layer 180b, a connecting through portion, and a second through portion. The second extension portion 1840e may extend through the entire first insulator stack portion 121s.

[0286] The first connecting part 1830c's first through part can be passed through as follows Figures 7 to 10 The first etching process shown is used to form the first connection portion 1830c. The side insulating layer of the first connection portion 1830c can be formed through, as shown... Figures 11 to 13 The process shown is used to form the connection. The connecting through portion of the first connecting portion 1830c can be formed through, as shown in the diagram. Figure 14 The process shown is used to form the second through portion. The second through portion of the first connecting portion 1830c can be formed through, as shown in the diagram. Figure 15The second etching process shown is used to form the second extension 1840e. The through portion can be formed by, for example... Figures 7 to 10 The first etching process shown is used to form the side insulating layer 180b. Figures 11 to 13 The process shown forms on the side surface of the through portion of the second extension 1840e. However, the embodiment is not limited to this; the side insulating layer 180b may not be formed on the side surface of the through portion of the second extension 1840e. A through-sacrificial layer may be formed in the first connecting portion 1830c and the second extension 1840e.

[0287] Subsequently, a second insulating stack portion 122s can be formed. A via portion (e.g., second connection portion 1840c) containing a second connection gate contact 1840 and a via portion (e.g., first extension portion 1830e) containing a first connection gate contact 1830 can be formed. The second connection portion 1840c may include a first through portion, a side insulating layer 180b, a connection through portion, and a second through portion. The first extension portion 1830e may extend through the entire second insulating stack portion 122s.

[0288] The first through-section of the second connecting part 1840c can be made of Figures 7 to 10 The first etching process shown is used to form the second connection portion 1840c. The side insulating layer can be formed by... Figures 11 to 13 The process shown is used to form the second connecting portion 1840c. The connecting through portion can be formed by... Figure 14 The process shown is used to form the second through portion. The second through portion of the second connecting portion 1840c can be formed by... Figure 15 The second etching process shown is used to form the portion. The through portion of the first extension 1830e can be formed by... Figures 7 to 10 The first etching process shown forms the side insulating layer 180b. Figures 11 to 13 The process shown is formed on the side surface of the through portion of the first extension 1830e. However, the embodiment is not limited to this, and the side insulating layer 180b may not be formed on the side surface of the through portion of the first extension 1830e. The through sacrificial layer may be removed in the first connecting portion 1830c and the second extension 1840e to form a through-hole.

[0289] The first connecting gate contact 1830 may have a bent portion due to the width difference at the boundary between the first insulating stack portion 121s and the second insulating stack portion 122s. For example, the first connecting gate contact 1830 may have a bent portion due to the width difference between the first connecting portion 1830c and the first extension portion 1830e at the boundary between the first insulating stack portion 121s and the second insulating stack portion 122s. The second connecting gate contact 1840 may have a bent portion due to the width difference at the boundary between the first insulating stack portion 121s and the second insulating stack portion 122s. For example, the second connecting gate contact 1840 may have a bent portion due to the width difference between the second extension portion 1840e and the second connecting portion 1840c at the boundary between the first insulating stack portion 121s and the second insulating stack portion 122s. However, the embodiments are not limited to this.

[0290] Subsequently, the conductive portion 180a can be formed by filling the via with a conductive material. This forms the gate contact 180. Therefore, it is suitable for embodiments that include a large number of gate electrodes in the gate stack structure 120, and the process for forming the gate contact 180 can be easily performed.

[0291] After the processes of forming the second insulating stack portion 122s and forming a portion of the via in the second insulating stack portion 122s, processes for forming an opening for the separation structure, replacing the sacrificial insulating layer 130s with a gate electrode, and forming the separation structure 146 can be performed. In some embodiments, the processes for forming the opening for the separation structure, replacing the sacrificial insulating layer 130s with a gate electrode, and forming the separation structure 146 can be performed between the processes for forming the second insulating stack portion 122s and forming a portion of the via in the second insulating stack portion 122s.

[0292] Based on the above references Figure 36 The description, as an example, depicts an insulating stack structure 120s comprising a first insulating stack portion 121s and a second insulating stack portion 122s. However, the embodiments are not limited thereto. In some embodiments, the insulating stack structure 120s may include three or more insulating stack portions. In this case, partial processing may be repeated. In local processes, a portion of multiple insulating stack portions (e.g., one or more insulating stack portions) may be formed, and a portion of a through-hole may be formed.

[0293] exist Figure 36 In the example shown, the semiconductor device is a bonded semiconductor device. However, the embodiments are not limited thereto. In some embodiments, in Figure 1In the semiconductor device shown, the insulating stack structure 120s may include a plurality of insulating stack portions, and in this example, a partial process may be repeatedly performed. In the partial process, a portion corresponding to at least one of the plurality of insulating stack portions may be formed, and thereafter, portions of the plurality of vias may be formed in the at least one of the plurality of insulating stack portions.

[0294] The following will describe in detail an example of an electronic system that includes semiconductor devices.

[0295] Figure 37 This is a schematic view of an electronic system including semiconductor devices according to an embodiment.

[0296] Reference Figure 37 The electronic system 1000 according to an embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0297] Semiconductor device 1100 may be a non-volatile memory device, such as a reference. Figures 1 to 36 The described NAND flash memory device. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S disposed on the first structure 1100F. In some embodiments, the first structure 1100F may be configured to be adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0298] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to embodiments, the plurality of lower transistors LT1 and LT2 and the plurality of upper transistors UT1 and UT2 may be modified differently.

[0299] In this embodiment, the lower transistor LT1 or LT2 may include a ground select transistor, and the upper transistor UT1 or UT2 may include a string select transistor. The first lower gate line LL1 and the second lower gate line LL2 may be the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0300] The common source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending into the second structure 1100S within the first structure 1100F. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending into the second structure 1100S within the first structure 1100F.

[0301] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations for selecting at least one memory cell transistor from a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0302] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0303] Processor 1210 controls the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be sent through NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0304] Figure 38 This is a perspective view schematically illustrating an electronic system including a semiconductor device according to an embodiment.

[0305] Reference Figure 38 The electronic system 2000 according to an embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 disposed on the main substrate 2001.

[0306] The main substrate 2001 may include a connector 2006 comprising a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In embodiments, the electronic system 2000 may communicate with the external host via any interface, such as Universal Serial Bus (USB), PCI-Express, Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In embodiments, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0307] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0308] DRAM 2004 can be a buffer memory used to mitigate or buffer the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 can also be a high-speed cache memory and can also provide space for temporary data storage during the control operation of the semiconductor package 2003. When the electronic system 2000 includes DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0309] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 disposed on the package substrate 2100, an adhesive layer 2300 at the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0310] The package substrate 2100 may be a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 37 Input / output pads 1101. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Semiconductor chip 2200 may include reference... Figures 1 to 36 The semiconductor device described.

[0311] In an embodiment, the connection structure 2400 may be a bonding wire electrically connecting the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire type, and the semiconductor chips 2200 may be electrically connected to the on-package pads 2130 of the package substrate 2100 using a bonding wire type. According to an embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of a bonding wire type connection structure 2400.

[0312] In an embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interpolator substrate, different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected with each other via wiring on the interpolator substrate.

[0313] Figure 39 and Figure 40 These are schematic cross-sectional views of a semiconductor package according to an embodiment. Figure 39 and Figure 40 Show each Figure 38 An embodiment of a semiconductor package 2003 is shown, and conceptually illustrated by cutting along line I-I'. Figure 38 The semiconductor packaging area obtained in 2003.

[0314] Reference Figure 39 In semiconductor packaging 2003, the packaging substrate 2100 can be a printed circuit board. The packaging substrate 2100 may include a packaging substrate body portion 2120, a top packaging pad 2130 on the upper surface of the packaging substrate body portion 2120, a bottom packaging pad 2125 disposed on or exposed through the lower surface of the packaging substrate body portion 2120, and internal wiring 2135 electrically connecting the top packaging pad 2130 and the bottom packaging pad 2125 within the packaging substrate body portion 2120. The top packaging pad 2130 can be electrically connected to the connection structure 2400. The bottom packaging pad 2125 can be connected to the wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 via conductive connection portions 2800, such as... Figure 38 As shown.

[0315] Semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and a separation structure 3230 passing through the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see reference). Figure 37 ) gate connection line.

[0316] In the semiconductor chip 2200 or semiconductor device according to the embodiment, the gate contact 180 can be disposed in an insulating stack structure to be disposed in a space separated from the penetrating dummy structure, and can stably form the first through portion of the via. This can improve the performance and productivity of the semiconductor chip 2200 or semiconductor device.

[0317] Each of the semiconductor chips 2200 may include peripheral wiring 3110 electrically connected to the first structure 3100 and extending into the second structure 3200 through wiring 3245. Through wiring 3245 may penetrate the gate stack structure 3210 and may be further disposed outside the gate stack structure 3210. Each semiconductor chip 2200 may further include input / output connection wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and input / output pads 2210 electrically connected to the input / output connection wiring 3265.

[0318] In an embodiment, within a semiconductor package 2003, multiple semiconductor chips 2200 can be electrically connected to each other via a connection structure 2400 having a bonding lead type. In some embodiments, multiple semiconductor chips 2200 or multiple portions constituting multiple semiconductor chips 2200 can be electrically connected via a connection structure including a through-silicon via (TSV).

[0319] Reference Figure 40 In a semiconductor package 2003A, each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding type.

[0320] The first structure 4100 may include a peripheral circuit region, which includes peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 located between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 penetrating the gate stack structure 4210, and a word line WL electrically connected to the channel structure 4220 and the gate stack structure 4210 (see [link to relevant documentation]). Figure 37The second bonding structure 4250. For example, the second bonding structure 4250 can be electrically connected to the channel structure 4220 and the word line WL via a bit line 4240 electrically connected to the channel structure 4220 and a gate connection wiring electrically connected to the word line WL. The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 can contact and bond to each other. For example, the bonding portion of the first bonding structure 4150 and the second bonding structure 4250 may include copper (Cu).

[0321] In the semiconductor chip 2200a or semiconductor device according to the embodiment, the gate contact 180 can be disposed in the insulating stack structure 120s in a space separated from the penetrating dummy structure, and the first through portion of the via can be stably formed. This improves the performance and productivity of the semiconductor chip 2200a or semiconductor device.

[0322] Each of the semiconductor chips 2200a may further include an input / output pad 2210 and an input / output connection wiring 4265 at the lower portion of the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0323] In an embodiment, within a semiconductor package 2003A, multiple semiconductor chips 2200a can be electrically connected to each other via a connection structure 2400 having a bonding lead type. In some embodiments, multiple semiconductor chips 2200a, or multiple portions constituting multiple semiconductor chips 2200a, can be electrically connected via a connection structure including a through-silicon via (TSV).

[0324] While some examples have been described in conjunction with what are now considered to be some exemplary embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, and that this disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The unit array area and the connection area, wherein the connection area includes a first area and a second area. The semiconductor device includes: A stacked structure includes a gate stacked structure and an insulating stacked structure, wherein the gate stacked structure is located in the cell array region and the first region, and includes a plurality of gate electrodes and a plurality of interlayer insulating layers, wherein the insulating stacked structure is located in the second region, and includes a plurality of sacrificial insulating layers and a plurality of interlayer insulating layers; A channel structure that passes through the gate stack structure in the cell array region; and A plurality of gate contacts, which are located in the second region and are electrically connected to at least a portion of the plurality of gate electrodes in the first region. Each of the plurality of gate contacts includes a conductive portion and a side insulating layer. The conductive portion includes a through-hole that passes through the insulating stack structure and a connecting portion that extends horizontally to have an area larger than that of the through-hole. The side insulating layer is located on at least a portion of the side surface of the conductive portion, and the plurality of gate contacts include a first contact. The connecting portion has a first surface and a second surface that are opposite to each other, and The penetrating portion of the first contact member includes a first portion located on the first surface of the connecting portion and a second portion located on the second surface of the connecting portion.

2. The semiconductor device according to claim 1, wherein, The side surface of the connection portion in the second region is connected to the side surface of one of the multiple gate electrodes in the first region.

3. The semiconductor device according to claim 1, wherein, The side insulating layer of the first contact is on the side surface of the first portion and spaced apart from the second portion.

4. The semiconductor device according to claim 1, further comprising: The dummy structure is penetrated, which is located in the first region and separated from the plurality of gate contacts in the second region.

5. The semiconductor device according to claim 1, further comprising: The first wiring portion is on the first surface of the stacked structure; as well as The second wiring portion is located on the second surface of the stacked structure opposite to the first surface of the stacked structure. Wherein, the first contact element includes a first connecting contact element, and In the first connecting contact, the first portion is electrically connected to the first wiring portion, and the second portion is electrically connected to the second wiring portion.

6. The semiconductor device according to claim 1, further comprising: The first wiring portion is on the first surface of the stacked structure; as well as The second wiring portion is located on the second surface of the stacked structure opposite to the first surface of the stacked structure. Wherein, the first contact element includes a second connecting contact element, and In the second connecting contact, the first portion is electrically connected to one of the first wiring portion and the second wiring portion, and is electrically insulated from the other of the first wiring portion and the second wiring portion.

7. The semiconductor device according to claim 1, in, The plurality of gate contacts includes a second contact having a structure or shape different from that of the first contact, and In the second contact member, the connecting portion is located at the end of the penetrating portion.

8. The semiconductor device according to claim 1, in, The first contact includes an extension portion, and The extended portion extends horizontally from the second portion and is electrically insulated from the plurality of gate electrodes of the gate stack structure.

9. The semiconductor device according to claim 8, wherein, The area of ​​the extended portion is smaller than the area of ​​the connecting portion.

10. The semiconductor device according to claim 8, wherein, The extension portion is located at the end of the first contact member.

11. The semiconductor device according to claim 8, wherein, The second portion extends through the extended portion and includes portions on the first surface of the extended portion and portions on the second surface of the extended portion.

12. The semiconductor device according to claim 8, in, The extended portion includes multiple extended portions, and The multiple extended portions may have the same area or different areas.

13. The semiconductor device according to claim 1, further comprising: The extended virtual structure includes a virtual penetration section and a virtual extension section. The dummy penetration portion passes through the insulating stack structure, and the dummy extension portion extends horizontally to have an area larger than that of the dummy penetration portion.

14. The semiconductor device according to claim 13, wherein, The extended dummy structure includes at least one of insulating and conductive materials.

15. The semiconductor device according to claim 1, further comprising: A separation structure that passes through the stacked structure. The separation structure includes multiple first separation structures and second separation structures. Each of the plurality of first separation structures extends in a first direction. Wherein, the second separation structure is located between two adjacent first separation structures among the plurality of first separation structures, and extends to a length less than the length of the plurality of first separation structures, and The second region is located between the two adjacent first separation structures and is spaced apart from the second separation structure.

16. The semiconductor device according to claim 15, wherein, The second separation structure includes a plurality of separation portions spaced apart from each other in the first direction.

17. The semiconductor device according to claim 15, in, The gate stack structure includes a first stack portion and a second stack portion stacked on the first stack portion in the thickness direction, and The second separation structure in the first stacked portion and the second separation structure in the second stacked portion have different planar shapes.

18. The semiconductor device according to claim 1, in, The plurality of gate electrodes include a series selection electrode, and In the first region, the string select contact is electrically connected to the string select electrode and has a shape different from that of the plurality of gate electrodes.

19. A semiconductor device, comprising: A stacked structure, comprising a gate stacked structure, wherein the gate stacked structure includes a plurality of gate electrodes and a plurality of interlayer insulating layers; A channel structure that passes through the gate stack structure; to A plurality of gate contacts pass through the stacked structure and are electrically connected to at least a portion of the plurality of gate electrodes. Each of the plurality of gate contacts includes a conductive portion and a side insulating layer. The conductive portion includes a through portion that passes through the stacked structure and a connecting portion that extends horizontally to have an area larger than that of the through portion. The side insulating layer is located on the side surface of the conductive portion. The plurality of gate contacts include a first contact. The connecting portion has a first surface and a second surface that are opposite to each other. The penetrating portion of the first contact member includes a first portion located on the first surface of the connecting portion and a second portion located on the second surface of the connecting portion. The side insulating layer of the first contact is on the side surface of the first portion and spaced apart from the second portion.

20. An electronic system comprising: Main substrate; A semiconductor device on the main substrate; as well as A controller, which is electrically connected to the semiconductor device on the main substrate, The semiconductor device includes a unit array region and a connection region, wherein the connection region includes a first region and a second region. The semiconductor device includes: A stacked structure includes a gate stacked structure and an insulating stacked structure, wherein the gate stacked structure is located in the cell array region and the first region, and includes a plurality of gate electrodes and a plurality of interlayer insulating layers, wherein the insulating stacked structure is located in the second region, and includes a plurality of sacrificial insulating layers and the plurality of interlayer insulating layers; A channel structure that passes through the gate stack structure in the cell array region; and A plurality of gate contacts are located in the second region and are electrically connected to at least a portion of the plurality of gate electrodes in the first region. Each of the plurality of gate contacts includes a conductive portion and a side insulating layer. The conductive portion includes a through-hole that passes through the insulating stack structure and a connecting portion that extends horizontally to have an area larger than that of the through-hole. The side insulating layer is located on at least a portion of the side surface of the conductive portion, and the plurality of gate contacts include a first contact. The connecting portion has a first surface and a second surface that are opposite to each other, and The penetrating portion of the first contact member includes a first portion located on the first surface of the connecting portion and a second portion located on the second surface of the connecting portion.

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