Method of manufacturing a silicon carbide power device
By using a self-aligned ion implantation process, the JFET region and well region of silicon carbide power devices are defined using only two photomasks, and spacers are used for positioning. This solves the problems of high manufacturing cost and implantation area error, achieving cost reduction and improved accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HON HAI PRECISION INDUSTRY CO LTD
- Filing Date
- 2024-12-20
- Publication Date
- 2026-06-23
AI Technical Summary
In the fabrication of silicon carbide power devices, each ion implantation process requires the use of a photomask, resulting in high manufacturing costs and the problem of ion implantation area errors.
Ion implantation is performed using a self-aligned method, with only two photomasks used to define the JFET region and the well region. Other implantation areas are defined by spacers, which are used to locate the ion implantation regions.
This significantly reduces manufacturing costs and effectively minimizes errors in the ion implantation region.
Smart Images
Figure CN122269731A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to silicon carbide power device technology and a method for manufacturing silicon carbide power devices. Background Technology
[0002] Currently, in the process of manufacturing silicon carbide power devices, each ion implantation process requires the use of a corresponding photomask, which results in high manufacturing costs. Furthermore, different ion implantation processes using photomasks may cause errors (offsets) in the ion implantation region. Summary of the Invention
[0003] This invention relates to a method for manufacturing silicon carbide power devices, which can be fabricated in a self-aligned manner and thus reduce manufacturing costs.
[0004] According to an embodiment of the present invention, a method for manufacturing a silicon carbide power device includes the following steps: A substrate is provided, and an epitaxial layer is formed on the surface of the substrate. A first patterned mask layer is formed on the surface of the epitaxial layer, exposing a portion of the surface. A first ion implantation process is performed to form a junction field-effect transistor (JFET) region within the epitaxial layer. The first patterned mask layer is removed. A second patterned mask layer is formed on the surface of the epitaxial layer, exposing the surface of the epitaxial layer outside the JFET region. A second ion implantation process is performed to form well regions within the epitaxial layer on both sides of the JFET region. A first spacer is formed on the sidewall of the second patterned mask layer to shield a portion of the well region. A third ion implantation process is performed to form a self-aligned first heavily doped region within the well region. A second spacer is formed on the side of the first spacer to shield a portion of the first heavily doped region. A fourth ion implantation process is performed to form a self-aligned second heavily doped region within the first heavily doped region. The second patterned mask layer, the first spacer, and the second spacer are removed. A gate structure is formed.
[0005] According to an embodiment of the present invention, another method for manufacturing a silicon carbide power device includes the following steps: A substrate is provided, and an epitaxial layer is formed on the surface of the substrate. A first patterned mask layer is formed on the surface of the epitaxial layer, exposing a portion of the surface. A first ion implantation process is performed to form a junction field-effect transistor (JFET) region within the epitaxial layer. The first patterned mask layer is removed. A second patterned mask layer is formed on the surface of the epitaxial layer, exposing the surface of the epitaxial layer outside the JFET region. A second ion implantation process is performed to form well regions within the epitaxial layer on both sides of the JFET region. A first spacer is formed on the sidewall of the second patterned mask layer, and then a second spacer is formed on the side of the first spacer to shield a portion of the well region. A third ion implantation process is performed to form a self-aligned second heavily doped region within the well region. A third spacer is formed on the side of the second spacer to shield the second heavily doped region. The second spacer is removed to expose a portion of the well region. A fourth ion implantation process is performed to form a self-aligned first heavily doped region between the second heavily doped region and the JFET region. Remove the second patterned mask layer, the first spacer, and the third spacer. Form the gate structure.
[0006] Based on the above, this invention employs a self-aligned approach, requiring only the initial definition of the JFET region and well region using a photomask; the remaining implantation regions can be defined by the formation of spacers. Therefore, the silicon carbide power device process of this invention only requires two photomasks, significantly reducing costs. Furthermore, self-alignment achieves ion implantation positioning through spacers, effectively reducing the offset of the ion implantation region compared to photolithography using photomasks. Attached Figure Description
[0007] Figures 1A to 1J This is a schematic cross-sectional view of the manufacturing process of a silicon carbide power device according to the first embodiment of the present invention;
[0008] Figures 2A to 2F This is a schematic cross-sectional view of the manufacturing process of a silicon carbide power device according to a second embodiment of the present invention. Detailed Implementation
[0009] The following is a detailed description of the embodiments in conjunction with the accompanying drawings; however, the provided embodiments are not intended to limit the scope of the invention. Furthermore, for ease of explanation, the dimensions of the regions or films shown in the drawings are not to actual scale.
[0010] Figures 1A to 1J This is a schematic cross-sectional view of the manufacturing process of a silicon carbide power device according to the first embodiment of the present invention.
[0011] Please refer to Figure 1AA substrate 100 is provided, and an epitaxial layer 102 is formed on the surface of the substrate 100, wherein the substrate 100 is, for example, an N-type silicon carbide substrate, and the epitaxial layer 102 is, for example, an N-type epitaxial layer.
[0012] Next, please refer to Figure 1B A current spread layer (CSL) can be formed within the epitaxial layer 102. In this embodiment, if the epitaxial layer 102 is an N-type epitaxial layer, the current spread layer CSL can be an N-type region. Methods for forming the current spread layer CSL include, but are not limited to, directly performing a CSL ion implantation process IM0 on the epitaxial layer 102 to form a continuous implantation region within the epitaxial layer 102, and the region where the current spread layer CSL is formed is relatively deep.
[0013] Next, please refer to Figure 1C First, a first patterned mask layer 104 can be formed on the surface 102s of the epitaxial layer 102, exposing a portion of the surface 102s. Then, a first ion implantation process IM1 is performed to form a junction field-effect transistor (JFET) region 106 within the epitaxial layer 102. The method for forming the first patterned mask layer 104 can be, for example but not limited to, depositing a hard mask material over the entire surface 102s of the epitaxial layer 102, and then patterning it using a photomask process to obtain a first patterned mask layer 104 covering a portion of the surface 102s of the epitaxial layer 102. Therefore, the first patterned mask layer 104 can be a hard mask, but is not limited to this.
[0014] Then, please refer to Figure 1D Remove Figure 1C After the first patterned mask layer 104, a second patterned mask layer 108 is formed on the surface 102s of the epitaxial layer 102, exposing the surface 102s of the epitaxial layer 102 outside the JFET region 106. The method for forming the second patterned mask layer 108 includes, but is not limited to, depositing a hard mask material over the entire surface 102s of the epitaxial layer 102, and then patterning it using a photomask process to obtain a second patterned mask layer 108 covering a portion of the surface 102s of the epitaxial layer 102. Therefore, the second patterned mask layer 108 can be a hard mask, but is not limited to this. Then, a second ion implantation process IM2 is performed to form well regions 110 within the epitaxial layers 102 on both sides of the JFET region 106. In some embodiments, if the epitaxial layer 102 is an N-type epitaxial layer, the well region 110 can be a P-type well. In some embodiments, the lower portion of the well region 110 may be connected to the current distribution layer CSL, or extend into the current distribution layer CSL.
[0015] Next, please refer to Figure 1EA first spacer 112 is formed on the sidewalls 108s of the second patterned mask layer 108 to partially shield the well region 110. The second patterned mask layer 108 may be, for example, an oxide layer, and the first spacer 112 may be, for example, a polysilicon spacer, but is not limited thereto. In other embodiments, the first spacer 112 may be selected from materials that have etch selectivity with respect to the second patterned mask layer 108. The method of forming the first spacer 112 may include, but is not limited to, forming a spacer material layer conformally on the surface 102s of the epitaxial layer 102, covering the surface 102s and the sidewalls 108s and top 108t of the second patterned mask layer 108, and then anisotropically etching the spacer material layer until the surface 102s of the epitaxial layer 102 is exposed. Due to the process characteristics of the first spacer 112, the dimensions of the first spacers 112 located on both sides of the second patterned mask layer 108 are similar.
[0016] Then, please refer to Figure 1F A third ion implantation process IM3 is performed to form a self-aligned first heavily doped region HD1 within the well region 110. Since the second patterned mask layer 108 and the first spacer 112 partially cover the surface 102s, the first heavily doped region HD1 is self-aligned within the well region 110 outside the first spacer 112.
[0017] Then, please refer to Figure 1G A second spacer 114 is formed on the side 112s of the first spacer 112 to partially shield the first heavily doped region HD1. If the first spacer 112 is a polysilicon spacer, the second spacer 114 can be an oxide spacer, but is not limited to this. In other embodiments, the second spacer 114 can be selected from a material that has etch selectivity with respect to the first spacer 112. The method of forming the second spacer 114 includes, but is not limited to, forming a spacer material layer conformally on the surface 102s of the epitaxial layer 102, covering the surface 102s, the top 108t of the second patterned mask layer 108, and the first spacer 112, and then anisotropically etching the spacer material layer until the surface 102s of the epitaxial layer 102 is exposed. Due to the process characteristics of the second spacer 114, the dimensions of the second spacers 114 located on both sides of the first spacer 112 are similar.
[0018] Next, please refer to Figure 1HA fourth ion implantation process IM4 is performed to form a self-aligned second doped region HD2 within the first heavily doped region HD1. In some embodiments, the doping concentration of the fourth ion implantation process IM4 is greater than the doping concentration of the third ion implantation process IM3, so that the original first heavily doped region HD1 is transformed into a second heavily doped region HD2 with a different conductivity mode. In some embodiments, the doping depth d2 of the second heavily doped region HD2 is, for example, greater than the doping depth d1 of the first heavily doped region HD1. In this embodiment, the first heavily doped region HD1, for example, is an N+ region, serving as the source region of the subsequently formed silicon carbide power device; the second heavily doped region HD2, for example, is a P+ region, which can be used to stabilize the potential.
[0019] Then, please refer to Figure 1I Remove Figure 1H The second patterned mask layer 108, the first spacer 112, and the second spacer 114 are included. Afterwards, an annealing process can be performed to uniformly diffuse the doped region formed in the aforementioned steps into the desired area and eliminate defects in the implanted region. Since only two photomask processes (i.e., forming) are required in the five-stage ion implantation process of this embodiment, this method is more efficient. Figure 1C The first patterned mask layer 104 and Figure 1D The second patterned mask layer 108 can significantly reduce costs, and because the spacer dimensions (such as width) on both sides are similar, the formed first doped region HD1 and second doped region HD2 will have almost no obvious errors.
[0020] Next, please refer to Figure 1J A gate structure 116 is formed. The method for forming the gate structure 116 includes, but is not limited to, forming a gate insulating layer 118 on the surface 102s of the epitaxial layer 102, and then forming a gate electrode 120 on the gate insulating layer 118. Next, a back-to-office (BEOL) structure 122 can be formed. The method for forming the BEOL structure 122 includes, but is not limited to, forming an inner dielectric layer (ILD) and forming contact windows 124a-124b therein that electrically connect the gate electrode 120, the first heavily doped region HD1, and the second heavily doped region HD2.
[0021] Figures 2A to 2F This is a schematic cross-sectional view of the manufacturing process of a silicon carbide power device according to a second embodiment of the present invention, wherein the method is based on... Figure 1D The process begins after the steps described above, in which the formation order of the first heavily doped region HD1 and the second heavily doped region HD2 is changed. Furthermore... Figures 2A to 2F The same reference numerals as in the first embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the first embodiment, which will not be repeated here.
[0022] Please refer to Figure 2A After forming the well region 110, a first spacer 112 is formed on the sidewall 108s of the second patterned mask layer 108, and then a second spacer 200 is formed on the sidewall 112s of the first spacer 112 to partially shield the well region 110. In some embodiments, the second spacer 200 may be an oxide spacer. To accommodate subsequent processes, the height h1 of the first spacer 112 may be greater than the height h2 of the second spacer 200, but is not limited thereto. In some embodiments, the thickness t1 of the second patterned mask layer 108 is greater than the height h2 of the second spacer 200. The method of forming the second spacer 200 includes, for example but not limited to, forming a spacer material layer conformally on the epitaxial layer 102, and then isotropically etching the spacer material layer until the epitaxial layer 102 is exposed.
[0023] Next, please refer to Figure 2B A third ion implantation process IM3' is then performed to form a self-aligned second heavily doped region HD2 within the well region 110. The third ion implantation process IM3' differs from the third ion implantation process IM3 in the first embodiment.
[0024] Then, please refer to Figure 2C A third spacer 202 is formed on the side 200s of the second spacer 200 to shield the second heavily doped region HD2. In some embodiments, if the second spacer 200 is an oxide spacer, the third spacer 202 may be a nitride spacer or a polysilicon spacer. The method for forming the third spacer 202 can refer to the above description of the formation of the second spacer 200, and will not be repeated here.
[0025] Next, please refer to Figure 2D Remove first Figure 2C The second spacer 200 exposes a portion of the well region 110. The second spacer 200 can be removed, for example, by isotropic etching. During isotropic etching, if the second patterned mask layer 108 and the second spacer 200 are both oxides, the second patterned mask layer 108 will also be etched together, but will not be completely removed. Then, a fourth ion implantation process IM4' is performed to form a self-aligned first heavily doped region HD1 between the second heavily doped region HD2 and the JFET region 106, with the first heavily doped region HD1 and the JFET region 106 separated by a distance. The fourth ion implantation process IM4' differs from the fourth ion implantation process IM4 in the first embodiment. In some embodiments, since the second heavily doped region HD2 and the first heavily doped region HD1 are implanted into the well region 110 respectively, the fourth ion implantation process IM4' and the third ion implantation process IM3' can have parameters such as doping concentration and doping depth adjusted as needed, so that the second heavily doped region HD2 and the first heavily doped region HD1 have the same or similar doping concentration and / or doping depth, but are not limited thereto.
[0026] Next, please refer to Figure 2E Remove Figure 2C After the second patterned mask layer 108, the first spacer 112 and the third spacer 202 are formed, an annealing process can be performed to uniformly diffuse the doped region formed in the aforementioned steps into the desired region and eliminate defects in the implanted region.
[0027] Then, please refer to Figure 2F , can be according to Figure 1J The process involves first forming a gate structure 116, and then forming a back-to-office (BEOL) structure 122. In some embodiments, the gate structure 116 includes a gate insulating layer 118 and a gate electrode 120 thereon. In some embodiments, the BEOL structure 122 includes an inner dielectric layer (ILD), contact windows 124a-124b, etc.
[0028] In summary, this invention utilizes a self-aligned approach for multi-channel ion implantation to reduce the positional error of the implantation area caused by exposure, while also reducing the cost of photomask fabrication in silicon carbide processes.
[0029] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for manufacturing a silicon carbide power device, characterized in that, include: A substrate is provided, on the surface of which an epitaxial layer is formed; A first patterned mask layer is formed on the surface of the epitaxial layer, exposing a portion of the surface; A first ion implantation process is performed to form a JFET region within the epitaxial layer; Remove the first patterned mask layer; A second patterned mask layer is formed on the surface of the epitaxial layer to expose the surface of the epitaxial layer outside the JFET region; A second ion implantation process is performed to form a well region within the epitaxial layer on both sides of the JFET region; A first spacer is formed on the sidewall of the second patterned mask layer to partially cover the trap region; A third ion implantation process is performed to form a self-aligned first heavily doped region within the well region; A second spacer is formed on the side of the first spacer to shield part of the first heavily doped region; A fourth ion implantation process is performed to form a self-aligned second doped region within the first heavily doped region; Remove the second patterned mask layer, the first spacer, and the second spacer; and A gate structure is formed.
2. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that, Before forming the JFET, a current distribution layer is formed within the epitaxial layer.
3. The method for manufacturing a silicon carbide power device according to claim 2, characterized in that, The epitaxial layer is an N-type epitaxial layer, and the current distribution layer is an N-type region.
4. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that, The well region is a P-type well, the first heavily doped region is an N+ region, and the second heavily doped region is a P+ region.
5. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that, The second patterned mask layer is an oxide layer, the first spacer is a polysilicon spacer, and the second spacer is an oxide spacer.
6. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that, After removing the second patterned mask layer, the first spacer, and the second spacer, an annealing process is also performed.
7. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that, The doping depth of the second doped region is greater than that of the first doped region.
8. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that, The doping concentration of the fourth ion implantation process is greater than that of the third ion implantation process.
9. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that, The first patterned mask layer and the second patterned mask layer include hard masks.
10. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that, After forming the gate structure, the process also includes forming the subsequent process structure.
11. A method for manufacturing a silicon carbide power device, characterized in that, include: A substrate is provided, on the surface of which an epitaxial layer is formed; A first patterned mask layer is formed on the surface of the epitaxial layer, exposing a portion of the surface; A first ion implantation process is performed to form a JFET region within the epitaxial layer; Remove the first patterned mask layer; A second patterned mask layer is formed on the surface of the epitaxial layer to expose the surface of the epitaxial layer outside the JFET region; A second ion implantation process is performed to form a well region within the epitaxial layer on both sides of the JFET region; A first spacer is formed on the sidewall of the second patterned mask layer; A second spacer is formed on the side of the first spacer to partially shield the trap area; A third ion implantation process is performed to form a self-aligned second heavily doped region within the well region; A third spacer is formed on the side of the second spacer to shield the second heavily doped region; Remove the second spacer to expose a portion of the trap area; A fourth ion implantation process is performed to form a self-aligned first heavily doped region between the second heavily doped region and the JFET region; Remove the second patterned mask layer, the first spacer, and the third spacer; and A gate structure is formed.
12. The method for manufacturing a silicon carbide power device according to claim 11, characterized in that, Before forming the JFET, a current distribution layer is formed within the epitaxial layer.
13. The method for manufacturing a silicon carbide power device according to claim 12, characterized in that, The epitaxial layer is an N-type epitaxial layer, and the current distribution layer is an N-type region.
14. The method for manufacturing a silicon carbide power device according to claim 11, characterized in that, The well region is a P-type well, the first heavily doped region is an N+ region, and the second heavily doped region is a P+ region.
15. The method for manufacturing a silicon carbide power device according to claim 11, characterized in that, The second patterned mask layer is an oxide layer, the first spacer is a polysilicon spacer, the second spacer is an oxide spacer, and the third spacer is a nitride spacer or a polysilicon spacer.
16. The method for manufacturing a silicon carbide power device according to claim 11, characterized in that, After removing the second patterned mask layer, the first spacer, and the third spacer, an annealing process is also performed.
17. The method for manufacturing a silicon carbide power device according to claim 11, characterized in that, The thickness of the second patterned mask layer is greater than the height of the second spacer.
18. The method for manufacturing a silicon carbide power device according to claim 11, characterized in that, The height of the first spacer is greater than the height of the second spacer.
19. The method for manufacturing a silicon carbide power device according to claim 11, characterized in that, The first patterned mask layer and the second patterned mask layer include hard masks.
20. The method for manufacturing a silicon carbide power device according to claim 11, characterized in that, After forming the gate structure, the process also includes forming the subsequent process structure.