Manufacturing process of a HEMT device with field plates

Abstract

Modified fabrication processes for transistors with field plates, such as gallium nitride heterostructure transistors, reduce exposure of surfaces near the transistor channel, mitigating damage and performance degradation from sensitive surfaces and interfaces exposed to high temperatures and the risk of etch-induced damage. Such processes include sequential dielectric formation and patterning, allowing for gate electrode and field plate electrode formation after high temperature processing steps. A passivation layer can also serve as an etch stop for other dielectric materials, enabling protection of the channel region during dry etch processes followed by selective wet etching that removes the passivation layer immediately prior to gate electrode formation and other steps. Such methods also enable surface modification processes to be performed to selectively enhance channel conductivity, followed by passivation of the modified surface to maintain the enhanced conductivity during subsequent processing steps.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to transistors having field plates and methods for manufacturing such devices. Background Technology

[0002] Semiconductor devices are used in a wide variety of electronic components and systems. High-power, high-frequency transistors are used in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly well-suited for these RF power and power electronics applications due to its excellent electronic and thermal properties. Specifically, GaN's high electron velocity and high breakdown field strength make devices made from this material ideal for RF power amplifiers and high-power switching applications. Field plates are used to reduce gate-drain feedback capacitance and increase the device breakdown voltage in high-frequency transistors. Therefore, semiconductors, especially GaN transistors with field plates, are needed. Summary of the Invention

[0003] According to a first aspect of the present invention, a method of manufacturing a semiconductor device, the method comprising: receiving a semiconductor substrate having a channel region capable of operating as a transistor channel, wherein the channel region extends between a first current terminal region at a first end of the channel region and a second current terminal region at a second end of the channel region, wherein a first dielectric stack is disposed directly on a top surface of the channel region; patterning the first dielectric stack to simultaneously form: a first opening in the first dielectric stack, the first opening being located between the first end of the channel region and the second end of the channel region; and a second opening, the second opening passing through at least one of the first dielectric stacks between the first opening and the second end of the channel region. The method comprises: forming a dielectric spacer layer over a patterned first dielectric stack and within the first and second apertures; patterning the spacer layer to selectively remove the spacer layer over the first aperture; forming a conductive gate electrode in a gate aperture having a location defined by the first aperture, directly contacting the top surface of the channel region; forming an interlayer dielectric layer over the gate electrode; selectively removing the interlayer dielectric layer to form a field plate aperture having a location defined by the second aperture; and forming a conductive field plate electrode in the field plate aperture; wherein the first dielectric stack comprises: a first dielectric layer; and a first etch stop layer, the first etch stop layer being disposed directly on the first dielectric layer.

[0004] In one or more embodiments, the method further includes: forming a second dielectric stack directly on the spacer layer, the second dielectric stack including a second etch-stop layer and a second dielectric layer directly on the second etch-stop layer; removing the second dielectric layer above the first opening by using a first etch without removing the etch-stop layer, and removing the second etch-stop layer by using a second etch without removing the spacer layer; patterning the second dielectric stack to form a patterned portion of the second dielectric stack exposing the spacer layer in the first aperture; and patterning the spacer layer using a third etch to expose the top surface of the channel region in the first opening.

[0005] In one or more embodiments, the first dielectric layer and the second dielectric layer are formed from silicon nitride material using low-pressure chemical vapor deposition (LPCVD); and the first etch stop layer and the second etch stop layer are formed from aluminum oxide material.

[0006] In one or more embodiments, the first etch stop layer, the second etch stop layer, or both the first etch stop layer and the second etch stop layer are formed using atomic layer deposition (ALD).

[0007] In one or more embodiments, the method further includes: protecting the patterned portion of the second dielectric stack above the second opening from the first etch, the second etch, and the third etch; and selectively removing at least a portion of the patterned portion of the second dielectric stack above the second opening by: selectively removing the second dielectric layer using a fourth etch that does not remove the second etch stop layer; and selectively removing the second etch stop layer using a fifth etch that does not remove the spacer layer; wherein a first portion of the field plate electrode is directly disposed on the spacer layer in the field plate aperture above the second opening.

[0008] In one or more embodiments, the width of the field plate aperture at the second dielectric layer is wider than the width of the second opening in the first dielectric layer, and the center of the field plate aperture is offset from the center of the second opening.

[0009] In one or more embodiments, the first dielectric stack further includes a third dielectric layer directly disposed on the first etch-stop layer; and patterning the first dielectric stack includes: patterning the third dielectric layer using a first etch that does not remove the first etch-stop layer to form the first opening in the third dielectric layer; patterning the third dielectric layer using the first etch to form the second opening in the third dielectric layer; removing the first etch-stop layer from the first opening and the second opening using a second etch that does not remove the first dielectric layer; forming a masked portion of the third dielectric layer surrounding the second opening using a masking material; selectively removing the remaining third dielectric layer surrounding the masked portion of the third dielectric layer by using a third etch that does not remove the first etch-stop layer to form an exposed portion of the first dielectric layer; forming the first opening in the first dielectric layer below the first opening in the third dielectric layer using a fourth etch that does not remove the top surface of the channel region; and removing the first etch-stop layer from the exposed portion of the first dielectric layer using a fifth etch that does not remove the first dielectric layer.

[0010] In one or more embodiments, the method further includes: forming a second etch-stop layer over the patterned first dielectric stack prior to forming the spacer layer; wherein patterning the spacer layer to selectively remove the spacer layer around the first opening includes etching the spacer layer using a sixth etch that does not remove the second etch-stop layer; and wherein the method further includes removing the second etch-stop layer from the first opening using a seventh etch that does not remove the top surface of the channel region prior to forming the gate electrode.

[0011] In one or more embodiments, the method further includes selectively removing the spacer layer within the field plate aperture using a seventh etch that does not remove the second etch termination layer.

[0012] In one or more embodiments, the method further includes removing the second etch termination layer from the field plate aperture using an eighth etch that does not remove the first dielectric layer or the third dielectric layer.

[0013] In one or more embodiments, the width of the field plate aperture at the third dielectric layer is wider than the width of the second opening in the first dielectric layer, and the center of the field plate aperture is offset from the center of the second opening.

[0014] In one or more embodiments, the first dielectric layer and the second dielectric layer are formed from silicon nitride material using low-pressure chemical vapor deposition (LPCVD); and the first etch stop layer and the second etch stop layer are formed from aluminum oxide material.

[0015] In one or more embodiments, the first etch stop layer, the second etch stop layer, or both the first etch stop layer and the second etch stop layer are formed using atomic layer deposition (ALD).

[0016] In one or more embodiments, the method further includes thermally annealing the substrate at a temperature greater than 300°C to reduce charge trapping in the remaining portion of the first etch-stop layer.

[0017] In one or more embodiments, the spacer layer is patterned to selectively remove the spacer layer above the first opening, leaving a portion of the spacer layer intact along the sidewall of the first opening. Attached Figure Description

[0018] This disclosure is illustrated by means of examples, embodiments, etc., and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The accompanying drawings, together with the detailed description, are incorporated in and form a part of this specification, and are used to further illustrate examples, embodiments, etc., and to explain various principles and advantages based on this disclosure. In the accompanying drawings:

[0019] Figure 1 This is a schematic cross-sectional view of an example transistor according to one or more embodiments.

[0020] Figure 2A , Figure 2B and Figure 2C This illustrates an embodiment of a method for manufacturing, for example... Figure 1 A flowchart of the steps in an example process for a transistor with a field plate.

[0021] Figure 3 This is a schematic cross-sectional view of another example transistor according to one or more embodiments.

[0022] Figure 4A and Figure 4B A flowchart illustrating steps in an additional example process for manufacturing a transistor having a field plate, according to embodiments of this document.

[0023] Figure 5 This is a cross-sectional schematic diagram showing a portion of a transistor according to one or more embodiments in more detail.

[0024] Figure 6This is a schematic cross-sectional view of another example transistor with a field plate according to one or more embodiments.

[0025] Figure 7A and Figure 7B This illustrates a transistor suitable for manufacture according to one or more embodiments (e.g., Figure 6 A flowchart of the steps of an example process for a transistor.

[0026] Figure 8A Another example transistor according to one or more embodiments is shown.

[0027] Figure 8B Another example transistor according to one or more embodiments is shown.

[0028] Figure 8C The gate of the transistor is shown in more detail.

[0029] Figure 9A and Figure 9B This illustrates a method for manufacturing transistors according to one or more embodiments (e.g. Figure 8A or Figure 8B A flowchart of steps in an example process for a transistor.

[0030] Figure 9C Depicted in one or more embodiments in, for example Figure 9A and Figure 9B The steps performed in processes such as manufacturing.

[0031] Figure 9D Depicted in one or more embodiments in, for example Figure 9A and Figure 9B The steps performed in processes such as manufacturing.

[0032] Figure 10A and Figure 10B Describing and Figure 9A and Figure 9B Alternative processes related to the process.

[0033] Figure 11 This is a cross-sectional view of another example transistor according to one or more embodiments.

[0034] Figure 12A and Figure 12B This illustrates a method of manufacturing, for example, according to one or more embodiments. Figure 11 A flowchart of the steps of an example process for transistors, including transistors and related transistors.

[0035] Figure 13 This is a cross-sectional view of another example transistor according to one or more embodiments.

[0036] Figure 14A and Figure 14B This illustrates a method of manufacturing, for example, according to one or more embodiments. Figure 13 A flowchart of the steps of an example process for transistors, including transistors and related transistors. Detailed Implementation

[0037] The following detailed description is provided as examples for understanding purposes and is not intended to limit the embodiments and uses of this disclosure. It should be understood that many related technologies and apparatuses, as well as apparatus variations, are disclosed for ease of understanding, and these technologies and variations can be combined in various ways. It should also be understood that the applicant has chosen to claim protection for a specific combination of the disclosed technologies and / or apparatuses, and not for every disclosed combination. Furthermore, there is no intention to be bound by any explicit or implicit theory presented in the foregoing technical fields, background art, or specific embodiments.

[0038] For simplicity and clarity, the elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements or regions in the figures may be enlarged relative to other elements or regions to aid in understanding embodiments of the invention. Unless otherwise stated, directional references, such as “top,” “bottom,” “left,” “right,” “above,” “below,” etc., are not intended to claim any preferred orientation, but are for illustrative purposes and refer to the orientation of one or more corresponding figures. Furthermore, for clarity, well-known and conventional features may be omitted from the figures and detailed descriptions.

[0039] Figure 1 This is a schematic cross-sectional view of an example transistor according to one or more embodiments. Transistor 100 is formed on a semiconductor substrate 102 and has a channel region 110 adjacent to the top surface 112 of the substrate 102. Transistor 100 includes a first current terminal 120 electrically coupled to a first end of the channel region 110 and a second current terminal 125 electrically coupled to a second end of the channel region 110 opposite to the first current terminal 120. It should be understood that the features of the transistor 100 described above (and other example transistors herein) are compatible with various transistor technologies. For example, transistor 100 and / or any other example transistor according to embodiments herein may be a metal-MOSFET or MISFET fabricated on a silicon substrate or any other suitable semiconductor substrate. For example, in one or more embodiments, the transistor, such as transistor 100, is a high electron mobility transistor (“HEMT”) based on a group III-V compound semiconductor, also referred to as a heterostructure field-effect transistor (“HFET”). In such embodiments, according to known techniques, the effective semiconductor channel may be a 2D electron gas (“2DEG”) formed at a semiconductor heterojunction disposed together with the channel region 110.

[0040] A passivation material 115 (e.g., a dielectric) is disposed on the top surface 112, covering the channel region 110. A first current terminal 120 and a second current terminal 125 can be formed by any suitable method. For example, these two current terminals can be suitable doped regions within the semiconductor substrate 102, or as metal contacts deposited in recesses of the substrate 102 or on the surface of the substrate 102. The current terminals 120, 125 can be covered by corresponding metal contacts (not shown) that penetrate one or more dielectric layers to make direct electrical contact with the current terminals, or contacted in any other suitable manner.

[0041] Passivation material 115 is covered by dielectric materials 142 and 145 (interlayer dielectric 145), as shown. A conductive first electrode (hereinafter referred to as the control electrode or gate 130) contacts the channel region 110 through an aperture 135 in the passivation material 115 and the dielectric materials 140, 142. As shown, the gate 130 has a first end 132 in contact with the channel region 110 within the aperture, and optionally a second end 134 suspended above the passivation dielectric material 140. Although the gate 130 is depicted as having vertical sidewalls, it should be understood that the gate 130 may have any suitable geometry. For example, the first end 132 of the control electrode may have curved or sloping sidewalls. Similarly, the second end 134 of the gate 130 may have curved or sloping sidewalls, and the top surface (farthest from the channel region 110) may have any suitable geometry. The gate 130 is disposed along the length of the channel region 110 between a first current terminal 120 and a second current terminal 125.

[0042] It should be understood that the first current terminal 120 can be used as, for example, the source terminal of transistor 100, and the second current terminal 125 can be used as, for example, the drain terminal of transistor 100. It should also be understood that the gate 130 is suitable as a control electrode of transistor 100, such that when a suitable bias voltage is applied to the gate 130, the channel region 110 is configured to provide a conductive path between the first current terminal 120 and the second current terminal 125.

[0043] Additional dielectric material covers various portions of the gate 130 and the channel region 110. For example, such as Figure 1 As shown, in one or more embodiments, interlayer dielectric material 145 covers the gate, and in some regions, dielectric material 140 or dielectric material 142 and passivation material 115 are also covered. Figure 1As shown, transistor 100 further includes a second electrode (hereinafter referred to as field plate 150) having a first end 152 disposed above channel region 110 between gate 130 and second current terminal 125, and a second end 154 extending away from substrate 102. As shown, the field portion of field plate 150 closest to channel region 110 is disposed within an aperture 155 in dielectric material 142, and additional portions of field plate 150 are disposed within wider apertures in interlayer dielectric material 145. As shown, in one or more embodiments, a portion of field plate 150 may cover dielectric material 142 and also cover interlayer dielectric material 145 in the region between aperture 155 and current terminal 125 (which may function as drain of transistor 100).

[0044] It should be understood that only a portion of field plate 150 is shown, and field plates such as field plate 150 may remain "floating" (i.e., not directly connected to any other part of the transistor), coupled to a fixed potential reference such as a power supply voltage terminal or ground terminal, or coupled to another part of the transistor, such as the gate, source, or drain terminals such as gate 130 (e.g., current terminals 120 or 125). As a non-limiting example, field plate 150 may include a portion covering gate 130 and extending further over channel region 110 (e.g., portion 154a indicated by dashed lines). In this example, field plate 150 may also directly contact current terminal 120 configured as the source of transistor 100. In another non-limiting example, field plate 150 may include a portion extending toward current terminal 125 (e.g., portion 154b indicated by dashed lines). Additionally, in one or more embodiments, aperture 155 may be formed only in interlayer dielectric 145, such that a second end 154 of field plate 150 is disposed on dielectric material 142 rather than passivation material 115.

[0045] It should be understood that when the first current terminal 120 is used as the source terminal of transistor 100, the field plate 150 can be configured as a field plate coupling the source. The field plate 150 can be coupled to the current terminal 120 (which can be used as the source of transistor 100) via one or more additional conductive interconnects not shown. In one or more embodiments, the field plate 150 can extend at one or more locations to directly contact the current terminal 120 (i.e., in the shown cross-sectional plane or in one or more other cross-sectional planes of transistor 100). In transistor 100, during operation of transistor 100, the conductivity of the channel region 110 will be affected by the potentials of the gate 130 and the field plate 150. It should be understood that the field plate 150 is primarily capacitively coupled to the channel region 110 across the field passivation material 115. Simultaneously, the field plate 150 is also primarily capacitively coupled to the gate 130 across the interlayer dielectric material 145.

[0046] In one or more embodiments, additional passivation material 147 is deposited within the field plate orifice 155 prior to the formation of the field plate 150. In one or more such embodiments, passivation material 115 is removed from the bottom of the orifice 155 prior to the formation of the field plate 150.

[0047] Generally, compared to other similar transistors without such field plates, field plates such as field plate 150 can be used to reduce the gate-drain feedback capacitance (“C”) in transistors such as transistor 100 when coupled to the source terminal of the transistor. GD However, adding a field plate that couples the source to the control electrode (e.g., gate 130) often introduces additional capacitance between the gate and the source ("C"). GS This is typically an undesirable compromise. In the embodiments described herein, multiple dielectric layers can be used to implement C. GD The expected value, while reducing the additional C introduced by the field plate. GS In addition, the shape of the field plate electrode, especially the shape near the channel region (e.g., the first end 152 of the field plate 150), can affect the electric field distribution in the channel region, which in turn can affect the performance characteristics of the transistor, such as the breakdown voltage (as a non-limiting example).

[0048] It should be understood that, in one or more embodiments, the various dielectric layers and electrodes described herein may be jointly configured and arranged to achieve certain performance metrics or other device characteristics, and such metrics may be defined in absolute or relative terms. Non-limiting examples include, for example, C. GD and / or C GS The absolute capacitance value, and the ratio between such capacitance values. These and other capacitance values ​​can be expressed as absolute capacitance, or capacitance per unit cross-sectional area, or capacitance per unit length.

[0049] In the transistor 100 and related transistors according to the embodiments described herein, certain advantages can be achieved by using multiple dielectric layers configured as described. Specifically, the relative permittivity and thickness of each of these materials can be selected to achieve desired performance characteristics and facilitate various manufacturing processes in the embodiments herein. In one or more embodiments, the passivation material 115 is silicon oxide or aluminum oxide. In one or more embodiments, the dielectric material 140 is a nitride, and the dielectric material 142 is also a nitride. For example, in Figure 1 In the example, the relative thickness and dielectric constant of the passivation material 115 often determine the influence of the field plate 150 (which operates as a field plate for coupling the source) on the channel region 110 and C of the transistor 100. GD The effect of (i.e., the capacitance between gate 130 and the second current terminal 125). Meanwhile, the dielectric constant and thickness of dielectric materials 140, 142, and 145 will largely determine the additional C. GSPenalty. Therefore, a material with a relatively high dielectric constant can be selected as the passivation material 115 to maximize the effect of the field plate 150 on the channel region 110. Therefore, it should be understood that, according to the embodiments herein, the presence of the interlayer dielectric material 145 can reduce the C introduced by the portion of the field plate 150 covering the gate 130 in at least two ways. GS Penalty. First, the distance between the field plate 150 and the gate 130 can be increased by the additional thickness added by the interlayer dielectric material 145 disposed on the dielectric material 142 and the gate 130. Second, the interlayer dielectric material 145 can be selected to have a lower dielectric constant than the dielectric material 142, thereby further reducing the unwanted additional C. GS .

[0050] It should be understood that the portions of the gate 130 and field plate 150 closest to the channel region 110 often significantly affect the operating characteristics of the transistor 100. This is especially true, as in one or more embodiments, if the passivation material 115 is relatively thin compared to the dielectric materials 140, 142 and / or if the passivation material 115 has a relatively high dielectric constant compared to the dielectric materials 140, 142 and 145. In such embodiments, it should be understood that the characteristics of the transistor 100, such as C... GS C DS The source-drain breakdown voltage (as a non-limiting example) will depend on the relative positioning of the gate 130 and the field plate 150, specifically the center-to-center distance between the first end 132 of the gate 130 within the aperture 135 and the first end 152 of the field plate 150 within the aperture 155.

[0051] In one or more embodiments, the passivation material 115 is an alumina material with a thickness ranging from 20 to 5,000 angstroms. In one or more embodiments, the passivation material 115 has a thickness ranging from 50 to 1,000 angstroms. In one or more embodiments, the dielectric material 140 is silicon nitride with a thickness ranging from 100 to 2,000 angstroms, but other ranges may be used in one or more other embodiments. In one or more embodiments, the dielectric material 142 has a thickness ranging from 50 to 2,000 angstroms, but other ranges may be used in one or more other embodiments. In one or more embodiments, the interlayer dielectric material 145 is silicon oxide or silicon nitride with a thickness ranging from 20 to 10,000 angstroms.

[0052] While the above thickness ranges are given as examples, it should be understood that other ranges apply in one or more embodiments. It should be further understood that the choice of material and thickness for various dielectrics can be expressed based on the equivalent oxide thickness (“EOT”, i.e., the SiO2 thickness required to produce the same capacitance in a capacitor structure when using different dielectrics). For example, a SiO2 layer with a relative permittivity of 3.8 can be used as a reference. For illustration, it can be said that a 10 nm thick SiO2 layer has a 10 nm EOT, while a 10 nm thick Si3N4 layer with a relative permittivity of 9.5 has only a 4 nm EOT due to the higher electrical permeability of the Si3N4 material.

[0053] In one or more embodiments, such as transistor 100, the transistor is a gallium nitride (GaN)-based HEMT. In one or more embodiments of this type, a 2DEG is formed at the interface between the GaN layer and an aluminum-doped layer, the aluminum-doped layer having the chemical formula Al. x Ga 1-x N or Al x In (1-x) N describes the stoichiometric composition, where x is between 0 and 1. In such embodiments, it should be understood that the effective channel may be embedded within the channel region 110 and does not extend to the top surface 112 of the channel region 110. In one or more embodiments, the passivation material 115 may be a material that provides surface passivation for the channel region 110 (e.g., by mitigating the effects of undesirable available electronic energy states caused by dangling bonds at the top surface 112 of the substrate 102).

[0054] Along these lines, channel region 110 is shown as region 111 between gate 130 and current terminal 125, region 111 being shaded to indicate portions of channel region 110 with modified electrical properties. This will be discussed in conjunction with... Figure 2A , Figure 2B and Figure 2C To further explain, the conductivity of the channel region can be modified by selectively applying a surface treatment to the top surface 112 of the substrate. Such surface treatments can affect the properties of the 2DEG (or 2DHG) formed at the buried heterojunction through various mechanisms, including but not limited to reducing charge trapping at the top surface 112 and / or increasing the 2DEG conductivity at and / or below the 111 region.

[0055] As will be further explained, transistors such as transistor 100 can be manufactured using various processes that protect surfaces important to device performance from processing steps that may damage these surfaces or alter them in an undesirable manner. As indicated above and further described below, such processes can also be used to intentionally alter portions of such surfaces. Furthermore, in some such processes, it is desirable to alter specific portions of the surface, and then additional processing steps are performed to ensure that the desired surface alteration is retained during further processing. For example, when transistors such as transistor 100 are in a conducting state, where a conductive path is formed in the channel region 110 between current terminals 120, 125, it may be necessary to increase the conductivity of the channel region 110. It is noteworthy that transistors 100 and other transistors according to embodiments herein can be manufactured using a process in which the location of the region undergoing surface modification is self-aligned with the location of the gate electrode, field plate, or similar structure (one example of a process is process 200 below) (i.e., one or more process steps defining the final location of one or more structures or features also simultaneously define the final location of the modified region and the distance between those elements, even if the structure or feature itself is formed or completed at different times).

[0056] Increasing the conductivity of the channel region 110 can produce a higher maximum drain current density, which can provide better power handling in power devices such as RF switches and amplifiers, and can also reduce parasitic resistance in areas that make electrical contact with the device (e.g., source and drain connections). However, increasing the channel conductivity can lead to increased gate leakage. Therefore, it may be necessary to selectively increase the channel conductivity between the gate 130 and the current terminal (e.g., current terminal 125) that operates as the drain, while leaving the channel region 110 unmodified below or immediately adjacent to the gate 130. However, this level of control may be difficult or impossible to achieve using conventional transistor design and process flows. Modified surfaces can also reduce charge trapping at surfaces (e.g., in GaN heterostructures), which can result in devices exhibiting improved performance (e.g., higher operating power density).

[0057] Figure 2A , Figure 2B and Figure 2C Example steps in an example process 200 for manufacturing a transistor having a field plate, according to embodiments of this document, are shown. The following is in conjunction with… Figure 1 The process 200 is described in terms of the fabrication of transistor 100. Process 200 enables selective modification of the channel region 110 in region 111 while protecting the channel region below gate 130.

[0058] Process 200 includes fabrication on substrate 102. Figure 1Steps 210, 220, 230, 240, 250, 260, 270, 280, and 290 performed by transistor 100. As described below, although gate 130 may be formed at a later time, process 200 can provide certain advantages by allowing the relative positioning of aperture 135 and surface-modified region 111 (and thus the final positioning of gate 130) to be determined simultaneously in a single patterning step (e.g., by a single photolithographic exposure).

[0059] As mentioned above, including Figures 2A to 2C The diagrams are not necessarily drawn to scale. Therefore, it should be understood that... Figures 2A to 2C Certain details regarding the relative dimensions and geometry of various elements may be omitted for the purposes of process 200 depicted in the figures and other processes depicted in subsequent figures. It should also be understood that, for clarity, well-known parts of process 200, such as the photolithography patterning step (as a non-limiting example), may not be shown, and for clarity, a series of multiple process steps may be described as a single step.

[0060] At the start of process 200, substrate 102 may already have channel region 110 and other existing structures, such as bonding. Figure 1 The current terminals 120 and 125 are described. In step 210, dielectric material 140 is patterned on the top surface 112 of substrate 102 to define the location of aperture 135. Dielectric material 140 can be patterned by any suitable method, including but not limited to subtractive processes, which include depositing a blanket film followed by photolithographic patterning and etching to remove unwanted material from the top surface 112. Other processes, such as additive processes, can also be used, which include photolithographically patterning a resist used as a mask for depositing dielectric material 140, followed by a stripping process to remove unwanted material not directly deposited on the top surface 112 of substrate 102.

[0061] The sidewalls of the aperture 135, defined by the dielectric material 140, may have any suitable profile. As a non-limiting example, the sidewalls of the aperture 135 may be inclined as shown, or the sidewalls may be vertical. It should be understood that the sidewall profiles of the aperture and other related structures can be controlled by selecting the etching process and process parameters. For example, an isotropic etching process or an anisotropic etching process may be used.

[0062] As shown, in step 220, passivation material 115 has been deposited or otherwise formed over the top surface 112 and the exposed portion of the patterned dielectric material 140. The passivation material 115 and the dielectric material 140, and / or the relative thickness of these materials, can be selected such that the passivation material 115 can be removed by a suitable selective etching process that does not etch the dielectric material 140 or the substrate 102. For example, in one or more embodiments, the passivation material 115 is aluminum oxide. In one or more such embodiments, the passivation material is deposited by a process that produces a conformal layer with a thickness in the range of 10 to 400 angstroms; as a non-limiting example, this process includes atomic layer deposition (ALD). Subsequently, a photoresist or any other suitable masking material 222 is deposited over the passivation material 115 and patterned as shown.

[0063] In step 230, the passivation material 115 is patterned to selectively remove the passivation material 115 above region 111. A surface modification process 232 is performed on the newly exposed portion of the top surface 112 to improve the conductivity of the channel region 110 during operation of the transistor 100 and / or modify the surface properties of the GaN surface above region 111. The surface treatment process can be any of a number of suitable processes, including, as non-limiting examples, wet chemical surface treatment, plasma-based surface treatment, thermal annealing in a controlled atmosphere, ion bombardment or controlled etching to thin the top surface 112 (e.g., via atomic layer etching or another suitable process), or any suitable combination of such processes. During the surface modification process 232, the remaining portions of the top surface 112 are protected from modification by the remaining passivation material 115 and dielectric material 140. In one or more embodiments, the masking material 222 is removed prior to performing the surface modification process 232. In one or more embodiments, the passivation material 115 is also partially removed near the current terminal 120, thereby allowing the surface modification process 232 to modify the channel region 110 near the current terminal 120, excluding region 111. It should be understood that because the dielectric material 140 is patterned in process 200 prior to the deposition of the passivation material 115, a coarse-grained lithography process can be used to define the openings in which the passivation material 115 is removed, wherein any exposed portions of the dielectric material act as hard masks precisely defining the positioning of the modified regions.

[0064] In step 240, dielectric material 142 is deposited or otherwise formed on top surface 112. It should be understood that, in one or more embodiments, additional passivation material 115 may be deposited or otherwise formed over region 111 prior to dielectric material 142, as indicated by the dashed portion of passivation material 115 shown in step 240. The additional passivation material 115 can be used to prevent alterations to the modified surface due to oxidation or other environmental processes, and can protect the modified properties of the portion of top surface 112 above region 111 during subsequent process steps that might otherwise damage the modified electrical properties of region 111 within channel region 110. After depositing dielectric material 142, masking material 242 is patterned as shown to expose dielectric material 142 over orifice 135. In one or more embodiments, depositing or redepositing a passivation material (e.g., passivation material 115) on the exposed portion of the top surface of the channel region (e.g., the top surface 112 of the channel region 110) can also improve (or further improve) the conductivity of the channel region below the interface between the channel region and the (re)deposited passivation material.

[0065] In step 250, the dielectric material 142 above the orifice 135 is selectively removed, thereby exposing the passivation material 115. The thickness and composition of the dielectric material 142 can be selected so that a selective etching process can be used to remove the dielectric material 142, which preferentially etches the dielectric material 142 rather than the passivation material 115, which may act as an etching terminator. This allows for the use of processes such as sputtering etching or reactive ion etching to etch relatively thick dielectric material 142 (e.g., in one or more embodiments, the dielectric material 142 or similar material has a thickness between 50 and 2000 angstroms, inclusive), processes that could damage the top surface 112 if it is not protected by the passivation material 115. Meanwhile, the relatively thin passivation material 115 can be rapidly removed by a suitable wet chemical etching process that will not damage the top surface 112 once it is exposed.

[0066] In step 260, the exposed passivation material 115 is removed using a suitable etching process. As a non-limiting example, buffered oxide etching (BOE) can be used to remove aluminum oxide. The gate 130 can then be formed immediately after removing the passivation material 115 in the aperture 135 to minimize the exposure of the top surface 112 beneath the gate 130 to environmental factors (e.g., oxygen) before the gate 130 is formed. The gate 130 can be formed using any suitable process, including photolithographic patterning, followed by deposition of any suitable metal (e.g., gold, nickel, titanium nitride, tungsten titanate, and any suitable combination or alloy thereof).

[0067] As shown, the positioning and dimensionalization of the patterned dielectric material 142 can define the shape of the gate 130, including the relative widths of the first end 132 and the second end 134 of the gate 130. As an example, in one or more embodiments, the gate, such as the gate 130, does not necessarily have the depicted “T-shaped” or “mushroom-shaped” profile. As will be understood from the further description below, the dielectric material 142 can also be used to define, for example, a combination of... Figure 2C Positioning of the field plate 150 as described in steps 270, 280 and 290.

[0068] In step 270, an interlayer dielectric material 145 is deposited over the substrate 102, including the gate 130. The interlayer dielectric material 145 can be any suitable dielectric, including silicon oxide, silicon nitrite, etc., as non-limiting examples. In some applications, a thickness between 500 and 5000 angstroms will be desirable, but any suitable thickness can be used.

[0069] In step 280, the interlayer dielectric material 145 is etched to define an aperture 155 for the field plate 150. Optionally, as shown, additional passivation material 147 may be deposited over the interlayer dielectric material 145, and then the field plate 150 is formed within the aperture 155 as shown in step 290. The field plate 150 may be formed using any suitable process, including, as a non-limiting example, photolithographic patterning followed by metal deposition using sputtering, thermal evaporation, etc. If additional passivation material 115 is formed in step 240, it may be used as an etch terminator for selectively etching the interlayer dielectric material 145 and the dielectric material 142. If necessary, any additional passivation material 115 remaining in the aperture after etching the interlayer dielectric material 145 may be removed by wet etching, followed by deposition of additional passivation material 147 to provide a pristine surface before forming the field plate 150. In one or more embodiments, an aperture, such as orifice 155, extends through both the interlayer dielectric material 145 and all or part of the dielectric material 142. For example, in transistor 100, the dielectric material 142 is completely removed from the bottom of orifice 155. In one or more such embodiments, additional dielectric material may be deposited in the orifice to achieve a desired distance between the first end 152 of field plate 150 and the top surface 112 in orifice 155.

[0070] In one or more embodiments, the passivation material, such as passivation material 115, is aluminum oxide (e.g., Al2O3 or Al2O4). x (where x is a fraction less than or greater than three). In one or more embodiments, the dielectric material, such as dielectric material 140, is a silicon nitride layer (e.g., SiN or SiN). x(where x is a fraction less than or greater than 1). In one or more embodiments, the dielectric material, such as dielectric material 142, is a silicon nitride layer (e.g., SiN or SiN). x (where x is a fraction less than or greater than 1). In one or more embodiments, the dielectric material, such as interlayer dielectric material 145, is a silicon nitride layer (e.g., SiN or SiN). x (where x is a fraction less than or greater than 1). If the passivation material 115 is aluminum oxide, it can be quickly removed using potassium hydroxide solution, buffered oxide etchant (BOE) solution, or tetramethylammonium hydroxide (TMAH) solution without removing other dielectric materials such as silicon nitride.

[0071] It should be understood that etching can be said to “not remove” a particular material when the etching rate for that material is zero or negligibly slow relative to another material that is considered to be preferentially etched; or etching can be said to be selective when etching preferentially removes one material at a faster rate than the other (e.g., if the etching rate of one material is at least twice as fast as the rate of the other). BOE solutions or dilute hydrofluoric acid are non-limiting examples of suitable wet etching of alumina (or silicon oxide) with respect to silicon nitride. It should be understood that other combinations of materials with suitable etching can also be used. For example, silicon nitride can be used as a passivation (or etch-stopping) material and silicon oxide for other thicker dielectric layers, and vice versa. As another example, silicon oxide can be used as a passivation (and / or etch-stopping) material and alumina can be used for thicker dielectric layers.

[0072] Figure 3 This is a schematic cross-sectional view of another example transistor according to one or more embodiments. Transistor 300 differs from transistor 100 in the construction of the aperture 155 for the field plate 150. Specifically, in transistor 100, aperture 155 passes through passivation material 115 and dielectric material 142, while in transistor 300, aperture 155 also passes through a portion of dielectric material 140 that is not present in transistor 100. (See below for further details.) Figure 4A and Figure 4B Further described, transistor 300 can be manufactured in a single process, wherein the relative positioning and size of aperture 135 and the position of region 111 are defined in a photolithography step (i.e., the aperture 135 where gate 130 is disposed is self-aligned with the position of region 111). Additionally, in process 400, gate aperture 135 can also be self-aligned with field plate aperture 155.

[0073] Figure 4A and Figure 4B Steps in an example process 400 for manufacturing a transistor (e.g., transistor 100) according to one or more embodiments are shown. Process 400 includes... Figure 4A Steps 420, 430, and 440 of the alternative processes 220, 230, and 240 shown in process 200. Process 400 also includes... Figure 4B Steps 450, 460, and 470 are shown. As described above and further below, although the gate 130 and field plate 150 can be formed in separate steps, process 400 provides certain advantages by allowing the relative positioning of aperture 135 and aperture 155 to be determined simultaneously in a single patterning step (e.g., by a single photolithography exposure).

[0074] In step 420, passivation material 115 is deposited or otherwise formed over the top surface 112 and the exposed portion of dielectric material 140, which has previously been patterned similarly to the dielectric material 140 shown in step 210 of process 200. However, in step 420, the dielectric material 140 has been patterned to define the positions of both apertures 135 and 155, thereby creating three segments on the dielectric material 140 on the top surface 112 of the substrate 102 instead of Figure 2A and Figure 2B The two sections are shown. As shown, photoresist or other masking material 422 is deposited and patterned to define the area in which the passivation material 115 will be removed, as described below in conjunction with step 430. In one or more embodiments, the dashed portions of the masking material 422 are also removed to allow removal of the passivation material 115 near the current terminal 120 (e.g., as described in conjunction with step 220 of process 200 above).

[0075] In step 430, the passivation material 115 is patterned to selectively remove the passivation material 115 over region 111. A surface modification process 232 is performed on the newly exposed portion of the top surface 112 to improve the conductivity of the channel region 110 during operation of transistor 100. Because additional dielectric material 140 is present at step 430 compared to step 230 of process 200, the extent of region 111 affected by surface modification process 232 in transistor 300 is smaller than the extent of region 111 in transistor 100. In one or more embodiments, surface modification processes such as surface modification process 232 are not performed, and steps such as step 430 may be omitted. In one or more embodiments, after completing surface modification process 232, additional passivation material 115 is deposited over the exposed portion of dielectric material 140 and region 111.

[0076] In step 440, as shown, a spacer layer (dielectric material 142) is deposited or otherwise formed over the top surface 112. If additional passivation material 115 is deposited prior to the formation of the spacer layer, the additional passivation material 115 can be used to prevent alterations to the modified surface due to oxidation or other environmental processes, and can protect the modified properties of the portion of the top surface 112 above the region 111 during subsequent process steps that might otherwise damage the modified electrical properties of the region 111 within the channel region 110. In one or more embodiments where the dielectric material is deposited directly on the top surface 112 above the region 111, the dielectric material can also provide similar protection to the electrical properties of the region 111. In one or more embodiments where the passivation material 115 acts as an etch stop, the passivation material 115 can be removed via suitable wet etching and then redeposited to mitigate any etch damage to the original layer of passivation material 115.

[0077] In step 450, the passivation material 115 and the dielectric material 140 are patterned, and then the field plate 150 is formed using a method substantially similar to that described in steps 250 and 260 of the bonding process 200.

[0078] In step 460, similar to step 270 of process 200, an interlayer dielectric material 145 is deposited over the substrate 102 including the gate 130, and then the interlayer dielectric material 145, dielectric material 142, and dielectric material 140 are etched, as shown. In one or more embodiments, the passivation material at the bottom of the orifice 155 is then removed by selective wet etching to expose the top surface 112 of the substrate 102. Additional passivation material 147 is deposited over the top surface 112 and the interlayer dielectric material 145, and then the field plate 150 is formed in step 470. In one or more embodiments, the additional passivation material 147 is deposited over the passivation material 115 at an appropriate location on the top surface 112 remaining within the orifice 155.

[0079] Figure 5 This is a schematic cross-sectional view of a transistor 500 having a field plate according to one or more embodiments, the field plate being able to be produced in relation to the aperture 155 by modifying processes such as process 400. Figure 5 The dielectric layers in regions 590 and 595 shown are fabricated with one or more "stepped" openings. For example, step 460 of process 400 may be modified to remove a larger portion of the dielectric material 142 surrounding the opening 555 than the dielectric material 140 itself, to create a step or staircase in region 590, region 595, or both (see example...). Figure 6 (Stepped arrangement of dielectric materials 140 and 142 in the middle). When manufacturing Figure 5When the structure and related structures are configured, the passivation material 115 can be used as an etch terminator for an etch process that selectively removes the dielectric material 142. The overall size of the aperture 555 can be selected to achieve any desired result. For example, it should be understood that the size of the aperture 555 and the configuration of the field plate 550 can be adjusted to achieve a desired electric field distribution in the channel region 110 during operation of the transistor 500.

[0080] Figure 6 This is a schematic cross-sectional view of a transistor 600 having a field plate 650 according to one or more embodiments. The field plate 650 can be manufactured by modifying processes such as process 200 or process 400 to create an aperture associated with an orifice 155, wherein the field plate 650 is separated from the channel region 110 by both a dielectric material 140 and a passivation material 115. The orifice 655, unlike the orifice 155, is formed in the dielectric material 142 without penetrating the dielectric material 140. In some designs, such an arrangement may be desirable, enabling C... DS With C GD The expected compromise between the two, and the electric field control in the channel region 110 caused by the large thickness of the dielectric material between the field plate 650 and the channel region 110.

[0081] Figure 7A and Figure 7B This is a flowchart illustrating the steps of process 700 suitable for manufacturing transistor 600. It should be understood that, for clarity, steps substantially similar to those described in conjunction with process 200 or process 400 have been omitted. In step 720 (compared to steps 210-220 of process 200 or step 420 of process 400), dielectric material 140 and passivation material 115 are patterned as shown, and then masking material 722 is structurally patterned. If necessary, the masking material 722 to the left of the dashed line can be removed to allow surface treatment of a portion of the top surface 112 near the current terminal 120 in addition to region 111. In process 700, the relative width of the dielectric material 140 between the aperture 135 and the current terminal 125 is larger than in process 200.

[0082] In step 730 (e.g., step 230 of process 200 or step 430 of process 400), as shown, the passivation material 115 above region 111 is selectively removed. If necessary, the passivation material 115 above current terminal 120 may also be removed (if the masking material 722 is patterned in step 720 to expose the area indicated by the dashed boundary). A surface modification process 232 is performed on the newly exposed portion of the top surface 112 to improve the conductivity of the channel region 110 in region 111 during operation of transistor 600. Dielectric material 140 may act as a hard mask during surface modification 232, protecting the channel region 110 outside of 111 from modification. If necessary, the masking material 722 may remain in place during step 730 and subsequently removed.

[0083] In step 740, the passivation material 115 may be removed and the passivation material 115 may be redeposited over region 111, and a dielectric material 142 may be deposited over the passivation material 115, thereby forming the gate 130, as described in steps 250 and 260 of process 200.

[0084] In step 760, an aperture 655 is formed in the interlayer dielectric material 145, dielectric material 142, and dielectric material 115, and in step 770, a field plate 650 is formed within the aperture 655. In one or more embodiments, as shown, the aperture 655 terminates at the passivation material 115. In one or more other embodiments, the passivation material 115 is removed at the bottom of the aperture 655, and the aperture 655 terminates at the dielectric material 140. In one or more other embodiments, the passivation material 115 is removed at the bottom of the aperture 655. Another dielectric material 147 is deposited, and the aperture 655 terminates at the dielectric material 147.

[0085] Figure 8A Another example transistor according to one or more embodiments is shown. In example transistor 800A, passivation material 115 is present beneath dielectric material 140 and dielectric material 142. Transistor 800 can be manufactured using techniques related to those described above in processes 200 and 400, such as in combination with... Figures 9A to 9D Further detailed description. It is worth noting that, if combined with... Figures 9A to 9DFurthermore, the field plate 850 can be placed directly on the passivation material 115 without exposing the top surface 112 above the channel region 110 beneath the field plate 850 to the surrounding environment. In some applications, minimizing the exposure of the top surface 112 of the substrate 102 beneath the field plate 150 may be desirable, for example, to reduce damage to the GaN surface caused by dry etching. The dielectric material 115, which acts as an etch stop, can optionally be removed by wet etching, and another dielectric material 147 can be deposited to separate the field plate 850 from the top surface 112, thereby reducing potential damage to the original dielectric material 115 caused by dry etching.

[0086] Figure 8B Another example transistor according to one or more embodiments is shown. Similar to example transistor 800A, in transistor 800B, passivation material 115 is present beneath dielectric material 140 and dielectric material 142. Notably, in transistor 800B, as shown, the aperture 855 is “stepped.” As shown, the aperture 855 may also be lined with additional passivation material 147, which may be the same or different material from the passivation material 115. It should be understood that the relative dimensions of each step in the aperture 855 can be any suitable size. For example, the relative width of the step on either side of the aperture 855 may be wider than the step on the opposite side to achieve a desired electric field distribution in the channel region 110 during operation of transistor 800B.

[0087] Figure 8C The gate 830B of transistor 800B is shown in more detail. In one or more embodiments, as shown, apertures such as aperture 835 include spacers such as spacers 831, 832, etc. The spacers are formed from residual portions of dielectric material 142. The presence or absence of such spacers, and if present, the relative dimensions of such spacers, can be controlled by varying process parameters during the fabrication of transistors such as transistor 800A or transistor 800B. The spacers can be used to reduce the effective gate length (“Lg”) determined by the length of the gate 830B directly contacting the channel region 110, to achieve higher switching frequencies during operation of transistor 800B and other transistors according to embodiments herein. The process including the spacers can be used to adjust the geometry of the gate (e.g., gate 830B) with a degree of dimensional accuracy greater than that of the photolithographic patterning process used. It should be understood that spacers such as spacers 831, 832, etc., can also be used, for example, in conjunction with the following. Figure 9A , Figure 9B and Figure 9C The further described process 900 and other processes disclosed herein are incorporated into the other transistors disclosed herein.

[0088] Figure 9A , Figure 9B , Figure 9C and Figure 9D The illustration shows steps in an example process for manufacturing a transistor (e.g., transistor 800A or 800B) according to one or more embodiments. Process 900 includes... Figure 9A and Figure 9B Steps 910, 920, 930, 940, 950, and 960 are shown and are described below with reference to the manufacture of transistor 800A. In one or more embodiments, process 900 further includes... Figure 9C Steps 970B and 980B are shown. In one or more embodiments, process 900 includes... Figure 9C Steps 970C and 980C are shown. Before process 900 begins, substrate 102 may have a first layer (layer 115a) of passivation material 115 and a dielectric material 140 covering the top surface 112 of substrate 102.

[0089] Prior to step 910, the dielectric material 140 has been patterned as shown by selectively removing the third dielectric material 140 using an appropriate etching process that does not remove the passivation material 115 layer 115a, thereby defining the locations of orifices 835 and 855, which will ultimately define the locations of the gate 830 and the field plate 850. The sidewalls of the dielectric material 140 may be inclined as shown, with different slopes, or may be vertical, depending on the selection of processing parameters chosen for the etching process used. As shown, a masking material 912 (e.g., photoresist) is patterned over the passivation material 115 layer 115a and the dielectric material 140, thereby allowing the dielectric material 140 to be used as a hard mask along with the photoresist to protect other areas (e.g., orifices 835 and 855) from removal while the passivation material is selectively removed over region 111. If necessary, the passivation material 115 layer 115a can also be removed near the current terminal 120. In this case, the masking material 922 to the left of the dashed line is also removed.

[0090] In step 920, the masking material 912 may remain in place as shown, or it may be removed before performing the surface modification process 232. The surface modification process 232 is performed on the newly exposed portion of the top surface 112 to improve the conductivity of the channel region 110 during operation of the transistors 800A or 800B. If surface modification is not performed, steps 920 and 930 can be omitted. It is worth noting that the dielectric material 140 can act as a hard mask, defining both the edges of region 111 and protecting adjacent portions of the top surface 112 from the surface modification process 232. Therefore, the exact location of the edges of the masking material 912 is not critical. In some applications, this may be desirable because it allows for greater tolerances in the photolithography process used to pattern the masking material 912.

[0091] In step 930, the remaining exposed portion of layer 115a of passivation material 115 is removed from top surface 112, and an additional layer 115b of passivation material 115 is deposited or otherwise formed on top surface 112 and on dielectric material 140. The additional passivation material 115 (layer 115b) can be used to prevent the modified surface in region 111 from being altered due to oxidation or other environmental processes, and can protect the modified properties of the portion of top surface 112 above region 111 during subsequent process steps.

[0092] In step 940, dielectric material 142 is deposited or otherwise formed over dielectric material 140 and passivation material 115b.

[0093] In step 950, the dielectric material 142 is selectively removed via a suitable etching process, as shown, wherein the passivation material 115b acts as an etching terminator. If a suitable anisotropic etching process is used, the residual dielectric material 142 will remain along the sidewalls of the aperture 835, as indicated by the dashed lines within the aperture 835 (e.g., Figure 8C (The spacers 831 and 832 shown).

[0094] In step 960, the exposed portion of the passivation material 115 of the layer 115b in the aperture 835 is removed using a suitable etching process that does not damage the exposed top surface 112 in the aperture 835 (e.g., wet etching that selectively removes the passivation material of layer 115b without damaging the top surface 112 of the substrate 102), and then the gate 830 (or gate 830B) is formed within the aperture 835. The geometry of the gate 830 or 830B may vary and has been discussed above in conjunction with the gate 130.

[0095] Figure 9CSteps 970B and 980B, performed in one or more embodiments (e.g., after step 960 of process 900), are depicted. In step 970B, an interlayer dielectric material 145 is deposited over gate 830 (or gate 830B), and an orifice 855 is exposed by selectively removing the interlayer dielectric material 145 and dielectric material 142. A residual layer 115b of passivation material 115 remains on the top surface 112 within the orifice 855, and in step 980B, a field plate 850 is formed within the orifice 855.

[0096] Figure 9D Steps 970C and 980C, performed in one or more embodiments, are depicted. In step 970C, an interlayer dielectric material 145 is deposited over gate 830 (or gate 830B), and an orifice 855 is exposed by selectively removing the interlayer dielectric material 145 and dielectric material 142. After step 960 of the removal process 900, a residual portion of layer 115b of passivation material 115 remains on the top surface 112 within the orifice 855, followed by the deposition of additional passivation material 147. The additional passivation material 147 (which may be the same material as passivation material 115) is lined on the sidewalls of the orifice 855 and optionally covers the interlayer dielectric material 145. In step 980C, a field plate 850 is formed within the orifice 855.

[0097] It should be understood that, in one or more embodiments, Figure 9C or Figure 9D The arrangement of the field plate 850 shown can be modified by using the process steps and / or related process steps disclosed above. For example, if the dielectric material 140 is patterned in a different manner than at step 910 (e.g., compared to the arrangement of the dielectric material 140 at step 720 of process 700), an aperture 855 can be defined in the dielectric material 142 instead of the dielectric material 140, so that the lower end of the field plate 850 rests on the top of the dielectric material 140 (see, for example...). Figure 6 China and Figure 7A and Figure 7B (The arrangement of the field plate 650 at step 770 in the middle).

[0098] Alternatively, it should be understood that, in one or more embodiments, the relevant arrangement of the field plate 850 can also be achieved by changing the width of the dielectric material 140 and adjusting the positioning of the masking material 942 in step 940 to leave an area in which the dielectric material 142 remains above a sufficiently wide portion of the dielectric material 140. In such embodiments, orifices for the field plate may be formed in the portion of the dielectric material 142 disposed above an uninterrupted section of the dielectric material 140.

[0099] Figure 10A and Figure 10BAn alternative process 1000 related to process 900 is described. One difference between process 1000 and process 900 can be seen at step 1010, where a three-layer dielectric stack is formed on substrate 102. The stack includes two layers of passivation material 115: a first layer 115a is directly on the top surface 112 of substrate 102 and is separated from the second layer 115b by an intercalation layer of dielectric material 140.

[0100] Step 1020 can be performed similarly to step 910 of process 900. In step 1020, layer 115b of passivation material 115 can be patterned as an etch mask for material 140, wherein selective etching preferentially removes passivation material 115, and then etches dielectric material 140 using etch that preferentially removes dielectric material 140, wherein the first layer 115a of passivation material 115 serves as an etch stop. The resulting structure defines the locations of apertures 1035 and 1055 that can be used to form a gate (e.g., gate 130 or 830) and a field plate (e.g., field plate 150, field plate 550, field plate 650, or field plate 850).

[0101] In step 1030, a patterned combination of photoresist and material 140 is used as a hard mask to pattern the passivation material layer 115a to selectively remove the passivation material 115 above region 111. A surface modification process 232 is performed on the newly exposed portion of the top surface 112 to improve the conductivity of the channel region 110 during operation of transistor 800A or 800B. Steps 1030 and 1040 can be omitted if surface modification is not performed.

[0102] In step 1040, a dielectric material 142 is deposited or otherwise formed over a dielectric material 140 and two layers of passivation material 115 (layers 115a, 115b) as shown, and a masking material 1042 (e.g., photoresist) is formed as shown.

[0103] In step 1050, as shown, the dielectric material 142 is selectively removed via a suitable etching process, wherein the passivation material 115 (layer 115b) serves as an etching terminator. If a suitable anisotropic etching process is used, the residual dielectric material 142 will be retained along the sidewalls of the aperture 1035, as indicated by the dashed lines within the aperture 1035 (spacers 1031, 1032; for example, Figure 8C The spacers 831 and 832 shown are used. The exposed passivation material 115 is removed using a suitable etching process that does not damage the exposed top surface 112 in the aperture 835 (e.g., wet etching that selectively removes the passivation material 115 without damaging the top surface 112 of the substrate 102).

[0104] In step 1060, a gate 830 (or gate 830B) is formed within the aperture 835. The geometry of gate 830 or 830B may vary and has been discussed above in conjunction with gate 130. The field plate can be fabricated by performing steps similar to those described above in conjunction with other processes, wherein an interlayer dielectric material, such as interlayer dielectric material 145, is formed over the gate and the region surrounding aperture 1055, and then patterned to allow the formation of the field plate within aperture 1055.

[0105] Figure 11 This is a cross-sectional view of another example transistor according to one or more embodiments. Transistor 1100 includes a structure having adjustable geometry for a gate and field plate, said structure being fabricated in a process of forming and patterning a critical dielectric structure prior to the formation of the gate and field plate, thereby avoiding potential damage or performance degradation that could occur during the high-temperature dielectric formation process if the gate and field plate were formed in an earlier process step. Specifically, transistor 1100 includes a first layer 140a and a second layer 140b of dielectric material 140 separated by a thin layer 115a of passivation material 115. Dielectric material 142 covers the second layer 140b of dielectric material 140, wherein the second layer 115b of passivation material 115 is interposed between the second layer 140b of dielectric material 140 and dielectric material 142.

[0106] A gate 1130 is formed within an aperture 1135 in a first layer 140a of dielectric material 140. As shown, gate spacers 1131 and 1132 (e.g., spacers 831, 832) may be included within the gate aperture 1135, or gate spacers 1131 and 1132 may be omitted. A field plate 1150 is formed within an aperture 1155 in a second layer 140b of dielectric material 140, thereby allowing the field plate 1150 to be disposed at a controlled distance above the top surface 112 of the substrate 102 in the channel region 110. The field plate 1150 may have a stepped profile as shown, with portions resting on the second layer 140b of dielectric material 140 on either side of the aperture 1155. Alternatively, additional passivation material 147 may be lining the aperture 1155 and covering the interlayer dielectric material 145, as indicated by the dashed area directly surrounding the field plate 1150.

[0107] It should be understood that in the transistor 1100 and other transistors described herein, the apertures 1135 and 1155 and the surrounding dielectric structure can have any suitable sidewall profile. For example, any sidewalls depicted can be vertical or inclined at any suitable slope, depending on the processing parameters selected during the manufacture of the transistor 1100. Similarly, the gate 1130 and field plate 1150 can have any suitable shape.

[0108] In one or more embodiments, the dashed portions of the first layer 115a and the second layer 115b of the passivation material 115 are absent. In such embodiments, the portion of the top surface 112 of the field plate 1150 closest to the substrate 102 in the aperture 1155 is in direct contact with the first layer 140a of the dielectric material 140. In some applications, this configuration may be desirable to reduce charge trapping within or on the surface of the passivation material 115 near the field plate 1150.

[0109] Figure 12A and Figure 12B This is a flowchart illustrating steps of an example process suitable for manufacturing transistors such as transistor 1100 and related transistors according to one or more embodiments. Process 1200 includes the steps described below. Figure 11 The manufacturing steps 1210, 1220, 1230, 1240, 1250, and 1260 of transistor 1100 are described. As with the other processes described above, process 1200 is a process in which the gate (e.g., gate 1130) and the field plate (e.g., field plate 1350) are self-aligned with each other during a patterning step prior to the formation of both the gate and the field plate.

[0110] In step 1210, substrate 102 has a dielectric stack, shown as disposed on a top surface 112 above channel region 110. A first layer 140a of dielectric material 140 is disposed directly on top surface 112, followed by a passivation material 115 (a first layer 155a of passivation material 115) and a second layer 140b of dielectric material 140 directly above the passivation material layer 115a. It should be understood that in one or more embodiments, the first layer 140a and the second layer 140b of dielectric material 140 are the same material but may have different thicknesses. In one or more other embodiments, a material different from dielectric material 140 may replace the first layer 140a or the second layer 140b of dielectric material 140. As shown, a masking material 1212 (e.g., photoresist) is patterned over the second layer 140b of dielectric material 140.

[0111] In step 1220, the second layer 140b of the dielectric material 140 is patterned as shown to define the location of the aperture 1135 in the aperture 1155, and the passivation material layer 115a is removed from the exposed portion of the first layer 140a of the dielectric material 140 using any suitable process, including those described above in conjunction with related processes. The passivation material layer 115a can be used as an etch terminator (i.e., a hard mask) for an etching process that removes a portion of the second layer 140b of the dielectric material 140. Subsequently, the passivation material layer 115a can be removed by a selective etching process, which may include wet chemical etching or dry plasma etching using a masking material 1212 as a mask for the etching process. Afterward, the masking material 1212 is removed, and an additional masking material 1222 (e.g., a photoresist that may be the same as or different from the masking material 1212) is patterned over the structure as shown.

[0112] In step 1230, the dielectric stack is further patterned to make room for the gate 1130, which will be formed in the aperture 1135 during subsequent steps. Additional portions of the second layer 140b of the dielectric material 140 are removed, along with a portion of the first layer 140a of the dielectric material 140, to expose the top surface 112 at the bottom of the aperture 1135. Alternatively, a portion of the second layer 140b of the dielectric material 140 may be removed between the aperture 1155 and the current terminal 125 (e.g., to make room for an electrode (not shown) that contacts the current terminal 125). Afterward, a portion of the passivation material 115 layer 115a can be removed using a masking material 1222 as an etching mask, employing any suitable dry or wet etching process.

[0113] In step 1240, as patterned in step 1230, additional passivation material 115 (layer 115b of passivation material 115) is deposited over the dielectric stack. Dielectric material 142 is then deposited on the passivation material 115b. It should be understood that in one or more embodiments, a material different from the passivation material 115 may be used as the passivation material 115b.

[0114] In step 1250, the dielectric stack is further patterned to expose the top surface 112 of the substrate 102 in the aperture 1135, and then the gate 1130 is formed in the aperture 1135. In one or more embodiments, the etching process for selectively removing the dielectric material 142 is adjusted to leave residual dielectric material 142 in the aperture 1135, thereby forming a gate spacer (e.g., Figure 11(Spacers 1131, 1132). Meanwhile, in one or more other embodiments, the dielectric material 142 and the passivation material 115 are completely removed from the top surface 112 of the substrate 102 in the aperture 1135, so that there are no spacers in the aperture 1135 surrounding the gate 1130. The passivation material 115 can be removed using wet chemical etching to avoid plasma damage to the top surface 112 that would otherwise occur with a plasma etching process.

[0115] In step 1260, as shown, an interlayer dielectric material 145 is deposited on the gate 1130 and the remaining patterned dielectric material, and then the interlayer dielectric material 145 and dielectric material 142 are selectively removed as shown. As previously described, the passivation material 115 in the aperture 1155 can act as an etch stop. The layer 115b of the passivation material 115 within the aperture 1155 can then be removed by a wet etching process. In one or more embodiments, additional dielectric material (which may be the same as or different from the passivation material 115b) is redeposited in the aperture 1155. This allows the distance between the bottom and top surfaces 112 of the field plate 1150 to be adjusted as needed. The field plate 1150 can then be formed in the aperture 1155 as previously described in conjunction with the relevant processes.

[0116] Figure 13 This is a cross-sectional view of another example transistor according to one or more embodiments. Transistor 1300 is associated with transistor 1100 and includes a similar structure having adjustable geometry for the gate and field plate, said structure being fabricated in a sequentially formed and patterned process in which critical dielectric structures are provided to allow protection of the top surface 112 above the channel region 110 from potential damage from high-temperature process steps. Transistor 1300 differs from transistor 1100 in the dielectric stacking around the field plate. For example, transistor 1300 includes a first layer 140a and a second layer 140b of dielectric material 140, having a three-layer structure between the two layers 140a, 140b. A first layer 115a of passivation material 115 is disposed directly on the first layer 140a of dielectric material 140 and is separated from the second layer 115b of passivation material 115 by dielectric material 142. The second layer 140b of dielectric material 140 is disposed directly on the second layer 115b of passivation material 115. In aperture 1355, field plate 1350 is separated from top surface 112 of substrate 102 by dielectric material 142. The thickness of dielectric material 142 can be selected to achieve a specific electric field distribution in channel region 110 during operation of transistor 1300.

[0117] In transistor 1300 and related transistors, the first layer 140a and the second layer 140b may have different thicknesses. Similarly, in transistor 1300 and related transistors, layers 115a and 115b may have different thicknesses. It should also be understood that in one or more embodiments, layers 140a and 140b are made of different materials. Similarly, in one or more embodiments, layers 115a and 115b are made of different materials.

[0118] Figure 14A and Figure 14B This is a flowchart illustrating steps of an example process suitable for manufacturing transistors such as transistor 1300 and related transistors according to one or more embodiments. Process 1400 includes the steps described below. Figure 13 The manufacturing process of transistor 1300 is described in steps 1410, 1420, 1430, 1440, 1450, and 1460. As with the other processes described above, process 1400 is a process in which the gate 1330 and the field plate 1350 are self-aligned with each other during the patterning steps prior to the formation of both the gate 1330 and the field plate 1350.

[0119] In step 1410, the substrate 102 has a dielectric stack, which is shown to be disposed on a top surface 112 above the channel region 110. A first layer 140a of dielectric material 140 is disposed directly on the top surface 112, followed by a first layer 115a of passivation material 115 disposed directly on the first layer 140a of dielectric material 140.

[0120] In step 1420, the first layer 140a of the dielectric material 140 is patterned as shown to define the locations of apertures 1335 and 1355. The layer 115a of the passivation material 115 is removed from the exposed portion of the top surface 112 of the substrate 102 using any suitable process (including those described above in conjunction with related processes). If the passivation material 115 is over-etched, the underlying dielectric material 140 may have a sloping profile in apertures 1335 and 1355 after the first layer 140a of the dielectric material 140 has been properly etched (e.g., using anisotropic etching). It should be understood that the relative dimensions of the different layers are enlarged for clarity, and the etched sidewall profiles are not depicted in subsequent steps.

[0121] In step 1430, an additional dielectric layer is deposited over the area previously patterned in step 1420. Dielectric material 142 is deposited, followed by a second layer 115b of passivation material 115, and then a second layer 140b of dielectric material 140. Masking material 1432 (e.g., photoresist) is patterned over the structure as shown.

[0122] In step 1440, the dielectric stack is removed in the region surrounding the aperture 1335. Etching steps of any suitable order can be used to remove the second layer 140b of the dielectric material 140, the second layer 115b of the passivation material 115, and the dielectric material 142. For example, these layers can be removed sequentially. As a non-limiting example, the second layer 140b of the dielectric material 140 can be removed using selective etching that terminates at the second layer 115b of the passivation material 115. The dielectric material 142 can then be removed by selective etching that terminates at the first layer 115a of the passivation material 115. In one or more embodiments, similar to the related processing steps described above, a pattern similar to the patterned dielectric material 142 can be formed in the aperture 1335 by controlling the etching for patterning the dielectric material 142 (see, for example, the description of steps 1240 and 1250 of process 1200 above). Figure 11 The spacers 1131 and 1132 shown are spacers ( Figure 13 or Figure 14A and Figure 14B (Not shown in the text).

[0123] In step 1450, a first layer 115a of passivation material 115 is removed from the region surrounding orifice 1335, and then a gate 1330 is formed in orifice 1335. In step 1460, an interlayer dielectric material 145 is deposited over gate 1330, and then the interlayer dielectric material 145 and a second layer 140b of dielectric material are selectively removed as shown, wherein the second layer 115b of passivation material 115 acts as an etch stop. The remaining passivation material 115 is removed from orifice 1355 (e.g., using a suitable wet etching as described above), leaving dielectric material 142 on the top surface 112 in orifice 1355. Field plate 1350 may be formed after step 1460 is completed.

[0124] Example

[0125] The features of the embodiments can be understood with the help of one or more of the following examples:

[0126] Example 1: An apparatus or method comprising a semiconductor substrate having a channel region operable as a transistor channel. The channel region extends between a first current-end region at a first end of the channel region and a second current-end region at a second end of the channel region. A first dielectric stack is disposed directly on the top surface of the channel region. The first dielectric stack includes a first dielectric layer and a first etch-stop layer disposed directly on the first dielectric layer. The first dielectric stack is patterned to simultaneously form: a first opening in the first dielectric stack located between the first end of the channel region and the second end of the channel region; and a second opening extending through at least a portion of the first dielectric stack between the first opening and the second end of the channel region. A dielectric spacer layer is formed over the patterned first dielectric stack and within first and second apertures.

[0127] The spacer layer is patterned to selectively remove the spacer layer above the first opening, and a conductive gate electrode is formed in a gate aperture having a location defined by the first opening, directly contacting the top surface of the channel region. An interlayer dielectric is formed above the gate electrode, and the interlayer dielectric is selectively removed to form a field plate aperture having a location defined by the second opening, and a conductive field plate electrode is formed in the field plate aperture.

[0128] Example 2: The apparatus or method according to Example 1 further includes a second dielectric stack formed directly on the spacer layer, the second dielectric stack including a second etch-stop layer and a second dielectric layer directly on the second etch-stop layer. The second dielectric stack is patterned to form a patterned portion of the second dielectric stack exposing the spacer layer in the first aperture by removing the second dielectric layer above the first opening using a first etch that does not remove the etch-stop layer, and by removing the second etch-stop layer using a second etch that does not remove the spacer layer. The spacer layer is patterned using a third etch to expose the top surface of the channel region in the first opening.

[0129] Example 3: The apparatus or method according to Example 1 or Example 2, wherein a first dielectric layer and a second dielectric layer are formed from silicon nitride material using low-pressure chemical vapor deposition (LPCVD), and wherein a first etch stop layer and a second etch stop layer are formed from aluminum oxide material.

[0130] Example 4: An apparatus or method according to any one of Examples 1 to 3, wherein the first etch stop layer, the second etch stop layer, or both the first etch stop layer and the second etch stop layer are formed using atomic layer deposition (ALD).

[0131] Example 5: An apparatus or method according to any one of Examples 1 to 4, wherein a patterned portion of a second dielectric stack above a second opening is protected from a first etching, a second etching, and a third etching. At least a portion of the patterned portion of the second dielectric stack above the second opening is selectively removed by using a fourth etching that does not remove the second etch stop layer to selectively remove the second dielectric layer. The second etch stop layer is selectively removed by a fifth etching that does not remove the spacer layer. A first portion of the field plate electrode is directly disposed on the spacer layer in the field plate aperture above the second opening.

[0132] Example 6: An apparatus or method according to any one of Examples 1 to 5, wherein the width of the field plate aperture at the second dielectric layer is wider than the width of the second opening in the first dielectric layer, and the center of the field plate aperture is offset from the center of the second opening.

[0133] Example 7: An apparatus or method according to any one of Examples 1 to 6, wherein the first dielectric stack further includes a third dielectric layer directly disposed on the first etch-stop layer; and wherein patterning the first dielectric stack includes: patterning the third dielectric layer to form the first opening in the third dielectric layer using a first etch that does not remove the first etch-stop layer; patterning the third dielectric layer to form the second opening in the third dielectric layer using the first etch; removing the first etch-stop layer from the first opening and the second opening using a second etch that does not remove the first dielectric layer; forming a masked portion of the third dielectric layer surrounding the second opening using a masking material; selectively removing the remaining third dielectric layer surrounding the masked portion of the third dielectric layer by using a third etch that does not remove the first etch-stop layer, forming an exposed portion of the first dielectric layer; forming the first opening in the first dielectric layer below the first opening in the third dielectric layer using a fourth etch that does not remove the top surface of the channel region; and removing the first etch-stop layer from the exposed portion of the first dielectric layer using a fifth etch that does not remove the first dielectric layer.

[0134] Example 8: The apparatus or method according to any one of Examples 1 to 7 further includes: forming a second etch-stop layer over the patterned first dielectric stack prior to forming the spacer layer; wherein patterning the spacer layer to selectively remove the spacer layer around the first opening includes etching the spacer layer using a sixth etch that does not remove the second etch-stop layer; and wherein the method further includes removing the second etch-stop layer from the first opening using a seventh etch that does not remove the top surface of the channel region prior to forming the gate electrode.

[0135] Example 9: The apparatus or method according to any one of Examples 1 to 8 further includes selectively removing the spacer layer within the field plate aperture using a seventh etch that does not remove the second etch termination layer.

[0136] Example 10: The apparatus or method according to any one of Examples 1 to 9 further includes removing the second etch termination layer from the field plate aperture using an eighth etch that does not remove the first dielectric layer or the third dielectric layer.

[0137] Example 11: An apparatus or method according to any one of Examples 1 to 10, wherein the width of the field plate aperture at the third dielectric layer is wider than the width of the second opening in the first dielectric layer, and the center of the field plate aperture is offset from the center of the second opening.

[0138] Example 12: An apparatus or method according to any one of Examples 1 to 11, wherein a first dielectric layer and a second dielectric layer are formed from silicon nitride material using low-pressure chemical vapor deposition (LPCVD), and wherein a first etch stop layer and a second etch stop layer are formed from aluminum oxide material.

[0139] Example 13: An apparatus or method according to any one of Examples 1 to 12, wherein the first etch stop layer, the second etch stop layer, or both the first etch stop layer and the second etch stop layer are formed using atomic layer deposition (ALD).

[0140] Example 14: The apparatus or method according to any one of Examples 1 to 13 further includes thermally annealing the substrate at a temperature greater than 300°C to reduce charge trapping in the remaining portion of the first etch-stop layer.

[0141] Example 15: An apparatus or method according to any one of Examples 1 to 14, wherein the spacer layer is patterned to selectively remove the spacer layer above the first opening such that a portion of the spacer layer remains intact along the sidewall of the first opening.

[0142] The foregoing specific embodiments and the figures mentioned therein are examples. These examples are illustrative in nature and are not intended to limit the embodiments of this disclosure or the use of such embodiments. Therefore, it should be understood that the application of the embodiments of this disclosure is not limited to the details of the construction and arrangement of the components set forth in the foregoing description or shown in the accompanying drawings.

[0143] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical connections between various components. It should be noted that many alternative or additional functional relationships or physical connections may exist in one or more embodiments of this disclosure.

[0144] As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary should not be construed as preferred or advantageous over other embodiments. Furthermore, no explicit or implicit theory presented in the foregoing technical field, background art, or specific embodiments is intended to bind you. It should be understood that other wording and terminology used herein for descriptive purposes should not be considered limiting.

[0145] Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. In this document, “A, B, and / or C” is defined as “A or B or C” or any combination of A, B, or C.

[0146] As used herein, unless explicitly stated otherwise, “connection” means that one element is directly engaged to (or directly connected to) another element in an electrical or non-electrical manner, and not necessarily mechanically. Similarly, unless otherwise explicitly stated, “coupling” means that one element is directly or indirectly engaged to (or directly or indirectly connected to) another element in an electrical or non-electrical manner, and not necessarily mechanically. Therefore, although the schematic illustrations of the figures may depict exemplary arrangements of elements, additional intermediate elements, means, features, or components may be present in one or more embodiments of the subjects depicted.

[0147] Unless explicitly indicated by the context, the terms "first," "second," and other such numerical terms referring to structures do not imply order or sequence. Therefore, the terms "first," "second," "third," "fourth," etc., as used in the description and claims (if present) are used to distinguish similar elements and are not necessarily used to describe a particular sequence or chronological order. It should be understood that the numerical terms used herein are interchangeable where appropriate, such that embodiments of the invention described herein can, for example, operate in an order other than that described herein or otherwise.

[0148] As used herein, the terms “approximately,” “about,” “basically,” and “substantially” mean sufficient to achieve the purpose of the statement in a practical manner, and that minor defects (if present) are not important to the purpose of the statement. In accordance with these principles, when references are made to measurable quantities, including but not limited to dimensions, these terms mean that the quantity is equal to the stated value, subject to acceptable tolerances of any method or apparatus chosen for manufacturing the described structure or measuring the described quantity or dimension.

[0149] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement the described embodiments or embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method includes: A semiconductor substrate is received having a channel region capable of operating as a transistor channel, wherein the channel region extends between a first current terminal region at a first end of the channel region and a second current terminal region at a second end of the channel region, wherein a first dielectric stack is directly disposed on the top surface of the channel region. Pattern the first dielectric stack to simultaneously form: A first opening in the first dielectric stack, the first opening being located between the first end of the channel region and the second end of the channel region; A second opening extends through at least a portion of the first dielectric stack between the first opening and the second end of the channel region; A dielectric spacer layer is formed above a patterned first dielectric stack and within the first and second orifices; The spacer layer is patterned to selectively remove the spacer layer above the first opening; A conductive gate electrode is formed in a gate aperture having a position defined by the first opening, which directly contacts the top surface of the channel region; An interlayer dielectric layer is formed above the gate electrode; Selectively remove the interlayer dielectric layer to form a field plate aperture having a location defined by the second opening; and A conductive field plate electrode is formed in the orifice of the field plate; The first dielectric stack includes: First dielectric layer; and The first etch stop layer is disposed directly on the first dielectric layer.

2. The method of claim 1, wherein, In addition, including: A second dielectric stack is formed directly on the spacer layer, the second dielectric stack including a second etch stop layer and a second dielectric layer directly on the second etch stop layer; The second dielectric layer above the first opening is removed by a first etching that does not remove the etch stop layer, and the second etch stop layer is removed by a second etching that does not remove the spacer layer. The second dielectric stack is patterned to form a patterned portion of the second dielectric stack that exposes the spacer layer in the first aperture. as well as The spacer layer is patterned using a third etch to expose the top surface of the channel region in the first opening.

3. The method according to claim 2, characterized in that, The first dielectric layer and the second dielectric layer are formed from silicon nitride material using low-pressure chemical vapor deposition (LPCVD); and The first etch stop layer and the second etch stop layer are formed of alumina material.

4. The method according to claim 3, characterized in that, The first etch stop layer, the second etch stop layer, or both the first etch stop layer and the second etch stop layer are formed using atomic layer deposition (ALD).

5. The method according to claim 2, characterized in that, In addition, including: Protect the patterned portion of the second dielectric stack above the second opening from the effects of the first etch, the second etch, and the third etch; as well as At least a portion of the patterned portion of the second dielectric stack above the second opening is selectively removed in the following manner: The second dielectric layer is selectively removed using a fourth etch that does not remove the second etch stop layer; as well as The second etch stop layer is selectively removed using a fifth etch that does not remove the spacer layer; The first part of the field plate electrode is directly disposed on the spacer layer in the field plate aperture above the second opening.

6. The method according to claim 5, characterized in that, The width of the field plate aperture at the second dielectric layer is wider than the width of the second opening in the first dielectric layer, and the center of the field plate aperture is offset from the center of the second opening.

7. The method according to claim 1, characterized in that, The first dielectric stack further includes a third dielectric layer directly disposed on the first etch stop layer; and Patterning the first dielectric stack includes: The third dielectric layer is patterned using a first etch that does not remove the first etch stop layer to form the first opening in the third dielectric layer; The third dielectric layer is patterned using the first etching to form the second opening in the third dielectric layer; The first etch termination layer is removed from the first opening and the second opening using a second etch that does not remove the first dielectric layer; A masking portion of the third dielectric layer surrounding the second opening is formed using a masking material; An exposed portion of the first dielectric layer is formed by selectively removing the remaining third dielectric layer surrounding the masked portion of the third dielectric layer using a third etch that does not remove the first etch stop layer. The first opening in the first dielectric layer is formed below the first opening in the third dielectric layer using a fourth etching that does not remove the top surface of the channel region; and The first etch stop layer is removed from the exposed portion of the first dielectric layer using a fifth etch that does not remove the first dielectric layer.

8. The method according to claim 7, characterized in that, In addition, including: Before forming the spacer layer, a second etch stop layer is formed over the patterned first dielectric stack; Patterning the spacer layer to selectively remove the spacer layer around the first opening includes etching the spacer layer using a sixth etch that does not remove the second etch stop layer; and The method further includes removing the second etch stop layer from the first opening using a seventh etch that does not remove the top surface of the channel region before forming the gate electrode.

9. The method according to claim 7, characterized in that, The first etch stop layer, the second etch stop layer, or both the first etch stop layer and the second etch stop layer are formed using atomic layer deposition (ALD).

10. The method according to claim 1, characterized in that, The spacer layer is patterned to selectively remove the spacer layer above the first opening, leaving a portion of the spacer layer intact along the sidewall of the first opening.

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