Semiconductor structure and method of fabricating the same
By forming an ultrathin second wetting layer in the back gate process and immediately forming a conductive layer, the problem of missing aluminum filling caused by poor continuity of the wetting layer in the high-k metal gate process is solved, and the filling effect of the conductive layer and device performance are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAHONG INTEGRATED CIRCUIT (CHENGDU) CO LTD
- Filing Date
- 2026-03-30
- Publication Date
- 2026-06-23
AI Technical Summary
In high-k metal gate processes with back gate technology, the poor continuity of the sidewall wetting layer of the gate trench leads to aluminum filling defects at the top of the metal gate, affecting device performance.
If the time interval between the formation of the first wetting layer and the formation of the conductive layer is greater than a preset value, an ultrathin second wetting layer is formed on the first wetting layer, and the conductive layer is formed immediately thereafter, so as to form a continuous intermetallic compound transition layer at the interface and improve the continuity of the wetting layer.
It improves the deposition effect of the conductive layer, prevents the gate trench top opening from being sealed prematurely, reduces the generation of voids in the lower part of the gate trench, and reduces the possibility of missing aluminum filling defects at the top of the metal gate.
Smart Images
Figure CN122269743A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] In high-k metal gate processes employing a back-gate technology, after removing the dummy polysilicon gate, a TiN layer is first deposited as a work function layer for the PMOS region. Then, a wetting layer, which is a titanium thin film deposited by the Extensa PVD system, is deposited on the work function layer. Finally, an aluminum layer is deposited on the wetting layer. However, due to the high mobility of Ti atoms, they tend to aggregate and form island-like structures, reducing the continuity of the wetting layer. Furthermore, due to equipment malfunctions and other reasons, the interval between depositing the wetting layer and the aluminum layer increases, further reducing the continuity of the wetting layer.
[0003] Due to the large aspect ratio of the gate trench, the surface mobility of Al atoms is insufficient at low temperatures (≤400℃), and its filling ability is greatly affected by the wetting layer. When the continuity of the wetting layer on the sidewall of the gate trench deteriorates, TiN under Ti is exposed at discontinuous Ti locations. These exposed areas easily adsorb oxygen in the process environment. When aluminum atoms reach these exposed areas, they not only fail to form a TiAl3 transition layer but may also form aluminum oxide, preventing aluminum atoms from flowing downwards. Instead, they can only grow laterally at the top of the gate trench (because the geometric shielding effect is weak at the top of the gate trench, and the PVD-deposited Ti layer usually has the best continuity and is the densest). This causes the opening at the top of the gate trench to be sealed prematurely, forming voids in the middle and lower part of the gate trench. In the subsequent chemical mechanical polishing process, half of the gate is polished away, exposing the previously formed voids. This manifests as an Al missing defect at the top of the metal gate, with consequences including:
[0004] 1) Uneven thickness of the work function layer leads to threshold voltage drift;
[0005] 2) An abnormally high gate resistance leads to a decrease in device performance;
[0006] 3) Increased interface defects lead to increased leakage current. Summary of the Invention
[0007] The purpose of this application is to provide a semiconductor structure and its fabrication method, which solves the problem of aluminum filling defects at the top of the metal gate caused by the poor continuity of the sidewall wetting layer of the gate trench during the aluminum filling of the metal gate in the high-k metal gate process using the back gate process in the prior art.
[0008] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor structure, which may include at least the following steps:
[0009] A substrate is provided on which gate trenches are formed;
[0010] A first wetting layer is formed on the bottom and sidewalls of the gate trench;
[0011] When the time interval between the formation of the first wetting layer and the formation of the conductive layer is greater than a preset value, a second wetting layer is formed on the first wetting layer. The thickness of the second wetting layer is less than the thickness of the first wetting layer. The conductive layer is formed on the second wetting layer so that a portion of the conductive layer reacts with a portion of the second wetting layer, and a continuous intermetallic compound transition layer is formed at the junction of the conductive layer and the second wetting layer.
[0012] Furthermore, the aspect ratio of the gate trench is greater than or equal to 3:1.
[0013] Furthermore, the first wetting layer and the second wetting layer are made of the same material.
[0014] Furthermore, the second wetting layer comprises metallic titanium.
[0015] Furthermore, the conductive layer comprises aluminum or an aluminum alloy.
[0016] Furthermore, prior to the formation of the first wetting layer, the method further includes:
[0017] A power function layer is formed on the bottom and sidewalls of the gate trench.
[0018] Furthermore, the thickness of the second wetting layer is 1 to 20 angstroms.
[0019] Furthermore, the deposition time of the second wetting layer is 0.5 seconds to 1.5 seconds.
[0020] Furthermore, the preset value is 6 minutes.
[0021] To address the aforementioned technical problems, this application also provides a semiconductor structure, which is fabricated using the method described above.
[0022] Compared with the prior art, the technical solution of this application has at least one of the following beneficial effects:
[0023] In a semiconductor structure and its fabrication method provided in this application, when the interval between the formation of the first wetting layer and the formation of the conductive layer is greater than a preset value of 6 minutes, an ultra-thin second wetting layer is formed on the first wetting layer to improve the continuity of the wetting layer. Then, a conductive layer is immediately formed on the second wetting layer, so that a continuous intermetallic compound transition layer can be formed at the junction of the second wetting layer and the conductive layer, which improves the deposition effect of the conductive layer and ensures that the opening at the top of the gate trench is not sealed prematurely when the conductive layer is filled, thereby reducing the generation of voids in the lower part of the gate trench and reducing the possibility of aluminum filling defects at the top of the metal gate after subsequent chemical mechanical polishing. Attached Figure Description
[0024] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0025] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;
[0026] Figures 2-5 This is a schematic diagram of the fabrication process of a semiconductor structure fabrication method provided in one embodiment of this application.
[0027] in, Figures 2-5 The specific reference numerals in the attached figures are as follows:
[0028] 1-Substrate; 2-Gate trench; 3-Work function layer; 4-First wetting layer; 5-Second wetting layer; 6-Intermetallic compound transition layer; 7-Conductive layer.
[0029] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0030] To make the technical solutions and advantages of the embodiments of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the implementation methods described herein. Rather, these implementation methods are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.
[0031] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the present application. It is understood that the meanings of "on," "above," and "over" in the present application should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the present application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.
[0032] As described in the background section, in high-k metal gate processes using a back-gate process, after removing the dummy polysilicon gate, a TiN layer is first deposited as a work function layer for the PMOS region. Then, a wetting layer is deposited on the work function layer. The wetting layer is a titanium thin film deposited by the Extensa PVD system. Finally, an aluminum layer is deposited on the wetting layer. However, due to the high mobility of Ti atoms, they tend to aggregate and form island-like structures, which reduces the continuity of the wetting layer. Furthermore, due to equipment malfunctions and other reasons, the interval between depositing the wetting layer and depositing the aluminum layer increases, further reducing the continuity of the wetting layer. Due to the large aspect ratio of the gate trench, the surface mobility of Al atoms is insufficient in low-temperature environments (≤400℃), and its filling ability is greatly affected by the wetting layer. When the continuity of the wetting layer on the sidewall of the gate trench deteriorates, TiN under Ti is exposed at discontinuous Ti locations. These exposed areas easily adsorb oxygen in the process environment. When aluminum atoms reach these exposed areas, they not only fail to form a TiAl3 transition layer, but may also form aluminum oxide, preventing aluminum atoms from flowing downwards. Instead, they can only grow laterally at the top of the gate trench (because the geometric shielding effect is weak at the top of the gate trench, and the Ti layer deposited by PVD usually has the best continuity and is the densest). This causes the opening at the top of the gate trench to be sealed prematurely, and voids to form in the middle and lower part of the gate trench. In the subsequent chemical mechanical polishing process, half of the gate is polished away, exposing the previously formed voids. The phenomenon is that aluminum filling defects are generated at the top of the metal gate, leading to adverse consequences.
[0033] To address the above problems, this application proposes an improved solution: when the interval between the formation of the first wetting layer and the formation of the conductive layer exceeds a preset value of 6 minutes, an ultra-thin second wetting layer is formed on the first wetting layer to improve the continuity of the wetting layer. Then, the conductive layer is immediately formed on the second wetting layer, allowing a continuous intermetallic compound transition layer to be formed at the interface between the second wetting layer and the conductive layer. This improves the deposition effect of the conductive layer, ensuring that the opening at the top of the gate trench is not prematurely sealed during conductive layer filling, reducing the generation of voids in the lower part of the gate trench, and thus reducing the possibility of aluminum filling defects at the top of the metal gate after subsequent chemical mechanical polishing. (Reference) Figure 1 , Figure 1 This is a schematic flowchart illustrating the method for fabricating the semiconductor structure provided in the embodiments of this application; as shown Figure 1 As shown, the method for fabricating the semiconductor structure may include the following steps:
[0034] Step S101: Provide a substrate on which a gate trench is formed;
[0035] Step S102: A power function layer is formed on the bottom and sidewalls of the gate trench;
[0036] Step S103: A first wetting layer is formed on the work function layer;
[0037] Step S104: When the time interval between the formation of the first wetting layer and the formation of the conductive layer is greater than a preset value, a second wetting layer is formed on the first wetting layer. The thickness of the second wetting layer is less than the thickness of the first wetting layer. The conductive layer is immediately formed on the second wetting layer so that a portion of the conductive layer reacts with a portion of the second wetting layer, forming a continuous intermetallic compound transition layer at the junction of the conductive layer and the second wetting layer.
[0038] The method for fabricating the semiconductor structure proposed in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application. Many specific details are set forth in the following description to provide a thorough understanding of this application; however, this application may also be implemented in other ways different from those described herein, and therefore this application is not limited to the specific embodiments disclosed below.
[0039] See Figure 2In step S101 above, a substrate 1 is first provided. The substrate 1 can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. It also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Alternatively, it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz substrate, or a glass substrate. Exemplarily, the substrate 1 in this embodiment is preferably a silicon wafer. A dielectric layer planarized by chemical mechanical polishing is formed on the substrate 1. A dummy polysilicon gate structure is formed in the dielectric layer. After the dummy polysilicon gate structure is removed by selective etching, the gate trench 2 is exposed in the dielectric layer. To simplify the drawings, only one gate trench 2 is shown in the drawings of this embodiment. However, those skilled in the art will understand that multiple gate trenches 2 can be formed in the actual semiconductor structure fabrication process. In this embodiment, the aspect ratio of the gate trench 2 is greater than or equal to 3:1.
[0040] See Figures 2-3 In step S102 above, a work function layer 3 is formed on the bottom and sidewalls of the gate trench 2 by physical vapor deposition process; wherein the material of the work function layer 3 includes titanium nitride (TiN) and the thickness ranges from 40 angstroms to 80 angstroms.
[0041] Continue reading Figures 2-3 In step S103 above, a first wetting layer 4 is formed on the work function layer 3 by physical vapor deposition; wherein the material of the first wetting layer 4 includes metallic titanium (Ti), and the thickness ranges from 70 angstroms to 100 angstroms. Figure 3 As shown, due to the high mobility of titanium atoms, the first wetting layer 4 aggregates to form an island-like structure with poor continuity; secondly, due to machine malfunctions and other reasons, the interval between the formation of the first wetting layer 4 and the formation of the conductive layer 7 will increase, which will further reduce the continuity of the first wetting layer 4.
[0042] See Figure 4In step S104 above, when the interval between the formation of the first wetting layer 4 and the formation of the conductive layer 7 is greater than a preset value, an ultrathin second wetting layer 5 is formed on the first wetting layer 4 by physical vapor deposition. The preset value is 6 minutes because, according to experimental data, when the interval between the formation of the first wetting layer 4 and the formation of the conductive layer 7 is greater than 6 minutes, the number of aluminum filling defects generated subsequently will be greater than 100, and it is necessary to take improvement measures. When the interval between the formation of the first wetting layer 4 and the formation of the conductive layer 7 is less than 1 minute, the number of aluminum filling defects generated subsequently will be less than 10, and it is not necessary to take improvement measures. The material of the second wetting layer 5 is preferably titanium (Ti), with a thickness ranging from 1 angstrom to 20 angstroms, which is less than the thickness of the first wetting layer 4, and the deposition time is 0.5 seconds to 1.5 seconds. The formation of the second wetting layer 5 improves the continuity of the titanium film at the bottom and sidewalls of the gate trench 2, inhibits the formation of aluminum oxide, provides a good substrate environment for the conductive layer 7, improves the filling effect of the conductive layer 7, ensures that the opening at the top of the gate trench 2 will not be sealed prematurely when the conductive layer 7 is filled, and reduces the generation of voids in the lower part of the gate trench 2.
[0043] See Figure 5 Immediately after the formation of the second wetting layer 5, a conductive layer 7 is formed on the second wetting layer 5. The material of the conductive layer 7 includes aluminum or an aluminum alloy. In a preferred embodiment of this application, the conductive layer 7 is an aluminum layer, which is formed by a two-step cold / hot aluminum physical vapor deposition reflow filling process. The first step deposits a cold aluminum seed layer at a typical temperature of about 270°C, the main purpose of which is to uniformly and continuously form an extremely thin seed layer at the bottom and sidewalls of the gate trench. The second step fills the hot aluminum body at a typical temperature of about 400°C, with the hot aluminum filling the cold aluminum seed layer from the bottom of the gate trench upwards. The reason for forming the conductive layer 7 immediately is to prevent Ti from re-agglomerating, which would lead to Ti discontinuity. After the conductive layer 7 is formed, a portion of the conductive layer 7 reacts with a portion of the second wetting layer 5, forming a continuous intermetallic compound transition layer 6 at the interface between the conductive layer 7 and the second wetting layer 5. The intermetallic compound transition layer 6 includes titanium trialuminate (TiAl3). The metal-covalent bonding characteristics of the continuous titanium trialuminate transition layer can strongly connect the second wetting layer 5 and the conductive layer 7, providing a low-resistance flow channel for aluminum atom filling, improving the filling effect of the aluminum layer, preventing the opening at the top of the gate trench 2 from being prematurely sealed, reducing the generation of voids in the lower part of the gate trench 2, and allowing the conductive layer 7 that has not reacted with the second wetting layer 5 to fill the remaining space of the entire gate trench 2, thereby effectively reducing the number of aluminum filling defects at the top of the metal gate after subsequent chemical mechanical polishing.
[0044] In other embodiments, a semiconductor structure is also provided, wherein the semiconductor structure can be fabricated using the methods described above, as detailed above, and will not be repeated here.
[0045] In summary, in the semiconductor structure and fabrication method provided in this application, when the interval between the formation of the first wetting layer and the formation of the conductive layer is greater than a preset value of 6 minutes, an ultra-thin second wetting layer is formed on the first wetting layer to improve the continuity of the wetting layer. Then, the conductive layer is immediately formed on the second wetting layer, so that a continuous intermetallic compound transition layer can be formed at the junction of the second wetting layer and the conductive layer. This improves the deposition effect of the conductive layer, ensures that the opening at the top of the gate trench is not sealed prematurely when the conductive layer is filled, reduces the generation of voids in the lower part of the gate trench, and thus reduces the possibility of aluminum filling defects at the top of the metal gate after subsequent chemical mechanical polishing.
[0046] It should be noted that although preferred embodiments have been disclosed above in this application, these embodiments are not intended to limit this application. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of this application based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which gate trenches are formed; A first wetting layer is formed on the bottom and sidewalls of the gate trench; When the time interval between the formation of the first wetting layer and the formation of the conductive layer is greater than a preset value, a second wetting layer is formed on the first wetting layer. The thickness of the second wetting layer is less than the thickness of the first wetting layer. The conductive layer is formed on the second wetting layer so that a portion of the conductive layer reacts with a portion of the second wetting layer, and a continuous intermetallic compound transition layer is formed at the junction of the conductive layer and the second wetting layer.
2. The method as described in claim 1, characterized in that, The aspect ratio of the gate trench is greater than or equal to 3:
1.
3. The method as described in claim 1, characterized in that, The first wetting layer and the second wetting layer are made of the same material.
4. The method as described in claim 1, characterized in that, The second wetting layer comprises titanium.
5. The method as described in claim 1, characterized in that, The conductive layer comprises aluminum or an aluminum alloy.
6. The method as described in claim 1, characterized in that, Before the formation of the first wetting layer, the method further includes: A power function layer is formed on the bottom and sidewalls of the gate trench.
7. The method as described in claim 1, characterized in that, The thickness of the second wetting layer is 1 to 20 angstroms.
8. The method as described in claim 1, characterized in that, The deposition time of the second wetting layer is 0.5 seconds to 1.5 seconds.
9. The method as described in claim 1, characterized in that, The preset value is 6 minutes.
10. A semiconductor structure, characterized in that, It is prepared by the method described in any one of claims 1 to 9.