Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The structure includes: a substrate, the substrate including opposite first and second surfaces, the substrate including a plurality of pixel regions and a plurality of isolation regions surrounding the pixel regions; a light sensing structure located in a pixel region; an isolation structure located in an isolation region; a first electrical connection structure located on the first surface of the substrate, the first electrical connection structure electrically connected to the isolation structure, the first electrical connection structure including a first connection layer, the first connection layer parallel to the surface of the substrate, and the first connection layer located above a portion of the pixel region, the first connection layer having a transmittance greater than a transmittance of the isolation structure. The light sensing efficiency of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Due to the characteristics of its application scenarios, the core performance requirements of automotive 3D distance imaging systems are long detection distance, high ambient brightness, and high driving speed. Therefore, compared with DTOF (Direct Time Flight) optical sensors used in mobile terminals, they usually have performance requirements of high gain, high sensitivity, and high temporal resolution.

[0003] A common optical sensor for 3D distance imaging systems is the silicon photomultiplier tube (SiPM). A SiPM consists of multiple single-photon avalanche diodes (SPADs) connected in parallel. Typically, each SPAD unit is independently connected in series with a quenching resistor, while the cathode and anode are connected in parallel. One array outputs a signal as one pixel; multiple arrays can achieve 3D imaging.

[0004] The high gain requirements of single-photon avalanche diode (SPAD) sensors in 3D distance imaging systems often necessitate higher overvoltages for the SPADs to achieve higher photon detection efficiency, thus requiring higher operating voltages. This presents greater challenges to requirements such as reduced electrical isolation and dark count rate (DCR) of the devices.

[0005] However, improving the photoelectric efficiency of single-photon avalanche diodes while reducing the electrical isolation / dark count rate (DCR) of the device remains a problem that needs to be solved. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the photoelectric efficiency of a single-photon avalanche diode.

[0007] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a first surface and a second surface opposite to each other, the substrate including a plurality of pixel regions and a plurality of isolation regions surrounding the pixel regions; a photosensitive structure located within the pixel regions; an isolation structure located within the isolation regions; and a first electrical connection structure located on the first surface of the substrate, the first electrical connection structure being electrically connected to the isolation structure, the first electrical connection structure including a first connection layer, the first connection layer being parallel to the substrate surface and located above a portion of the pixel regions, the transmittance of the first connection layer being greater than the transmittance of the isolation structure.

[0008] Optionally, the transmittance of the first connecting layer is greater than 98%.

[0009] Optionally, the material of the first connecting layer includes graphene.

[0010] Optionally, the isolation structure includes: an isolation layer and an insulating layer located on the sidewall surface of the isolation layer, the insulating layer being located between the isolation layer and the substrate; the first electrical connection structure is electrically connected to the isolation layer.

[0011] Optionally, the first electrical connection structure further includes a second connection layer located on a first surface of the substrate and electrically connected to the substrate.

[0012] Optionally, the transmittance of the second connecting layer is greater than that of the insulating layer.

[0013] Optionally, the material of the second connecting layer is the same as the material of the first connecting layer.

[0014] Optionally, the transmittance of the second connecting layer is greater than 98%.

[0015] Optionally, the material of the second connecting layer includes graphene.

[0016] Optionally, the material of the insulating layer includes tungsten; the material of the insulating layer includes silicon oxide.

[0017] Optionally, it further includes: a first dielectric structure located on a first surface of the substrate, the first interconnect layer located within the first dielectric structure, and the second interconnect layer located within the first dielectric structure and within the substrate.

[0018] Optionally, it also includes: a plurality of first grooves located within the pixel area of ​​the substrate, wherein the first surface of the substrate exposes the top of the plurality of first grooves, and the cross-sectional shape of the first grooves includes an "inverted pyramid" shape; the first dielectric structure is also located within the plurality of first grooves.

[0019] Optionally, the substrate further includes a device region and a non-device region, wherein the device region includes the pixel region and the isolation region; the second connection layer is located in the non-device region.

[0020] Optionally, the thickness of the first connecting layer ranges from 1000 angstroms to 3000 angstroms.

[0021] Optionally, it further includes: a second dielectric structure located on a first surface of the substrate and a second connection structure located within the second dielectric structure, the second connection structure being electrically connected to the photosensitive structure; a carrier substrate and a third dielectric structure located on the carrier substrate, the second dielectric structure being bonded to the third dielectric structure.

[0022] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first surface and a second surface opposite to each other, the substrate including a plurality of pixel regions and a plurality of isolation regions surrounding the pixel regions; forming a photosensitive structure in the pixel regions; forming an isolation structure in the isolation regions; forming a first electrical connection structure on the first surface of the substrate, the first electrical connection structure being electrically connected to the isolation structure, the first electrical connection structure including a first connection layer, the first connection layer being parallel to the substrate surface and located above a portion of the pixel regions, the transmittance of the first connection layer being greater than the transmittance of the isolation structure.

[0023] Optionally, the method of forming the isolation structure includes: forming a first opening in the isolation region, the first opening penetrating the substrate from a first surface of the substrate; forming an insulating layer on the sidewall of the first opening; forming a first dielectric structure on the first surface of the substrate, the first dielectric structure exposing the top of the first opening; and forming an isolation layer in the first opening, the insulating layer being located on the sidewall of the isolation layer.

[0024] Optionally, the insulating layer and the first dielectric structure are formed simultaneously; the method for forming the insulating layer and the first dielectric structure includes: forming a dielectric material layer on the sidewall of the first opening and on the first surface of the substrate, the dielectric material layer sealing the top of the first opening; etching the dielectric material layer at the top of the first opening to form a first dielectric structure on the first surface of the substrate and an insulating layer on the sidewall of the first opening, and forming a second opening at the top of the first opening, the second opening communicating with the first opening, and the insulating layer also being located within the second opening.

[0025] Optionally, the substrate further includes a device region and a non-device region, the device region including the pixel region and the isolation region; forming a first electrical connection structure on a first surface of the substrate includes: etching a dielectric material layer and the substrate on the non-device region; forming a second groove within the first dielectric structure and the substrate, the depth of the second groove being less than the depth of the first opening; forming a second connection layer within the second groove, the second connection layer being electrically connected to the substrate; forming a first connection layer on the first dielectric structure, the first connection layer being electrically connected to the isolation layer and the second connection layer, the first connection layer being parallel to the substrate surface, the transmittance of the first connection layer being greater than the transmittance of the isolation structure, and the first connection structure including the first connection layer and the second connection layer.

[0026] Optionally, the second interconnect layer and the isolation layer are formed simultaneously; the method for forming the second interconnect layer and the isolation layer includes: etching the dielectric material layer at the top of the first opening, etching the dielectric material layer and the substrate on the non-device area, forming a second groove in the first dielectric structure and the substrate; forming an isolation material layer in the first opening, the second opening, the second groove and on the first dielectric structure; planarizing the isolation material layer until the surface of the first dielectric structure is exposed, forming the isolation layer in the first opening and the second opening, and forming the second interconnect layer in the second groove.

[0027] Optionally, the material of the second connecting layer is the same as the material of the first connecting layer.

[0028] Optionally, before forming the isolation structure within the isolation region, the method further includes: forming a plurality of first grooves within the pixel region, wherein the first surface of the substrate exposes the tops of the plurality of first grooves, and the cross-sectional shape of the first grooves includes an "inverted pyramid" shape; the first dielectric structure is also located within the plurality of first grooves.

[0029] Optionally, after forming a photosensitive structure within the pixel region, the method further includes: forming a second dielectric structure and a second connection structure located within the second dielectric structure on a second surface of the substrate, the second connection structure being electrically connected to the photosensitive structure; providing a support substrate; forming a third dielectric structure on the support substrate; bonding the third dielectric structure to the second dielectric structure; and after bonding the third dielectric structure to the second dielectric structure, flipping the substrate to form the isolation structure within the isolation region.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] In the structure of the present invention, the first connecting layer is parallel to the substrate surface and is located above a portion of the pixel area. The transmittance of the first connecting layer is greater than that of the isolation layer. Therefore, when a negative potential is applied to the isolation layer through the first connecting structure, the first connecting layer conducts electricity while not obstructing much light entering the pixel area, which greatly improves the photosensitivity.

[0032] Furthermore, the first connecting layer is made of graphene. Graphene possesses excellent electrical properties, exhibiting a carrier mobility of up to 15000 m² / V·s and a conductivity exceeding 1000 S / cm at room temperature. In addition, graphene also has excellent light transmittance, with a transmittance of up to 98% in the near-infrared and visible light bands for a single layer. Therefore, while the first connecting layer provides good conductivity, it does not obstruct light entering the pixel area, significantly improving photosensitivity.

[0033] In the formation method of the present invention, the first connecting layer is parallel to the substrate surface and is located above a portion of the pixel area. The transmittance of the first connecting layer is greater than that of the isolation layer. Therefore, when a negative potential is applied to the isolation layer through the first connecting structure, the first connecting layer conducts electricity while not causing much obstruction to the light entering the pixel area, which greatly improves the photosensitivity. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the semiconductor structure in one embodiment;

[0035] Figures 2 to 10 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention;

[0036] Figures 11 to 14 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention. Detailed Implementation

[0037] As described in the background section, improving the photoelectric efficiency of single-photon avalanche diodes while reducing the electrical isolation / dark count rate (DCR) of the device remains a problem that needs to be solved. This will now be analyzed and explained with reference to specific embodiments.

[0038] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment.

[0039] Please refer to Figure 1The semiconductor structure includes: a substrate 100, the substrate 100 including opposing first and second surfaces, the substrate 100 including a plurality of pixel regions and a plurality of isolation regions surrounding the pixel regions; a photosensitive structure 101 located within the pixel regions; an isolation structure located within the isolation regions, the isolation structure including an isolation layer 114 and an insulating layer 113 located on the sidewall surface of the isolation layer 114, the insulating layer 113 being located between the isolation layer 114 and the substrate 100; a plurality of first grooves located within the pixel regions, the first surface of the substrate 100 exposing the tops of the plurality of first grooves; a first dielectric structure 114 located on the first surface of the substrate 100, the first dielectric structure 114 also being located within the first grooves; and a first electrical connection structure located on the first surface of the substrate 100, the first electrical connection structure being electrically connected to the isolation layer 114, the first electrical connection structure including: a first connection layer 117 located on the first dielectric structure 114 parallel to the surface of the substrate 100, and a connection layer 117 located within the first dielectric structure 114 and the substrate 100. The substrate 100 includes a second connecting layer 116 and a third connecting layer 115 located within the first dielectric structure 114 and on the isolation layer 114. The first connecting layer 117 is located on the third connecting layer 115 and the second connecting layer 116. The substrate 100 has a second dielectric structure on its second surface and a second connecting structure within the second dielectric structure. The second connecting structure is electrically connected to the photosensitive structure 101. The second dielectric structure includes a first dielectric layer 102, a second dielectric layer 103, a third dielectric layer 104, and a fourth dielectric layer 105 stacked sequentially on the second surface of the substrate 200. The second connecting structure includes a first plug 106 located within the first dielectric layer 102, a first conductive layer 107 located within the second dielectric layer 103, a second plug 108 located within the third dielectric layer 104, and a second conductive layer 109 located within the fourth dielectric layer 105. The substrate 110 has a carrier substrate 110 and a third dielectric structure 111 located on the carrier substrate 110. The second dielectric structure is bonded to the third dielectric structure 111.

[0040] In the semiconductor structure, the first connection structure is used to apply a negative potential to the isolation layer 114, so that positive charges can be accumulated in the silicon substrate on the sidewall of the isolation layer 114 to prevent the increase of dark count rate caused by interface states, thereby reducing the dark count rate (DCR).

[0041] However, the first connection structure is usually made of an opaque metal, such as aluminum. When the first connection layer 117, which is parallel to the surface of the substrate 100, connects the isolation layer 114, it will inevitably block part of the pixel area, thereby reducing the amount of light entering the pixel area and affecting the photosensitive efficiency of the pixel area.

[0042] To address the aforementioned issues, the present invention provides a semiconductor structure and its formation method. The first connection layer is parallel to the substrate surface and is located above a portion of the pixel area. The transmittance of the first connection layer is greater than that of the isolation layer. Therefore, when a negative potential is applied to the isolation layer through the first connection structure, the first connection layer conducts electricity while not significantly blocking the light entering the pixel area, thereby greatly improving the photosensitivity.

[0043] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 2 to 10 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention.

[0045] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 including a first surface S1 and a second surface S2 opposite to each other, the substrate 200 including a plurality of pixel regions A and a plurality of isolation regions B surrounding the pixel regions A.

[0046] The pixel region A is used to form a photosensitive device, and the isolation region B surrounds the pixel region A to isolate the pixel region A and prevent optical crosstalk between adjacent pixel regions A.

[0047] In this embodiment, the substrate 200 further includes a device region and a non-device region, wherein the device region includes the pixel region A and the isolation region B.

[0048] In this embodiment, the substrate 200 is made of silicon.

[0049] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0050] Please continue to refer to this. Figure 2 A photosensitive structure 201 is formed within pixel region A.

[0051] In this embodiment, the photosensitive structure 201 is a photodiode. The process for forming the photosensitive structure 201 includes ion implantation.

[0052] In this embodiment, the second surface S2 of the substrate exposes the surface of the photosensitive structure 201.

[0053] Please refer to Figure 3A second dielectric structure and a second connection structure located within the second dielectric structure are formed on the second surface S2 of the substrate 200, and the second connection structure is electrically connected to the photosensitive structure 201.

[0054] The second dielectric structure includes: a first dielectric layer 202, a second dielectric layer 203, a third dielectric layer 204 and a fourth dielectric layer 205 sequentially stacked on the second surface of the substrate 200.

[0055] The second connection structure includes: a first plug 206 located within a first dielectric layer 202, the first plug 206 being located on and electrically connected to a photosensitive structure 201; a first conductive layer 207 located within a second dielectric layer 203, the first conductive layer 207 being located on the first dielectric layer 202 and the first plug 206, and electrically connected to the first plug 206; a second plug 208 located within a third dielectric layer 204, the second plug 208 being located on and electrically connected to the first conductive layer 207; and a second conductive layer 209 located within a fourth dielectric layer 205, the second conductive layer 209 being located on the third dielectric layer 204 and the second plug 208, and electrically connected to the second plug 208.

[0056] The material of the second dielectric structure includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0057] In this embodiment, the material of the second dielectric structure includes silicon oxide.

[0058] The material of the second connection structure includes a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0059] Please refer to Figure 4 Provide a support substrate 210; form a third dielectric structure 211 on the support substrate 210; and bond the third dielectric structure 211 to the second dielectric structure.

[0060] The material of the third dielectric structure 211 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0061] In this embodiment, the material of the third dielectric structure 211 includes silicon oxide.

[0062] Please refer to Figure 5After bonding the third dielectric structure 211 to the second dielectric structure, the substrate 200 is flipped to form a plurality of first grooves 220 in the pixel area A. The first surface S1 of the substrate 200 exposes the top of the plurality of first grooves 220. The cross-sectional shape of the first grooves 220 includes an inverted pyramid shape.

[0063] The cross-sectional shape of the first groove 220 includes an inverted pyramid shape. When the light is incident on the first surface of the substrate 200 from any direction, the probability of entering the pixel area A can be increased, thereby increasing the area of ​​the first surface S1 of the pixel area A, increasing the photosensitive area, increasing the amount of light entering the pixel area A, and improving the photosensitive efficiency.

[0064] In this embodiment, the bottom of the first groove 220 is the apex of the "inverted pyramid" shape.

[0065] In this embodiment, the depth of the first groove 220 is less than the thickness of the substrate 200.

[0066] The process for forming the first groove 220 includes a dry etching process.

[0067] In other embodiments, the first groove may not be formed.

[0068] Next, an isolation structure is formed within isolation region B; a first electrical connection structure is formed on the first surface S1 of substrate 200, the first electrical connection structure being electrically connected to the isolation structure. The first electrical connection structure includes a first connection layer parallel to the surface of substrate 200, and the transmittance of the first connection layer is greater than the transmittance of the isolation structure. Please refer to [reference needed] for the formation process of the isolation structure and the first electrical connection structure. Figures 6 to 10 .

[0069] Please refer to Figure 6 A first opening 221 is formed in the isolation region B, and the first opening 221 extends through the first surface S1 of the substrate 200.

[0070] In this embodiment, the first opening 221 exposes the surface of the second medium structure.

[0071] The method for forming the first opening 221 includes: forming a patterned layer (not shown) on a first surface S1 of a substrate 200, wherein the patterned layer exposes a portion of the surface of the isolation region B; etching the substrate 200 using the patterned layer as a mask until the surface of the second dielectric structure is exposed, thereby forming the first opening 221 in the isolation region B.

[0072] The etching process for the substrate 200 includes a dry etching process.

[0073] Please refer toFigure 7 A dielectric material layer 222 is formed on the sidewall of the first opening 221 and on the first surface S1 of the substrate 200, and the dielectric material layer 222 closes the top of the first opening 221.

[0074] In this embodiment, the dielectric material layer 222 is also located within a plurality of the first grooves 220.

[0075] The process for forming the dielectric material layer 222 includes a chemical vapor deposition process, which has a relatively fast deposition rate, thereby enabling it to be formed on the sidewall of the first opening 221 and to seal the top of the first opening 221.

[0076] The dielectric material layer 222 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0077] In this embodiment, the material of the dielectric material layer 222 includes silicon oxide.

[0078] Please refer to Figure 8 The dielectric material layer 222 at the top of the first opening 221 is etched to form a first dielectric structure 224 on the first surface S1 of the substrate 200 and an insulating layer 223 on the sidewall of the first opening 221, and a second opening 225 at the top of the first opening 221 is formed. The second opening 225 is connected to the first opening 221, and the first dielectric structure 224 exposes the top of the first opening 221.

[0079] In this embodiment, while etching the dielectric material layer 222 at the top of the first opening 221, the method also includes etching the dielectric material layer 222 and the substrate 200 on the non-device area, and forming a second groove 226 in the first dielectric structure 224 and the substrate 200, wherein the depth of the second groove 226 is less than the depth of the first opening 221.

[0080] In this embodiment, the first dielectric structure 224 is also located within a plurality of the first grooves 220. This is to prevent the material of the isolation layer from filling into the first grooves 220 and affecting the amount of light transmitted during the subsequent formation of the isolation layer.

[0081] Please refer to Figure 9 An isolation layer 228 is formed within the first opening 221 and the second opening 225, and the insulating layer 223 is located on the sidewall of the isolation layer 228.

[0082] The insulating layer 223 is used to electrically isolate the isolation layer 228 and the substrate 200, so as to prevent the isolation layer 228 and the substrate 200 from directly contacting each other and causing a short circuit.

[0083] Please continue to refer to this. Figure 9 A second connection layer 227 is formed in the second groove 226, and the second connection layer 227 is electrically connected to the substrate 200.

[0084] In this embodiment, the isolation layer 228 and the second connecting layer 227 are formed simultaneously, and the isolation layer 228 and the second connecting layer 227 are made of the same material.

[0085] The method for forming the second connecting layer 227 and the isolation layer 228 includes: forming an isolation material layer (not shown) in the first opening 221, the second opening 225, the second groove 226 and on the first dielectric structure 224; planarizing the isolation material layer until the surface of the first dielectric structure 224 is exposed; forming the isolation layer 228 in the first opening 221 and the second opening 225; and forming the second connecting layer 227 in the second groove 226.

[0086] In this embodiment, the materials of the second connecting layer 227 and the insulating layer 228 include opaque metals, including tungsten.

[0087] The isolation layer 228 is made of an opaque metal. On the one hand, it can effectively block light from adjacent pixel areas A, preventing optical crosstalk between them. On the other hand, the isolation layer 228 is subsequently connected to an external circuit through a first connection structure and loaded with a negative potential. This allows positive charges to accumulate in the silicon substrate on the sidewall of the isolation layer 228, preventing the increase in dark count rate caused by interface states and thus reducing the dark count rate (DCR).

[0088] In other embodiments, the isolation layer and the second connecting layer may be formed asynchronously, and the materials of the isolation layer and the second connecting layer may be different.

[0089] Please refer to Figure 10 A first connection layer 229 is formed on the first dielectric structure 224. The first connection layer 229 is electrically connected to the isolation layer 228 and the second connection layer 227. The first connection layer 229 is parallel to the surface of the substrate 200 and is located above a portion of the pixel area A. The transmittance of the first connection layer 229 is greater than that of the isolation layer 228. The first connection structure includes the first connection layer 229 and the second connection layer 227.

[0090] The formation process of the first connection layer 229 includes: forming a connection material layer (not shown) on the first dielectric structure 224; etching the connection material layer until the surface of the first dielectric structure 224 is exposed, and forming the first connection layer 229 on the first dielectric structure 224.

[0091] In this embodiment, the transmittance of the first connecting layer 229 is greater than that of the isolation layer 228, the material of the first connecting layer 229 is different from that of the isolation layer 228, and the material of the first connecting layer 229 is different from that of the second connecting layer 227.

[0092] In this embodiment, the transmittance of the first connecting layer 229 is greater than 98%. The material of the first connecting layer 229 is a transparent conductive material. Therefore, while the first connecting layer 229 conducts electricity, it does not significantly obstruct the light entering the pixel area A, thereby greatly improving the photosensitivity.

[0093] In this embodiment, the first connecting layer 229 is made of graphene. The graphene material has excellent electrical properties, exhibiting a carrier mobility of up to 15000 m² / V·s and a conductivity exceeding 1000 S / cm at room temperature; furthermore, graphene also has excellent light transmittance, with a transmittance of up to 98% in the near-infrared and visible light bands for single-layer graphene.

[0094] Therefore, when a negative potential is applied to the isolation layer 228 through the first connection structure, the first connection layer 229 has good conductivity and will not block the light entering the pixel area A, which will greatly improve the photosensitivity.

[0095] In this embodiment, the thickness of the first connecting layer 229 ranges from 1000 angstroms to 3000 angstroms.

[0096] Figures 11 to 14 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0097] Please refer to Figure 11 , Figure 11 In order to be in Figure 7 Based on the schematic diagram, the dielectric material layer 222 on the top of the first opening 221 is etched to form a first dielectric structure 224 on the first surface S1 of the substrate 200 and an insulating layer 223 on the sidewall of the first opening 221, and a second opening 225 on the top of the first opening 221 is formed. The second opening 225 is connected to the first opening 221, and the first dielectric structure 224 exposes the top of the first opening 221.

[0098] Please refer to the process of forming the first opening 221 and the second opening 225. Figure 8 This will not be elaborated upon here.

[0099] Please refer to Figure 12 An isolation layer 301 is formed within the first opening 221 and the second opening 225, and the insulating layer 223 is located on the sidewall of the isolation layer 301.

[0100] The insulating layer 223 is used to electrically isolate the isolation layer 301 and the substrate 200, so as to prevent the isolation layer 301 and the substrate 200 from directly contacting each other and causing a short circuit.

[0101] Please refer to Figure 13 The dielectric material layer 222 and the substrate 200 on the non-device area are etched to form a second groove 302 in the first dielectric structure 224 and the substrate 200. The depth of the second groove 302 is less than the depth of the first opening 221.

[0102] Please refer to Figure 14 A second connection layer 303 is formed in the second groove 302, and the second connection layer 303 is electrically connected to the substrate 200; a first connection layer 304 is formed on the first dielectric structure 224, and the first connection layer 304 is electrically connected to the isolation layer 301 and the second connection layer 303. The first connection layer 304 is parallel to the surface of the substrate 200 and is located above a portion of the pixel area A. The transmittance of the first connection layer 304 is greater than the transmittance of the isolation layer 301. The first connection structure includes the first connection layer 304 and the second connection layer 303.

[0103] In this embodiment, the material of the second connecting layer 303 is the same as the material of the first connecting layer 304.

[0104] In this embodiment, the transmittance of the second connecting layer 303 and the first connecting layer 304 is greater than 98%. The materials of the second connecting layer 303 and the first connecting layer 304 are transparent conductive materials. Therefore, while the first connecting layer 304 conducts electricity, it does not significantly obstruct the light entering the pixel area A, thus greatly improving the photosensitivity.

[0105] In this embodiment, the materials of the second connecting layer 303 and the first connecting layer 304 include graphene. The graphene material has excellent electrical properties, exhibiting a carrier mobility of up to 15000 m² / V·s and a conductivity exceeding 1000 S / cm at room temperature; furthermore, graphene also has very good light transmittance, with transmittance in the near-infrared and visible light bands reaching up to 98% for single-layer graphene.

[0106] Therefore, when a negative potential is applied to the isolation layer 301 through the first connection structure, the first connection layer 304 has good conductivity and will not block the light entering the pixel area A, which will greatly improve the photosensitivity.

[0107] The thickness of the second connecting layer 303 and the first connecting layer 304 ranges from 1000 angstroms to 3000 angstroms.

[0108] In this embodiment, the second connecting layer 303 and the first connecting layer 304 are formed simultaneously. The formation process of the second connecting layer 303 and the first connecting layer 304 includes: forming a connecting material layer (not shown) in the second groove 302 and on the first dielectric structure 224; etching the connecting material layer until the surface of the first dielectric structure 224 is exposed; forming the first connecting layer 304 on the first dielectric structure 224; and forming the second connecting layer 303 in the second groove 302.

[0109] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including opposing first and second surfaces, the substrate including a plurality of pixel regions and a plurality of isolation regions surrounding the pixel regions; Photosensitive structures located within the pixel area; The isolation structure located within the isolation zone; A first electrical connection structure is located on a first surface of a substrate, the first electrical connection structure is electrically connected to the isolation structure, the first electrical connection structure includes a first connection layer, the first connection layer is parallel to the substrate surface and is located above a portion of the pixel area, and the transmittance of the first connection layer is greater than the transmittance of the isolation structure.

2. The semiconductor structure as described in claim 1, characterized in that, The transmittance of the first connecting layer is greater than 98%.

3. The semiconductor structure as described in claim 2, characterized in that, The material of the first connecting layer includes graphene.

4. The semiconductor structure as described in claim 1, characterized in that, The isolation structure includes: an isolation layer and an insulating layer located on the sidewall surface of the isolation layer, the insulating layer being located between the isolation layer and the substrate; the first electrical connection structure is electrically connected to the isolation layer.

5. The semiconductor structure as described in claim 4, characterized in that, The first electrical connection structure further includes a second connection layer located on the first surface of the substrate and electrically connected to the substrate.

6. The semiconductor structure as described in claim 5, characterized in that, The transmittance of the second connecting layer is greater than that of the insulating layer.

7. The semiconductor structure as described in claim 6, characterized in that, The material of the second connecting layer is the same as that of the first connecting layer.

8. The semiconductor structure as described in claim 7, characterized in that, The transmittance of the second connecting layer is greater than 98%.

9. The semiconductor structure as described in claim 8, characterized in that, The material of the second connecting layer includes graphene.

10. The semiconductor structure as described in claim 4, characterized in that, The material of the isolation layer includes tungsten; The insulating layer is made of silicon oxide.

11. The semiconductor structure as described in claim 5, characterized in that, Also includes: A first dielectric structure located on a first surface of a substrate, wherein the first interconnecting layer is located within the first dielectric structure, and the second interconnecting layer is located within the first dielectric structure and within the substrate.

12. The semiconductor structure as claimed in claim 11, characterized in that, Also includes: A plurality of first grooves are located within the pixel area of ​​the substrate, the first surface of the substrate exposing the tops of the plurality of first grooves, and the cross-sectional shape of the first grooves includes an "inverted pyramid" shape; The first medium structure is also located within several of the first grooves.

13. The semiconductor structure as described in claim 11, characterized in that, The substrate further includes a device region and a non-device region, the device region including the pixel region and the isolation region; the second connection layer is located in the non-device region.

14. The semiconductor structure as claimed in claim 1, characterized in that, The thickness of the first connecting layer ranges from 1000 angstroms to 3000 angstroms.

15. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: A second dielectric structure located on a first surface of a substrate and a second connection structure located within the second dielectric structure, wherein the second connection structure is electrically connected to the photosensitive structure; A supporting substrate and a third dielectric structure located on the supporting substrate, wherein the second dielectric structure is bonded to the third dielectric structure.

16. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including opposing first and second surfaces, the substrate including a plurality of pixel regions and a plurality of isolation regions surrounding the pixel regions; A photosensitive structure is formed within the pixel area; An isolation structure is formed within the isolation zone; A first electrical connection structure is formed on a first surface of a substrate. The first electrical connection structure is electrically connected to the isolation structure. The first electrical connection structure includes a first connection layer. The first connection layer is parallel to the surface of the substrate and is located above a portion of the pixel area. The transmittance of the first connection layer is greater than the transmittance of the isolation structure.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the isolation structure includes: forming a first opening in the isolation region, the first opening penetrating the substrate from a first surface of the substrate; forming an insulating layer on the sidewall of the first opening; forming a first dielectric structure on the first surface of the substrate, the first dielectric structure exposing the top of the first opening; and forming an isolation layer in the first opening, the insulating layer being located on the sidewall of the isolation layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The insulating layer and the first dielectric structure are formed simultaneously; The method for forming the insulating layer and the first dielectric structure includes: forming a dielectric material layer on the sidewall of the first opening and a first surface of the substrate, wherein the dielectric material layer closes the top of the first opening; The dielectric material layer at the top of the first opening is etched to form a first dielectric structure on the first surface of the substrate and an insulating layer on the sidewall of the first opening, and a second opening is formed at the top of the first opening. The second opening is connected to the first opening, and the insulating layer is also located inside the second opening.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The substrate further includes a device region and a non-device region, the device region including the pixel region and the isolation region; a first electrical connection structure is formed on a first surface of the substrate, including: etching a dielectric material layer and the substrate on the non-device region; forming a second groove within the first dielectric structure and the substrate, the depth of the second groove being less than the depth of the first opening; forming a second connection layer within the second groove, the second connection layer being electrically connected to the substrate; forming a first connection layer on the first dielectric structure, the first connection layer being electrically connected to the isolation layer and the second connection layer, the first connection layer being parallel to the substrate surface, the transmittance of the first connection layer being greater than the transmittance of the isolation structure, the first connection structure including the first connection layer and the second connection layer.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The second connection layer and the isolation layer are formed simultaneously; the method for forming the second connection layer and the isolation layer includes: etching the dielectric material layer at the top of the first opening, etching the dielectric material layer and the substrate on the non-device area, forming a second groove in the first dielectric structure and the substrate; forming an isolation material layer in the first opening, the second opening, the second groove and on the first dielectric structure; planarizing the isolation material layer until the surface of the first dielectric structure is exposed, forming the isolation layer in the first opening and the second opening, and forming the second connection layer in the second groove.

21. The method for forming a semiconductor structure as described in claim 19, characterized in that, The material of the second connecting layer is the same as that of the first connecting layer.

22. The method for forming a semiconductor structure as described in claim 18, characterized in that, Before forming the isolation structure within the isolation region, the method further includes: forming a plurality of first grooves within the pixel region, wherein the first surface of the substrate exposes the tops of the plurality of first grooves, and the cross-sectional shape of the first grooves includes an "inverted pyramid" shape; the first dielectric structure is also located within the plurality of first grooves.

23. The method for forming a semiconductor structure as described in claim 18, characterized in that, After forming a photosensitive structure within the pixel region, the method further includes: forming a second dielectric structure and a second connection structure located within the second dielectric structure on a second surface of the substrate, the second connection structure being electrically connected to the photosensitive structure; providing a support substrate; forming a third dielectric structure on the support substrate; bonding the third dielectric structure to the second dielectric structure; and after bonding the third dielectric structure to the second dielectric structure, flipping the substrate to form the isolation structure within the isolation region.

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