Semiconductor device and method of manufacturing the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHAN XINXIN SEMICON MFG CO LTD
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-23
Smart Images
Figure CN122269849A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and its manufacturing method. Background Technology
[0002] How to integrate photodetectors with silicon nitride waveguides is a problem that urgently needs to be solved. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which can realize the integration of photodetectors and waveguides.
[0004] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:
[0005] An SOI substrate is provided, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a first semiconductor layer, the SOI substrate comprising a detector region and a waveguide region, wherein a first waveguide is formed in the first semiconductor layer of the waveguide region;
[0006] A first insulating dielectric layer and a second waveguide are formed, wherein the first insulating dielectric layer covers the first semiconductor layer, and the second waveguide is formed in the first insulating dielectric layer above the first waveguide;
[0007] The first insulating dielectric layer is etched to expose the first semiconductor layer of the detector region;
[0008] A second semiconductor layer is formed on the exposed first semiconductor layer;
[0009] A semiconductor absorber layer is formed on the second semiconductor layer.
[0010] Optionally, the upper surface of the semiconductor absorption layer is not lower than the upper surface of the second waveguide.
[0011] Optionally, the second waveguide is made of silicon nitride, which is deposited using LPCVD process and then annealed.
[0012] Optionally, before forming the semiconductor absorber layer on the second semiconductor layer, the method of manufacturing the semiconductor device further includes:
[0013] A first doped region and a second doped region are formed in the second semiconductor layer, the first doped region and the second doped region are spaced apart, and the doping types of the first doped region and the second doped region are opposite.
[0014] Optionally, the step of forming the semiconductor absorber layer on the second semiconductor layer includes:
[0015] A second insulating dielectric layer is formed to cover the second semiconductor layer;
[0016] The second insulating dielectric layer is etched to expose a portion of the first doped region and a portion of the second doped region;
[0017] A semiconductor absorber layer is formed on the exposed first and second doped regions and extends to the second insulating dielectric layer;
[0018] The semiconductor absorber layer above the upper surface of the second insulating dielectric layer is removed using a chemical mechanical polishing process.
[0019] Optionally, the method for manufacturing the semiconductor device further includes:
[0020] A third doped region and a fourth doped region are formed in the first doped region and the second doped region on both sides of the semiconductor absorption layer, respectively. The third doped region has the same doping type as the first doped region, and the fourth doped region has the same doping type as the second doped region. The doping concentrations of the third doped region and the fourth doped region are greater than the doping concentrations of the first doped region and the second doped region, respectively.
[0021] Optionally, the method for manufacturing the semiconductor device further includes:
[0022] A conductive plug is formed, which is used to electrically lead out the first doped region and the second doped region or the third doped region and the fourth doped region.
[0023] Optionally, the SOI substrate further includes a modulator region and a coupler region, wherein a modulator is formed in the first semiconductor layer of the modulator region and a coupler is formed in the first semiconductor layer of the coupler region.
[0024] The present invention also provides a semiconductor device, comprising:
[0025] The SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer, and a first semiconductor layer. The SOI substrate includes a detector region and a waveguide region, and a first waveguide is formed in the first semiconductor layer of the waveguide region.
[0026] A second semiconductor layer is formed on the first semiconductor layer of the detector region;
[0027] A semiconductor absorption layer is formed on the second semiconductor layer;
[0028] An insulating dielectric layer and a second waveguide, wherein the insulating dielectric layer covers the first semiconductor layer, the second semiconductor layer and the semiconductor absorption layer, and the second waveguide is formed in the insulating dielectric layer above the first waveguide.
[0029] Optionally, the upper surface of the semiconductor absorption layer is not lower than the upper surface of the second waveguide.
[0030] Optionally, the longitudinal section of the structure formed by the second semiconductor layer and the first semiconductor layer of the detector region is convex.
[0031] Optionally, the upper surface of the second semiconductor layer is located between the upper and lower surfaces of the second waveguide.
[0032] Optionally, the semiconductor device further includes:
[0033] The first doped region and the second doped region are formed in the second semiconductor layer on both sides of the semiconductor absorption layer, and the first doped region and the second doped region extend below the semiconductor absorption layer. The doping types of the first doped region and the second doped region are opposite.
[0034] Optionally, the semiconductor device further includes:
[0035] The third and fourth doped regions are formed in the first and second doped regions on both sides of the semiconductor absorption layer, respectively. The third doped region has the same doping type as the first doped region, and the fourth doped region has the same doping type as the second doped region. The doping concentrations of the third and fourth doped regions are greater than the doping concentrations of the first and second doped regions, respectively.
[0036] The semiconductor device further includes:
[0037] A conductive plug is used to electrically lead out the first doped region and the second doped region, or the third doped region and the fourth doped region.
[0038] Optionally, the SOI substrate further includes a modulator region and a coupler region, wherein a modulator is formed in the first semiconductor layer of the modulator region and a coupler is formed in the first semiconductor layer of the coupler region.
[0039] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0040] 1. A method for manufacturing a semiconductor device according to the present invention includes: providing an SOI substrate, the SOI substrate including, from bottom to top, a lower substrate, an insulating buried layer, and a first semiconductor layer, the SOI substrate including a detector region and a waveguide region, wherein a first waveguide is formed in the first semiconductor layer of the waveguide region; forming a first insulating dielectric layer and a second waveguide, the first insulating dielectric layer covering the first semiconductor layer, the second waveguide being formed in the first insulating dielectric layer above the first waveguide; etching the first insulating dielectric layer to expose the first semiconductor layer of the detector region; forming a second semiconductor layer on the exposed first semiconductor layer; and forming a semiconductor absorption layer on the second semiconductor layer. This enables the integration of a photodetector and a waveguide.
[0041] 2. The semiconductor device of the present invention includes: an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer, and a first semiconductor layer, the SOI substrate including a detector region and a waveguide region, a first waveguide formed in the first semiconductor layer of the waveguide region; a second semiconductor layer formed on the first semiconductor layer of the detector region; a semiconductor absorption layer formed on the second semiconductor layer; an insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the first semiconductor layer, the second semiconductor layer, and the semiconductor absorption layer, the second waveguide formed in the insulating dielectric layer above the first waveguide. This enables the integration of a photodetector and a waveguide. Attached Figure Description
[0042] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0043] Figures 2a to 2l yes Figure 1 A schematic diagram of a device in one embodiment of a method for manufacturing a semiconductor device is shown.
[0044] Among them, the appendix Figures 1-2 The annotations in the attached figures are explained as follows:
[0045] 101-Lower substrate; 102-Buried insulating layer; 103-First semiconductor layer; 11-First insulating dielectric layer; 111-First insulating layer; 112-Second insulating layer; 12-Second waveguide; 13-Second semiconductor layer; 131-First opening; 14-Semiconductor absorption layer; 151-First doped region; 152-Second doped region; 16-Second insulating dielectric layer; 161-Second opening; 171-Third doped region; 172-Fourth doped region; 18-Conductive plug; 181-Through hole; 19-Third insulating dielectric layer; A1-Detector region; A2-Modulator region; A3-Waveguide region; A4-Coupled region. Detailed Implementation
[0046] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its manufacturing method proposed in this invention will be further described in detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0047] An embodiment of the present invention provides a method for manufacturing a semiconductor device, see below. Figure 1 ,from Figure 1 As can be seen from the above, the method for manufacturing the semiconductor device includes:
[0048] Step S1: Provide an SOI substrate, the SOI substrate including a lower substrate, an insulating buried layer and a first semiconductor layer from bottom to top, the SOI substrate including a detector region and a waveguide region, and a first waveguide is formed in the first semiconductor layer of the waveguide region;
[0049] Step S2: A first insulating dielectric layer and a second waveguide are formed, wherein the first insulating dielectric layer covers the first semiconductor layer, and the second waveguide is formed in the first insulating dielectric layer above the first waveguide;
[0050] Step S3: Etch the first insulating dielectric layer to expose the first semiconductor layer of the detector region;
[0051] Step S4: Form a second semiconductor layer on the exposed first semiconductor layer;
[0052] Step S5: Form a semiconductor absorber layer on the second semiconductor layer.
[0053] See below. Figures 2a to 2l The manufacturing method of the semiconductor device provided in this embodiment will be described in detail. Figures 2a to 2l This is a schematic diagram of a longitudinal cross-section.
[0054] Follow step S1, refer to Figure 2a and Figure 2b An SOI (Semiconductor-On-Insulator) substrate is provided, the SOI substrate comprising, from bottom to top, a lower substrate 101, an insulating buried layer 102 and a first semiconductor layer 103, the SOI substrate comprising a detector region A1 and a waveguide region A3, wherein a first waveguide is formed in the first semiconductor layer 103 of the waveguide region A3.
[0055] The detector region A1 is used to form a photodetector, and the waveguide region A3 is used to form a waveguide.
[0056] The first semiconductor layer 103 can be made of semiconductor materials such as silicon.
[0057] In one embodiment, such as Figure 2a and Figure 2b As shown, the SOI substrate may further include a modulator region A2 and a coupler region A4. A modulator is formed in the first semiconductor layer 103 of the modulator region A2, and a coupler is formed in the first semiconductor layer 103 of the coupler region A4.
[0058] In one embodiment, the photodetector and the modulator are active devices, and the first waveguide and the coupler are passive devices.
[0059] It should be noted that the first semiconductor layer 103 may include not only modulators and couplers, but also other active and / or passive devices.
[0060] In the provided Figure 2a In one embodiment of the SOI substrate shown, the upper surfaces of the first semiconductor layer 103, comprising the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4, are flush; the first semiconductor layer 103 is patterned by etching, such as... Figure 2b As shown, the first semiconductor layers 103 of the detector region A1, modulator region A2, waveguide region A3, and coupler region A4 are spaced apart, forming the first waveguide, the modulator, and the coupler. Furthermore, the surfaces of the highest points of the first semiconductor layers 103 of the detector region A1, modulator region A2, waveguide region A3, and coupler region A4 are flush after patterning. In one embodiment, after patterning, the first semiconductor layers 103 of the detector region A1, modulator region A2, waveguide region A3, and coupler region A4 are interconnected and / or coupled at other locations, enabling optical signals to be transmitted among the first semiconductor layers 103 of the detector region A1, modulator region A2, waveguide region A3, and coupler region A4.
[0061] The type of the first waveguide is not limited; for example, it can be a ridge waveguide (such as...). Figure 2b As shown, the longitudinal section of a ridge waveguide is convex, and a strip waveguide (such as...) Figure 2b As shown, the longitudinal section of the strip waveguide is rectangular, the groove waveguide is rectangular, and the grating waveguide is at least one of the following:
[0062] The type of modulator is not limited; for example, the longitudinal section of the modulator can be a shape with two grooves (e.g., Figure 2b (as shown) or convex shapes, etc.
[0063] The type of coupler is not limited; for example, the coupler can be... Figure 2bThe grating coupler shown is an example.
[0064] According to step S2, a first insulating dielectric layer 11 and a second waveguide 12 are formed. The first insulating dielectric layer 11 covers the first semiconductor layer 103, and the second waveguide 12 is formed in the first insulating dielectric layer 11 above the first waveguide.
[0065] The first insulating dielectric layer 11 also covers the gap between the patterned detector region A1, the modulator region A2, the waveguide region A3 and the coupler region A4, and the first semiconductor layer 103.
[0066] The first insulating dielectric layer 11 covers the first semiconductor layer 103, which enables the first insulating dielectric layer 11 and the insulating buried layer 102 to wrap the first semiconductor layer 103, thereby preventing the optical signal from leaking out of the first semiconductor layer 103.
[0067] In one embodiment, the step of forming the first insulating dielectric layer 11 and the second waveguide 12 may include: as follows Figure 2b As shown, a first insulating layer 111 is formed to cover the patterned first semiconductor layer 103 and the gap between the first semiconductor layer 103 and the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4; then, as Figure 2c As shown, a waveguide material layer is formed on the first insulating layer 111, and a second waveguide 12 is formed above the first waveguide after etching the waveguide material layer; then, a second insulating layer 112 is formed on the first insulating layer 111, and the second insulating layer 112 covers the first insulating layer 111 and the second waveguide 12; the first insulating layer 111 and the second insulating layer 112 constitute the first insulating dielectric layer 11.
[0068] In other embodiments, other methods can be used to form the first insulating dielectric layer 11 and the second waveguide 12. For example, the first insulating layer 111 can be formed first to cover the patterned first semiconductor layer 103 and the gap between the first semiconductor layer 103 of the detector region A1, the modulator region A2, the waveguide region A3 and the coupler region A4. Then, the first insulating layer 111 above the first waveguide is etched to form a groove, and the groove is filled with waveguide material to form the second waveguide 12. Then, the second insulating layer 112 is formed to cover the first insulating layer 111 and the second waveguide 12.
[0069] Preferably, the second waveguide 12 is formed inside the first insulating dielectric layer 11 above the first waveguide, that is, the first insulating dielectric layer 11 does not expose the second waveguide 12, so that the first insulating dielectric layer 11 can protect the second waveguide 12 in subsequent processes and avoid damage to the second waveguide 12.
[0070] The first insulating dielectric layer 11 can be made of insulating materials such as silicon oxide.
[0071] The second waveguide 12 is formed above the first waveguide, and optical signals can be transmitted between the second waveguide 12 and the first waveguide.
[0072] The transmission loss of the second waveguide 12 for optical signals is less than that of the first waveguide. The second waveguide 12 is preferably made of silicon nitride.
[0073] When the second waveguide 12 is made of silicon nitride, it is preferable to use LPCVD (Low Pressure Chemical Vapor Deposition) process to deposit the silicon nitride and then anneal the silicon nitride.
[0074] In one embodiment, the process temperature for depositing the silicon nitride can be greater than 600°C, and the process temperature for annealing can be greater than 1000°C.
[0075] Compared to the deposition of silicon nitride using PECVD (Plasma Enhanced Chemical Vapor Deposition), the silicon nitride deposition process using LPCVD in this embodiment has a higher process temperature, and there is also an annealing process with a higher process temperature after deposition, which results in better quality silicon nitride (e.g., higher density), fewer defects in silicon nitride, and thus less loss when optical signals are transmitted in silicon nitride.
[0076] Since the second waveguide 12, made of silicon nitride, is formed using LPCVD and annealing processes before the subsequent formation of the semiconductor absorption layer 14, it is possible to avoid damage to the semiconductor absorption layer 14 due to excessively high process temperatures.
[0077] The second waveguide 12 is spaced apart from the first waveguide by a certain distance; in one embodiment, the distance between the second waveguide 12 and the first waveguide can be...
[0078] In one embodiment, the height of the second waveguide 12 can be
[0079] Follow step S3, see [link / reference] Figure 2d The first insulating dielectric layer 11 is etched to expose the first semiconductor layer 103 of the detector region A1.
[0080] like Figure 2d As shown, considering the precision of photolithography, when performing the photolithography process to form a patterned photoresist layer, and using the patterned photoresist layer as a mask to etch the first insulating dielectric layer 11 to form a first opening 131 that exposes the first semiconductor layer 103 of the detector region A1, preferably, the first opening 131 exposes the first semiconductor layer 103 in the middle region of the detector region A1, and the first opening 131 does not expose the first semiconductor layer 103 in the edge region of the detector region A1, so as to prevent the first opening 131 from shifting due to photolithography, thereby exposing the peripheral region of the first semiconductor layer 103 of the detector region A1.
[0081] Follow step S4, see Figure 2e A second semiconductor layer 13 is formed on the exposed first semiconductor layer 103.
[0082] The second semiconductor layer 13 can elevate the subsequently formed semiconductor absorption layer 14, optimize the overall structure, and provide greater redundancy for subsequent device structures.
[0083] If the first opening 131 exposes the first semiconductor layer 103 in the middle region of the detector region A1, the longitudinal section of the structure formed by the second semiconductor layer 13 and the first semiconductor layer 103 of the detector region A1 is convex.
[0084] In one embodiment, the upper surface of the second semiconductor layer 13 is located between the upper and lower surfaces of the second waveguide 12. This prevents the height of the second semiconductor layer 13 from being too low, which would necessitate a very high height for the subsequently formed semiconductor absorption layer 14 to ensure that the upper surface of the semiconductor absorption layer 14 is not lower than the upper surface of the second waveguide 12. This, in turn, prevents the semiconductor absorption layer 14 from being too high, which would reduce the detector bandwidth. The height of the second semiconductor layer 13 can, for example, be greater than or equal to...
[0085] The second semiconductor layer 13 can be made of semiconductor materials such as silicon.
[0086] Follow step S5, see [link / reference] Figure 2j A semiconductor absorption layer 14 is formed on the second semiconductor layer 13.
[0087] In one embodiment, the upper surface of the semiconductor absorption layer 14 is not lower than the upper surface of the second waveguide 12.
[0088] Preferably, the semiconductor absorber layer 14 can be made of Ge, InGaAs, or InGaAsP, etc.; in other embodiments, the semiconductor absorber layer 14 can be made of Si, GeAs, or InP, etc.
[0089] In one embodiment, the semiconductor absorption layer 14 is undoped, that is, the semiconductor absorption layer 14 is in an intrinsic state.
[0090] The height of the semiconductor absorption layer 14 needs to be controlled within a certain range to avoid excessively high heights that would result in an excessively long path for the optical signal during transmission within it, thereby preventing excessively long transmission times and frequency reduction, and ultimately reducing the bandwidth of the detector. In one embodiment, the height of the semiconductor absorption layer 14 can be located at...
[0091] In one embodiment, before forming the semiconductor absorber layer 14 on the second semiconductor layer 13, the method of manufacturing the semiconductor device further includes: as follows Figure 2f As shown, a first doped region 151 and a second doped region 152 are formed in the second semiconductor layer 13. The first doped region 151 and the second doped region 152 are arranged at intervals, and the doping types of the first doped region 151 and the second doped region 152 are opposite.
[0092] In one embodiment, the step of forming the semiconductor absorber layer 14 on the second semiconductor layer 13 includes: as follows Figure 2g As shown, a second insulating dielectric layer 16 is formed to cover the second semiconductor layer 13, and the second insulating dielectric layer 16 at least fills the first opening 131; then, as Figure 2h As shown, the second insulating dielectric layer 16 is etched to form a second opening 161. In one embodiment, the second opening 161 exposes a portion of the first doped region 151 and a portion of the second doped region 152, and exposes the second semiconductor layer 13 between the first doped region 151 and the second doped region 152; then, as... Figure 2i As shown, a semiconductor absorber layer 14 is formed on the exposed first doped region 151 and second doped region 152 and extends onto the second insulating dielectric layer 16, i.e., the semiconductor absorber layer 14 fills the second opening 161; then, as Figure 2j As shown, the semiconductor absorption layer 14 above the upper surface of the second insulating dielectric layer 16 is removed by chemical mechanical polishing, while the semiconductor absorption layer 14 in the second opening 161 is retained.
[0093] In one embodiment, if the upper surface of the semiconductor absorption layer 14 is lower than the upper surface of the second waveguide 12, the second waveguide 12 will also be ground when the semiconductor absorption layer 14, which is higher than the upper surface of the second insulating dielectric layer 16, is removed by chemical mechanical polishing, resulting in damage to the second waveguide 12. Therefore, by defining that the upper surface of the semiconductor absorption layer 14 is not lower than the upper surface of the second waveguide 12, damage to the second waveguide 12 can be avoided when grinding the semiconductor absorption layer 14.
[0094] In one embodiment, the method of manufacturing the semiconductor device further includes:
[0095] like Figure 2k As shown, a third insulating dielectric layer 19 is formed on the first insulating dielectric layer 11, the second insulating dielectric layer 16, and the semiconductor absorber layer 14; then, the third insulating dielectric layer 19 and the second insulating dielectric layer 16 are etched to form vias 181 that expose the first doped region 151 and the second doped region 152 on both sides of the semiconductor absorber layer 14; then, an ion implantation process is performed to form a third doped region 171 and a fourth doped region 172 in the first doped region 151 and the second doped region 152 on both sides of the semiconductor absorber layer 14, respectively. The third doped region 171 has the same doping type as the first doped region 151, and the fourth doped region 172 has the same doping type as the second doped region 152. The doping concentrations of the third doped region 171 and the fourth doped region 172 are greater than the doping concentrations of the first doped region 151 and the second doped region 152, respectively.
[0096] like Figure 2l As shown, conductive material is filled into the through-hole 181 to form conductive plugs 18 in the second insulating dielectric layer 16 and the third insulating dielectric layer 19 on the third doped region 171 and the fourth doped region 172.
[0097] The third doped region 171 is formed in the first doped region 151, and the fourth doped region 172 is formed in the second doped region 152, so that the third doped region 171 is in full contact with the first doped region 151, and the fourth doped region 172 is in full contact with the second doped region 152, ensuring that the first doped region 151 and the second doped region 152 can be electrically connected through the third doped region 171 and the fourth doped region 172, respectively.
[0098] In other embodiments, the third doped region 171 may not be formed in the first doped region 151, and the fourth doped region 172 may not be formed in the second doped region 152. That is, the first doped region 151 and the second doped region 152 are located below the semiconductor absorption layer 14, and the third doped region 171 and the fourth doped region 172 are respectively formed in the second semiconductor layer 13 on both sides of the semiconductor absorption layer 14. The third doped region 171 is connected to the first doped region 151, and the fourth doped region 172 is connected to the second doped region 152, so that the first doped region 151 and the second doped region 152 can be electrically connected through the third doped region 171 and the fourth doped region 172, respectively. In this embodiment, the steps of forming the first doped region 151, the second doped region 152, the third doped region 171, and the fourth doped region 172 may include: after forming the second semiconductor layer 13, forming a second insulating dielectric layer 16 to cover the second semiconductor layer 13, the second insulating dielectric layer 16 at least filling the first opening 131; then, etching the second insulating dielectric layer 16 to form a second opening 161, the second opening 161 exposing a portion of the second semiconductor layer 13; then, forming the first doped region 151 and the second doped region 152 in the exposed second semiconductor layer 13, the first doped region 151 and the second doped region 152 being spaced apart. The process involves setting up a semiconductor absorber layer 14 in the second opening 161, then forming a third insulating dielectric layer 19 on the first insulating dielectric layer 11, the second insulating dielectric layer 16, and the semiconductor absorber layer 14; then etching the third insulating dielectric layer 19 and the second insulating dielectric layer 16 to form vias 181 exposing the second semiconductor layers 13 on both sides of the semiconductor absorber layer 14; then performing ion implantation and annealing processes to form a third doped region 171 and a fourth doped region 172 in the second semiconductor layers 13 on both sides of the semiconductor absorber layer 14; and finally filling the vias 181 with conductive material to form conductive plugs 18.
[0099] The conductive plug 18 is used to electrically lead out the first doped region 151 and the second doped region 152 or the third doped region 171 and the fourth doped region 172.
[0100] In one embodiment, prior to forming the conductive plug 18, a metal silicide layer (not shown) may be formed on the surfaces of the third doped region 171 and the fourth doped region 172 to reduce the contact resistance between the third doped region 171 and the fourth doped region 172 and the conductive plug 18, respectively.
[0101] When the first doped region 151 and the third doped region 171 are P-type doped and the second doped region 152 and the fourth doped region 172 are N-type doped, the first doped region 151, the semiconductor absorption layer 14, and the second doped region 152 form a horizontal PIN junction; when the first doped region 151 and the third doped region 171 are N-type doped and the second doped region 152 and the fourth doped region 172 are P-type doped, the first doped region 151, the semiconductor absorption layer 14, and the second doped region 152 form a horizontal NIP junction.
[0102] As can be seen from the above, by forming the second semiconductor layer 13 on the first semiconductor layer 103 in the detector region A1, the height of the semiconductor layer (including the first semiconductor layer 103 and the second semiconductor layer 13) in the detector region A1 is higher than the height of the semiconductor layer (including the first semiconductor layer 103) in the waveguide region A3. Furthermore, the upper surface of the semiconductor absorption layer 14 on the semiconductor layer of the detector region A1 after chemical mechanical polishing is not lower than the upper surface of the second waveguide 12. This allows the height of the semiconductor absorption layer 14 to be controlled within a certain range (e.g., the height is located at...). This not only improves the bandwidth of the photodetector, but also allows for the fabrication of a low-loss second waveguide 12 using a higher process temperature before forming the semiconductor absorption layer 14 (e.g., using LPCVD and annealing processes to form a second waveguide 12 made of silicon nitride), thereby enabling the high-bandwidth photodetector and the low-loss second waveguide 12 to be integrated into the same process.
[0103] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer, and a first semiconductor layer, the SOI substrate comprising a detector region and a waveguide region, wherein a first waveguide is formed in the first semiconductor layer of the waveguide region; forming a first insulating dielectric layer and a second waveguide, the first insulating dielectric layer covering the first semiconductor layer, the second waveguide being formed in the first insulating dielectric layer above the first waveguide; etching the first insulating dielectric layer to expose the first semiconductor layer of the detector region; forming a second semiconductor layer on the exposed first semiconductor layer; and forming a semiconductor absorption layer on the second semiconductor layer. The semiconductor device manufacturing method provided by the present invention enables the integration of a photodetector and a waveguide.
[0104] An embodiment of the present invention provides a semiconductor device, comprising: an SOI substrate, the SOI substrate including, from bottom to top, a lower substrate, an insulating buried layer, and a first semiconductor layer, the SOI substrate including a detector region and a waveguide region, a first waveguide being formed in the first semiconductor layer of the waveguide region; a second semiconductor layer formed on the first semiconductor layer of the detector region; a semiconductor absorption layer formed on the second semiconductor layer; an insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the first semiconductor layer, the second semiconductor layer, and the semiconductor absorption layer, the second waveguide being formed in the insulating dielectric layer above the first waveguide.
[0105] See below. Figure 2l The semiconductor device provided in this embodiment is described in detail.
[0106] The SOI (Semiconductor-On-Insulator) substrate includes a lower substrate 101, an insulating buried layer 102, and a first semiconductor layer 103 from bottom to top. The SOI substrate includes a detector region A1 and a waveguide region A3, and a first waveguide is formed in the first semiconductor layer 103 of the waveguide region A3.
[0107] The detector region A1 is used to form a photodetector, and the waveguide region A3 is used to form a waveguide.
[0108] The first semiconductor layer 103 can be made of semiconductor materials such as silicon.
[0109] In one embodiment, such as Figure 2l As shown, the SOI substrate may further include a modulator region A2 and a coupler region A4. A modulator is formed in the first semiconductor layer 103 of the modulator region A2, and a coupler is formed in the first semiconductor layer 103 of the coupler region A4.
[0110] In one embodiment, the photodetector and the modulator are active devices, and the first waveguide and the coupler are passive devices.
[0111] It should be noted that the first semiconductor layer 103 may include not only modulators and couplers, but also other active and / or passive devices.
[0112] In one embodiment, the first semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4 are spaced apart, and / or the surfaces of the highest points of the first semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4 are flush. In another embodiment, the first semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4 are interconnected and / or coupled at other locations, enabling optical signals to be transmitted among the first semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4.
[0113] The type of the first waveguide is not limited; for example, it can be a ridge waveguide (such as...). Figure 2l As shown, the longitudinal section of a ridge waveguide is convex, and a strip waveguide (such as...) Figure 2l As shown, the longitudinal section of the strip waveguide is rectangular, the groove waveguide is rectangular, and the grating waveguide is at least one of the following:
[0114] The type of modulator is not limited; for example, the longitudinal section of the modulator can be a shape with two grooves (e.g., Figure 2l (as shown) or convex shapes, etc.
[0115] The type of coupler is not limited; for example, the coupler can be... Figure 2l The grating coupler shown is an example.
[0116] The second semiconductor layer 13 is formed on the first semiconductor layer 103 of the detector region A1.
[0117] The second semiconductor layer 13 can elevate the subsequently formed semiconductor absorption layer 14, optimize the overall structure, and provide greater redundancy for subsequent device structures.
[0118] Preferably, the second semiconductor layer 13 is formed on the middle region of the first semiconductor layer 103 in the detector region A1, such that the longitudinal section of the structure formed by the second semiconductor layer 13 and the first semiconductor layer 103 in the detector region A1 is convex, in order to avoid the opening where the second semiconductor layer 13 is formed (i.e., Figure 2d When the first opening 131 in the detector region is opened, the photolithography is offset due to the problem of photolithography precision, thereby avoiding the second semiconductor layer 13 from being offset to the peripheral area of the first semiconductor layer 103 of the detector region A1.
[0119] The semiconductor absorption layer 14 is formed on the second semiconductor layer 13.
[0120] Preferably, the semiconductor absorber layer 14 can be made of Ge, InGaAs, or InGaAsP, etc.; in other embodiments, the semiconductor absorber layer 14 can be made of Si, GeAs, or InP, etc.
[0121] In one embodiment, the semiconductor absorption layer 14 is undoped, that is, the semiconductor absorption layer 14 is in an intrinsic state.
[0122] The height of the semiconductor absorption layer 14 needs to be controlled within a certain range to avoid excessively high heights that would result in an excessively long path for the optical signal during transmission within it, thereby preventing excessively long transmission times and frequency reduction, and ultimately reducing the bandwidth of the detector. In one embodiment, the height of the semiconductor absorption layer 14 can be located at...
[0123] The insulating dielectric layer covers the first semiconductor layer 103, the second semiconductor layer 13, and the semiconductor absorption layer 14, and the second waveguide 12 is formed in the insulating dielectric layer above the first waveguide.
[0124] In one embodiment, the upper surface of the semiconductor absorption layer 14 is not lower than the upper surface of the second waveguide 12.
[0125] The insulating dielectric layer also covers the gap between the first semiconductor layer 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4.
[0126] The insulating dielectric layer covers the first semiconductor layer 103, which enables the insulating dielectric layer and the insulating buried layer 102 to encapsulate the first semiconductor layer 103, thereby preventing optical signals from leaking out of the first semiconductor layer 103.
[0127] The insulating dielectric layer may include a multilayer structure. Figure 2lIn the illustrated embodiment, the insulating dielectric layer includes a first insulating dielectric layer 11, a second insulating dielectric layer 16, and a third insulating dielectric layer 19. The first insulating dielectric layer 11 includes a stacked first insulating layer 111 and a second insulating layer 112. The first insulating layer 111 covers the first semiconductor layer 103 and the gap between the first semiconductor layer 103 and the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4. The second waveguide 12 is formed on the first insulating layer 111 above the first waveguide, and the second insulating layer 112 covers the second waveguide 12. The second semiconductor layer 13 is formed in the first insulating dielectric layer 11 on the first semiconductor layer 103 in the detector region A1. The second insulating dielectric layer 16 is formed on the second semiconductor layer 13. The semiconductor absorption layer 14 is formed in the second insulating dielectric layer 16 on the second semiconductor layer 13. The third insulating dielectric layer 19 covers the first insulating dielectric layer 11, the second insulating dielectric layer 16, and the semiconductor absorption layer 14. It should be noted that the composition of the insulating dielectric layer is not limited to... Figure 2l The example shown.
[0128] If the upper surface of the semiconductor absorption layer 14 is lower than the upper surface of the second waveguide 12, the second waveguide 12 will also be ground when the semiconductor absorption layer 14, which is higher than the upper surface of the second insulating dielectric layer 16, is removed by chemical mechanical polishing, resulting in damage to the second waveguide 12. Therefore, by defining that the upper surface of the semiconductor absorption layer 14 is not lower than the upper surface of the second waveguide 12, damage to the second waveguide 12 can be avoided when grinding the semiconductor absorption layer 14.
[0129] The insulating dielectric layer can be made of insulating materials such as silicon oxide.
[0130] The second waveguide 12 is formed above the first waveguide, and optical signals can be transmitted between the second waveguide 12 and the first waveguide.
[0131] The transmission loss of the second waveguide 12 for optical signals is less than that of the first waveguide. The second waveguide 12 is preferably made of silicon nitride.
[0132] When the second waveguide 12 is made of silicon nitride, it is preferable to use LPCVD (Low Pressure Chemical Vapor Deposition) process to deposit the silicon nitride and then anneal the silicon nitride.
[0133] In one embodiment, the process temperature for depositing the silicon nitride can be greater than 600°C, and the process temperature for annealing can be greater than 1000°C.
[0134] Compared to the deposition of silicon nitride using PECVD (Plasma Enhanced Chemical Vapor Deposition), the silicon nitride deposition process using LPCVD in this embodiment has a higher process temperature, and there is also an annealing process with a higher process temperature after deposition, which results in better quality silicon nitride (e.g., higher density), fewer defects in silicon nitride, and thus less loss when optical signals are transmitted in silicon nitride.
[0135] The second waveguide 12, made of silicon nitride, can be formed using LPCVD and annealing processes before the semiconductor absorption layer 14 is formed, thus avoiding damage to the semiconductor absorption layer 14 due to excessively high process temperatures.
[0136] The second waveguide 12 is spaced apart from the first waveguide by a certain distance; in one embodiment, the distance between the second waveguide 12 and the first waveguide can be...
[0137] In one embodiment, the height of the second waveguide 12 can be
[0138] In one embodiment, the upper surface of the second semiconductor layer 13 is located between the upper and lower surfaces of the second waveguide 12. This prevents the height of the second semiconductor layer 13 from being too low, which would necessitate a very high height for the semiconductor absorption layer 14 to ensure that its upper surface is not lower than the upper surface of the second waveguide 12. This, in turn, prevents the semiconductor absorption layer 14 from being too high, which would reduce the detector bandwidth. The height of the second semiconductor layer 13 can, for example, be greater than or equal to...
[0139] The second semiconductor layer 13 can be made of semiconductor materials such as silicon.
[0140] In one embodiment, the semiconductor device further includes a first doped region 151 and a second doped region 152 formed in the second semiconductor layer 13 on both sides of the semiconductor absorption layer 14, and the first doped region 151 and the second doped region 152 extend below the semiconductor absorption layer 14, wherein the doping types of the first doped region 151 and the second doped region 152 are opposite.
[0141] In one embodiment, the semiconductor device further includes:
[0142] The third doped region 171 and the fourth doped region 172 are formed in the first doped region 151 and the second doped region 152 on both sides of the semiconductor absorption layer 14, respectively. The third doped region 171 has the same doping type as the first doped region 151, and the fourth doped region 172 has the same doping type as the second doped region 152. The doping concentrations of the third doped region 171 and the fourth doped region 172 are greater than the doping concentrations of the first doped region 151 and the second doped region 152, respectively.
[0143] Conductive plugs 18 are formed in the insulating dielectric layer on the third doped region 171 and the fourth doped region 172.
[0144] The third doped region 171 is formed in the first doped region 151, and the fourth doped region 172 is formed in the second doped region 152, so that the third doped region 171 is in full contact with the first doped region 151, and the fourth doped region 172 is in full contact with the second doped region 152, so that the first doped region 151 and the second doped region 152 can be electrically connected through the third doped region 171 and the fourth doped region 172, respectively.
[0145] In other embodiments, the third doped region 171 may not be formed in the first doped region 151, and the fourth doped region 172 may not be formed in the second doped region 152. That is, the first doped region 151 and the second doped region 152 are located below the semiconductor absorption layer 14, and the third doped region 171 and the fourth doped region 172 are respectively formed in the second semiconductor layer 13 on both sides of the semiconductor absorption layer 14. The third doped region 171 is connected to the first doped region 151, and the fourth doped region 172 is connected to the second doped region 152, so that the first doped region 151 and the second doped region 152 can be electrically connected through the third doped region 171 and the fourth doped region 172, respectively.
[0146] The conductive plug 18 is used to electrically lead out the first doped region 151 and the second doped region 152 or the third doped region 171 and the fourth doped region 172.
[0147] In one embodiment, a metal silicide layer (not shown) may be formed between the third doped region 171 and the fourth doped region 172 and the conductive plug 18, respectively, to reduce the contact resistance between the third doped region 171 and the fourth doped region 172 and the conductive plug 18, respectively.
[0148] When the first doped region 151 and the third doped region 171 are P-type doped and the second doped region 152 and the fourth doped region 172 are N-type doped, the first doped region 151, the semiconductor absorption layer 14, and the second doped region 152 form a horizontal PIN junction; when the first doped region 151 and the third doped region 171 are N-type doped and the second doped region 152 and the fourth doped region 172 are P-type doped, the first doped region 151, the semiconductor absorption layer 14, and the second doped region 152 form a horizontal NIP junction.
[0149] As can be seen from the above, because the second semiconductor layer 13 is formed on the first semiconductor layer 103 of the detector region A1, the height of the semiconductor layer (including the first semiconductor layer 103 and the second semiconductor layer 13) of the detector region A1 is higher than the height of the semiconductor layer (including the first semiconductor layer 103) of the waveguide region A3. Furthermore, the upper surface of the semiconductor absorption layer 14 on the semiconductor layer of the detector region A1 is not lower than the upper surface of the second waveguide 12. This allows the height of the semiconductor absorption layer 14 to be controlled within a certain range (e.g., the height is located at...). This not only improves the bandwidth of the photodetector, but also allows for the fabrication of a low-loss second waveguide 12 using a higher process temperature before forming the semiconductor absorption layer 14 (e.g., using LPCVD and annealing processes to form a second waveguide 12 made of silicon nitride), thereby enabling the high-bandwidth photodetector and the low-loss second waveguide 12 to be integrated into the same process.
[0150] In summary, this invention provides a semiconductor device comprising: an SOI substrate, the SOI substrate including, from bottom to top, a lower substrate, an insulating buried layer, and a first semiconductor layer; the SOI substrate including a detector region and a waveguide region, wherein a first waveguide is formed in the first semiconductor layer of the waveguide region; a second semiconductor layer formed on the first semiconductor layer of the detector region; a semiconductor absorption layer formed on the second semiconductor layer; an insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the first semiconductor layer, the second semiconductor layer, and the semiconductor absorption layer, the second waveguide being formed in the insulating dielectric layer above the first waveguide. The semiconductor device provided by this invention enables the integration of a high-bandwidth photodetector with a low-loss waveguide.
[0151] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: An SOI substrate is provided, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a first semiconductor layer, the SOI substrate comprising a detector region and a waveguide region, wherein a first waveguide is formed in the first semiconductor layer of the waveguide region; A first insulating dielectric layer and a second waveguide are formed, wherein the first insulating dielectric layer covers the first semiconductor layer, and the second waveguide is formed in the first insulating dielectric layer above the first waveguide; The first insulating dielectric layer is etched to expose the first semiconductor layer of the detector region; A second semiconductor layer is formed on the exposed first semiconductor layer; A semiconductor absorber layer is formed on the second semiconductor layer.
2. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The upper surface of the semiconductor absorption layer is not lower than the upper surface of the second waveguide.
3. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The second waveguide is made of silicon nitride, which is deposited using LPCVD process and then annealed.
4. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, Before forming the semiconductor absorber layer on the second semiconductor layer, the method of manufacturing the semiconductor device further includes: A first doped region and a second doped region are formed in the second semiconductor layer, the first doped region and the second doped region are spaced apart, and the doping types of the first doped region and the second doped region are opposite.
5. The method for manufacturing a semiconductor device as claimed in claim 4, characterized in that, The step of forming the semiconductor absorber layer on the second semiconductor layer includes: A second insulating dielectric layer is formed to cover the second semiconductor layer; The second insulating dielectric layer is etched to expose a portion of the first doped region and a portion of the second doped region; A semiconductor absorber layer is formed on the exposed first and second doped regions and extends to the second insulating dielectric layer; The semiconductor absorber layer above the upper surface of the second insulating dielectric layer is removed using a chemical mechanical polishing process.
6. The method for manufacturing a semiconductor device as claimed in claim 5, characterized in that, The method for manufacturing the semiconductor device further includes: A third doped region and a fourth doped region are formed in the first doped region and the second doped region on both sides of the semiconductor absorption layer, respectively. The third doped region has the same doping type as the first doped region, and the fourth doped region has the same doping type as the second doped region. The doping concentrations of the third doped region and the fourth doped region are greater than the doping concentrations of the first doped region and the second doped region, respectively.
7. The method of manufacturing a semiconductor device as described in claim 4 or 6, characterized in that, The method for manufacturing the semiconductor device further includes: A conductive plug is formed, which is used to electrically lead out the first doped region and the second doped region or the third doped region and the fourth doped region.
8. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The SOI substrate further includes a modulator region and a coupler region. A modulator is formed in the first semiconductor layer of the modulator region, and a coupler is formed in the first semiconductor layer of the coupler region.
9. A semiconductor device, characterized in that, include: The SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer, and a first semiconductor layer. The SOI substrate includes a detector region and a waveguide region, and a first waveguide is formed in the first semiconductor layer of the waveguide region. A second semiconductor layer is formed on the first semiconductor layer of the detector region; A semiconductor absorption layer is formed on the second semiconductor layer; An insulating dielectric layer and a second waveguide, wherein the insulating dielectric layer covers the first semiconductor layer, the second semiconductor layer and the semiconductor absorption layer, and the second waveguide is formed in the insulating dielectric layer above the first waveguide.
10. The semiconductor device as claimed in claim 9, characterized in that, The upper surface of the semiconductor absorption layer is not lower than the upper surface of the second waveguide.
11. The semiconductor device as claimed in claim 9, characterized in that, The longitudinal section of the structure formed by the second semiconductor layer and the first semiconductor layer in the detector region is convex.
12. The semiconductor device as claimed in claim 9, characterized in that, The upper surface of the second semiconductor layer is located between the upper and lower surfaces of the second waveguide.
13. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device further includes: The first doped region and the second doped region are formed in the second semiconductor layer on both sides of the semiconductor absorption layer, and the first doped region and the second doped region extend below the semiconductor absorption layer. The doping types of the first doped region and the second doped region are opposite.
14. The semiconductor device as claimed in claim 13, characterized in that, The semiconductor device further includes: The third and fourth doped regions are formed in the first and second doped regions on both sides of the semiconductor absorption layer, respectively. The third doped region has the same doping type as the first doped region, and the fourth doped region has the same doping type as the second doped region. The doping concentrations of the third and fourth doped regions are greater than the doping concentrations of the first and second doped regions, respectively.
15. The semiconductor device as claimed in claim 13 or 14, characterized in that, The semiconductor device further includes: A conductive plug is used to electrically lead out the first doped region and the second doped region, or the third doped region and the fourth doped region.
16. The semiconductor device as claimed in claim 9, characterized in that, The SOI substrate further includes a modulator region and a coupler region. A modulator is formed in the first semiconductor layer of the modulator region, and a coupler is formed in the first semiconductor layer of the coupler region.