Method of manufacturing a reconstituted wafer, large size reconstituted wafer and bonded structure

Abstract

The present application belongs to the technical field of semiconductor device processing and manufacturing, and relates to a manufacturing method of a reconstructed wafer, a large-size reconstructed wafer manufactured by the method and a bonding structure comprising the wafer. The method comprises the following steps: providing a donor wafer, cutting the donor wafer into multiple sub-pieces along the thickness direction; providing a support wafer with a larger size, bonding the multiple sub-pieces to the surface of a temporary bonding layer of the support wafer, and performing a planarization treatment on the surface to ensure the flatness of the whole surface; providing a transfer wafer with a size greater than or equal to that of the support wafer, bonding one side of the sub-pieces of the support wafer to the transfer wafer; separating the sub-pieces from the temporary bonding layer by debonding and transferring the sub-pieces to the transfer wafer; bonding the transfer wafer to a receiver wafer, transferring the film layer to the receiver wafer, and finally obtaining a high-quality reconstructed wafer. The large-size reconstructed wafer has a performance comparable to that of a whole bonding wafer, and can be directly used for re-encapsulation bonding with a single device or a whole wafer.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device processing and manufacturing technology, specifically relating to a method for manufacturing a reconstructed wafer, a large-size reconstructed wafer obtained by the method, and a bonding structure containing the reconstructed wafer. Background Technology

[0002] Currently, the global semiconductor industry has entered a stage of large-scale development, with large-size wafers becoming the mainstream trend due to their higher integration and lower unit manufacturing costs. Limited by the intrinsic properties of materials, silicon, silicon oxide, and silicon photonics can be used to fabricate large-size wafers such as 12 inches; however, compound semiconductor materials such as lithium niobate, indium phosphide, and gallium arsenide are difficult to fabricate into large-size single crystals, resulting in limited size of composite wafers based on these materials, which cannot meet the demand for larger wafers. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention aims to provide a method for manufacturing reconstructed wafers, enabling the fabrication of large-size reconstructed wafers. The large-size reconstructed wafers produced by this invention possess performance comparable to solid-bonded wafers and can be directly used for repackaging and bonding with individual devices or entire wafers.

[0004] To achieve this objective, the present invention adopts the following technical solution:

[0005] A method for manufacturing a reconstructed wafer includes: providing a donor wafer, cutting the donor wafer into multiple sub-wafers along the thickness direction, or directly providing multiple sub-wafers, wherein the multiple sub-wafers provided are also pre-cut from a material equivalent to the donor wafer;

[0006] Provide support wafers;

[0007] The multiple sub-pieces are temporarily bonded to the surface of the supporting wafer;

[0008] The multiple sub-wafers temporarily bonded to the support wafer are planarized to make the surface flat;

[0009] A transit wafer is provided to be temporarily bonded to the sub-wafer side of the supporting wafer using a first bonding method;

[0010] Perform debonding to detach the multiple sub-wafers from the support wafer and transfer them to the transfer wafer;

[0011] An ion implantation process is performed to form ion implantation layers in the plurality of sub-sheets, the ion implantation layers separating the sub-sheets into film layers and remaining proton sub-sheets;

[0012] A acceptor wafer is provided, and the film layer side of the intermediate wafer is bonded to the acceptor wafer using a second bonding method;

[0013] A heat treatment is performed to crack the ion implantation layer, and the film is transferred to the acceptor wafer to obtain a reconstructed wafer.

[0014] Preferably, the sub-wafer and the supporting wafer are temporarily bonded together by a temporary bonding layer;

[0015] The temporary bonding layer is disposed on the support wafer and / or the sub-wafer.

[0016] Preferably, the donor wafer material includes at least one selected from lithium niobate (LiNbO3, abbreviated as LN), lithium tantalate, indium phosphide (InP) or gallium arsenide (GaAs), gallium nitride, silicon carbide, zinc oxide, zinc selenide, aluminum nitride, gallium oxide, diamond, barium titanate, yttrium aluminum garnet, silicon germanium, vanadium oxide, and sapphire. Correspondingly, the sub-wafer, the film layer includes at least one of the above materials.

[0017] Preferably, the supporting wafer and the transit wafer are, but are not limited to, any one of silicon, silicon oxide, silicon carbide, diamond, and sapphire.

[0018] Preferably, the film thickness is 50nm-10μm, for example 100nm, 300nm, 500nm, 700nm, 1μm, 3μm, 7μm, 10μm.

[0019] Preferably, the debonding includes exposing the temporary bonded layer to a non-room temperature environment.

[0020] Preferably, the non-room temperature environment includes temperatures below 15°C or above 25°C, such as -150°C, -100°C, -50°C, -20°C, or 50°C, 100°C, 200°C, 400°C, 600°C, 1000°C, 1300°C, etc.

[0021] Preferably, the temporary bonding layer comprises an organic material layer or an inorganic material layer;

[0022] The organic material layer includes polyimide, polyhydroxy ether, or temporary bonding adhesive;

[0023] The inorganic materials include SiO2, Ge, Ti, W, Al, TiN, TaN, and WN.

[0024] Preferably, the temporary bonding layer is a thermal stress temporary bonding layer;

[0025] The thermal stress temporary bonding layer includes a first sublayer and a second sublayer, the first sublayer and the second sublayer having different coefficients of thermal expansion, and the shear force generated by the difference in thermal expansion coefficients causes the interface to separate.

[0026] Preferably, the temporary bonding layer is a low-temperature embrittlement material layer, which is separated at the interface by low-temperature catalysis.

[0027] Preferably, the temporary bonding layer includes a silicon oxide material layer; the silicon oxide material layer contains an ion implantation layer; and the surface of the temporary bonding layer is acid-washed to form ion flow channels.

[0028] Preferably, the planarization process includes chemical mechanical polishing and / or superatom beam trimming.

[0029] Preferably, the plurality of said film layers are arranged closely or spaced apart on the surface of the receptor wafer;

[0030] Preferably, the spacing between adjacent film layers in the close arrangement is <50 μm;

[0031] Preferably, the spacing between adjacent film layers in the spacing arrangement is ≥50μm.

[0032] Preferably, after providing the donor wafer, a temporary bonding layer is first prepared on the surface of the donor wafer, and then the donor wafer is cut into multiple sub-wafers;

[0033] Preferably, the temporary bonding layer side of the plurality of sub-wafers is bonded to the surface of the temporary bonding layer of the supporting wafer.

[0034] Preferably, after the multiple sub-wafers are detached from the temporary bonding layer and transferred to the intermediate wafer, the residual temporary bonding layer on the surface of the multiple sub-wafers is removed.

[0035] Preferably, the first bonding method includes room temperature bonding;

[0036] The second bonding method includes hydrophilic bonding.

[0037] Preferably, the planarization process makes the surface roughness Ra of the plurality of sub-pieces < 1 nm, for example, 0.9 nm, 0.8 nm, 0.7 nm, 0.6 nm, 0.5 nm, 0.4 nm, 0.3 nm, 0.2 nm, and 0.1 nm.

[0038] Preferably, the surface coplanarity of the plurality of said sub-pieces is <10nm, for example, 0.5nm, 1nm, 2nm, 5nm, 8nm.

[0039] Preferably, the donor wafer has a first size; the support wafer has a second size; the transfer wafer has a third size; and the recipient wafer has a fourth size; the first size is smaller than the second size; and the second size is not smaller than the third or fourth size.

[0040] Preferably, the second size is 12 inches.

[0041] Large-size reconstructed wafers are prepared according to the manufacturing method described above;

[0042] The large-size reconstructed wafer includes stacked film layers and acceptor wafers;

[0043] The acceptor wafer includes patterned wafers or bare wafers.

[0044] Preferably, the large-size reconstruction wafer has a size specification of ≥12 inches;

[0045] And / or the surface roughness Ra of the film layer is less than 1 nm;

[0046] And / or the surface coplanarity of the film layer is <10 nm.

[0047] A bonding structure includes a structure to be bonded, wherein the bonding surface of the structure to be bonded is bonded to a reconstructed wafer prepared by the manufacturing method described above, or bonded to a large-size reconstructed wafer as described above.

[0048] The structure to be bonded includes a chip, a patterned wafer, a bare wafer, or a semiconductor device.

[0049] The semiconductor device includes a laser, detector, modulator, resonator, filter, or sensor. The beneficial effects of this invention are:

[0050] The reconstructed wafer manufacturing method provided by this invention reconstructs large-size wafers from small-size sub-wafers, overcoming the intrinsic material limitation of compound semiconductors in fabricating large-size single crystals. Wafer reconstruction is achieved through temporary bonding, room-temperature bonding, and hydrophilic bonding. Superatom beam trimming technology is employed to avoid lattice damage while maintaining nanoscale flatness, ensuring crystal quality. The resulting large-size reconstructed wafer exhibits performance comparable to a fully bonded wafer, with no damage to the functional layers and excellent thickness uniformity. It can be directly used for repackaging and bonding with individual devices or entire wafers. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the manufacturing process of the reconstructed wafer of the present invention;

[0052] In the figure: 1: donor wafer; 11: sub-wafer; 111: film layer; 2: support wafer; 21: temporary bonding layer; 3: transfer wafer; 4: acceptor wafer. Detailed Implementation

[0053] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it.

[0054] like Figure 1As shown, the reconstructed wafer manufacturing method provided in this embodiment mainly includes the following steps: providing a donor wafer 1 and cutting it into multiple sub-wafers 11; or directly providing multiple pre-cut sub-wafers 11. A support wafer 2 with a temporary bonding layer 21 is provided; sub-wafers 11 are bonded to the temporary bonding layer 21 of the support wafer 2; the entire surface of the sub-wafers 11 on the support wafer 2 is planarized to achieve a surface coplanarity of 0.5 nm for the multiple sub-wafers 11 on the entire surface; a transfer wafer 3 is provided, and the sub-wafers 11 of the support wafer 2 are bonded to the transfer wafer 3 using a room temperature bonding method; debonding is performed to transfer the sub-wafers 11 to the transfer wafer 3; an ion implantation process is performed on the sub-wafers 11 on the transfer wafer 3 to form an ion implantation layer in the sub-wafers 11, the ion implantation layer separating the sub-wafers 11 into a film layer 111 and a remaining sub-wafer; the film layer 111 of the transfer wafer 3 is bonded to the acceptor wafer 4 using a hydrophilic bonding method; heat treatment is performed to crack the ion implantation layer, and the film layer 111 is transferred to the acceptor wafer 4 to obtain a reconstructed wafer.

[0055] The method of this embodiment first provides a donor wafer 1, which has a first size (8 inches). In this embodiment, the donor wafer 1 is selected from lithium niobate. Due to the limitations of the intrinsic properties of lithium niobate material, it is difficult to achieve high-quality large-size wafer fabrication. Therefore, the method of this embodiment is needed to achieve large-size reconstruction.

[0056] The donor wafer 1 is cut into multiple sub-wafers 11 along its thickness direction. The cutting method can employ conventional cutting techniques in the art, such as laser cutting, diamond wheel cutting, or stealth cutting. The dimensions of the resulting sub-wafers 11 are determined based on the dimensions and arrangement of the supporting wafer 2 to ensure that the multiple sub-wafers 11 can be completely arranged on the surface of the supporting wafer 2.

[0057] A support wafer 2 is provided, the support wafer 2 having a second size (12 inches), the second size being larger than the first size. In this embodiment, the support wafer 2 is a silicon wafer.

[0058] The supporting wafer 2 includes a temporary bonding layer 21, which has the property that the sub-wafer 11 bonded thereto can be detached upon debonding. According to different embodiments of the present invention, the temporary bonding layer 21 can be of various types:

[0059] In a preferred embodiment, the temporary bonding layer 21 includes an ion implantation layer, and the surface of the temporary bonding layer 21 is acid-processed to form ion flow channels. Specifically, the temporary bonding layer 21 includes a silicon oxide material layer, which is formed on the surface of the supporting wafer 2 by methods such as thermal oxidation, chemical vapor deposition (CVD), or physical vapor deposition (PVD), and has a thickness ranging from 100 nm to 2 μm.

[0060] The ion-implanted layer is formed by ion implantation into a silicon oxide layer. The implanted ions can be selected from hydrogen ions (H+). + Helium ions (He) + Alternatively, hydrogen-helium co-injection can be used, with an injection energy range of 1 keV to 80 keV and an injection dose range of 1 × 10¹. 3 ions / cm² to 1×10¹ 6 The implantation depth is controlled at 1 / 2 to above the thickness of the silicon oxide layer to form an ion-rich defect layer inside the silicon oxide layer.

[0061] The acid processing includes treating the surface of the temporary bonding layer 21 with hydrofluoric acid. Specifically, the silicon oxide layer with the ion implantation layer is immersed in a 0.1% to 30% aqueous solution of hydrofluoric acid for 1 to 100 seconds at a temperature of 10°C to 50°C. The hydrofluoric acid reacts with the silicon oxide, disrupting the ring structure formed by the silicon-oxygen bonds and creating channels within the oxide layer that allow ions to pass through. These channels are nanoscale microporous structures, providing pathways for the release of ions during subsequent debonding.

[0062] In another embodiment, the temporary bonding layer 21 is a thermally stressed temporary bonding layer. The thermally stressed temporary bonding layer includes a first sublayer and a second sublayer, the first sublayer and the second sublayer having different coefficients of thermal expansion, and the shear force generated by the difference in the coefficients of thermal expansion causes the interface to separate.

[0063] Specifically, the first sublayer can be a silicon oxide layer with a thickness of 50 nm to 500 nm and a coefficient of thermal expansion of approximately 0.5 × 10⁻⁶. -6 / ℃; the second sublayer can be a silicon nitride layer or a metal layer (such as an aluminum layer or a copper layer), with a thickness of 50nm to 500nm and a coefficient of thermal expansion of approximately 2.3×10⁻⁶. -6 / ℃ (silicon nitride) or 23×10 -6 / ℃ (aluminum). Two layers of material are sequentially deposited on the surface of the supporting wafer 2 using methods such as PECVD, sputtering, or evaporation. When the temperature changes, shear stress is generated at the interface between the two layers due to the difference in thermal expansion coefficients. When the stress exceeds the interfacial bonding strength, the interface separates.

[0064] In another embodiment, the temporary bonding layer 21 is a pyrolytic material layer. The pyrolytic material layer is formed by methods such as spin coating, spraying, or deposition, and has a thickness of 100 nm to 5 μm. The pyrolytic material layer can be an organic material layer or an inorganic material layer. The organic material layer includes polyimide, polyhydroxy ether, or temporary bonding adhesive, while the inorganic material layer includes SiO2, Ge, Ti, W, Al, TiN, TaN, WN (tungsten nitride), etc. When an organic material is selected as the pyrolytic material layer, thermal decomposition can be achieved by increasing the ambient temperature, such as heat treatment at 200°C to 400°C, thereby separating the interface. When an inorganic material is selected as the pyrolytic material layer, the interface can be separated by laser ablation. The laser ablation process for debonding can be referenced from existing mature technologies, and will not be described in detail in this application.

[0065] In another embodiment, the temporary bonding layer 21 is a low-temperature embrittlement material layer. Materials such as modified epoxy resin and polystyrene can be selected. These materials are solid at room temperature and can provide good support. They undergo a brittle transition at low temperatures. When the temperature drops to the transition temperature, such as below -50°C, the material becomes embrittled, the interfacial bonding strength is significantly reduced, and it is easy to separate under external force.

[0066] The plurality of sub-pieces 11 are temporarily bonded to the surface of the temporary bonding layer 21 of the supporting wafer 2. The bonding method can be direct bonding, including hydrophilic bonding, room temperature bonding, or adhesive bonding. For embodiments using ion implantation-type temporary bonding layers, hydrophilic bonding is preferred.

[0067] Prior to hydrophilic bonding, the bonding surfaces of the sub-wafer 11 and / or the supporting wafer 2 are subjected to standard cleaning (RCA cleaning or ozone water treatment) to hydroxylate the surfaces and form hydrophilic surfaces. Bonding is performed at room temperature, with appropriate pressure applied (typically 0.1 MPa to 10 MPa) to ensure close contact between the two surfaces, achieving initial bonding through intermolecular forces. Subsequently, a low-temperature annealing at around 200°C can be performed to enhance the bonding strength. This temperature is insufficient to precipitate ion-implanted elements and will not cause interface separation.

[0068] The film layer 111 is planarized to make its entire surface flat. The planarization process includes superatom beam trimming.

[0069] The superatomic beam trimming employs superatomic beam polishing technology. Superatoms are nanoscale particles composed of hundreds to thousands of gas molecules / atoms (such as Ar, He, Kr, NF3, etc.) bound together by van der Waals forces. In ionization collisions and electromagnetic field motion, they can be considered as a single "atom," with a mass and collision cross-section several to thousands of times greater than that of a single atom. The gas source can be argon, helium, or xenon, with argon being preferred.

[0070] The superatomic beam is generated as follows: a working gas is introduced into an ion source, and the gas is ionized by electron bombardment or radio frequency discharge to form plasma; in the plasma, ions and neutral atoms / molecules combine through van der Waals forces to form superatoms; small-mass superatoms and monatomic ions that do not meet the standards are removed by magnetic sieving, so that the proportion of superatoms is >90%, and a single superatom is composed of ≥50 basic particles (atoms and / or molecules).

[0071] When a superatomic beam bombards a material surface, it produces a lateral sputtering effect and a localized thermal annealing effect, as well as a localized pulsed high temperature. The process is gentle and does not cause overall damage to the substrate and / or the film layer. During the trimming process, the superatomic beam energy is controlled between 1 keV and 50 keV, the beam current density is between 1 μA / cm² and 100 μA / cm², and the processing time is between 1 minute and 60 minutes.

[0072] After superatom beam trimming, the surface roughness Ra of film 111 is <0.5 nm, and the surface coplanarity of film 111 is <1 nm. The lattice of film 111 is undamaged and does not affect the performance of subsequent fabricated devices.

[0073] A transfer wafer 3 is provided, which has a third size (12 inches or larger). The transfer wafer 3 is a silicon wafer with the same or larger size as the support wafer 2 to ensure that the sub-wafer 11 transferred from the support wafer 2 can be fully supported. Preferably, the transfer wafer 3 is a silicon wafer with a surface oxide layer, which is beneficial to improving bonding quality.

[0074] One side of the sub-wafer 11 supporting wafer 2 is bonded to the intermediate wafer 3 using a room temperature bonding process, thus forming a strong bond between the sub-wafer 11 and the intermediate wafer 3. This room temperature bonding is performed at a vacuum level ≤ 5 × 10⁻⁶. -6 The bonding process is carried out under a high vacuum environment of Pa. Before bonding, the interface to be bonded is first activated to form highly active dangling bonds. Then, pressure is applied at room temperature (25°C) to complete the bonding. Since the bonding process does not require high-temperature annealing, the failure of the temporary bonding layer 21 during the process can be effectively avoided.

[0075] This method first pre-bonds the sub-chips 11 onto the support wafer 2 under relatively relaxed process conditions. Then, through a single high-precision room temperature bonding, multiple sub-chips 11 can be bonded to the intermediate wafer 3 in one go, significantly reducing process difficulty and shortening the process cycle. Compared with the method of bonding multiple sub-chips 11 to the intermediate wafer 3 one by one using room temperature bonding, this method does not require maintaining a high vacuum state in the bonding chamber for a long time. At the same time, it can avoid problems such as particle contamination of sub-chips 11 caused by the robotic arm transferring wafer by wafer, particle impurities generated by the friction of the robotic arm movement, and poor positioning accuracy consistency caused by multiple wafer transfers.

[0076] Debonding is performed to detach multiple sub-wafers 11 from the temporary bonding layer 21 and transfer them to the intermediate wafer 3. Debonding includes exposing the temporary bonding layer 21 to a non-room temperature environment, which includes below 15°C or above 25°C.

[0077] For ion-implanted temporary bonding layers: Annealing is performed at a temperature of 400°C for 10 to 120 minutes. Under high temperature, hydrogen or helium ions in the ion-implanted layer gain sufficient energy to move between the silicon oxide lattice and precipitate at the temporary bonding interface through the channels formed by the previous acid treatment. Bubbles or cracks are formed at the interface, causing the two temporarily bonded silicon oxide layers to separate and the sub-wafer 11 is transferred to the intermediate wafer 3.

[0078] For thermal stress temporary bonding layers: thermal cycling is performed, with the temperature increasing from room temperature to 150°C to 300°C or decreasing to -50°C to -100°C, utilizing the shear force generated by the difference in thermal expansion coefficients to separate the interfaces.

[0079] For temporary bonded layers of pyrolytic materials: heat to the thermal decomposition temperature of 200℃ to 600℃ to decompose the pyrolytic material and separate the interface, or separate the interface by laser ablation.

[0080] For low-temperature embrittlement temporary bonded layers: cool to -50°C to -150°C below the embrittlement temperature, embrittle the material, and then apply mechanical force to separate the interface.

[0081] Because the sub-chip 11 bonded to the intermediate wafer 3 is small, the internal stress generated by its coefficient of thermal expansion after changes in ambient temperature is more easily released than that of the whole wafer, thus preventing fragmentation.

[0082] After the sub-wafer 11 is detached and transferred to the intermediate wafer 3, temporary bonding layer 21 material may remain on the surface of the plurality of sub-wafers 11. It can be removed by wet etching with hydrofluoric acid solution (concentration 0.1% to 10%), or by dry etching with CF4 / CHF3 plasma, or by chemical mechanical polishing (CMP) or superatom beam trimming until the original surface of the sub-wafer 11 is exposed.

[0083] An ion implantation process is performed on the sub-wafer 11 on the intermediate wafer 3 to form an ion implantation layer in the sub-wafer 11. The ion implantation layer separates the sub-wafer 11 into a film layer 111 and the remaining proton sub-wafer. The energy, dose, and depth of ion implantation can be conventionally adjusted according to different materials and needs. This technology is relatively mature and will not be described in detail in the embodiments of this application.

[0084] A hydrophilic bonding method is used to bond the film layer 111 of the intermediate wafer 3 to the acceptor wafer 4. Heat treatment is then performed to crack the ion implantation layer, transferring the film layer 111 to the acceptor wafer 4 to obtain a reconstructed wafer. The remaining proton wafer is retained on the intermediate wafer 3, which, after surface planarization, can be ion implanted again for repeated use until the remaining thickness is insufficient to support ion implantation. The heat treatment also enhances the bonding strength between the film layer 111 and the acceptor wafer 4, ensuring the strength meets industrial requirements.

[0085] In the reconstructed wafer, multiple film layers 111 can be arranged in a close-packed or spaced-out manner on the surface of the acceptor wafer 4.

[0086] Close arrangement: The spacing between adjacent film layers 111 is <50μm, preferably less than 20μm, and more preferably less than 5μm. This arrangement is suitable for applications requiring large-area continuous film layers 111, such as large-area optoelectronic integrated devices. Spacing arrangement: The spacing between adjacent film layers 111 is ≥50μm, preferably 100μm to 10mm. This arrangement is suitable for applications requiring independent functional units, such as array sensors or discrete device integration. The spacing areas can be filled with insulating material or left empty, depending on subsequent process requirements.

[0087] After obtaining the reconstructed wafer, the surface of the reconstructed wafer is planarized to ensure that the surface roughness Ra of the film layer 111 is <0.5nm and the coplanarity of the film layer 111 is <1nm. The planarization process preferably employs superatomic beam trimming, or chemical mechanical polishing followed by superatomic beam trimming. Because large-size reconstructed wafers are 12 inches or larger, achieving the desired overall coplanarity using only chemical mechanical polishing is difficult. Superatomic beam trimming, however, can achieve overall coplanarity trimming. The resulting large-size reconstructed wafer possesses performance comparable to a fully bonded wafer, with excellent thickness uniformity, and can be directly used for repackaging and bonding with individual devices or entire wafers, ensuring the performance of the reconstructed wafer.

[0088] In another embodiment, a temporary bonding layer 21 is first prepared on the surface of the donor wafer 1, and then the donor wafer 1 is cut into multiple sub-pieces 11; then the temporary bonding layer 21 of the multiple sub-pieces 11 is bonded to the surface of the temporary bonding layer 21 of the supporting wafer 2.

[0089] Specifically, a temporary silicon oxide bonding layer 21 with a thickness of 100 nm to 1 μm is prepared on the surface of donor wafer 1 by thermal oxidation or CVD. Ion implantation and acid treatment are then performed to form ion flow channels, with process parameters identical to those of the temporary bonding layer 21 on support wafer 2. After dicing, the temporary bonding layer 21 side of the sub-wafer 11 faces the temporary bonding layer 21 side of support wafer 2, forming a temporary bonding structure through hydrophilic bonding. The design of the temporary bonding layers 21 on both sides ensures more thorough interface separation during debonding, reducing residue.

[0090] After being transferred to the intermediate wafer 3, the residual temporary bonding layer 21 on the surface of the sub-wafer 11 is removed. After planarization of the sub-wafer 11 side, subsequent steps of ion implantation, hydrophilic bonding, annealing, dicing, and trimming are performed to obtain the reconstructed wafer.

[0091] This invention also provides a large-size reconstruction wafer, manufactured by any of the methods described above. The size of the large-size reconstruction wafer is the same as or larger than that of the intermediate wafer 3, and can be 12 inches or larger. The reconstruction wafer includes a recipient wafer 4 and a film layer 111 thereon. The recipient wafer 4 includes a patterned wafer or a bare wafer. The patterned wafer refers to the formation of precise and controllable micro-nano structures on the surface through processes such as photolithography, etching, and deposition, including lines, gates, dots, alignment marks, test keys, and analog device patterns. The material of the film layer 111 includes at least one of lithium niobate (LiNbO3, abbreviated as LN), lithium tantalate, indium phosphide (InP) or gallium arsenide (GaAs), gallium nitride, silicon carbide, zinc oxide, zinc selenide, aluminum nitride, gallium oxide, diamond, barium titanate, yttrium aluminum garnet, silicon germanium, vanadium oxide, and sapphire.

[0092] The film layer 111 of the large-size reconstructed wafer has a surface roughness Ra < 0.5 nm, a surface coplanarity < 10 nm, preferably a surface coplanarity < 5 nm, more preferably a surface coplanarity < 1 nm, and excellent thickness uniformity. It can be directly used for repackaging and bonding with individual devices or the entire wafer.

[0093] This invention also provides a bonding structure, including a structure to be bonded, wherein the bonding surface of the structure to be bonded is bonded to the aforementioned large-size reconstructed wafer.

[0094] The structure to be bonded includes a chip, a wafer, or a semiconductor device. The semiconductor device includes a laser, a detector, a modulator, a resonator, a filter, or a sensor.

[0095] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art will be able to make various obvious changes, readjustments, and substitutions without departing from the scope of protection of the present invention. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a reconstructed wafer, characterized in that, include: A donor wafer (1) is provided, and the donor wafer (1) is cut into multiple sub-wafers (11) along the thickness direction; or multiple sub-wafers (11) are provided directly. Provide support wafers (2); The multiple sub-pieces (11) are temporarily bonded to the support wafer (2); The multiple sub-pieces (11) temporarily bonded to the support wafer (2) are planarized to make the surface flat; The intermediate wafer (3) is provided to bond the sub-wafer (11) temporarily bonded to the support wafer (2) to the intermediate wafer (3) in a first bonding manner. Debonding is performed to detach the multiple sub-pieces (11) from the support wafer (2) and transfer them to the transfer wafer (3). Ion implantation is performed to form ion implantation layers in a plurality of the sub-sheets (11), the ion implantation layers separating the sub-sheets (11) into a film layer (111) and a remaining proton sheet; A acceptor wafer (4) is provided, and the film layer (111) side of the transfer wafer (3) is bonded to the acceptor wafer (4) in a second bonding manner. Perform heat treatment to crack the ion implantation layer and transfer the film (111) to the acceptor wafer (4) to obtain the reconstructed wafer.

2. The manufacturing method according to claim 1, characterized in that, The sub-wafer (11) is temporarily bonded to the supporting wafer (2) through a temporary bonding layer (21); The temporary bonding layer (21) is disposed on the support wafer (2) and / or the sub-wafer (11).

3. The manufacturing method according to claim 2, characterized in that, The debonding includes placing the temporary bonded layer (21) in a non-room temperature environment.

4. The manufacturing method according to claim 2, characterized in that, The temporary bonding layer (21) includes an organic material layer or an inorganic material layer; The organic material layer includes polyimide, polyhydroxy ether, or temporary bonding adhesive; The inorganic materials include SiO2, Ge, Ti, W, Al, TiN, TaN, and WN.

5. The manufacturing method according to claim 2, characterized in that, The temporary bonding layer (21) is a thermal stress temporary bonding layer; The thermal stress temporary bonding layer includes a first sublayer and a second sublayer, the first sublayer and the second sublayer having different coefficients of thermal expansion, and the shear force generated by the difference in thermal expansion coefficients causes the interface to separate.

6. The manufacturing method according to claim 2, characterized in that, The temporary bonding layer (21) is a low-temperature embrittlement material layer, which is separated at the interface by low-temperature catalysis.

7. The manufacturing method according to claim 2, characterized in that, The temporary bonding layer (21) includes a silicon oxide material layer; the silicon oxide material layer contains an ion implantation layer; and the surface of the temporary bonding layer (21) is acid-washed to form ion flow channels.

8. The manufacturing method according to claim 1, characterized in that, The planarization process includes chemical mechanical polishing and / or superatomic beam trimming.

9. The manufacturing method according to claim 1, characterized in that, Multiple film layers (111) are arranged closely or spaced apart on the surface of the acceptor wafer (4); In the close arrangement, the interval between adjacent membrane layers (111) is <50μm; The spacing between adjacent membrane layers (111) in the spacing arrangement is ≥50μm.

10. The manufacturing method according to claim 2, characterized in that, Also includes: After providing the donor wafer (1), a temporary bonding layer (21) is first prepared on the surface of the donor wafer (1), and then the donor wafer (1) is cut into multiple sub-wafers (11).

11. The manufacturing method according to claim 1, characterized in that, The first bonding method includes room temperature bonding; The second bonding method includes hydrophilic bonding.

12. The manufacturing method according to claim 1 or 8, characterized in that, The planarization process makes the surface roughness Ra of the plurality of sub-pieces (11) < 1 nm; and / or makes the surface coplanarity of the plurality of sub-pieces (11) < 10 nm.

13. The manufacturing method according to claim 1, characterized in that, The donor wafer (1) has a first size; the support wafer has a second size; the transfer wafer has a third size; the acceptor wafer has a fourth size; the first size is smaller than the second size; The second dimension is not smaller than the third or fourth dimension.

14. A large-size reconstructed wafer, characterized in that, Prepared by the manufacturing method according to any one of claims 1-13; The large-size reconstruction wafer includes stacked film layers (111) and acceptor wafers (4). The acceptor wafer (4) includes a patterned wafer or a bare wafer.

15. The large-size reconstructed wafer according to claim 14, characterized in that, The size of the large-size reconstructed wafer is ≥12 inches; And / or the surface roughness Ra of the film (111) is < 1 nm; And / or the surface coplanarity of the film (111) is <10 nm.

16. A bonding structure, characterized in that, Includes a structure to be bonded, wherein the bonding surface of the structure to be bonded is bonded to a reconstructed wafer prepared by the manufacturing method according to any one of claims 1-13, or bonded to a large-size reconstructed wafer according to any one of claims 14-15; The structure to be bonded includes a chip, a patterned wafer, a bare wafer, or a semiconductor device. The semiconductor device includes a laser, a detector, a modulator, a resonator, a filter, or a sensor.

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