Test method, device and equipment of automatic test equipment

Abstract

This application discloses a testing method, apparatus, and equipment for an automatic testing device. It acquires test information of the product under test in response to test command information. The test information includes multiple cycle test information. Each cycle test information is parsed to obtain clock configuration information for that cycle. A sampling clock signal corresponding to each cycle test information is generated based on the clock configuration information. The product under test is tested based on the sampling clock signal corresponding to each cycle test information to obtain test data for each cycle test information. The test data and expected data for each cycle test information are analyzed to obtain the test result of the product under test. By testing in segments based on each cycle test information and generating corresponding sampling clock signals, a dynamically adjustable and configurable sampling clock signal is provided, thus solving the problem of how to improve the testing speed of the testing equipment.

Description

Technical Field

[0001] This application relates to the field of equipment testing technology, and in particular to a testing method, apparatus and equipment for an automatic testing device. Background Technology

[0002] ATE (Automatic Test Equipment) is a specialized device used for automated testing of semiconductor devices, electronic components, or complete systems. Its core objective is to verify the functionality, performance, and reliability of the device under test (DUT) through high-speed, high-precision electrical testing, ensuring compliance with design specifications or industry standards. The clock signal is a critical component of the ATE, directly affecting test accuracy and synchronization.

[0003] In existing technologies, the clock signal of the ATE (Automatic Test Equipment) uses a traditional strobe signal, which samples data using only a single edge (such as the rising edge) per cycle, or a multi-edge strobe signal. This results in a limited and relatively fixed number of configurable strobe points, hindering dynamic configuration and adjustment, and concentrating the ATE's test rate at low to medium speeds (such as 400MHz). With the iterative updates of DDR memory chips, the test rate requirements for test equipment are constantly increasing. Therefore, there is an urgent need for an automated test equipment method that can improve the test rate of test equipment to solve the above problems. Summary of the Invention

[0004] This application provides a testing method, apparatus, and equipment for an automatic testing device. By performing testing in segments based on test information of each cycle, setting clock configuration information based on the test information of each cycle, and generating a sampling clock signal corresponding to the test information of each cycle in real time, a dynamically adjustable and configurable sampling clock signal is provided. The product to be tested is tested based on the sampling clock information to obtain test results and provide customers with accurate information, thus solving the problem of how to improve the testing speed of testing equipment.

[0005] According to one aspect of this application, a testing method for an automatic testing device is provided, the method comprising: In response to test command information, the test information of the product to be tested is obtained; the test information includes test information from multiple cycles. The test information for each cycle is parsed to obtain the clock configuration information for each cycle of test information; Based on the clock configuration information of each cycle test information, a sampling clock signal corresponding to each cycle test information is generated; The product under test is tested based on the sampling clock signal corresponding to the test information of each cycle, and the test data of each cycle test information is obtained. The test results of the product under test are obtained by analyzing the test data and expected data of each test cycle.

[0006] In one possible implementation, the test information for each cycle includes a configuration parameter address. The step of parsing the test information for each cycle to obtain the clock configuration information for each cycle of test information includes: Retrieve the test configuration parameters stored in the test information for each period; the test configuration parameters include a first configuration parameter and a second configuration parameter. The first configuration parameter and the second configuration parameter are compared to obtain the comparison result; Based on the comparison results, the clock configuration information for each cycle of test information is determined.

[0007] In one possible implementation, determining the clock configuration information for each cycle of test information based on the comparison result includes: If the comparison result indicates that the first configuration parameter is equal to the second configuration parameter, the first configuration parameter is determined to be the clock configuration information; If the comparison result indicates that the first configuration parameter is greater than or less than the second configuration parameter, the first configuration parameter and the second configuration parameter are determined to be the clock configuration information.

[0008] In one possible implementation, the generation of the sampling clock signal corresponding to each cycle of test information based on the clock configuration information for each cycle includes: Determine the temporal resolution and test period of the test information; the test period is used to divide the test information into multiple test periods. The initial sampling sequence of test information for each period is determined based on the time resolution and the test period; Based on the clock configuration information and initial sampling sequence of each cycle test information, a sampling clock signal corresponding to each cycle test information is generated.

[0009] In one possible implementation, the initial sampling sequence includes multiple configurable bits, each configurable bit corresponding to an initial value of a first value, and the first configuration parameter represents a high-level active bit; The generation of the sampling clock signal corresponding to each cycle of test information, based on the clock configuration information and initial sampling sequence of each cycle of test information, includes: When the clock configuration information is the first configuration parameter, the target configuration bit is determined from multiple configurable bits based on the first configuration parameter; The initial values ​​corresponding to the target configuration bit and the configurable bits following the target configuration bit are modified to the second value to obtain a single-edge sampling clock signal; the first value is less than the second value; The single-edge sampling clock signal is determined to be the sampling clock signal of the periodic test information corresponding to the clock configuration information.

[0010] In one possible implementation, the second configuration parameter represents a low-level active bit, and the method further includes: When the clock configuration information is the first configuration parameter and the second configuration parameter, a first target configuration bit is determined from multiple configurable bits based on the first configuration parameter, and a second target configuration bit is determined from multiple configurable bits based on the second configuration parameter; Modify the initial values ​​of the first target configuration bit, the second target configuration bit, and the configurable bits between the first target configuration bit and the second target configuration bit to the second value to obtain a multi-edge sampling clock signal; The multi-edge sampling clock signal is determined to be the sampling clock signal of the periodic test information corresponding to the clock configuration information.

[0011] In one possible implementation, the test configuration parameters further include a third configuration parameter, which represents a plurality of active high-level bits. The third configuration parameter includes N high-level configuration parameters, where N is greater than a first number and N is less than or equal to a second number, and the second number is greater than the first number. The method further includes: When the clock configuration information is the third configuration parameter, the target configuration bit is determined from multiple configurable bits based on each high-level configuration parameter; The initial values ​​of the target configuration bit corresponding to each high-level configuration parameter and the configurable bits following the target configuration bit are modified to the second value to obtain the initial modification sequence corresponding to each high-level configuration parameter. Based on the initial modification sequence corresponding to each high-level configuration parameter, a bitwise XOR calculation is performed to obtain the sampling clock signal of the periodic test information corresponding to the third configuration parameter.

[0012] In one possible implementation, the step of testing the product under test based on the sampling clock signal corresponding to each cycle of test information to obtain test data for each cycle of test information includes: Obtain the test input data corresponding to the test information for each cycle; The test input data is input into the product under test to obtain the output data of the test information for each cycle. The output data of each cycle of test information is sampled based on the sampling clock signal corresponding to each cycle of test information to obtain the test data of each cycle of test information.

[0013] In one possible implementation, the analysis of the test data based on the test information of each cycle and the expected data of the test information of each cycle to obtain the test results of the product under test includes: The test data for each period of test information is matched with the expected data for each period of test information to obtain the matching result for each period of test information; If the matching result indicates that the test data does not match the expected data, the periodic test information corresponding to the mismatched test data and the expected data is determined to be abnormal test information. The test results of the product under test are generated based on the abnormal test information.

[0014] On the other hand, a testing apparatus for an automated testing device is provided, the apparatus comprising: The test information acquisition module is used to acquire test information of the product to be tested in response to test command information; the test information includes test information from multiple cycles. The parsing module is used to parse the test information for each cycle to obtain the clock configuration information for each cycle of test information; The clock signal generation module is used to generate the sampling clock signal corresponding to each cycle of test information based on the clock configuration information of each cycle of test information. The testing module is used to test the product under test based on the sampling clock signal corresponding to the test information of each cycle, and to obtain the test data of the test information of each cycle. The analysis module is used to analyze the test data and expected data of each test cycle to obtain the test results of the product under test.

[0015] In one possible implementation, the test information for each cycle includes a configuration parameter address, and the parsing module is used for: Retrieve the test configuration parameters stored in the test information for each period; the test configuration parameters include a first configuration parameter and a second configuration parameter. The first configuration parameter and the second configuration parameter are compared to obtain the comparison result; Based on the comparison results, the clock configuration information for each cycle of test information is determined.

[0016] In one possible implementation, the parsing module is further configured to: If the comparison result indicates that the first configuration parameter is equal to the second configuration parameter, the first configuration parameter is determined to be the clock configuration information; If the comparison result indicates that the first configuration parameter is greater than or less than the second configuration parameter, the first configuration parameter and the second configuration parameter are determined to be the clock configuration information.

[0017] In one possible implementation, the clock signal generation module is configured to: Determine the temporal resolution and test period of the test information; the test period is used to divide the test information into multiple test periods. The initial sampling sequence of test information for each period is determined based on the time resolution and the test period; Based on the clock configuration information and initial sampling sequence of each cycle test information, a sampling clock signal corresponding to each cycle test information is generated.

[0018] In one possible implementation, the initial sampling sequence includes multiple configurable bits, each configurable bit corresponding to an initial value of a first value, where the first configuration parameter represents a high-level active bit; the clock signal generation module is further configured to: When the clock configuration information is the first configuration parameter, the target configuration bit is determined from multiple configurable bits based on the first configuration parameter; The initial values ​​corresponding to the target configuration bit and the configurable bits following the target configuration bit are modified to the second value to obtain a single-edge sampling clock signal; the first value is less than the second value; The single-edge sampling clock signal is determined to be the sampling clock signal of the periodic test information corresponding to the clock configuration information.

[0019] In one possible implementation, the second configuration parameter represents a low-level active bit, and the clock signal generation module is further configured to: When the clock configuration information is the first configuration parameter and the second configuration parameter, a first target configuration bit is determined from multiple configurable bits based on the first configuration parameter, and a second target configuration bit is determined from multiple configurable bits based on the second configuration parameter; Modify the initial values ​​of the first target configuration bit, the second target configuration bit, and the configurable bits between the first target configuration bit and the second target configuration bit to the second value to obtain a multi-edge sampling clock signal; The multi-edge sampling clock signal is determined to be the sampling clock signal of the periodic test information corresponding to the clock configuration information.

[0020] In one possible implementation, the test configuration parameters further include a third configuration parameter, which represents a plurality of active high-level bits. The third configuration parameter includes N high-level configuration parameters, where N is greater than a first number and N is less than or equal to a second number, and the second number is greater than the first number. The clock signal generation module is also used for: When the clock configuration information is the third configuration parameter, the target configuration bit is determined from multiple configurable bits based on each high-level configuration parameter; The initial values ​​of the target configuration bit corresponding to each high-level configuration parameter and the configurable bits following the target configuration bit are modified to the second value to obtain the initial modification sequence corresponding to each high-level configuration parameter. Based on the initial modification sequence corresponding to each high-level configuration parameter, a bitwise XOR calculation is performed to obtain the sampling clock signal of the periodic test information corresponding to the third configuration parameter.

[0021] In one possible implementation, the test module is used for: Obtain the test input data corresponding to the test information for each cycle; The test input data is input into the product under test to obtain the output data of the test information for each cycle. The output data of each cycle of test information is sampled based on the sampling clock signal corresponding to each cycle of test information to obtain the test data of each cycle of test information.

[0022] In one possible implementation, the analysis module is used for: The test data for each period of test information is matched with the expected data for each period of test information to obtain the matching result for each period of test information; If the matching result indicates that the test data does not match the expected data, the periodic test information corresponding to the mismatched test data and the expected data is determined to be abnormal test information. The test results of the product under test are generated based on the abnormal test information.

[0023] On the other hand, an electronic device is provided, including a processor and a memory, wherein the memory stores at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement a test method for an automated test device according to any of the above aspects.

[0024] On the other hand, a computer-readable storage medium is provided, wherein at least one instruction or at least one program is stored therein, the at least one instruction or the at least one program being loaded and executed by a processor to implement a test method of an automated test apparatus as described in any of the above aspects.

[0025] On the other hand, a computer program product or computer program is provided, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the testing method of the automated testing apparatus described in any of the above aspects.

[0026] This application embodiment obtains test information for the product under test in response to test command information. The test information includes multiple cycle test information. Each cycle test information is parsed to obtain clock configuration information. A sampling clock signal corresponding to each cycle test information is generated based on the clock configuration information. The product under test is tested based on the sampling clock signal corresponding to each cycle test information to obtain test data for each cycle test information. The test data and expected data for each cycle test information are analyzed to obtain the test result of the product under test. By testing in segments based on each cycle test information, setting clock configuration information based on each cycle test information, and generating a sampling clock signal corresponding to each cycle test information in real time, a dynamically adjustable and configurable sampling clock signal is provided. Based on this sampling clock information, the product under test is tested to obtain test results, providing accurate information to customers and solving the problem of how to improve the testing speed of testing equipment. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart illustrating the testing method of the automatic testing equipment provided in the embodiments of this application; Figure 2 This is a schematic block diagram of the automatic testing equipment provided in the embodiments of this application; Figure 3 This is a second schematic block diagram of the automatic testing equipment provided in the embodiments of this application; Figure 4This is a first schematic diagram of the sampling clock signal of the automatic testing equipment provided in the embodiments of this application; Figure 5 This is a second schematic diagram of the sampling clock signal of the automatic testing equipment provided in the embodiments of this application; Figure 6 This is a schematic diagram of the data acquisition module of the automatic testing equipment provided in the embodiments of this application; Figure 7 This is a schematic block diagram of the testing device of the automatic testing equipment provided in the embodiments of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] In existing technologies, ATE test equipment used in DDR memory chips implements strobe sampling, but the strobe can only be configured at a limited number of fixed points, which is not conducive to dynamic configuration and adjustment. Alternatively, for some low-speed tests such as MemoryCP at 400MHz, some strobe sampling is possible, but the range is very small. For some medium-speed tests such as 800MHz, 1.6GHz, or 2GHz, there is no proposed multi-edge dynamically adjustable strobe. The present application provides a test method for an automatic test equipment, which proposes a method for dynamically configuring the data sampling clock point at the receiving end of a medium-speed tester.

[0031] This application provides a testing method for an automatic testing device. The method performs testing using test information in segments for each cycle. Clock configuration information is set based on the test information in each cycle, generating a sampling clock signal corresponding to each cycle's test information. This provides a dynamically adjustable and configurable sampling clock signal. The product under test is then tested based on this sampling clock information to obtain test results and provide accurate information to the customer. (See also...) Figure 1 The testing method of the automatic testing equipment includes steps S101 to S109.

[0032] In step S101, in response to the test instruction information, the test information of the product to be tested is obtained; the test information includes multiple cycle test information.

[0033] In one possible implementation, the test information is a pattern (test mode) written by the host computer in semiconductor testing. This pattern is a set of pre-designed data sequences, control signals, and timing instructions based on the test requirements of the product under test (DUT), used to verify the functionality, performance, and reliability of the DUT. Specifically, the pattern is generated by the test engineer via a host computer (test control computer) and downloaded to the test equipment (such as ATE), guiding the test instrument to send specific signals to the DUT and compare the output results.

[0034] In one possible implementation, the test instruction information is a test program containing many lines, i.e., multiple cycle test information, with each line being a cycle test information, i.e., TS (test cycle).

[0035] In one possible implementation, the test instruction information includes the waveform of the corresponding pin in each TS (Test Switch) based on the pin requirements in the chip datasheet. The designer determines whether a strobe clock is needed by writing the software pattern. Specifically, the pin is the physical interface of the electronic device (such as a chip, connector, or circuit board).

[0036] In one possible implementation, the strobe clock is a timing control signal used to synchronize data transmission or signal sampling, commonly found in high-speed digital interfaces (such as DDR memory, Flash memory, and high-speed serial communication). Its function is to ensure that data is captured or transmitted within the correct time window, avoiding errors caused by timing deviations.

[0037] In one possible implementation, the product under test (DUT) is a device under test (DUT), a DDR memory chip, or a NAND flash memory. Specifically, the DUT is the object of the ATE test, and a test plan needs to be designed according to its type (digital / analog / RF).

[0038] In one possible implementation, the automatic test equipment is an ATE device, which can simulate the input conditions (voltage, timing waveform) when the chip is working, collect the output results of the chip (DDR), and store, analyze and judge the output results.

[0039] In one possible implementation, such as Figure 2 As shown, the ATE device mainly consists of the following parts: ALPG: Algorithmic Pattern Generator; PDS: Programmable data selector; FC: Format control, waveform control; DR(PE): Dynamic Recompilation (Pin Electronics), driver; CP(PE): Compare (Pin Electronics), comparator; SC: Sense control, transmission control; AFM: Address Fail memory; DDR (Double Data Rate) is a high-speed memory. SOFT (Soft Error): Memory error.

[0040] In one possible implementation, such as Figure 2 As shown, the product under test is a DUT, which is electrically connected to DR (PE) and CP (PE) respectively, so as to test the DUT based on the ATE equipment.

[0041] In one possible implementation, the Algorithmic Pattern Generator (ALPG) is a core module in the semiconductor test equipment (ATE). It dynamically generates complex test signal patterns to verify the functionality and performance of memory or other digital chips. Its key feature is the real-time generation of test sequences through algorithms, rather than relying on pre-stored fixed patterns, thus efficiently covering various test scenarios. Specifically, these test scenarios include: dynamically generating test patterns, generating address, data, and control signal sequences in real-time according to test requirements without pre-storing a large number of static patterns; supporting complex algorithms, implementing memory-specific test algorithms such as March, Checkerboard, and Butterfly to detect cell defects, coupling faults, etc.; and flexibly adapting to interfaces, supporting different memory protocols (such as DDR and NAND Flash) and high-speed timing requirements (such as multi-edge Strobe).

[0042] In one possible implementation, a PDS (Programmable Analyzer) is a functional module in a digital circuit or test equipment used to dynamically select an input data source based on configuration and route it to a specified output channel. In a semiconductor test equipment (ATE), it connects a specific data source to the test instrument or the DUT (Device Under Test). Specifically, in DRAM / NAND Flash testing, the PDS is used to select different test modes (such as the March algorithm or Checkerboard mode) and send them to specific pins of the chip under test. When testing multiple chips in parallel, the PDS can dynamically allocate different test data streams to each DUT, improving test throughput. The ATE uses the PDS module to dynamically allocate test modes to different DUT pins.

[0043] In one possible implementation, FC (Front-Cut Function) is a key function in digital test systems (such as memory ATE (Automatic Test Equipment) and logic testers). It defines and manages the timing, level, and protocol format of test data, ensuring that test signals strictly match the interface specifications of the device under test (DUT). It is particularly important in high-speed, high-precision testing, directly affecting the accuracy of test results. Specifically, in DDR interface testing, it precisely controls the timing relationship between DQS (Data Strobe) and DQ (Data Line) to ensure the synchronization of dual-edge sampling (DDR characteristic); in the NAND Flash command cycle, it defines the pulse width of control signals such as CLE (Command Latch Enable) and ALE (Address Latch Enable).

[0044] In one possible implementation, DR(PE) refers to the combined use of Debug Registers and PortableExecutable (PE file), primarily for hardware breakpoint debugging, reverse engineering, and vulnerability analysis. Specifically, DR(PE) is used to monitor access to specific memory addresses (read / write / execute) during PE file runtime, dynamically trace code execution flow, resist packing / obfuscation, and detect memory tampering (such as vulnerability exploitation analysis).

[0045] In one possible implementation, CP (PE) is used to compare the binary differences between two PE files (such as different versions of a DLL or malware sample). Specifically, it is used to compare the difference between the test data for each cycle of test information and the expected data for each cycle of test information.

[0046] In one possible implementation, the SC is used to control the reading, writing, and transmission of data. Specifically, the SC is used to receive data output by the CP, as well as to receive the sampling clock signal.

[0047] In one possible implementation, AFM refers to errors or management mechanisms related to address access failures in memory or storage systems, involving hardware failures, operating system handling, debugging methods, etc.

[0048] In one possible implementation, DDR (Double Data Rate) memory plays a crucial role in ATE (Automatic Test Equipment), primarily used to test the performance, reliability, and compatibility of high-speed memory chips. Specifically, DDR is used to verify basic read and write functions, including verifying the correctness of address lines, data lines, and control signals. Double Data Rate (DDR) is a high-speed memory technology that doubles bandwidth by transmitting data twice (on the rising and falling edges) within a single clock cycle.

[0049] In one possible implementation, SOFT is used to analyze error logs.

[0050] In one possible implementation, such as Figure 3 As shown, the ATE device also includes a TG (Transmission Gate), which is used to transmit signals. The working principle of the ATE device is as follows: Transmitter: ALPG can generate test vectors such as address, data, and read / write control required for memory chip testing in real time by executing the program. Many memory chips will time-division multiplex cmd / addr / data onto the same pin to save pins, resulting in a non-unique mapping relationship between ALPG output and ATE_PIN. PDS presets multiple sets of mapping relationships with ALPG output for each ATE_PIN. When PAT runs, ALPG outputs the PDS template number to control PDS to route ALPG output to the corresponding ATE_PIN. FC has a built-in waveform formatter that combines vectors BCLK1~N and timing information CCLK1~N transmitted by TG to output timing waveforms. PE(DR) modulates the timing waveforms onto the corresponding VIH / VIL of the chip. At this time, the corresponding waveform of each PIN is sent to the corresponding PIN of DUT. Receiver: The SC generates a sampling strobe clock based on the timing information CCLK1~N transmitted by the TG, samples the DUT return data, compares it with the expected value, and saves the error information based on whether there is an error in the comparison so that the host computer can read and analyze it.

[0051] In one possible implementation, ATE_PIN is the test pin or channel of the automated test device ATE, which is responsible for providing test signals to the chip and receiving its output signals.

[0052] In this implementation, test information with different test requirements is designed according to the product under test. The test information includes multiple periodic test information. The periodic test information is used as the core unit for testing, which facilitates the configuration of clock signals and error location.

[0053] In step S103, the test information for each cycle is parsed to obtain the clock configuration information for each cycle test information.

[0054] In one possible implementation, the test information for each cycle includes a configuration parameter address. The step of parsing the test information for each cycle to obtain the clock configuration information for each cycle of test information includes: Retrieve the test configuration parameters stored in the test information for each period; the test configuration parameters include a first configuration parameter and a second configuration parameter. The first configuration parameter and the second configuration parameter are compared to obtain the comparison result; Based on the comparison results, the clock configuration information for each cycle of test information is determined.

[0055] In one possible implementation, determining the clock configuration information for each cycle of test information based on the comparison result includes: If the comparison result indicates that the first configuration parameter is equal to the second configuration parameter, the first configuration parameter is determined to be the clock configuration information; If the comparison result indicates that the first configuration parameter is greater than or less than the second configuration parameter, the first configuration parameter and the second configuration parameter are determined to be the clock configuration information.

[0056] In one possible implementation, the test instruction information is a test program pattern. The pattern contains multiple lines, each line representing a single test cycle (TS), i.e., each line represents one cycle of test information. Within each TS, the software sets the waveform for the corresponding pin according to the chip datasheet pin requirements. The software-written pattern already determines whether a strobe clock is needed. The parameters of each TS also include pin format information and TS time settings, such as TS time = 5ns.

[0057] In one possible implementation, during semiconductor testing, the pattern (test mode) written by the host computer is a pre-designed set of data sequences, control signals, and timing instructions used to verify the functionality, performance, and reliability of the device under test (DUT). These patterns are generated by the test engineer via a host computer (test control computer) and downloaded to the test equipment (such as ATE), guiding the test instrument to send specific signals to the DUT and compare the output results.

[0058] In one possible implementation, the software sets whether a strobe clock (i.e., a multi-edge sampling clock signal) is needed in each TS (Transient Switch) according to the test requirements. If needed, it is configured as STRB1 or STRB2 according to the resolution. Specifically, the resolution can be 62.5 ps.

[0059] In one possible implementation, the value is configured to zero if not needed, and this configuration value is sent to the FPGA along with other parameters within the TS and stored in the designated RAM.

[0060] In one possible implementation, the test information for each cycle is parsed to obtain the clock configuration information for each cycle. The clock configuration information includes configuration parameter addresses and data. Specifically, the clock configuration information is in the form of configuration parameter address + data. For example, in the first line of the pattern, the configuration parameter address is 1, and the data includes the test configuration parameters, i.e., the configuration parameters of the strobe clock; in the second line of the pattern, the configuration parameter address is 2, and the data also includes the test configuration parameters; the test configuration parameters are then sent to the FPGA's RAM.

[0061] In one possible implementation, when a TS (Time Switch) is reached, the STRB1 and STRB2 values ​​are read in real time from the corresponding address in RAM based on the PC (Program Counter) controlled by the Sequence. These values ​​determine the positions of the rising and falling edges. Specifically, a strobe clock is generally required when reading data from the DUT (Data Under Test), but not when writing data to a specific address in the DUT. A strobe clock is required only within a specific line of a pattern, if that line is a read operation.

[0062] In one possible implementation, test configuration parameters are obtained from the address of the configuration parameters stored in the test information for each cycle. The test configuration parameters include a first configuration parameter and a second configuration parameter, where the first configuration parameter is STRB1 and the second configuration parameter is STRB2.

[0063] In one possible implementation, the first configuration parameter and the second configuration parameter are compared to obtain a comparison result.

[0064] In one possible implementation, if the comparison result indicates that the first configuration parameter is equal to the second configuration parameter, the first configuration parameter is determined to be the clock configuration information. If STRB1 = STRB2, the DUT under test may not require a dual-edge sampling clock, i.e., the DUT under test does not require a multi-edge sampling clock signal, and the clock configuration information of the periodic test information corresponding to the comparison result is determined to be STRB1.

[0065] In a possible implementation, when the comparison result indicates that the first configuration parameter is greater than or less than the second configuration parameter. That is, if STRB1 < STRB2 or STRB1 > STRB2, which means the DUT under test requires double-edge clock sampling, determine that the clock configuration information of the cycle test information corresponding to the comparison result is STRB1 and STRB2.

[0066] In this implementation, describe the clock configuration information of each cycle test information in each cycle test information, and determine the clock configuration information of the cycle test information based on the test configuration parameters stored at the configuration parameter address of each cycle test information, so as to configure different clock sampling information in real time, facilitating the subsequent generation of a dynamically adjustable and configurable sampling clock signal.

[0067] In step S105, generate a sampling clock signal corresponding to each cycle test information based on the clock configuration information of each cycle test information.

[0068] In a possible implementation, the generating a sampling clock signal corresponding to each cycle test information based on the clock configuration information of each cycle test information includes: Determine the time resolution and test period of the test information; the test period is used to divide the test information into multiple cycle test information; Determine the initial sampling sequence of each cycle test information based on the time resolution and the test period; Generate a sampling clock signal corresponding to each cycle test information based on the clock configuration information and the initial sampling sequence of each cycle test information.

[0069] In a possible implementation, the initial sampling sequence includes multiple configurable bits, and the initial value corresponding to each configurable bit is a first value, and the first configuration parameter represents a high-level valid bit; The generating a sampling clock signal corresponding to each cycle test information based on the clock configuration information and the initial sampling sequence of each cycle test information includes: When the clock configuration information is the first configuration parameter, determine the target configuration bit from the multiple configurable bits based on the first configuration parameter; Modify the initial values corresponding to the target configuration bit and the configurable bits after the target configuration bit to a second value to obtain a single-edge sampling clock signal; the first value is less than the second value; Determine the single-edge sampling clock signal as the sampling clock signal of the cycle test information corresponding to the clock configuration information.

[0070] In a possible implementation, the second configuration parameter represents a low-level valid bit, The method further includes: When the clock configuration information is the first configuration parameter and the second configuration parameter, determining a first target configuration bit from multiple configurable bits based on the first configuration parameter, and determining a second target configuration bit from multiple configurable bits based on the second configuration parameter; Modifying the initial values corresponding to the configurable bits between the first target configuration bit, the second target configuration bit, and the first target configuration bit and the second target configuration bit to the second value to obtain a multi-edge sampling clock signal; Determining that the multi-edge sampling clock signal is the sampling clock signal of the periodic test information corresponding to the clock configuration information.

[0071] In a possible implementation, the sampling clock signal is generated by a high-speed transceiver, and the high-speed transceiver is a hardware PHY integrated inside the FPGA chip. Through this high-speed transceiver, a strobe signal is sent and used as the sampling clock signal for the receiving side to read data from the DUT. Specifically, the sampling clock signal can be sent to the DUT through the TG.

[0072] In a possible implementation, the first value is less than the second value. Specifically, the first value can be 0 and the second value can be 1.

[0073] In a possible implementation, a high-speed transceiver is used, and the number of strobe points can be configured. Taking TS = 10ns as an example, the number of configurable points of strobeclk1 can be 10ns / 62.5ps = 160, and similarly, the number of configurable points of strobeclk2 can be 159, and the minimum interval between strobeclk1 and strobeclk2 is 62.5ps.

[0074] In a possible implementation, the magnitudes of STRB1 and STRB2 are judged. If STRB1 < STRB2, then the 160-bit data TS_D is configured as {0001(STRB1)11………111(STRB2)000000}, that is, the data value before the first target configuration bit corresponding to STRB1 is 0, the values of the configurable bits between STRB1 and STRB2 are 1, and the value after the second target configuration bit corresponding to STRB2 is 0.

[0075] In one possible implementation, if STRB1 > STRB2, then the 160-bit data TS_D is configured as {0001(STRB2)1111………1(STRB1)000000}, that is, the data value before the second target configuration bit corresponding to STRB2 is 0, the configuration bit between STRB2 and STRB1 is 1, and the value after the first target configuration bit corresponding to STRB1 is 0.

[0076] In one possible implementation, if STRB1=STRB2, the DUT being tested may not require multi-edge clock sampling, such as NAND FALSH. Therefore, the 160-bit data TS_D is configured as {0001(STRB1)11………111}, that is, all the data before the first target configuration bit corresponding to STRB1 is zero, and all the data after it is 1.

[0077] In one possible implementation, after the above configuration, the following can be obtained in real time: Figure 4 The sampling clock signal strobe_clock is shown. The data TS_D of the TS is stored in the corresponding RAM according to the parallel bit width of the high-speed transceiver. The TS_D is sent to the receiver within the TS as the acquisition clock for acquiring data from DDR.

[0078] In this implementation, the initial sampling sequence of the test information for each cycle is determined based on the set time resolution and the set test cycle. Based on the clock configuration information and the initial sampling sequence of the test information for each cycle, the sampling clock signal corresponding to the test information for each cycle is generated in real time, which improves the flexibility and accuracy of the sampling clock signal configuration and increases the test rate of the automatic test equipment.

[0079] In one possible implementation, the test configuration parameters further include a third configuration parameter, which represents a plurality of active high-level bits. The third configuration parameter includes N high-level configuration parameters, where N is greater than a first number and N is less than or equal to a second number, and the second number is greater than the first number. The method further includes: When the clock configuration information is the third configuration parameter, the target configuration bit is determined from multiple configurable bits based on each high-level configuration parameter; The initial values ​​of the target configuration bit corresponding to each high-level configuration parameter and the configurable bits following the target configuration bit are modified to the second value to obtain the initial modification sequence corresponding to each high-level configuration parameter. Based on the initial modification sequence corresponding to each high-level configuration parameter, a bitwise XOR calculation is performed to obtain the sampling clock signal of the periodic test information corresponding to the third configuration parameter.

[0080] In one possible implementation, the software sets whether a strobe clock is needed in each TS as described in the pattern according to the test requirements. If a strobe clock is needed, the clock configuration information is determined as the third configuration parameter. The N high-level configuration parameters are configured as STRB1, STRB2...STRBN at a resolution of 62.5ps. Specifically, N is generally limited according to customer needs, 1≤N≤16. In one possible implementation, if a strobe clock is not required, the configuration is set to zero, and this configuration value is sent to the FPGA along with other parameters within the TS and stored in a designated RAM.

[0081] In one possible implementation, when the TS is reached, the values ​​of STRB1, STRB2...STRBN are read from the corresponding addresses in RAM according to the PC pointer controlled by the Sequence, and the position of their values ​​is determined.

[0082] In one possible implementation, corresponding strobe clock signals are dynamically generated in parallel based on the values ​​of STRB1~STRBN for each TS. Because a high-speed transceiver is used, a large number of strobe points can be configured. For example, with TS=10ns, strobeclk1 can be configured with 10ns / 62.5ps=160 points, similarly strobeclk2 with 159 points, and strobeclkN with 144 points. The minimum interval between strobeclk1 and strobeclkN is 62.5ps. Specifically, each strobe clock can be configured with up to 160 points, supporting real-time dynamic configuration, multiple edges, online modification, simple setup, and high flexibility.

[0083] In one possible implementation, N (the number of STRBs) 160-bit registers are defined, meaning one register corresponds to each STRB. The position of the 160 bits in register regn is determined based on the value (position) of STRBN (1≤N≤16), and then the values ​​before and after the corresponding bits in register regn are assigned. For example, if STRBN=15, then the 160 bits of regn are assigned the following values: 000…1 (bit 15)111…1, meaning the values ​​before bit 15 are 0, and the values ​​after bit 15 are 1.

[0084] In one possible implementation, all STRBN values ​​are determined in parallel based on their values ​​to determine the corresponding regn160-bit register values. This gives us N 160-bit arrays, which are the initial modification sequences corresponding to the N high-level configuration parameters.

[0085] In one possible implementation, a bitwise XOR operation is performed based on the initial modification sequence corresponding to each high-level configuration parameter. This involves XORing N 160-bit arrays bit by bit to obtain the sampling clock signal for the periodic test information corresponding to the third configuration parameter. This yields the strobe signal strobeclk configured within the TS. Figure 5 As shown.

[0086] In one possible implementation, after the above calculations, the following can be obtained: Figure 5 The clock signal strobe_clock is shown. The data TS_D of the TS is stored in the corresponding RAM according to the parallel bit width of the high-speed transceiver. The TS_D is sent to the receiver within the TS as the acquisition clock for acquiring data from DDR.

[0087] In this implementation, when the periodic test information representation requires multi-edge clock signals, the sampling clock signal corresponding to each periodic test information is generated in real time based on the clock configuration information and the initial sampling sequence. This improves the flexibility and accuracy of the sampling clock signal configuration and meets the requirements of sampling clock signals in different scenarios.

[0088] In step S107, the product under test is tested based on the sampling clock signal corresponding to each cycle test information to obtain test data for each cycle test information.

[0089] In one possible implementation, the step of testing the product under test based on the sampling clock signal corresponding to each cycle of test information to obtain test data for each cycle of test information includes: Obtain the test input data corresponding to the test information for each cycle; The test input data is input into the product under test to obtain the output data of the test information for each cycle. The output data of each cycle of test information is sampled based on the sampling clock signal corresponding to each cycle of test information to obtain the test data of each cycle of test information.

[0090] In one possible implementation, such as Figure 6 The data acquisition module shown sets the comparison level threshold for the PE chip. Since DDR testing typically uses dual-level testing, it is necessary to set thresholds for both high-level (VOH) and low-level (VOL) levels for internal level comparison within the PE chip. Figure 6 As shown, the compared signals sig_H and sig_L will be output to the FPGA.

[0091] In one possible implementation, Pattern first sends a read command to the target address according to the timing requirements of each read command in the DUT manual. The FPGA uses the strobe_clock issued by the high-speed transceiver as the sampling clock to read the parallel data Rx_d_H / Rx_d_L issued by the DUT and save it to the FIFO. Specifically, the data bit width of DDR is such as 8 bits, 16 bits, etc.

[0092] In one possible implementation, test input data corresponding to each cycle of test information is obtained, the test input data is input to the product under test to obtain the output data of each cycle of test information, and the output data of each cycle of test information is sampled based on the sampling clock signal corresponding to each cycle of test information to obtain the test data of each cycle of test information.

[0093] In one possible implementation, the comparison level threshold of the PE chip is first set. Since DDR testing typically uses dual-level testing, thresholds for both the high-level (VOH) and low-level (VOL) levels need to be set for internal level comparison within the PE chip. Figure 3 As shown. The compared signals sig_H and sig_L will be output to the FPGA.

[0094] In this implementation, the product under test is tested based on the sampling clock signal corresponding to each cycle of test information to obtain test data for each cycle of test information. This facilitates subsequent analysis based on the test data and expected data for each cycle of test information to determine whether the test has passed and to quickly locate errors when they occur during testing.

[0095] In step S109, the test data and expected data of each cycle test information are analyzed to obtain the test results of the product under test.

[0096] In one possible implementation, the analysis of the test data based on the test information of each cycle and the expected data of the test information of each cycle to obtain the test results of the product under test includes: The test data for each period of test information is matched with the expected data for each period of test information to obtain the matching result for each period of test information; If the matching result indicates that the test data does not match the expected data, the periodic test information corresponding to the mismatched test data and the expected data is determined to be abnormal test information. The test results of the product under test are generated based on the abnormal test information.

[0097] In one possible implementation, test data for each cycle of test information, namely Rd_dout_H / Rd_dout_L, is read from the FIFO.

[0098] In one possible implementation, the expected data Exp_d is the data WR_d written to the DUT target address during pattern runtime. The written data can be obtained after a certain period of delay.

[0099] In one possible implementation, the test data Rd_dout_H / Rd_dout_L of each cycle test information is compared with the expected data Exp_d of each cycle test information. Data analysis and comparison are performed based on the values ​​of the expected data Exp_d and the received data Rd_dout_H / Rd_dout_L. Parallel comparison is used, and 8 / 16 bit width comparison is performed simultaneously. The truth table of the comparison logic combined with the output logic of the selected PE chip is shown in Table 1.

[0100] Table 1 Truth Table for Comparison Logic

[0101] In one possible implementation, as shown in Table 1, if the received data Rd_dout_H / Rd_dout_L are both 1 and the expected data Exp_d is 1, then the data is correct and marked as Pass; otherwise, if Rd_dout_H / Rd_dout_L are both incorrect, then it is marked as Fail.

[0102] In one possible implementation, as shown in Table 1, if the received data Rd_dout_H / Rd_dout_L are both 0 and the expected data is 0, then the data is correct and marked as Pass; otherwise, if Rd_dout_H / Rd_dout_L are both incorrect, then it is marked as Fail.

[0103] In one possible implementation, based on the comparison result, if any bit in the corresponding TS is faulty, the address, Rd_dout_H / Rd_dout_L, Exp_d, and STRB1 and STRB2 of that TS are stored in their respective registers and then saved to the FPGA's external DDR via the AXI interface. Finally, after the pattern execution is complete, the error data is read from the DDR via the Aurror interface and uploaded to the software for customer analysis. Specifically, a dynamically adjustable and configurable strobe signal is generated when reading data back from the DDR. By adjusting the high and low level thresholds within the PE, the collected data is compared with the expected data, and their equality is determined to identify the faulty data. The corresponding address, faulty data, and expected data are recorded to provide accurate information to the customer.

[0104] In this implementation, the test data and expected data of each test cycle are analyzed to obtain the test results of the product under test. The address, error data, expected data and other information corresponding to the test error are recorded to provide customers with accurate information and improve the readability of the test results.

[0105] The above embodiments of this application have the following beneficial effects: This application obtains test information of the product under test in response to test command information; the test information includes multiple cycle test information; each cycle test information is parsed to obtain clock configuration information for each cycle test information; a sampling clock signal corresponding to each cycle test information is generated based on the clock configuration information of each cycle test information; the product under test is tested based on the sampling clock signal corresponding to each cycle test information to obtain test data for each cycle test information; the test data and expected data of each cycle test information are analyzed to obtain the test result of the product under test. By testing each cycle test information as a segment, setting clock configuration information based on each cycle test information, and generating a sampling clock signal corresponding to each cycle test information, a dynamically adjustable and configurable sampling clock signal is provided. Based on this sampling clock information, the product under test is tested to obtain test results, providing accurate information to customers and solving the problem of how to improve the test speed of test equipment.

[0106] like Figure 7 As shown in the embodiments, this application also discloses a testing apparatus 700 for an automatic testing device, used to implement the testing apparatus method for the automatic testing device described in any of the above embodiments, the apparatus comprising: The test information acquisition module 701 is used to acquire test information of the product to be tested in response to test command information; the test information includes test information of multiple cycles; The parsing module 702 is used to parse the test information of each cycle to obtain the clock configuration information of each cycle test information; The clock signal generation module 703 is used to generate a sampling clock signal corresponding to each cycle of test information based on the clock configuration information of each cycle of test information. Test module 704 is used to test the product under test based on the sampling clock signal corresponding to each cycle test information to obtain test data for each cycle test information; The analysis module 705 is used to analyze the test data and expected data of each test cycle based on the test information of each cycle to obtain the test results of the product under test.

[0107] In one possible implementation, the test information for each cycle includes a configuration parameter address, and the parsing module 702 is used for: Retrieve the test configuration parameters stored in the test information for each period; the test configuration parameters include a first configuration parameter and a second configuration parameter. The first configuration parameter and the second configuration parameter are compared to obtain the comparison result; Based on the comparison results, the clock configuration information for each cycle of test information is determined.

[0108] In one possible implementation, the parsing module 702 is further configured to: If the comparison result indicates that the first configuration parameter is equal to the second configuration parameter, the first configuration parameter is determined to be the clock configuration information; If the comparison result indicates that the first configuration parameter is greater than or less than the second configuration parameter, the first configuration parameter and the second configuration parameter are determined to be the clock configuration information.

[0109] In one possible implementation, the clock signal generation module 703 is used for: Determine the temporal resolution and test period of the test information; the test period is used to divide the test information into multiple test periods. The initial sampling sequence of test information for each period is determined based on the time resolution and the test period; Based on the clock configuration information and initial sampling sequence of each cycle of test information, a sampling clock signal corresponding to each cycle of test information is generated.

[0110] In one possible implementation, the initial sampling sequence includes multiple configurable bits, each configurable bit corresponding to an initial value of a first value, wherein the first configuration parameter represents a high-level active bit; the clock signal generation module 703 is further configured to: When the clock configuration information is the first configuration parameter, the target configuration bit is determined from multiple configurable bits based on the first configuration parameter; The initial values ​​corresponding to the target configuration bit and the configurable bits following the target configuration bit are modified to the second value to obtain a single-edge sampling clock signal; the first value is less than the second value; The single-edge sampling clock signal is determined to be the sampling clock signal of the periodic test information corresponding to the clock configuration information.

[0111] In one possible implementation, the second configuration parameter represents a low-level active bit, and the clock signal generation module 703 is further configured to: When the clock configuration information is the first configuration parameter and the second configuration parameter, a first target configuration bit is determined from multiple configurable bits based on the first configuration parameter, and a second target configuration bit is determined from multiple configurable bits based on the second configuration parameter; Modify the initial values ​​of the first target configuration bit, the second target configuration bit, and the configurable bits between the first target configuration bit and the second target configuration bit to the second value to obtain a multi-edge sampling clock signal; The multi-edge sampling clock signal is determined to be the sampling clock signal of the periodic test information corresponding to the clock configuration information.

[0112] In one possible implementation, the test configuration parameters further include a third configuration parameter, which represents a plurality of active high-level bits. The third configuration parameter includes N high-level configuration parameters, where N is greater than a first number and N is less than or equal to a second number, and the second number is greater than the first number. The clock signal generation module 703 is also used for: When the clock configuration information is the third configuration parameter, the target configuration bit is determined from multiple configurable bits based on each high-level configuration parameter; The initial values ​​of the target configuration bit corresponding to each high-level configuration parameter and the configurable bits following the target configuration bit are modified to the second value to obtain the initial modification sequence corresponding to each high-level configuration parameter. Based on the initial modification sequence corresponding to each high-level configuration parameter, a bitwise XOR calculation is performed to obtain the sampling clock signal of the periodic test information corresponding to the third configuration parameter.

[0113] In one possible implementation, the test module 704 is used for: Obtain the test input data corresponding to the test information for each cycle; The test input data is input into the product under test to obtain the output data of the test information for each cycle. The output data of each cycle of test information is sampled based on the sampling clock signal corresponding to each cycle of test information to obtain the test data of each cycle of test information.

[0114] In one possible implementation, the analysis module 705 is used for: The test data for each period of test information is matched with the expected data for each period of test information to obtain the matching result for each period of test information; If the matching result indicates that the test data does not match the expected data, the periodic test information corresponding to the mismatched test data and the expected data is determined to be abnormal test information. The test results of the product under test are generated based on the abnormal test information.

[0115] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0116] This application provides an electronic device including a processor and a memory. The memory stores at least one instruction or at least one program. The at least one instruction or at least one program is loaded and executed by the processor to implement the testing method of any of the automatic testing devices provided in the above method embodiments.

[0117] Memory can be used to store software programs and modules. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory. Memory can primarily include a program storage area and a data storage area. The program storage area can store the operating system, application programs required for the functions, etc.; the data storage area can store data created based on the use of the device, etc. Furthermore, memory can include high-speed random access memory, and can also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, memory can also include a memory controller to provide the processor with access to the memory.

[0118] Embodiments of this application also provide a computer-readable storage medium, which can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a test method of an automatic test device. The at least one instruction or the at least one program is loaded and executed by the processor to implement any of the test methods of the automatic test device provided in the above-described method embodiments.

[0119] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0120] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0121] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0122] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0123] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A testing method for an automatic testing device, characterized in that, The method includes: In response to test command information, the test information of the product to be tested is obtained; the test information includes test information from multiple cycles. The test information for each cycle is parsed to obtain the clock configuration information for each cycle of test information; Based on the clock configuration information of each cycle test information, a sampling clock signal corresponding to each cycle test information is generated; The product under test is tested based on the sampling clock signal corresponding to the test information of each cycle, and the test data of each cycle test information is obtained. The test results of the product under test are obtained by analyzing the test data and expected data of each test cycle.

2. The testing method of the automatic testing equipment according to claim 1, characterized in that, The test information for each cycle includes the address of the configuration parameters. The step of parsing the test information for each cycle to obtain the clock configuration information for each cycle of test information includes: Retrieve the test configuration parameters stored in the test information for each period; the test configuration parameters include a first configuration parameter and a second configuration parameter. The first configuration parameter and the second configuration parameter are compared to obtain the comparison result; Based on the comparison results, the clock configuration information for each cycle of test information is determined.

3. The testing method of the automatic testing equipment according to claim 2, characterized in that, The clock configuration information for determining the test information for each cycle based on the comparison results includes: If the comparison result indicates that the first configuration parameter is equal to the second configuration parameter, the first configuration parameter is determined to be the clock configuration information; If the comparison result indicates that the first configuration parameter is greater than or less than the second configuration parameter, the first configuration parameter and the second configuration parameter are determined to be the clock configuration information.

4. The testing method of the automatic testing equipment according to claim 3, characterized in that, The generation of the sampling clock signal corresponding to each cycle of test information based on the clock configuration information of each cycle includes: Determine the temporal resolution and test period of the test information; the test period is used to divide the test information into multiple test periods. The initial sampling sequence of test information for each period is determined based on the time resolution and the test period; Based on the clock configuration information and initial sampling sequence of each cycle of test information, a sampling clock signal corresponding to each cycle of test information is generated.

5. The testing method of the automatic testing equipment according to claim 4, characterized in that, The initial sampling sequence includes multiple configurable bits, and the initial value corresponding to each configurable bit is a first value. The first configuration parameter represents a high-level active bit. The generation of the sampling clock signal corresponding to each cycle of test information, based on the clock configuration information and initial sampling sequence of each cycle of test information, includes: When the clock configuration information is the first configuration parameter, the target configuration bit is determined from multiple configurable bits based on the first configuration parameter; The initial values ​​corresponding to the target configuration bit and the configurable bits following the target configuration bit are modified to the second value to obtain a single-edge sampling clock signal; the first value is less than the second value; The single-edge sampling clock signal is determined to be the sampling clock signal of the periodic test information corresponding to the clock configuration information.

6. The testing method of the automatic testing equipment according to claim 5, characterized in that, The second configuration parameter represents the low-level active bit. The method further includes: When the clock configuration information is the first configuration parameter and the second configuration parameter, a first target configuration bit is determined from multiple configurable bits based on the first configuration parameter, and a second target configuration bit is determined from multiple configurable bits based on the second configuration parameter; Modify the initial values ​​of the first target configuration bit, the second target configuration bit, and the configurable bits between the first target configuration bit and the second target configuration bit to the second value to obtain a multi-edge sampling clock signal; The multi-edge sampling clock signal is determined to be the sampling clock signal of the periodic test information corresponding to the clock configuration information.

7. The testing method of the automatic testing equipment according to claim 5, characterized in that, The test configuration parameters also include a third configuration parameter, which represents multiple active high-level bits. The third configuration parameter includes N high-level configuration parameters, where N is greater than a first number and N is less than or equal to a second number, and the second number is greater than the first number. The method further includes: When the clock configuration information is the third configuration parameter, the target configuration bit is determined from multiple configurable bits based on each high-level configuration parameter; The initial values ​​of the target configuration bit corresponding to each high-level configuration parameter and the configurable bits following the target configuration bit are modified to the second value to obtain the initial modification sequence corresponding to each high-level configuration parameter. Based on the initial modification sequence corresponding to each high-level configuration parameter, a bitwise XOR calculation is performed to obtain the sampling clock signal of the periodic test information corresponding to the third configuration parameter.

8. The testing method of the automatic testing equipment according to claim 1, characterized in that, The test is performed on the product under test based on the sampling clock signal corresponding to each cycle of test information to obtain test data for each cycle of test information, including: Obtain the test input data corresponding to the test information for each cycle; The test input data is input into the product under test to obtain the output data of the test information for each cycle. The output data of each cycle of test information is sampled based on the sampling clock signal corresponding to each cycle of test information to obtain the test data of each cycle of test information.

9. The testing method of the automatic testing equipment according to claim 1, characterized in that, The test data based on the test information of each cycle and the expected data of the test information of each cycle are analyzed to obtain the test results of the product under test, including: The test data for each period of test information is matched with the expected data for each period of test information to obtain the matching result for each period of test information; If the matching result indicates that the test data does not match the expected data, the periodic test information corresponding to the mismatched test data and the expected data is determined to be abnormal test information. The test results of the product under test are generated based on the abnormal test information.

10. A testing device for an automatic testing equipment, characterized in that, The device includes: The test information acquisition module is used to acquire test information of the product to be tested in response to test command information; the test information includes test information from multiple cycles. The parsing module is used to parse the test information for each cycle to obtain the clock configuration information for each cycle of test information; The clock signal generation module is used to generate the sampling clock signal corresponding to each cycle of test information based on the clock configuration information of each cycle of test information. The testing module is used to test the product under test based on the sampling clock signal corresponding to the test information of each cycle, and to obtain the test data of the test information of each cycle. The analysis module is used to analyze the test data and expected data of each test cycle to obtain the test results of the product under test.

11. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory stores at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement the test method of the automatic test device as described in any one of claims 1 to 9.

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