Processors, chips, electronic devices and data processing methods

Abstract

The application discloses a processor, a chip, an electronic device and a data processing method. The processor comprises a floating point operation unit and a category detection unit, and an output end of the floating point operation unit is connected to an input end of the category detection unit. The application connects a category detection unit after the floating point operation unit used for performing a floating point operation operation. Thus, the floating point operation result can be detected by a hardware pipeline to belong to or not belong to a certain numerical category, and an additional category detection instruction does not need to be introduced into the processor, and thus the instruction overhead in the processor is saved.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a processor, chip, electronic device, and data processing method. Background Technology

[0002] The floating-point arithmetic unit in the processor is responsible for generating floating-point arithmetic results according to the relevant binary floating-point arithmetic standard.

[0003] However, the numerical category of the floating-point operation results generated by the floating-point unit is not fixed. For example, when overflow, illegal operation, or insufficient precision occurs during the operation, the floating-point unit will passively generate floating-point operation results of various numerical categories such as Not a Number (NaN), Infinity, Denormalized Number, and positive or negative zero.

[0004] In related technologies, in order to detect whether the above floating-point operation result belongs to or does not belong to a certain numerical category, in addition to having the processor execute floating-point operation instructions, the processor also needs to execute an additional category detection instruction, which increases the instruction overhead in the processor. Summary of the Invention

[0005] This application provides a processor, a chip, an electronic device, and a data processing method. The technical solutions provided by this application are as follows: According to one aspect of the embodiments of this application, a processor is provided, the processor including a floating-point arithmetic unit and a category detection unit, wherein the output terminal of the floating-point arithmetic unit is connected to the input terminal of the category detection unit; The floating-point arithmetic unit is used to perform floating-point arithmetic operations on the received operation array according to the operation instructions in the first floating-point arithmetic instruction, and obtain the floating-point arithmetic result of the operation array. The first floating-point arithmetic instruction further includes category indication information, which is used to indicate at least one numerical category from a pre-configured set of M numerical categories, where M is an integer greater than 1. The category detection unit is used to determine, from the M numerical categories, the first numerical category indicated by the category indication information; The category detection unit is further configured to detect whether the floating-point operation result of the operation array belongs to the first numerical category, so as to generate a first numerical category identifier, wherein the first numerical category identifier is used to indicate whether the floating-point operation result of the operation array belongs to or does not belong to the first numerical category.

[0006] According to one aspect of the embodiments of this application, a chip is provided, the chip including the processor described above.

[0007] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including the processor described above.

[0008] According to one aspect of the embodiments of this application, a data processing method is provided, applied to a processor, the processor including a floating-point arithmetic unit and a category detection unit, the output terminal of the floating-point arithmetic unit being connected to the input terminal of the category detection unit; the method includes: The floating-point arithmetic unit performs floating-point arithmetic operations on the received operation array according to the operation instructions in the first floating-point arithmetic instruction to obtain the floating-point arithmetic result of the operation array. The first floating-point arithmetic instruction further includes category indication information, which is used to indicate at least one numerical category from a pre-configured set of M numerical categories, where M is an integer greater than 1. The category detection unit determines the first numerical category indicated by the category indication information from the M numerical categories; The category detection unit detects whether the floating-point operation result of the operation array belongs to the first numerical category, so as to generate a first numerical category identifier, wherein the first numerical category identifier is used to indicate whether the floating-point operation result of the operation array belongs to or does not belong to the first numerical category.

[0009] The technical solutions provided in this application have at least the following beneficial effects: On the one hand, a category detection unit is connected after the floating-point arithmetic unit used to perform floating-point operations. This allows for hardware pipelined detection of whether the floating-point operation result belongs to or does not belong to a certain numerical category, eliminating the need to introduce additional category detection instructions into the processor and thus saving instruction overhead. On the other hand, by setting category indication information in the floating-point arithmetic instructions to indicate at least one numerical category from a pre-configured set of M numerical categories, and by having the category detection unit detect whether the floating-point operation result belongs to the numerical category indicated by the category indication information, the category detection function of the category detection unit can flexibly perform detection for multiple numerical categories, rather than targeting only a single numerical category. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a processor provided in one embodiment of this application; Figure 2 This is a schematic diagram of a processor provided in another embodiment of this application; Figure 3 This is a schematic diagram of a first storage unit and a second storage unit provided in one embodiment of this application; Figure 4 This is a flowchart illustrating an example of an infinite number detection method provided in one embodiment of this application; Figure 5This is a flowchart illustrating an example of a positive and negative zero detection method provided in one embodiment of this application; Figure 6 This is a schematic diagram of the second entry provided in one embodiment of this application; Figure 7 This is a flowchart of a thread-beam-level instruction processing procedure provided in one embodiment of this application; Figure 8 This is a flowchart of a data processing method provided in one embodiment of this application. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0012] In binary floating-point arithmetic standards, such as the IEEE 754 standard, floating-point numbers can be divided into multiple numerical categories. Therefore, the floating-point arithmetic unit in a processor may also produce floating-point operation results of multiple numerical categories. In this context, the following problems have been found in the floating-point number processing schemes for processors provided by related technologies: 1. Lack of a unified explicit representation of numerical categories.

[0013] Although the floating-point arithmetic unit in the processor can generate various floating-point arithmetic results according to the IEEE 754 rules, including positive and negative zero, positive and negative denormalized numbers, positive and negative infinity, NaN and positive constants, these numerical categories are only implicit in the bit representation of the results and cannot be substantially utilized.

[0014] 2. Positive and negative attribute information is difficult to utilize effectively in abnormal scenarios.

[0015] In relevant implementations, numerical categories such as +0.0 and -0.0, +Infinity and -Infinity, and positive and negative denormal are treated equally in most computational paths. Their sign bit information is not systematically incorporated into exception handling or control logic, resulting in the weakening or even loss of numerical semantics in the hardware pipeline.

[0016] 3. Reliance on software-based judgment leads to a decline in performance and energy efficiency.

[0017] When an application or runtime system needs to be aware of the numerical category of a floating-point operation result, it typically relies on additional instruction sequences or branch decisions. This approach is prone to thread divergence in the SIMD (Single Instruction Multiple Data) / SIMT (Single Instruction Multiple Threads) parallel execution model of a GPU (Graphics Processing Unit), increasing instruction overhead and reducing overall throughput and energy efficiency.

[0018] 4. Insufficient granularity of exception and debugging information.

[0019] Floating-point exceptions or status information often exist in a global or coarse-grained form, making it difficult to accurately associate them with specific floating-point instructions, threads, or warps. This limits their application value in scenarios such as numerical stability analysis, debugging, and fault-tolerant computation.

[0020] 5. It is difficult to support configurable and differentiated numerical processing strategies.

[0021] GPUs typically handle special values ​​such as denormal, infinity, and NaN in a fixed or highly restricted manner, lacking the ability to flexibly configure them at the hardware level based on execution mode, application scenario, or instruction attributes.

[0022] In response to the above problems, this application provides a design for performing numerical category detection on the floating-point operation result through a hardware pipeline after the floating-point operation instruction is executed. This will be described in more detail in the following embodiments.

[0023] Please refer to Figure 1 The diagram illustrates a processor 100 provided in one embodiment of this application. The processor 100 includes a floating-point arithmetic unit 10 and a category detection unit 20. The output of the floating-point arithmetic unit 10 is connected to the input of the category detection unit 20.

[0024] The floating-point arithmetic unit 10 is used to perform floating-point arithmetic operations on the received operand array according to the operation instructions in the first floating-point arithmetic instruction, and obtain the floating-point arithmetic result of the operand array.

[0025] The first floating-point instruction also includes category indication information, which is used to indicate at least one numerical category from a pre-configured set of M numerical categories, where M is an integer greater than 1.

[0026] In some embodiments, the processor 100 is a GPU.

[0027] In some embodiments, the processor 100 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. The processor 100 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 100 may further include an AI (Artificial Intelligence) processor for handling computational operations related to machine learning.

[0028] The aforementioned first floating-point arithmetic instruction can be any instruction in the processor 100 used to implement floating-point arithmetic. The aforementioned operand array includes at least one operand targeted by the first floating-point arithmetic instruction. For example, if the first floating-point arithmetic instruction is an addition instruction, the aforementioned operand array includes two operands to be added. For example, if the first floating-point arithmetic instruction is a subtraction instruction, the aforementioned operand array includes two operands to be subtracted.

[0029] In some embodiments, the above M numerical categories include at least two of the following numerical categories: equal to 0, greater than 0, less than 0, greater than or equal to 0, less than or equal to 0, denormalized number, infinity, normalized number, and not-numerical (NaN).

[0030] In some embodiments, the above M numerical categories include at least two of the following numerical categories: equal to 0, greater than 0, less than 0, greater than or equal to 0, less than or equal to 0, positive 0, negative 0, positive denormalized number (+denormal), negative denormalized number (-denormal), positive infinity (+infinity), negative infinity (-infinity), positive normalized number (+normal), negative normalized number (-normal), and not a number (NaN).

[0031] As can be seen, this application supports the use of a unified hardware design to perform judgments on different numerical categories of floating-point numbers. It can explicitly distinguish positive and negative attributes and different numerical ranges at the hardware level, thereby meeting the detection needs of various numerical categories and has good versatility.

[0032] The above M numerical categories can all be determined by parsing the sign bit, exponent field, and mantissa field of the floating-point number. For specific rules, please refer to the examples below, which will not be elaborated here.

[0033] In some embodiments, the category indication information includes M indicator bits, where one indicator bit corresponds to a numerical category, and different indicator bits among the M indicator bits correspond to different numerical categories. In some embodiments, at least one numerical category is indicated by setting the indicator bits corresponding to at least one numerical category to 1 and the indicator bits corresponding to other numerical categories to 0. In other embodiments, at least one numerical category is indicated by setting the indicator bits corresponding to at least one numerical category to 0 and the indicator bits corresponding to other numerical categories to 1.

[0034] The category detection unit 20 is used to determine the first numerical category indicated by the category indication information from M numerical categories.

[0035] In some embodiments, the category detection unit 20 is used to parse the M indicator bits included in the category indication information in the first floating-point arithmetic instruction to determine the first numerical category indicated by the category indication information.

[0036] The category detection unit 20 is also used to detect whether the floating-point operation result of the operand array belongs to the first numerical category, so as to generate the first numerical category identifier.

[0037] The first numerical category identifier indicates whether the floating-point operation result of the operand belongs to or does not belong to the first numerical category. The first numerical category can be any numerical category indicated by the category indication information in the first floating-point operation instruction.

[0038] In some embodiments, a first value category identifier of 1 indicates that the floating-point operation result of the operand belongs to the first value category, and a first value category identifier of 0 indicates that the floating-point operation result of the operand does not belong to the first value category. In other embodiments, a first value category identifier of 0 indicates that the floating-point operation result of the operand belongs to the first value category, and a first value category identifier of 1 indicates that the floating-point operation result of the operand does not belong to the first value category.

[0039] The first numerical category can be any one of the M numerical categories.

[0040] In some embodiments, the category detection unit 20 is used to detect whether the sign bit, exponent field and mantissa field of the floating-point operation result of the operand array conform to the discrimination rules of the first numerical category, so as to generate the first numerical category identifier.

[0041] The first numerical category discrimination rule refers to the rule for determining whether a floating-point number belongs to the first numerical category.

[0042] Optionally, if the sign bit, exponent field, and mantissa field of the floating-point operation result of the operand satisfy the discrimination rules of the first numerical category, the category detection unit 20 generates a first numerical category identifier indicating that the floating-point operation result of the operand belongs to the first numerical category. If the sign bit, exponent field, and mantissa field of the floating-point operation result of the operand do not satisfy the discrimination rules of the first numerical category, the category detection unit 20 generates a first numerical category identifier indicating that the floating-point operation result of the operand does not belong to the first numerical category.

[0043] Below, we will introduce some rules for classifying numerical values ​​by example: (1) The criteria for determining greater than zero are: the sign bit is 0, the exponent field and the mantissa field are not both 0, and it is not a non-numerical value.

[0044] (2) The criteria for being greater than or equal to 0 are: the sign bit is 0 or the exponent field and mantissa field are both 0 and not non-numerical.

[0045] (3) Rules for determining less than zero: the sign bit is 1, the exponent field and the mantissa field are not both 0, and it is not a non-numerical value.

[0046] (4) The rule for determining whether a number is less than or equal to zero is: the sign bit is 1 or the exponent field and the mantissa field are both 0, and the number is not a non-numeric number.

[0047] (5) The rule for determining positive 0 is: both the exponent field and the mantissa field are 0, and the sign bit is 0.

[0048] (6) The rule for determining negative 0 is: both the exponent field and the mantissa field are 0, and the sign bit is 1.

[0049] (7) The rule for distinguishing positive nonnormalized numbers: the exponent field is 0 and the mantissa field is non-zero, and the sign bit is 0.

[0050] (8) The rule for identifying negative denormalized numbers: the exponent field is 0 and the mantissa field is non-zero, and the sign bit is 1.

[0051] (9) The rule for determining positive infinity is: the exponent field is all 1s and the mantissa field is 0, and the sign bit is 0.

[0052] (10) The rule for determining negative infinity is: the exponent field is all 1s and the mantissa field is 0, and the sign bit is 1.

[0053] (11) Non-numerical discrimination rule: the exponent field is all 1 and the mantissa field is not 0.

[0054] (12) The rule for determining a normalized number: the exponent field is neither all 0s nor all 1s, and the sign bit is 0.

[0055] (13) The rule for distinguishing negative normalized numbers: the exponent field is neither all 0s nor all 1s, and the sign bit is 1.

[0056] It should be noted that the above discrimination rules can be applied to floating-point numbers with different precision and different encoding formats, such as FP16, BF16, FP32, FP64, etc., and can be extended or trimmed according to implementation requirements. This application does not limit this.

[0057] In the above embodiments, a unified combinational logic is used to parse the sign bit, exponent field, and mantissa field of the floating-point operation result to obtain the numerical category identifier. That is, this application can support the detection of various numerical categories of floating-point numbers using a unified detection logic, without needing to design separate hardware detection units for different numerical categories. Furthermore, the aforementioned combinational logic not only identifies special floating-point values ​​but also distinguishes their sign attributes, thereby fully preserving the semantic information of the floating-point operation result.

[0058] The technical solution provided in this application, on the one hand, connects a category detection unit after the floating-point arithmetic unit for performing floating-point operations. This enables the detection of whether the floating-point operation result belongs to or does not belong to a certain numerical category through a hardware pipeline, eliminating the need to introduce additional category detection instructions into the processor, thereby saving instruction overhead. On the other hand, by setting category indication information in the floating-point arithmetic instructions to indicate at least one numerical category from a pre-configured set of M numerical categories, and by having the category detection unit detect whether the floating-point operation result belongs to the numerical category indicated by the category indication information, the category detection function of the category detection unit is not limited to a single numerical category, but can perform flexible detection for multiple numerical categories.

[0059] In some embodiments, please refer to Figure 2 The processor 100 also includes a processing control unit 30 and a storage unit 40, and the output of the category detection unit 20 is connected to the input of the processing control unit 30.

[0060] The processing control unit 30 is used to write the floating-point operation result of the operation array and the first numerical category identifier into the storage unit 40.

[0061] In some embodiments, the storage unit 40 consists of registers.

[0062] In some embodiments, the processing control unit 30 is used to write the floating-point operation result of the operand array and the first numerical category identifier into the storage unit 40. That is, the storage location of the floating-point operation result of the operand array in the storage unit 40 corresponds to the storage location of the first numerical category identifier in the storage unit 40, and determining the storage location of one is equivalent to determining the storage location of the other.

[0063] In some embodiments, the processing control unit 30 is used to execute a preset processing strategy corresponding to the first numerical category identifier.

[0064] Specifically, the preset processing strategy corresponding to the first numerical category identifier is different when the floating-point operation result of the first numerical category identifier indicates that the first numerical category identifier belongs to the first numerical category, and when the floating-point operation result of the first numerical category identifier indicates that the first numerical category identifier does not belong to the first numerical category.

[0065] The preset processing strategy can be any operation that a processor may be involved in, such as information generation, data processing, and signal transmission. This application does not limit this.

[0066] In the above embodiment, a category detection unit 20 is provided between the floating-point arithmetic unit and the processing control unit for writing back the floating-point arithmetic results. This allows for the insertion of a numerical category detection step for the floating-point arithmetic results before the instruction write-back. Furthermore, this scheme not only determines the numerical category but also generates a corresponding numerical category identifier, which is then propagated and stored within the processor 100 along with the floating-point arithmetic results. This provides a direct basis for subsequent instruction execution, logic control, debugging, and statistical modules within the processor 100.

[0067] In the following embodiments, the complete instruction processing procedure in the processor 100 will be described in more detail.

[0068] In some embodiments, please refer to Figure 2 The processor 100 also includes an operand reading unit 50, and the storage unit 40 includes a first storage unit 41 and a second storage unit 42.

[0069] The operand reading unit 50 is used to receive the first floating-point operation instruction, send the operation instruction in the first floating-point operation instruction to the floating-point operation unit 10, and send the first read request to the first storage unit 41 according to the first positioning information in the first floating-point operation instruction.

[0070] The first positioning information is used to indicate the position of the operand array targeted by the first floating-point arithmetic instruction in the first storage unit 41. Optionally, the first positioning information is used to indicate the position of each operand in the operand array in the first storage unit 41. The operation instruction in the first floating-point arithmetic instruction is used to indicate the floating-point arithmetic operation to be performed by the first floating-point arithmetic instruction.

[0071] Optionally, the operand reading unit 50 may directly send the complete first floating-point operation instruction to the floating-point operation unit 10.

[0072] The first read request is a read request used to read the array being operated on.

[0073] For example, the first storage unit includes P first entries. First location information is used to indicate the first entry containing each operand in the operand array from among the P first entries. Therefore, a read request for reading the operand array can be generated based on the first location information.

[0074] The first storage unit 41 is used to output the operand array to the floating-point arithmetic unit 10 in response to the first read request.

[0075] The processing control unit 30 is used to write the floating-point operation result of the operation array into the first storage unit 41 and write the first numerical category identifier into the second storage unit 42.

[0076] Optionally, the storage location of the floating-point operation result of the operation array in the first storage unit 41 and the storage location of the first numerical category identifier in the second storage unit 42 are corresponding.

[0077] In some embodiments, please refer to Figure 3 The first storage unit 41 includes P first entries 411, and the second storage unit 42 includes P second entries 421. That is, the first entries 411 in the first storage unit 41 and the second entries 421 in the second storage unit 42 are in one-to-one correspondence. Specifically, when the floating-point operation result of the operand array is written to the i-th first entry among the P first entries, the first numerical category identifier is written to the i-th second entry among the P second entries. Here, P is an integer greater than N.

[0078] Optionally, the first entry 411 or the second entry 421 described above consists of one or more registers.

[0079] As can be seen, in the above embodiment, by setting up hardware, the detection of floating-point value categories and the storage of detection results are inserted into the complete instruction processing flow (instruction dispatch, execution and write-back). While saving instruction overhead, it ensures that the calculation results generated by the processor have corresponding category identifiers, thereby facilitating the subsequent use of floating-point data.

[0080] In some embodiments, the category indication information in the first floating-point arithmetic instruction can be transmitted to the category detection unit 20 in two ways, as detailed in Method 1 and Method 2 below.

[0081] In Method 1, the operand reading unit 50 is also used to send the category indication information in the first floating-point arithmetic instruction to the floating-point arithmetic unit 10. The floating-point arithmetic unit 10 is also used to provide the category indication information in the first floating-point arithmetic instruction to the category detection unit 20.

[0082] Optionally, the operand reading unit 50 directly sends the complete first floating-point operation instruction to the floating-point operation unit 10, which is used to provide the complete first floating-point operation instruction to the category detection unit 20.

[0083] In other words, in mode 1, the operand reading unit 50 sends the operation instruction in the first floating-point operation instruction to the floating-point operation unit 10, and at the same time, sends the category indication information in the first floating-point operation instruction. The floating-point operation unit 10, while providing the floating-point operation result of the operation array to the category detection unit 20, also transmits the received category indication information to the category detection unit 20.

[0084] In method 2, the operand reading unit 50 is also used to send the category indication information in the first floating-point arithmetic instruction to the category detection unit 20.

[0085] Optionally, the operand reading unit 50 may directly send the complete first floating-point operation instruction to the category detection unit 20.

[0086] In other words, in mode 2, the operand reading unit 50 can bypass the floating-point arithmetic unit 10 and directly transmit the category indication information in the first floating-point arithmetic instruction to the category detection unit 20.

[0087] In the above embodiment, after introducing a category detection unit that performs numerical category determination based on category indication information into the hardware pipeline of processor 100, the operand reading unit 50 is reused to realize the transmission of category indication information. This allows full utilization of the instruction parsing and sending functions of operand reading unit 50, avoiding the introduction of too much hardware into processor 100 and saving on implementation costs.

[0088] The technical solutions provided in the above embodiments will be illustrated below through two examples.

[0089] Please refer to Figure 4 The diagram illustrates a flowchart of an example of an infinite number detection method provided in one embodiment of this application. The method includes at least one of the following steps 410-460.

[0090] Step 410: The operand reading unit receives a floating-point addition instruction, wherein the category of the value indicated by the category indication information in the floating-point addition instruction includes positive infinity and negative infinity.

[0091] Step 420: The operand reading unit sends the operation instruction in the floating-point addition instruction to the floating-point arithmetic unit, and sends a first read request to the first storage unit according to the first positioning information in the floating-point addition instruction.

[0092] In step 430, the first storage unit responds to the first read request by outputting the operand array to the floating-point unit.

[0093] Step 440: The floating-point arithmetic unit performs floating-point addition on the two operands in the received operand array according to the operation instructions in the floating-point addition instruction, and obtains the floating-point operation result of the operand array.

[0094] Step 450: The category detection unit detects whether the floating-point operation result of the operand array belongs to positive infinity and negative infinity, and generates two numerical category identifiers.

[0095] Among them, one of the two numeric category identifiers indicates whether the floating-point operation result of the operand belongs to or does not belong to positive infinity, and the other numeric category identifier indicates whether the floating-point operation result of the operand belongs to or does not belong to negative infinity.

[0096] Step 460: The processing control unit writes the floating-point operation result of the operation array into the first storage unit and writes the two numerical category identifiers into the second storage unit.

[0097] As can be seen, by using the above method, without adding extra floating-point instructions, subsequent instructions or debugging modules in the processor can be made aware of whether the floating-point operation result is positive infinity or negative infinity.

[0098] Please refer to Figure 5 The diagram illustrates a flowchart of an example of a positive / negative zero detection method provided in one embodiment of this application. The method includes at least one of the following steps 510-560.

[0099] Step 510: The operand reading unit receives a floating-point subtraction instruction, wherein the category of the value indicated by the category indication information in the floating-point subtraction instruction includes positive 0 and negative 0.

[0100] Step 520: The operand reading unit sends the operation instruction in the floating-point subtraction instruction to the floating-point arithmetic unit, and sends a first read request to the first storage unit according to the first positioning information in the floating-point subtraction instruction.

[0101] In step 530, the first storage unit responds to the first read request by outputting the operand array to the floating-point unit.

[0102] Step 540: The floating-point arithmetic unit performs a floating-point subtraction operation on the two operands in the received operand array according to the operation instructions in the floating-point subtraction instruction, and obtains the floating-point operation result of the operand array.

[0103] Step 550: The category detection unit detects whether the floating-point operation result of the operation array belongs to positive 0 and negative 0, and generates two numerical category identifiers.

[0104] Among them, one of the two numeric category identifiers indicates whether the floating-point operation result of the operand belongs to or does not belong to positive 0, and the other numeric category identifier indicates whether the floating-point operation result of the operand belongs to or does not belong to negative 0.

[0105] Step 560: The processing control unit writes the floating-point operation result of the operation array into the first storage unit and writes the two numerical category identifiers into the second storage unit.

[0106] Optionally, these two numeric category identifiers can be used as metadata for the results of floating-point operations on the array.

[0107] As can be seen, the above method can preserve and propagate the semantics of positive and negative zero based on numerical category identifiers, thereby ensuring the distinguishability and traceability of positive and negative zero in the processor's floating-point computing pipeline.

[0108] In summary, this application explicitly places the numerical category detection logic in the completion or write-back stage of the floating-point operation instruction, rather than during the operation process or at the software level, thereby achieving real-time classification of floating-point operation results without increasing the number of instructions or affecting the semantics of the operation.

[0109] In addition, the technical solution provided in this application also supports generating numerical category identifiers at the warp level, which will be explained in more detail in the following embodiments.

[0110] In some embodiments, the first storage unit 41 is used to output N operation arrays to the floating-point arithmetic unit 10 in response to a first read request, where N is an integer greater than 1.

[0111] The floating-point arithmetic unit 10 is used to perform floating-point arithmetic operations in parallel on N operands using the first thread bundle according to the operation instructions in the first floating-point arithmetic instruction, so as to obtain the floating-point arithmetic results of each of the N operands.

[0112] Optionally, the first thread bundle includes N threads, one of which is used to perform floating-point operations on one of the N operand arrays. Different threads in the N threads are used on different operand arrays.

[0113] For example, the first thread bundle includes 32 threads, which are used to perform floating-point operations on 32 operands to obtain the floating-point operation results of each of the 32 operands, for a total of 32 floating-point operation results.

[0114] The category detection unit 20 is used to detect whether the floating-point operation results of each of the N operands belong to the first numerical category, so as to generate the first numerical category identifier vector.

[0115] The first numerical category identifier vector includes N first numerical category identifiers, each of which corresponds to a floating-point operation result of one of the N operands. Optionally, different first numerical category identifiers among the N first numerical category identifiers correspond to different floating-point operation results in the respective N operands; that is, there is a one-to-one correspondence between the N first numerical category identifiers and the respective floating-point operation results of the N operands.

[0116] In the first numerical category identifier vector, each first numerical category identifier is used to indicate whether the corresponding floating-point operation result belongs to or does not belong to the first numerical category.

[0117] For example, the first numerical category identifier vector includes 32 first numerical category identifiers, each of which is used to indicate whether the corresponding floating-point operation result among the 32 floating-point operation results belongs to or does not belong to the first numerical category.

[0118] Optionally, the category detection unit is used to detect in parallel whether the floating-point operation results of each of the N operation arrays belong to the first numerical category, so as to generate the first numerical category identifier vector.

[0119] In the above embodiment, the SIMD / SIMT execution characteristics of the processor are fully considered. For the floating-point operation results of each thread in the first thread bundle, a corresponding first numerical category identifier will be generated. Thus, the category detection stage can be embedded into the processing pipeline of floating-point operation instructions without destroying the original parallel model.

[0120] In some embodiments, the first storage unit 41 includes P first entries 411, and the second storage unit 42 includes P second entries 421.

[0121] The processing control unit 30 is used to write the floating-point operation results of each of the N operation arrays into the first storage unit 41 and write the N first numerical category identifiers into the second storage unit 42.

[0122] Specifically, for any one of the floating-point operation results in each of the N operation arrays, if the floating-point operation result is written into the i-th first entry of P first entries, the first numerical category identifier corresponding to the floating-point operation result is written into the i-th second entry of P second entries, where i is an integer less than or equal to P.

[0123] For example, each of the 32 floating-point operation results occupies one first entry, and the 32 floating-point operation results occupy a total of 32 first entries. Each of the 32 first numerical category identifiers occupies one second entry, and the 32 first numerical category identifiers occupy a total of 32 first entries. In this case, if the 32 floating-point operation results occupy the 33rd to 64th first entries out of P first entries, then the 32 first numerical categories also correspondingly occupy the 33rd to 64th second entries out of P second entries.

[0124] In some embodiments, each first entry 411 includes a portion of data bits in a register, or includes one or more registers; therefore, the first storage unit 41 may also be referred to as a register unit. Each second entry 421 includes a portion of data bits in a predicate register, or includes one or more predicate registers; therefore, the second storage unit 42 may also be referred to as a predicate register unit.

[0125] In the above embodiment, the hardware entries in the first storage unit 41 and the second storage unit 42 are set one-to-one, which makes it easy to store the floating-point operation results and the numerical category identifiers accordingly, thereby making it easier to use the semantics of the numerical category identifiers to guide the use of the floating-point operation results in the future.

[0126] In some embodiments, each second entry 421 includes M identifier storage areas, and different identifier storage areas in the M identifier storage areas correspond to one of the M numerical categories.

[0127] When the result of a floating-point operation is written to the i-th first entry among P first entries, the first numerical category identifier corresponding to the floating-point operation result is written to the identifier storage area corresponding to the first numerical category included in the i-th second entry.

[0128] For example, please refer to Figure 6 Each second entry 421 includes eight identifier storage areas 422, which correspond one-to-one with eight numerical categories (numerical category 1 to numerical category 8). If the first numerical category is numerical category 2, then the identifier of the first numerical category is written into the identifier storage area corresponding to numerical category 2.

[0129] In the above embodiment, the second entry will configure a corresponding identifier storage area for each numerical category, so that the second storage unit 42 can support maintaining multiple numerical category detection results for a floating-point operation result. When using the floating-point operation result, it can be determined from the corresponding identifier storage area whether the floating-point operation result is the corresponding numerical category according to the requirements, so that this solution can be widely applied to various use scenarios of the processor.

[0130] In some embodiments, the processing control unit 30 is further configured to generate a thread bundle-level event signal when a target first numerical category identifier exists among the N first numerical category identifiers. The target first numerical category identifier is used to indicate that the floating-point operation result belongs to the first numerical category, and the thread bundle-level event signal is used to indicate that there is a floating-point number belonging to the first numerical category in the operation result of the first thread bundle.

[0131] Thread bundle level event signals are signals used to propagate in the processor. They can be used to trigger subsequent modules in the processor to execute thread bundle level debugging records, statistical counts, etc. This application does not limit their specific functions.

[0132] For example, if the first numerical category includes non-numerical and infinite, then by using the above scheme, when the floating-point operation results of each of the N operands include non-numerical and infinite numbers, a thread bundle-level event signal can be generated to indicate that the first thread bundle has an abnormal value.

[0133] In the above embodiments, under the processor's SIMD / SIMT architecture, thread bundle-level event signals are generated, thereby supporting the realization of numerical category awareness and processing at the thread bundle level. Therefore, the technical solution provided in this application allows the category awareness of floating-point operation results to be accurately associated with specific floating-point instructions, threads, and thread bundles, which has good application value in scenarios such as numerical stability analysis, debugging, and fault-tolerant calculation.

[0134] In some embodiments, the category detection unit 20 is used to determine Q first numerical categories indicated by category indication information from M numerical categories, where Q is an integer greater than 1 and less than or equal to M.

[0135] The category detection unit 20 is used to detect whether the floating-point operation results of each of the N operation arrays belong to the first numerical category for any one of the Q first numerical categories, and to obtain the first numerical category identifier vector corresponding to the first numerical category.

[0136] The processing control unit 30 is used to write the floating-point operation results of each of the N operation arrays into the first storage unit 41, and to write the first numerical category identifier vectors corresponding to the Q first numerical categories into the second storage unit 42.

[0137] Among them, the Q first numerical categories are distinct numerical categories indicated by category indication information. The first numerical category identifier vector corresponding to the first numerical category includes N first numerical category identifiers, and the first numerical category identifiers in the first numerical category identifier vector are used to indicate whether the corresponding floating-point operation result belongs to or does not belong to the first numerical category.

[0138] For example, when Q=2 and N=32, the category detection unit 20 will generate two first numerical category identifier vectors, each containing 32 first numerical category identifiers. One first numerical category identifier vector indicates whether the corresponding floating-point operation result belongs to one of the two first numerical categories. The other first numerical category identifier vector indicates whether the corresponding floating-point operation result belongs to the other of the two first numerical categories. Thus, through this scheme, multiple numerical category identifiers corresponding to different numerical categories can be generated for a single floating-point operation result, ensuring flexible application of the floating-point operation result based on different numerical category identifiers in different scenarios.

[0139] To facilitate understanding, an example will be provided below to illustrate the above solution. Please refer to it. Figure 7 The diagram illustrates a flowchart of a thread-beam-level instruction processing procedure provided in one embodiment of this application. The procedure includes at least one of the following steps 710-770.

[0140] Step 710: The operand reading unit receives a floating-point arithmetic instruction, wherein the category of the numerical value indicated by the category indication information in the floating-point arithmetic instruction includes non-numerical and infinity.

[0141] Step 720: The operand reading unit sends the operation instruction in the floating-point operation instruction to the floating-point operation unit, and sends the first read request to the first storage unit according to the first positioning information in the floating-point operation instruction.

[0142] In step 730, the first storage unit responds to the first read request by outputting N operand arrays to the floating-point unit.

[0143] Step 740: The floating-point arithmetic unit performs floating-point arithmetic operations in parallel on N operands according to the operation instructions in the floating-point subtraction instruction, and obtains the floating-point arithmetic results of each of the N operands.

[0144] Step 750: The category detection unit detects in parallel whether the floating-point operation results of each of the N operation arrays belong to non-numerical and infinity, and generates two first numerical category identifier vectors.

[0145] One of the first numerical category identifier vectors is used to indicate whether the corresponding floating-point operation result is non-numerical, and the other of the first numerical category identifier vectors is used to indicate whether the corresponding floating-point operation result is infinity.

[0146] Step 760: If, in one of the two first numerical category identifier vectors, there is a first numerical category identifier indicating that the floating-point operation result belongs to a non-numerical or infinite value, the processing control unit generates a thread bundle-level event signal.

[0147] Step 770: The processing control unit writes the floating-point operation results of each of the N operation arrays into the first storage unit, and writes the first numerical category identifier of the two first numerical category identifier vectors into the second storage unit.

[0148] As can be seen, by using the above method, the parallel execution characteristics of the processor can be used to perform detection of multiple numerical categories on the results of multiple floating-point operations at the same time, which is beneficial for the rapid detection and management of abnormal values.

[0149] In some embodiments, the first storage unit 41 stores at least two floating-point numbers, and the second storage unit 42 stores at least two second numerical category identifiers corresponding to the floating-point numbers respectively. The second numerical category identifiers corresponding to the floating-point numbers are used to indicate whether the floating-point numbers belong to the second numerical category among the M numerical categories.

[0150] The second numerical category can be any one of the M numerical categories, and this application does not limit it.

[0151] In some embodiments, at least two floating-point numbers are obtained through the same floating-point arithmetic operations.

[0152] The operand reading unit 50 is also used to receive a second floating-point arithmetic instruction, which is used to instruct the execution of a floating-point arithmetic operation on a target floating-point number among at least two floating-point numbers, wherein the target floating-point number belongs to a second numerical category, or the target floating-point number does not belong to a second numerical category.

[0153] For example, the target floating-point number is a floating-point number greater than 0. The second floating-point instruction is used to instruct the performance of a floating-point operation on at least two floating-point numbers that are greater than 0.

[0154] It should be noted that the second floating-point arithmetic instruction can consist of a series of instructions, which may include various logical instructions for reading the second numerical category identifier from the second storage unit 42, performing branch judgments, and performing floating-point arithmetic operations.

[0155] The operand reading unit 50 is also used to determine the target floating-point number from at least two floating-point numbers based on the second numerical category identifiers corresponding to the at least two floating-point numbers respectively.

[0156] The second numeric category identifier corresponding to the floating-point number is used to indicate whether the floating-point number belongs to or does not belong to the second numeric category.

[0157] For example, if the second value category is greater than 0, the operand reading unit 50 reads the second value category identifiers corresponding to at least two floating-point numbers from the second storage unit to determine the target floating-point number greater than 0 from the at least two floating-point numbers.

[0158] The operand reading unit 50 is also used to send a second read request to the first storage unit 41.

[0159] The second read request is a read request used to read the target floating-point number.

[0160] The first storage unit 41 is also used to output the target floating-point number to the floating-point arithmetic unit 10 in response to the second read request.

[0161] The floating-point arithmetic unit 10 is used to perform floating-point arithmetic operations on the target floating-point number according to the operation instructions in the second floating-point arithmetic instruction.

[0162] In processors, the execution of floating-point arithmetic instructions involving path selection, such as if...else..., is frequently involved. The aforementioned scheme utilizes the numerical category identifier generated by the category detection unit 20 to select a specific value. In summary, this application achieves hardware-level detection with zero additional instruction overhead. This detection logic is implemented through combinational logic during the floating-point instruction completion stage. Even when path selection is involved, no additional floating-point arithmetic instructions need to be inserted, thus not affecting the processor's computational throughput.

[0163] In some embodiments, the processor 100 further includes a statistics unit (not shown in the figures). The statistics unit is used to perform a count on a target floating-point number among at least two floating-point numbers in response to a counting instruction.

[0164] In some embodiments, the category detection unit 20 is further configured to determine the target parsing method indicated by the configuration indication information in the first floating-point arithmetic instruction. The configuration indication information is used to indicate one parsing method from at least two pre-configured parsing methods. Each of the at least two parsing methods corresponds to M numerical categories, and the numerical categories corresponding to the at least two parsing methods are different from each other.

[0165] Optionally, at least the two parsing methods must correspond to M distinct numerical categories.

[0166] For example, M=4, the M types of numerical categories corresponding to parsing method 1 in at least two parsing methods are numerical category 1, numerical category 2, numerical category 3 and numerical category 4, and the M types of numerical categories corresponding to parsing method 2 in at least two parsing methods are numerical category 5, numerical category 6, numerical category 7 and numerical category 8.

[0167] The category detection unit 20 is used to parse the category indication information in the first floating-point arithmetic instruction according to the target parsing method, so as to determine the first numerical category indicated by the category indication information in the first floating-point arithmetic instruction from the M numerical categories corresponding to the target parsing method.

[0168] Optionally, the category detection unit 20 is used to parse the M indicator bits included in the category indication information of the first floating-point arithmetic instruction according to the target parsing method, so as to determine the first numerical category indicated by the category indication information. Each of the M indicator bits corresponds to a different numerical category under different parsing methods.

[0169] In the above embodiments, the fixed-length category indication information has different parsing methods, thereby enabling the detection requirements of multiple numerical categories to be covered with as few data bits as possible in floating-point arithmetic instructions, thus avoiding excessively long floating-point arithmetic instructions due to the introduction of the improvements in this application. For example, when the configuration indication information occupies 1 data bit and the category indication information includes 4 indication bits, assuming that the configuration indication information supports two parsing methods and the category indication information supports 4 numerical categories, then the detection requirements of up to 2 × 4 = 8 numerical categories can be met through the 5 data bits in the floating-point arithmetic instructions.

[0170] In summary, the counting scheme provided in this application has the following beneficial effects: (1) Provide a unified floating-point numerical semantic classification framework. This application realizes the systematic determination of multiple numerical categories such as NaN, Infinity, Denormal, Zero and Normal by uniformly parsing the sign bit, exponent field and mantissa field of floating-point operation results, rather than performing local detection only for a single outlier.

[0171] (2) Supports complete numerical semantic expression. This application not only identifies special values, but also distinguishes their symbolic attributes (e.g., +Infinity and -Infinity, +Zero and -Zero), thus fully preserving the semantic information of floating-point operation results.

[0172] (3) Implement hardware-level detection with zero additional instruction overhead. The detection logic is implemented through combinational logic during the floating-point instruction completion stage. No additional floating-point instructions need to be inserted, and the processor's computing throughput is not affected.

[0173] (4) Supports debugging, statistics and control logic extension. By generating a propagable numerical category identifier, this application can support extended functions such as anomaly statistics, numerical stability analysis and warp-level anomaly detection.

[0174] (5) Applicable to multiple floating-point formats, this detection mechanism can be extended to multiple floating-point formats such as FP16, BF16, FP32, and FP64, and has good system architecture versatility.

[0175] An exemplary embodiment of this application also provides a chip that includes the processor described above. This chip may be a GPU (Graphics Processing Unit) chip, a chip dedicated to implementing floating-point operations, or an AI chip; this application does not limit the specific application to this type of chip.

[0176] An exemplary embodiment of this application also provides an electronic device that includes the processor described above. For example, the electronic device includes a chip that includes the processor described above.

[0177] The electronic device can be such as a mobile phone, tablet computer, multimedia playback device, PC (Personal Computer), wearable device, in-vehicle terminal device, VR (Virtual Reality) device, AR (Augmented Reality) device, MR (Mixed Reality) device, etc., and this application does not limit it.

[0178] One embodiment of this application also provides a graphics card, which includes a chip that includes the processor described above.

[0179] One embodiment of this application also provides a computing cluster, which includes at least two graphics cards or at least two electronic devices. The graphics cards or electronic devices include the aforementioned processor.

[0180] The following are embodiments of the method of this application. For details not described in the embodiments of the method of this application, please refer to the embodiments of the processor above.

[0181] Please refer to Figure 8 The diagram illustrates a flowchart of a data processing method according to an embodiment of this application. The method is applied to a processor, which includes a floating-point arithmetic unit and a category detection unit. The output of the floating-point arithmetic unit is connected to the input of the category detection unit. The method includes at least one of the steps 810-830.

[0182] Step 810: The floating-point arithmetic unit performs floating-point arithmetic operations on the received operand array according to the operation instructions in the first floating-point arithmetic instruction, and obtains the floating-point arithmetic result of the operand array.

[0183] The first floating-point instruction also includes category indication information, which is used to indicate at least one numerical category from a pre-configured set of M numerical categories, where M is an integer greater than 1. Step 820: The category detection unit determines the first numerical category indicated by the category indication information from the M numerical categories.

[0184] Step 830: The category detection unit detects whether the floating-point operation result of the operation array belongs to the first numerical category, so as to generate the first numerical category identifier.

[0185] The first numerical category identifier is used to indicate whether the floating-point operation result of the operand array belongs to or does not belong to the first numerical category.

[0186] In some embodiments, the processor further includes a processing control unit and a storage unit, with the output of the category detection unit connected to the input of the processing control unit.

[0187] The above method also includes: the processing control unit writes the floating-point operation result of the operation array and the first numerical category identifier into the storage unit.

[0188] In some embodiments, the processor further includes an operand read unit, and the storage unit includes a first storage unit and a second storage unit. The method further includes: The operand reading unit receives a first floating-point arithmetic instruction, sends the operation instruction in the first floating-point arithmetic instruction to the floating-point arithmetic unit, and sends a first read request to the first storage unit according to the first positioning information in the first floating-point arithmetic instruction; wherein, the first positioning information is used to indicate the position of the operand array targeted by the first floating-point arithmetic instruction in the first storage unit.

[0189] In response to the first read request, the first storage unit outputs the operand array to the floating-point unit.

[0190] Step 830 above includes: the processing control unit writes the floating-point operation result of the operation array into the first storage unit and writes the first numerical category identifier into the second storage unit.

[0191] In some embodiments, the method further includes: the operand reading unit sending category indication information in the first floating-point arithmetic instruction to the floating-point arithmetic unit; the floating-point arithmetic unit providing the category indication information in the first floating-point arithmetic instruction to the category detection unit; or, the operand reading unit sending the category indication information in the first floating-point arithmetic instruction to the category detection unit.

[0192] In some embodiments, the first storage unit responds to a first read request by outputting an operand array to the floating-point unit, including: the first storage unit responds to a read request by outputting N operand arrays to the floating-point unit, where N is an integer greater than 1.

[0193] Step 810 above includes: the floating-point arithmetic unit performs floating-point arithmetic operations in parallel on N operands using the first thread bundle according to the operation instructions in the first floating-point arithmetic instruction, and obtains the floating-point arithmetic results of each of the N operands.

[0194] Step 820 above includes: the category detection unit detects whether the floating-point operation results of each of the N operation arrays belong to the first numerical category, so as to generate a first numerical category identifier vector, wherein the first numerical category identifier vector includes N first numerical category identifiers, and the N first numerical category identifiers correspond to the floating-point operation results of each of the N operation arrays.

[0195] In some embodiments, the first storage unit includes P first entries, and the second storage unit includes P second entries, where P is an integer greater than N.

[0196] Step 830 above includes: the processing control unit writes the floating-point operation results of each of the N operands into the first storage unit and writes the N first numerical category identifiers into the second storage unit; wherein, for any floating-point operation result among the floating-point operation results of the N operands, when the floating-point operation result is written into the i-th first entry of P first entries, the first numerical category identifier corresponding to the floating-point operation result is written into the i-th second entry of P second entries, where i is an integer less than or equal to P.

[0197] In some embodiments, each second entry includes M identifier storage areas, and different identifier storage areas in the M identifier storage areas correspond to one of the M numerical categories; when the floating-point operation result is written to the i-th first entry among P first entries, the identifier of the first numerical category corresponding to the floating-point operation result is written to the identifier storage area corresponding to the first numerical category included in the i-th second entry.

[0198] In some embodiments, the method further includes: a category detection unit determining Q first numerical categories indicated by category indication information from M numerical categories, where Q is an integer greater than 1 and less than or equal to M; Step 820 above includes: the category detection unit detects whether the floating-point operation results of each of the N operation arrays belong to the first numerical category for any one of the Q first numerical categories, and obtains the first numerical category identifier vector corresponding to the first numerical category; In addition, the processing control unit writes the floating-point operation results of each of the N operation arrays into the first storage unit, and writes the first numerical category identifier vectors corresponding to the Q first numerical categories into the second storage unit.

[0199] In some embodiments, the method further includes: when the processing control unit has a target first numerical category identifier among the N first numerical category identifiers, generating a thread bundle-level event signal, wherein the target first numerical category identifier is used to indicate that the floating-point operation result belongs to the first numerical category, and the thread bundle-level event signal is used to indicate that there is a floating-point number belonging to the first numerical category in the operation result of the first thread bundle.

[0200] In some embodiments, the first storage unit stores at least two floating-point numbers, and the second storage unit stores at least two second numerical category identifiers corresponding to the floating-point numbers respectively. The second numerical category identifiers corresponding to the floating-point numbers are used to indicate whether the floating-point numbers belong to the second numerical category among the M numerical categories.

[0201] The method further includes: an operand reading unit receiving a second floating-point arithmetic instruction, the second floating-point arithmetic instruction being used to instruct the execution of a floating-point arithmetic operation on a target floating-point number among at least two second floating-point numbers, wherein the target floating-point number belongs to a second numerical category, or the target floating-point number does not belong to a second numerical category; the operand reading unit determining the target floating-point number from at least two floating-point numbers according to the second numerical category identifiers corresponding to the at least two floating-point numbers respectively, the second numerical category identifiers being used to indicate whether the floating-point number belongs to or does not belong to a second numerical category; the operand reading unit sending a second read request to a first storage unit; the first storage unit responding to the second read request and outputting the target floating-point number to the floating-point arithmetic unit; and the floating-point arithmetic unit performing a floating-point arithmetic operation on the target floating-point number according to the operation instructions in the second floating-point arithmetic instruction.

[0202] In some embodiments, step 820 includes: a category detection unit detecting whether the sign bit, exponent field, and mantissa field of the floating-point operation result of the operation array conform to the discrimination rules of the first numerical category, so as to generate a first numerical category identifier.

[0203] In some embodiments, the M numerical categories include at least two of the following numerical categories: equal to 0, greater than 0, less than 0, greater than or equal to 0, less than or equal to 0, positive 0, negative 0, positive denormalized number, negative denormalized number, positive infinity, negative infinity, positive normalized number, negative normalized number, and not a number.

[0204] In some embodiments, the method further includes: a category detection unit determining a target parsing method indicated by configuration indication information in a first floating-point arithmetic instruction; the configuration indication information indicating a parsing method from at least two pre-configured parsing methods, each of the at least two parsing methods corresponding to M numerical categories, and the M numerical categories corresponding to the at least two parsing methods being distinct from each other. The category detection unit parses the category indication information in the first floating-point arithmetic instruction according to the target parsing method to determine the first numerical category indicated by the category indication information in the first floating-point arithmetic instruction from the M numerical categories corresponding to the target parsing method.

[0205] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0206] The above are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A processor, characterized in that, The processor includes a floating-point arithmetic unit and a category detection unit, wherein the output of the floating-point arithmetic unit is connected to the input of the category detection unit; The floating-point arithmetic unit is used to perform floating-point arithmetic operations on the received operation array according to the operation instructions in the first floating-point arithmetic instruction, and obtain the floating-point arithmetic result of the operation array. The first floating-point arithmetic instruction is an instruction for implementing floating-point arithmetic and is provided with category indication information. The category indication information is used to indicate at least one numerical category from a pre-configured set of M numerical categories. The operation array includes at least one operand targeted by the first floating-point arithmetic instruction, where M is an integer greater than 1. The category detection unit is used to determine, from the M numerical categories, the first numerical category indicated by the category indication information, wherein the first numerical category can be set to any one of the M numerical categories; The category detection unit is further configured to detect whether the floating-point operation result of the operation array belongs to the first numerical category indicated by the category indication information, so as to generate a first numerical category identifier, wherein the first numerical category identifier is used to indicate whether the floating-point operation result of the operation array belongs to or does not belong to the first numerical category.

2. The processor according to claim 1, characterized in that, The processor also includes a processing control unit and a storage unit, and the output of the category detection unit is connected to the input of the processing control unit; The processing control unit is used to write the floating-point operation result of the operation array and the first numerical category identifier into the storage unit.

3. The processor according to claim 2, characterized in that, The processor further includes an operand reading unit, and the storage unit includes a first storage unit and a second storage unit; The operand reading unit is configured to receive the first floating-point arithmetic instruction, send the operation instruction in the first floating-point arithmetic instruction to the floating-point arithmetic unit, and send a first read request to the first storage unit according to the first positioning information in the first floating-point arithmetic instruction; wherein, the first positioning information is used to indicate the position of the operand array targeted by the first floating-point arithmetic instruction in the first storage unit; The first storage unit is used to respond to the first read request by outputting the operand array to the floating-point arithmetic unit; The processing control unit is used to write the floating-point operation result of the operation array into the first storage unit and write the first numerical category identifier into the second storage unit.

4. The processor according to claim 3, characterized in that, The operand reading unit is further configured to send the category indication information in the first floating-point arithmetic instruction to the floating-point arithmetic unit; the floating-point arithmetic unit is further configured to provide the category indication information in the first floating-point arithmetic instruction to the category detection unit; or... The operand reading unit is also used to send the category indication information in the first floating-point operation instruction to the category detection unit.

5. The processor according to claim 3, characterized in that, The first storage unit is used to respond to the first read request by outputting N operand arrays to the floating-point arithmetic unit, where N is an integer greater than 1; The floating-point arithmetic unit is used to perform floating-point arithmetic operations in parallel on the N operands using a first thread bundle according to the operation instructions in the first floating-point arithmetic instruction, so as to obtain the floating-point arithmetic results of the N operands respectively. The category detection unit is used to detect whether the floating-point operation results of each of the N operation arrays belong to the first numerical category, so as to generate a first numerical category identifier vector, wherein the first numerical category identifier vector includes N first numerical category identifiers, and the N first numerical category identifiers correspond to the floating-point operation results of each of the N operation arrays.

6. The processor according to claim 5, characterized in that, The first storage unit includes P first entries, and the second storage unit includes P second entries, where P is an integer greater than N; The processing control unit is used to write the floating-point operation results of each of the N operation arrays into the first storage unit, and write the N first numerical category identifiers into the second storage unit; Specifically, for any one of the floating-point operation results of the N operation arrays, when the floating-point operation result is written into the i-th first entry of the P first entries, the first numerical category identifier corresponding to the floating-point operation result is written into the i-th second entry of the P second entries, where i is an integer less than or equal to P.

7. The processor according to claim 6, characterized in that, Each of the second entries includes M identifier storage areas, and different identifier storage areas in the M identifier storage areas correspond to one of the M numerical categories; When the floating-point operation result is written to the i-th first entry among the P first entries, the first numerical category identifier corresponding to the floating-point operation result is written to the identifier storage area corresponding to the first numerical category included in the i-th second entry.

8. The processor according to claim 5, characterized in that, The category detection unit is used to determine Q first numerical categories indicated by the category indication information from the M numerical categories, where Q is an integer greater than 1 and less than or equal to M; The category detection unit is used to detect, for any one of the Q first numerical categories, whether the floating-point operation result of each of the N operation arrays belongs to the first numerical category, and to obtain the first numerical category identifier vector corresponding to the first numerical category. The processing control unit is used to write the floating-point operation results of each of the N operation arrays into the first storage unit, and to write the first numerical category identifier vectors corresponding to the Q first numerical categories into the second storage unit.

9. The processor according to claim 5, characterized in that, The processing control unit is further configured to generate a thread bundle-level event signal when a target first numerical category identifier exists among the N first numerical category identifiers. The target first numerical category identifier is used to indicate that the floating-point operation result belongs to the first numerical category, and the thread bundle-level event signal is used to indicate that there is a floating-point number belonging to the first numerical category in the operation result of the first thread bundle.

10. The processor according to claim 3, characterized in that, The first storage unit stores at least two floating-point numbers, and the second storage unit stores second numerical category identifiers corresponding to the at least two floating-point numbers respectively. The second numerical category identifiers corresponding to the floating-point numbers are used to indicate whether the floating-point numbers belong to the second numerical category among the M numerical categories. The operand reading unit is further configured to receive a second floating-point arithmetic instruction, which is configured to instruct a floating-point arithmetic operation to be performed on a target floating-point number among the at least two second floating-point numbers, wherein the target floating-point number belongs to the second numerical category, or the target floating-point number does not belong to the second numerical category; The operand reading unit is further configured to determine the target floating-point number from the at least two floating-point numbers based on the second numerical category identifiers corresponding to the at least two floating-point numbers respectively; The operand reading unit is also used to send a second read request to the first storage unit; The first storage unit is also configured to, in response to the second read request, output the target floating-point number to the floating-point arithmetic unit; The floating-point arithmetic unit is used to perform floating-point arithmetic operations on the target floating-point number according to the operation instructions in the second floating-point arithmetic instruction.

11. The processor according to claim 1, characterized in that, The category detection unit is used to detect whether the sign bit, exponent field, and mantissa field of the floating-point operation result of the operand array conform to the discrimination rules of the first numerical category, so as to generate the first numerical category identifier.

12. The processor according to any one of claims 1 to 11, characterized in that, The M numerical categories include at least two of the following numerical categories: Equal to 0, greater than 0, less than 0, greater than or equal to 0, less than or equal to 0, positive 0, negative 0, positive denormalized number, negative denormalized number, positive infinity, negative infinity, positive normalized number, negative normalized number, not a number.

13. The processor according to any one of claims 1 to 11, characterized in that, The category detection unit is further configured to determine the target parsing method indicated by the configuration indication information in the first floating-point arithmetic instruction. The configuration indication information is configured to indicate one parsing method from at least two pre-configured parsing methods. Each of the at least two parsing methods corresponds to M numerical categories, and the M numerical categories corresponding to the at least two parsing methods are different from each other. The category detection unit is used to parse the category indication information in the first floating-point operation instruction according to the target parsing method, so as to determine the first numerical category indicated by the category indication information in the first floating-point operation instruction from the M numerical categories corresponding to the target parsing method.

14. A chip, characterized in that, The chip includes a processor as described in any one of claims 1 to 13.

15. An electronic device, characterized in that, The electronic device includes a processor as described in any one of claims 1 to 13.

16. A data processing method, characterized in that, The method is applied to a processor, which includes a floating-point arithmetic unit and a category detection unit, wherein the output of the floating-point arithmetic unit is connected to the input of the category detection unit; the method includes: The floating-point arithmetic unit performs floating-point arithmetic operations on the received operation array according to the operation instructions in the first floating-point arithmetic instruction, and obtains the floating-point arithmetic result of the operation array. The first floating-point arithmetic instruction is an instruction for implementing floating-point arithmetic and is equipped with category indication information. The category indication information is used to indicate at least one numerical category from a pre-configured set of M numerical categories, where M is an integer greater than 1. The category detection unit determines the first numerical category indicated by the category indication information from the M numerical categories, and the first numerical category can be set to any one of the M numerical categories; The category detection unit detects whether the floating-point operation result of the operation array belongs to the first numerical category indicated by the category indication information, so as to generate a first numerical category identifier, wherein the first numerical category identifier is used to indicate whether the floating-point operation result of the operation array belongs to or does not belong to the first numerical category.

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