A method for dynamic allocation and efficient transmission of PCIe resources

Abstract

This invention discloses a method for dynamic allocation and efficient transmission of PCIe resources, belonging to the field of computer hardware technology. The method first performs initialization operations on the PCIe link, enumerates connected devices and establishes a device resource mapping table, and allocates initial bandwidth to the link; it then monitors the link's data transmission load in real time, prioritizes device resources, constructs a bandwidth prediction model based on historical transmission data, and determines the future load state; it dynamically adjusts the bandwidth based on real-time load, resource priority, and prediction results, allocates idle PCIe link resources, and updates the device resource mapping table; finally, it performs data transmission optimization and energy efficiency management operations, completing data compression and decompression through a hardware acceleration module. This invention enables dynamic on-demand allocation of PCIe resources, improves bus resource utilization, optimizes data transmission efficiency, alleviates transmission congestion problems caused by multiple devices sharing a link, dynamically controls link power consumption, reduces processor operating load, and adapts to the operational needs of scenarios such as servers and data centers.

Description

Technical Field

[0001] This invention relates to the field of computer hardware technology, and in particular to a method for dynamic allocation and efficient transmission of PCIe resources. Background Technology

[0002] PCIe, as a high-speed serial computer expansion bus standard, is the core communication architecture connecting the central processing unit (CPU) and external expansion devices in modern computer systems. It is widely used in core areas such as servers, data centers, high-performance computing, and network communications, and can stably adapt to the connection and data interaction needs of various hardware peripherals such as graphics processors, solid-state storage devices, network adapters, and intelligent computing processors. With the continuous growth of data transmission volume and the increasing integration of hardware in the industry, parallel operation of multiple devices and high-density link deployment have become the mainstream trend in system design. The multi-channel transmission architecture and high-speed communication characteristics of PCIe have become widely adopted. Existing technologies have achieved basic initialization of PCIe links, peripheral enumeration, fixed bandwidth allocation, and basic device status monitoring. The overall technical architecture is mature and stable, becoming a key foundational technology supporting high-speed data interaction in modern hardware systems.

[0003] Existing PCIe resource management technologies generally employ fixed, static bandwidth allocation mechanisms, which cannot monitor link data transmission load in real time and perform dynamic resource adjustments. They also fail to optimize allocation logic by incorporating device task priorities and load prediction. As a result, a large number of idle PCIe link resources cannot be effectively allocated, leading to low overall bus resource utilization efficiency. In scenarios where multiple devices share the PCIe bus, the lack of targeted data transmission optimization methods results in high data transmission latency and a high risk of congestion. Furthermore, the inability to flexibly adjust link power consumption modes based on actual device operating conditions leads to poor system energy efficiency management. In addition, data compression and decompression operations rely on the central processing unit (CPU), further increasing the processor load and reducing overall system efficiency, making it difficult to adapt to the demands of high-density, high-load hardware operation. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for dynamic allocation and efficient transmission of PCIe resources.

[0005] The objective of this invention is achieved through the following technical solution: A method for dynamic allocation and efficient transmission of PCIe resources is provided, the method comprising: S1. After the system starts, it performs initialization operations on the PCIe link, enumerates all PCIe devices connected on the PCIe link, establishes a device resource mapping table, which includes PCIe device identifier, PCIe device allocated bandwidth, PCIe device transmission load status, PCIe device resource priority and PCIe link power consumption mode fields, and allocates initial bandwidth to the PCIe link, which is a preset bandwidth value. S2. Perform real-time monitoring of the data transmission load on the PCIe link, write the monitoring results into the device resource mapping table, determine the device transmission load status on the PCIe link based on the monitoring results, determine the device resource priority based on the device transmission load status and the preset priority scheduling rules, extract the load information from the historical transmission data, build a bandwidth prediction model based on the load information, and determine the future transmission load status through the bandwidth prediction model. S3. Based on the device transmission load status, device resource priority, and future transmission load status, perform dynamic adjustment operations on the bandwidth of the PCIe link, count the idle PCIe link resources, allocate the idle PCIe link resources to devices whose transmission load meets the preset conditions, and update the bandwidth allocation information in the device resource mapping table. S4. Based on the updated device resource mapping table, perform data transmission optimization operations on the PCIe link, perform energy efficiency management operations on the PCIe link, and complete data compression and decompression operations through the hardware acceleration module.

[0006] Furthermore, step S2 includes: S2.1. Collect real-time data transmission information on the PCIe link, including link throughput, packet queue length, and transmission delay; S2.2. Determine the device transmission load status based on real-time data transmission information. The device transmission load status includes unoccupied status, light load status, medium load status, and heavy load status. S2.3. Prioritize device resources according to the preset task type priority table, and map the task type corresponding to the device to the preset priority level; S2.4. Extract load characteristic information from historical transmission data. Load characteristic information includes load fluctuations in the time dimension, peak occurrence period, and average transmission rate. S2.5. A bandwidth prediction model is trained and generated based on load feature information. The bandwidth prediction model adopts a preset time-series prediction neural network structure, which includes an input layer, a hidden layer, and an output layer. The input layer receives load feature information, the hidden layer performs feature extraction and time-series correlation calculation on the load feature information, and the output layer outputs the transmission load status for a future set duration.

[0007] Furthermore, step S3 includes: S3.1. Extract the device transmission load status from the device resource mapping table, and compare the device transmission load status with the preset load thresholds, which include light load threshold, medium load threshold and heavy load threshold; S3.2. Filter out devices whose transmission load has reached the heavy load threshold and generate a list of devices to be allocated resources; S3.3. Calculate the total amount of idle PCIe link resources, which includes the number of unoccupied channels and the total available bandwidth; S3.4. Allocate idle PCIe link resources to devices in the list of devices to be allocated resources, and update the bandwidth allocation information in the device resource mapping table after the allocation is completed.

[0008] Furthermore, the data transmission optimization operation in step S4 includes: S4.1. Configure a data cache area inside the PCIe controller. The size of the data cache area is dynamically adjusted according to the device bandwidth allocation information in the device resource mapping table. S4.2. Enable the multi-channel transmission mode of the PCIe link and divide the data to be transmitted into transmission units according to the number of channels currently allocated; S4.3. Perform compression processing on the data to be transmitted. The compression processing is performed by the hardware acceleration module, which is a hardware compression and decompression acceleration module integrated inside the PCIe controller. The hardware compression and decompression acceleration module is directly connected to the data transmission channel of the PCIe controller. After the compression processing is completed, compressed data and compression identifier are generated. S4.4. Append a compression identifier to the header of the data transmission packet and transmit compressed data and data transmission packets via the PCIe link.

[0009] Furthermore, the energy efficiency management operations in step S4 include: S401. Extract the device transmission load status from the device resource mapping table to determine the working status of the device corresponding to the PCIe link; S402. The power consumption mode of the PCIe link is switched based on the device's working state. The power consumption modes include full power mode, medium power mode and low power mode. S403. Different power consumption modes correspond to different link transmission rates and the number of channels enabled. When switching power consumption modes, non-real-time data transmission is paused first. S404. After completing the power mode switching, resume data transmission and update the power mode information in the device resource mapping table.

[0010] Furthermore, in step S3, an idle PCIe link resource allocation operation is performed based on the device resource priority ranking result. The allocation operation is performed in descending order of priority. First, bandwidth resources that meet the transmission requirements of the device with the highest resource priority are allocated. The remaining idle PCIe link resources are allocated to devices with subsequent priorities in turn. If the remaining resources are insufficient to meet the transmission requirements of the next priority device, the current allocation operation is stopped and the allocation is performed again in the next bandwidth dynamic adjustment cycle. After the allocation is completed, a bandwidth allocation log is generated and stored in the system storage area. The system storage area is used to record all operation information and status information related to PCIe link resource allocation.

[0011] Furthermore, in step S4, it is determined whether the data to be transmitted meets the compression conditions. If the compression conditions are met, compression processing is performed on the data to be transmitted. When determining whether the data to be transmitted meets the compression conditions, the data type information of the data to be transmitted is first extracted, and the data type information is compared with the preset compressible data type table. If the comparison is consistent, it is determined that the compression conditions are met. The preset lossless compression algorithm is applied to the data to be transmitted that meets the compression conditions. The preset lossless compression algorithm includes the LZ77 algorithm and the Huffman coding algorithm. The compression ratio is the ratio of the compressed data size to the original data size to be transmitted. If the compression ratio is lower than the preset compression ratio threshold, the current compression processing is terminated, and the original data to be transmitted is transmitted directly.

[0012] Furthermore, in step S4, when the device is in an idle state, the PCIe link is switched to a preset low-power mode. When switched to the preset low-power mode, unused channels in the PCIe link are closed, the transmission rate of the PCIe link is adjusted to the preset low-power transmission rate, and the size of the data buffer area is adjusted to the preset minimum value. When a data transmission request is detected from the device, the closed channels are enabled in a preset order, the link transmission rate is increased accordingly, and the size of the data buffer area is restored to the corresponding bandwidth configuration value.

[0013] Furthermore, in step S3, the bandwidth dynamic adjustment operation is continuously executed. The execution cycle of the adjustment operation is consistent with the collection cycle of the real-time monitoring operation. Before each bandwidth dynamic adjustment operation, the data transmission load information on the PCIe link is collected again, and the load status information in the device resource mapping table is updated. The bandwidth adjustment is performed based on the updated device transmission load status, device resource priority, and future transmission load status. After the adjustment is completed, the validity of the bandwidth allocation is verified. If the verification is successful, the adjustment operation is completed.

[0014] Furthermore, in step S4, the data to be transmitted is split into different channels for parallel transmission. When splitting the data to be transmitted, a data block of a corresponding size is allocated to each channel according to the current available bandwidth and transmission delay of each channel. The size of the data block is proportional to the available bandwidth of the channel. The split data blocks are sent to the corresponding channels for transmission. During the transmission process, the transmission status of each channel is monitored in real time. If a transmission abnormality occurs in a certain channel, the remaining data blocks of that channel are redistributed to other normally operating channels for continued transmission.

[0015] The beneficial effects of this invention are: (1) By completing the entire process of PCIe link initialization, real-time load monitoring, dynamic bandwidth adjustment, data transmission optimization and energy efficiency management, the dynamic allocation and efficient transmission of PCIe resources are realized, the bus resource utilization efficiency is improved and the overall system operation status is optimized. (2) Bandwidth is allocated on demand by determining the equipment load status and scheduling resources according to priority. Multi-channel parallel transmission and data compression are used to reduce transmission resource occupation and alleviate transmission congestion when multiple devices share the link. (3) Switch the PCIe link power consumption mode according to the actual working status of the device, and complete the data compression and decompression operation through the hardware acceleration module. While ensuring transmission performance, reduce system power consumption and improve system operation stability and adaptability. Attached Figure Description

[0016] Figure 1 A flowchart illustrating the steps of a method for dynamic allocation and efficient transmission of PCIe resources; Figure 2 The flowchart illustrates the specific steps of a method for dynamic allocation and efficient transmission of PCIe resources provided in this embodiment. Detailed Implementation

[0017] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1 See Figure 1 This embodiment provides a method for dynamic allocation and efficient transmission of PCIe resources, the method including: S1. After the system starts, it performs initialization operations on the PCIe link, enumerates all PCIe devices connected on the PCIe link, establishes a device resource mapping table, which includes PCIe device identifier, PCIe device allocated bandwidth, PCIe device transmission load status, PCIe device resource priority and PCIe link power consumption mode fields, and allocates initial bandwidth to the PCIe link, which is a preset bandwidth value. S2. Perform real-time monitoring of the data transmission load on the PCIe link, write the monitoring results into the device resource mapping table, determine the device transmission load status on the PCIe link based on the monitoring results, determine the device resource priority based on the device transmission load status and the preset priority scheduling rules, extract the load information from the historical transmission data, build a bandwidth prediction model based on the load information, and determine the future transmission load status through the bandwidth prediction model. S3. Based on the device transmission load status, device resource priority, and future transmission load status, perform dynamic adjustment operations on the bandwidth of the PCIe link, count the idle PCIe link resources, allocate the idle PCIe link resources to devices whose transmission load meets the preset conditions, and update the bandwidth allocation information in the device resource mapping table. S4. Based on the updated device resource mapping table, perform data transmission optimization operations on the PCIe link, perform energy efficiency management operations on the PCIe link, and complete data compression and decompression operations through the hardware acceleration module.

[0019] In some embodiments, step S2 includes: S2.1. Collect real-time data transmission information on the PCIe link, including link throughput, packet queue length, and transmission delay; S2.2. Determine the device transmission load status based on real-time data transmission information. The device transmission load status includes unoccupied status, light load status, medium load status, and heavy load status. S2.3. Prioritize device resources according to the preset task type priority table, and map the task type corresponding to the device to the preset priority level; S2.4. Extract load characteristic information from historical transmission data. Load characteristic information includes load fluctuations in the time dimension, peak occurrence period, and average transmission rate. S2.5. A bandwidth prediction model is trained and generated based on load feature information. The bandwidth prediction model adopts a preset time-series prediction neural network structure, which includes an input layer, a hidden layer, and an output layer. The input layer receives load feature information, the hidden layer performs feature extraction and time-series correlation calculation on the load feature information, and the output layer outputs the transmission load status for a future set duration.

[0020] In some embodiments, step S3 includes: S3.1. Extract the device transmission load status from the device resource mapping table, and compare the device transmission load status with the preset load thresholds, which include light load threshold, medium load threshold and heavy load threshold; S3.2. Filter out devices whose transmission load has reached the heavy load threshold and generate a list of devices to be allocated resources; S3.3. Calculate the total amount of idle PCIe link resources, which includes the number of unoccupied channels and the total available bandwidth; S3.4. Allocate idle PCIe link resources to devices in the list of devices to be allocated resources, and update the bandwidth allocation information in the device resource mapping table after the allocation is completed.

[0021] In some embodiments, the data transmission optimization operation in step S4 includes: S4.1. Configure a data cache area inside the PCIe controller. The size of the data cache area is dynamically adjusted according to the device bandwidth allocation information in the device resource mapping table. S4.2. Enable the multi-channel transmission mode of the PCIe link and divide the data to be transmitted into transmission units according to the number of channels currently allocated; S4.3. Perform compression processing on the data to be transmitted. The compression processing is performed by the hardware acceleration module, which is a hardware compression and decompression acceleration module integrated inside the PCIe controller. The hardware compression and decompression acceleration module is directly connected to the data transmission channel of the PCIe controller. After the compression processing is completed, compressed data and compression identifier are generated. S4.4. Append a compression identifier to the header of the data transmission packet and transmit compressed data and data transmission packets via the PCIe link.

[0022] In some embodiments, the energy efficiency management operation in step S4 includes: S401. Extract the device transmission load status from the device resource mapping table to determine the working status of the device corresponding to the PCIe link; S402. The power consumption mode of the PCIe link is switched based on the device's working state. The power consumption modes include full power mode, medium power mode and low power mode. S403. Different power consumption modes correspond to different link transmission rates and the number of channels enabled. When switching power consumption modes, non-real-time data transmission is paused first. S404. After completing the power mode switching, resume data transmission and update the power mode information in the device resource mapping table.

[0023] In some embodiments, in step S3, an idle PCIe link resource allocation operation is performed based on the device resource priority ranking result. The allocation operation is performed in descending order of priority. First, bandwidth resources that meet the transmission requirements of the device with the highest resource priority are allocated. The remaining idle PCIe link resources are allocated to devices with subsequent priorities in turn. If the remaining resources are insufficient to meet the transmission requirements of the next priority device, the current allocation operation is stopped and the allocation is performed again in the next bandwidth dynamic adjustment cycle. After the allocation is completed, a bandwidth allocation log is generated and stored in the system storage area. The system storage area is used to record all operation information and status information related to PCIe link resource allocation.

[0024] In some embodiments, in step S4, it is determined whether the data to be transmitted meets the compression conditions. If the compression conditions are met, compression processing is performed on the data to be transmitted. When determining whether the data to be transmitted meets the compression conditions, the data type information of the data to be transmitted is first extracted, and the data type information is compared with a preset compressible data type table. If the comparison is consistent, it is determined that the compression conditions are met. A preset lossless compression algorithm is performed on the data to be transmitted that meets the compression conditions. The preset lossless compression algorithm includes the LZ77 algorithm and the Huffman coding algorithm. The compression ratio is the ratio of the compressed data size to the original data size to be transmitted. If the compression ratio is lower than the preset compression ratio threshold, the current compression processing is terminated, and the original data to be transmitted is transmitted directly.

[0025] In some embodiments, in step S4, when the device is in an idle state, the PCIe link is switched to a preset low-power mode. When switched to the preset low-power mode, unused channels in the PCIe link are closed, the transmission rate of the PCIe link is adjusted to a preset low-power transmission rate, and the size of the data buffer area is adjusted to a preset minimum value. When a data transmission request is detected, the closed channels are enabled in a preset order, the link transmission rate is increased accordingly, and the size of the data buffer area is restored to the configuration value of the corresponding bandwidth.

[0026] In some embodiments, in step S3, the bandwidth dynamic adjustment operation is continuously executed. The execution cycle of the adjustment operation is consistent with the acquisition cycle of the real-time monitoring operation. Before each bandwidth dynamic adjustment operation, the data transmission load information on the PCIe link is re-acquired, the load status information in the device resource mapping table is updated, and the bandwidth adjustment is performed based on the updated device transmission load status, device resource priority, and future transmission load status. After the adjustment is completed, the validity of the bandwidth allocation is verified. If the verification is successful, the adjustment operation is completed.

[0027] In some embodiments, in step S4, the data to be transmitted is split into different channels for parallel transmission. When splitting the data to be transmitted, a data block of a corresponding size is allocated to each channel according to the current available bandwidth and transmission delay of each channel. The size of the data block is proportional to the available bandwidth of the channel. The split data blocks are sent to the corresponding channels for transmission. During the transmission process, the transmission status of each channel is monitored in real time. If a transmission abnormality occurs in a certain channel, the remaining data blocks of that channel are redistributed to other normally operating channels for continued transmission.

[0028] Example 2 This embodiment provides a specific implementation process for a method of dynamic allocation and efficient transmission of PCIe resources. Through the standard PCIe bus hardware architecture and existing mature algorithm logic, it sequentially completes link initialization and resource mapping construction, load information collection and prediction model training, dynamic allocation and management of bandwidth resources, transmission process optimization, and link energy efficiency collaborative control operations. Figure 2 As shown, the specific implementation process is as follows: Step 1. Complete PCIe link initialization and device resource mapping construction: Step 1.1. After system startup, perform full-layer initialization of the PCIe link: The PCIe link is a layered physical transmission channel that conforms to the high-speed serial computer expansion bus standard. It adopts a point-to-point serial connection architecture and is mainly used to realize high-speed, low-latency data interaction between the central processing unit and external hardware devices. It is the core basic carrier for device communication in modern computer hardware systems. The PCIe link adopts a layered design architecture, which is divided into the transaction layer, data link layer and physical layer from top to bottom. Each layer undertakes different communication functions and works together to complete data encapsulation, transmission and parsing.

[0029] In this embodiment, the system startup phase first performs a full-level initialization operation on the PCIe link, which includes three phases in sequence: physical layer initialization, data link layer initialization, and transaction layer initialization.

[0030] The physical layer initialization phase mainly completes the detection of the physical status of the link, the synchronization of the clock signals of the transmitting and receiving ends, the negotiation of the link width and rate, and the physical connection calibration of the link by sending training sequences to eliminate link hardware failures and signal interference problems. The data link layer initialization phase mainly involves configuring link flow control parameters, initializing error detection and retransmission mechanisms, and establishing a reliable data transmission channel. The transaction layer initialization phase primarily completes transaction type configuration and address space mapping initialization, ensuring that the central processing unit can correctly access the registers and memory space of the PCIe device. Through full-level initialization operations, the PCIe link enters a stable and communicable working state, providing a reliable foundation for subsequent device connection identification and data transmission.

[0031] Step 1.2. Enumerate all PCIe devices connected to the PCIe link and collect basic information: PCIe devices are external expansion hardware components that are electrically connected to the computer system motherboard through the PCIe physical interface. They interact with the central processing unit through the PCIe bus to implement specific hardware functions. In this embodiment, all connected hardware devices on the PCIe bus are traversed according to the enumeration process defined by the PCIe bus specification, using device enumeration instructions provided by the system's underlying firmware.

[0032] During the enumeration process, the system sequentially sends configuration space read commands to each PCIe device, acquiring its unique hardware identifier, device type code, interface version information, basic operating parameters, resource requirements, and other information to complete the comprehensive identification and basic information collection of all PCIe devices. The collected device information will serve as the basis for subsequent resource allocation and management, ensuring the system can accurately identify each connected PCIe device and its basic attributes.

[0033] Step 1.3. Establish a standardized device resource mapping table and complete the initial information filling: The device resource mapping table is a structured data storage carrier in the system kernel space used to uniformly store and manage various resource information of all PCIe devices. It adopts a fixed field structure design to ensure the standardization of information storage and the efficiency of querying.

[0034] The device resource mapping table contains fixed information fields, specifically including PCIe device identifier, PCIe device allocated bandwidth, PCIe device transmission load status, PCIe device resource priority, and PCIe link power consumption mode. The PCIe device identifier field stores the unique hardware identifier of the device, enabling unique device identification; the PCIe device allocated bandwidth field stores the transmission bandwidth resources currently allocated to the device; the PCIe device transmission load status field stores the current resource occupancy level of the device; the PCIe device resource priority field stores the resource allocation priority level of the device; and the PCIe link power consumption mode field stores the current power consumption level of the corresponding link of the device. In this embodiment, all the basic information of the enumerated PCIe devices is filled into the corresponding fields of the device resource mapping table according to the field definitions, completing the initial information filling of the device resource mapping table and forming a unified device resource information management ledger, realizing centralized storage, unified management, and rapid retrieval of all PCIe device resource information.

[0035] Step 1.4. Allocate preset initial bandwidth to all PCIe links to complete basic resource configuration: The initial bandwidth is the PCIe link basic resource configuration value preset by the system, that is, the preset bandwidth value. This value is a fixed resource configuration during the system startup phase and is not adjusted with changes in real-time transmission load. It is only used to ensure that all PCIe devices can obtain basic transmission resource support during the startup phase.

[0036] In this embodiment, according to the system's preset bandwidth allocation rules, a corresponding preset initial bandwidth is allocated to each independent PCIe link to complete the initial configuration of link resources. After the initial bandwidth allocation is completed, the allocation result is synchronously written to the PCIe device allocated bandwidth field in the device resource mapping table, updating the resource configuration information in the device resource mapping table. This ensures that all PCIe devices can immediately obtain basic transmission resources after the system starts up, enabling normal initialization operation and data interaction.

[0037] Step 2. Conduct training for link load monitoring and bandwidth prediction model building: Step 2.1. Perform real-time monitoring of PCIe link data transmission load and update the resource mapping table: Data transmission load is a comprehensive reflection of the amount of data transmitted per unit time, the number of data transmission requests, the length of the data packet queue, and the degree of transmission congestion on the PCIe link. It is a core indicator for measuring the resource occupancy level of the PCIe link and the operating load of the equipment.

[0038] In this embodiment, the built-in PCIe link monitoring unit performs uninterrupted real-time monitoring of the data transmission status of all PCIe links. The PCIe link monitoring unit is integrated within the PCIe controller and directly collects physical and data link layer operational data through hardware probes, eliminating the need for a central processing unit to participate in the data acquisition process and ensuring that monitoring operations do not affect normal data transmission.

[0039] The monitoring unit continuously collects real-time transmission data of the PCIe link, including core parameters such as link throughput, packet queue length, transmission latency, and number of error packets. The collected raw data is initially processed and calculated to obtain real-time data transmission load information for each PCIe device. This calculated real-time load information is then written into the PCIe device transmission load status field of the device resource mapping table. This ensures that the load information in the device resource mapping table is synchronized with the actual operating status of the link in real time, providing accurate and real-time data support for subsequent resource priority allocation and dynamic bandwidth adjustment.

[0040] Step 2.2. Determine Device Transmission Load Status and Prioritize Device Resources: Device transmission load status is a standardized classification identifier used to categorize the resource occupancy of PCIe devices. By mapping continuous load values ​​to discrete status levels, subsequent resource scheduling logic is simplified. In this embodiment, based on transmission data acquired through real-time monitoring, the overall load level of each PCIe device is calculated. According to preset load level classification rules, the device transmission load status is divided into four levels: unoccupied, lightly loaded, medium-loaded, and heavily loaded, clearly distinguishing the resource demand and operating load levels of different devices. Based on determining the device transmission load status, and according to the preset priority scheduling rules, the priority of device resources is determined.

[0041] The preset priority scheduling rule is a pre-defined standard for determining the priority of PCIe device resource allocation. This standard is based on the type of task undertaken by the device, with different types of tasks corresponding to different priority levels. In this embodiment, the current task type undertaken by each PCIe device is matched with the preset priority scheduling rule to obtain the corresponding preset priority level. The priority level information is then written into the PCIe device resource priority field of the device resource mapping table, completing the unified division and recording of resource priorities for all devices.

[0042] Step 2.3. Extract historical transmission data and preprocess it to generate standardized load characteristic information: Historical transmission data is the complete transmission record data of all PCIe links continuously stored by the system in the past operating cycle. It contains the link operation status information under different time and load conditions and is the basic data source for building bandwidth prediction models.

[0043] In this embodiment, historical PCIe link transmission data within a specified time range is retrieved from the system's dedicated historical data storage area. Data cleaning and preprocessing operations are then performed on the original historical transmission data. The data cleaning operation is mainly used to remove outliers, missing values, and duplicate data from the original data, eliminating the interference of invalid data on model training. The preprocessing operation is mainly used to standardize the cleaned data, converting data with different dimensions and value ranges into standardized data in a unified format.

[0044] Based on the completed data preprocessing, load characteristic information reflecting load variation patterns is extracted from standardized historical transmission data. This load characteristic information is data with time-series characteristics obtained after feature engineering of the load information, specifically including time-dimensional load fluctuation characteristics, periodicity of load peak occurrences, and average transmission rate characteristics. The extracted load characteristic information will serve as input data for training the bandwidth prediction model, providing standardized training samples for the model.

[0045] Step 2.4. Construct a preset time-series prediction neural network structure and train it to generate a bandwidth prediction model: The bandwidth prediction model is a time-series prediction model used to predict the transmission load status of a PCIe link within a set time period in the future. By learning the time-series change patterns in historical load data, it achieves forward-looking prediction of the future load status, providing lead time for dynamic bandwidth adjustment. In this embodiment, a preset time-series prediction neural network structure is used to construct and train the bandwidth prediction model. The preset time-series prediction neural network structure adopts a three-layer feedforward neural network architecture, including an input layer, a hidden layer, and an output layer, with each layer connected in a fully connected manner.

[0046] The input layer is directly connected to the load feature information acquisition unit. The number of neurons in the input layer is consistent with the dimension of the load feature information, and it is used to receive the standardized load feature information after processing. The hidden layer consists of a preset number of neuron nodes. The number of neurons in each layer is set according to a preset rule. The neurons in the hidden layer are connected in a fully connected manner. Nonlinear transformation is achieved through activation functions. It is used to perform deep feature extraction and temporal correlation calculation on the load feature information. The output layer is directly connected to the system resource adjustment unit. The number of neurons in the output layer is consistent with the number of load state levels, and it is used to output the transmission load state for a future set duration.

[0047] During training, the preprocessed load feature information is used as the model's input data, and the actual load status at the corresponding time points in historical records is used as the labeled data. The backpropagation algorithm is employed to train the model. The backpropagation algorithm calculates the error between the model's output and the labeled data, propagating the error from the output layer back to the input layer. It adjusts the weight and bias parameters layer by layer, iterating until the bandwidth prediction model's prediction error reaches a preset range, thus completing the training and parameter solidification of the bandwidth prediction model.

[0048] Step 2.5. Input real-time load characteristic information and determine future transmission load status through the bandwidth prediction model: In this embodiment, the current load characteristic information, which is collected in real time and preprocessed, is input into the trained bandwidth prediction model. The bandwidth prediction model, based on its internally trained and fixed weight parameters and calculation logic, processes the input real-time load characteristic information and outputs the predicted transmission load status of each PCIe link within a set future time period. The future transmission load status information output by the bandwidth prediction model is temporarily stored in a dedicated cache area of ​​the system kernel as forward-looking data for subsequently initiating the dynamic bandwidth adjustment process. This allows bandwidth allocation to adapt to future load changes in advance, avoiding situations where resource allocation lags behind load demand.

[0049] Step 3. Implement dynamic adjustment of PCIe bandwidth and fine-grained allocation of idle resources: Step 3.1. Extract device resource information and complete load threshold comparison and heavy load device screening: The preset load threshold is a numerical standard pre-set by the system to distinguish the load levels of different devices. It is the core basis for determining whether a device needs additional bandwidth resources, specifically including three levels: light load threshold, medium load threshold, and heavy load threshold. In this embodiment, the current transmission load status information of all PCIe devices is extracted from the device resource mapping table, and the transmission load status of each device is compared with the preset load threshold one by one to determine the specific load level of each device.

[0050] Based on the load level determination, PCIe devices whose transmission load status reaches or exceeds the heavy load threshold are screened out. Their unique hardware identifiers, currently allocated bandwidth, resource priorities, and other information are then compiled to generate a list of devices awaiting resource allocation. This list is a structured list of all devices requiring additional bandwidth resources, clearly defining the target objects and basic information for this bandwidth adjustment, and providing clear guidance for subsequent idle resource statistics and allocation.

[0051] Step 3.2. Calculate the total amount of idle PCIe link resources in the system and determine the scale of allocable resources: Idle PCIe link resources refer to the idle transmission resources in the current PCIe link that are not occupied by any device. They are available resources that can be redistributed to heavily loaded devices. Specifically, they include two parts: the number of unoccupied physical channels and the total available bandwidth.

[0052] In this embodiment, all PCIe links and connected PCIe devices in the system are traversed, and the total bandwidth resources, allocated bandwidth resources, and unallocated bandwidth resources of each PCIe link are counted one by one, as well as the number of enabled and disabled physical channels in each link. By summarizing and calculating the unallocated bandwidth resources and the number of disabled physical channels of all links, the total amount of idle PCIe link resources in the global system is obtained, clarifying the scale of resources that can be reallocated during this bandwidth adjustment process, and providing basic resource boundary conditions for subsequent resource allocation operations.

[0053] Step 3.3. Execute idle resource allocation and complete resource mapping update according to device resource priority order: Based on the device resource priority information recorded in the list of devices to be allocated, sort all devices to be allocated in descending order of priority to generate a priority-sorted resource allocation queue. Based on the sorted resource allocation queue, perform the allocation operation of idle PCIe link resources, strictly following the order of priority from high to low.

[0054] First, the device with the highest resource priority is allocated sufficient bandwidth and physical channel resources to meet its transmission requirements. After resource allocation to the highest priority device, the total amount of remaining idle PCIe link resources is calculated, and these remaining idle resources are then allocated to the next highest priority devices in sequence. During resource allocation, it is continuously assessed whether the remaining idle PCIe link resources can meet the minimum transmission requirements of the next priority device. If the remaining resources are insufficient to meet the minimum transmission requirements of the next device, the allocation operation is immediately stopped, and devices that do not receive resource allocation will wait for the next bandwidth dynamic adjustment cycle to re-participate in resource allocation. After the resource allocation operation is completed, the allocated bandwidth and physical channel information are synchronously updated to the corresponding fields in the device resource mapping table, modifying the allocated bandwidth and resource occupancy status of the devices to ensure that the device resource mapping table is consistent with the current actual resource allocation status.

[0055] Step 3.4. Generate bandwidth allocation operation logs and keep the adjustment cycle synchronized with the monitoring cycle: The bandwidth allocation log is a structured text information that records the complete process of PCIe link resource allocation operations. It includes core information such as the execution time of the allocation operation, the allocation object, the amount of resources allocated, and the device status before and after the allocation. It is an important basis for subsequent system operation and maintenance and troubleshooting. In this embodiment, after each bandwidth allocation operation is completed, a corresponding bandwidth allocation log is automatically generated and stored in the system's dedicated log storage area.

[0056] The system storage area is a non-volatile storage module within the system used to store various operational logs, configuration information, and status information, capable of long-term preservation of various data generated during system operation. In this embodiment, dynamic adjustment of PCIe link bandwidth is continuously performed. The execution cycle of the adjustment operation is strictly consistent with the data collection cycle of the real-time monitoring operation to ensure that the bandwidth adjustment operation is synchronized with the update frequency of load information and responds promptly to changes in link load. Before each dynamic bandwidth adjustment operation, the latest data transmission load information on the PCIe link is re-collected, and the load status information in the device resource mapping table is updated to ensure that the bandwidth adjustment operation is performed based on the latest device operating status data.

[0057] Step 3.5. Verify the validity of the bandwidth allocation results and complete this adjustment process: After completing the bandwidth resource allocation and updating the device resource mapping table, verify the rationality and validity of this bandwidth allocation result. The verification operation mainly involves collecting device transmission status data within a set time period after the allocation is completed, comparing the changes in device load status, transmission delay, and data packet queue length before and after the allocation, and determining whether the bandwidth allocation has achieved the expected effect.

[0058] If the verification results show that the device's load status has been effectively alleviated and the transmission performance meets the expected requirements, then the bandwidth allocation is deemed valid, and the dynamic bandwidth adjustment operation is officially completed. If the verification results show that the bandwidth allocation has not achieved the expected effect, then the allocation result is marked as invalid, and the resource configuration state before allocation is restored, waiting for the next adjustment cycle to re-execute the resource allocation operation.

[0059] Step 4. Perform coordinated management and control of data transmission optimization and link energy efficiency: Step 4.1. Configure the PCIe controller data buffer area and enable multi-channel parallel transmission mode: The PCIe controller is the core hardware unit that manages all data transmission operations on the PCIe link. It is responsible for data encapsulation, transmission, reception, and parsing, and is the control core of the PCIe bus system. The data buffer area is a high-speed static random access memory integrated inside the PCIe controller. It is used to temporarily store data to be transmitted and received data, which can effectively alleviate the speed mismatch problem during data transmission and reduce transmission latency. In this embodiment, an independent data buffer area is configured for each connected PCIe device inside the PCIe controller. The size of the data buffer area is dynamically adjusted according to the device's currently allocated bandwidth information recorded in the device resource mapping table, so that the size of the buffer space is adapted to the transmission bandwidth scale of the device, avoiding transmission blockage caused by insufficient buffer space or resource waste caused by excessive buffer space.

[0060] After configuring the data buffer area, enable the multi-channel transmission mode of the PCIe link. Multi-channel transmission mode refers to a working mode that transmits data in parallel through multiple independent PCIe physical channels simultaneously. This fully utilizes the advantages of the PCIe link's multi-channel architecture and improves the overall transmission throughput of the link. After enabling multi-channel transmission mode, the continuous data stream to be transmitted is divided into a corresponding number of independent transmission units based on the number of physical channels currently allocated to the device, preparing for subsequent parallel transmission.

[0061] Step 4.2. Perform data splitting and parallel transmission and complete transmission status monitoring and anomaly handling: Further split the divided transmission units into appropriately sized data blocks. Based on the current available bandwidth and historical transmission delay of each physical channel, allocate data blocks of corresponding size to each channel. The size of the data block is proportional to the available bandwidth of the channel, so that the transmission load of each channel is balanced and avoids the situation where some channels are overloaded while some channels are idle.

[0062] The split data blocks are sent to their respective physical channels, enabling parallel data transmission across multiple channels. During this parallel transmission, the transmission status of each physical channel is monitored in real time, including parameters such as transmission rate, packet loss rate, and transmission latency. If a transmission anomaly is detected in a physical channel, such as channel failure, signal interruption, or transmission timeout, transmission on that channel is immediately suspended. The remaining untransmitted data blocks are retrieved and redistributed to less loaded normal channels based on their current load, ensuring the continuity and stability of the overall data transmission process and preventing the entire data transmission task from failing due to a single channel failure.

[0063] Step 4.3. Perform data compression and decompression processing via the hardware compression / decompression acceleration module: The hardware acceleration module is a dedicated hardware compression / decompression acceleration module integrated within the PCIe controller. This module uses dedicated hardware logic circuits to implement compression and decompression algorithms, has independent computing and control units, and is directly connected to the data transmission channel of the PCIe controller. It can directly complete compression and decompression operations in the data transmission pipeline without the need for the central processing unit to participate in the core computing process. In this embodiment, at the data sending end, compression processing is performed on the data to be transmitted, and all compression operations are independently completed by the hardware compression / decompression acceleration module.

[0064] Before compression, the data type information of the data to be transmitted is extracted and compared with the system's preset list of compressible data types. If the comparison results match, the data is deemed to meet the compression conditions and compression can be performed. The preset list of compressible data types is a list of data types that can be compressed without lossless compression, containing all data types suitable for lossless compression. For transmitted data that meets the compression conditions, a preset lossless compression algorithm is used for compression. The preset lossless compression algorithms include the LZ77 algorithm and the Huffman coding algorithm. The LZ77 algorithm is a lossless compression algorithm based on the sliding window dictionary matching principle. It compresses data by finding repeated byte sequences in the data and replacing the repeated sequences with pointers to the corresponding positions in the dictionary. The Huffman coding algorithm is a variable-length coding algorithm based on character frequency. It assigns shorter codes to characters with high frequency and longer codes to characters with low frequency, further reducing the data size.

[0065] During compression, the compression ratio is calculated in real time. The compression ratio is the ratio of the compressed data size to the original data size. If the calculated compression ratio is lower than a preset threshold, the compression is considered invalid, and the compression process is immediately terminated, directly transmitting the original data to avoid wasting system resources. After compression, compressed data and a corresponding compression identifier are generated. The compression identifier marks the data's compression status, the compression algorithm used, and the decompression parameters. This identifier is appended to the header of the transmission data packet and transmitted to the receiving end along with the compressed data via the PCIe link. At the receiving end, the hardware compression / decompression acceleration module reads the compression identifier from the header of the transmission data packet. Based on the information in the compression identifier, the corresponding decompression algorithm is used to decompress the compressed data, restoring the original data.

[0066] Step 4.4. Dynamically switch PCIe link power consumption modes based on device operating status: Extract the current transmission load status information of the PCIe device from the device resource mapping table, and determine the device operating status corresponding to the PCIe link based on the load status information. Dynamically switch the power consumption mode corresponding to the PCIe link according to the device operating status to achieve fine-grained control of link power consumption.

[0067] PCIe link power consumption modes refer to the link's power consumption operating level. Different power consumption modes correspond to different link transmission rates, the number of physical channels enabled, and operating voltages. Specifically, there are three levels: full power consumption mode, medium power consumption mode, and low power consumption mode. In full power consumption mode, the link enables all allocated physical channels, operating at the highest transmission rate and operating voltage, providing the maximum transmission bandwidth. In medium power consumption mode, the link disables some unnecessary physical channels, reducing the transmission rate and operating voltage to reduce power consumption while ensuring basic transmission performance. In low power consumption mode, the link retains only the minimum necessary physical channels, operating at the lowest transmission rate and operating voltage, minimizing link power consumption.

[0068] When switching power consumption modes, a power consumption mode switching request is first sent to the device, pausing non-real-time data transmission operations. The switching operation is only performed after the device completes its current transmission task, preventing data loss or transmission errors during the switching process. After the power consumption mode switch is complete, normal data transmission operations resume, and the new power consumption mode information is synchronously updated to the PCIe link power consumption mode field in the device resource mapping table to ensure the accuracy of the status information.

[0069] Step 4.5. Perform Idle State Low-Power Management and Fast Transmission Request Response: When the device's operating state is determined to be idle, switch the corresponding PCIe link to the preset low-power mode. When switching to the preset low-power mode, shut down all unused physical channels in the PCIe link, adjust the link's transmission rate to the preset low-power transmission rate, and simultaneously adjust the size of the corresponding data buffer area to the preset minimum value to minimize the link's static and dynamic power consumption.

[0070] In low-power mode, the system continuously monitors the transmission request status of devices. When a new data transmission request is detected, the link wake-up process is immediately initiated, gradually enabling physical channels that were disabled in low-power mode. This increases the link's transmission rate and operating voltage, while simultaneously restoring the data buffer size to the configured value corresponding to the currently allocated bandwidth. The link wake-up process employs a stepped approach to avoid sudden changes in power consumption and performance impacting system stability, ensuring a rapid response to device transmission requests and maintaining system responsiveness while reducing energy consumption.

[0071] In some embodiments, the bandwidth prediction model can be replaced by a sliding window average prediction model. The sliding window average prediction model is a classic prediction model based on smoothing time-series data in the prior art. It calculates the arithmetic mean of recent load data over a fixed period and directly outputs the future transmission load status. This model does not require a complex neural network training process, has a simple operation flow, low hardware resource consumption, and faster response speed. It is suitable for system operation scenarios with high real-time requirements and limited hardware resources.

[0072] In some embodiments, the preset lossless compression algorithm can be replaced by the DEFLATE algorithm. The DEFLATE algorithm is the most widely used general lossless compression algorithm in the prior art. It integrates the technical features of the LZ77 algorithm and the Huffman coding algorithm, and uses dynamic Huffman coding to further improve compression efficiency, while also having good data compatibility.

[0073] In some embodiments, the basis for prioritizing device resources can be replaced by the device hardware type. Data storage devices, network communication devices, and data computing devices are divided into different priority levels in sequence to adapt to the resource requirements of different types of hardware devices and improve the pertinence and rationality of resource allocation.

[0074] In some embodiments, the PCIe link bandwidth adjustment period can be dynamically adjusted according to the overall system load. When the overall system load is high, the bandwidth adjustment period is shortened to improve resource response speed; when the overall system load is low, the bandwidth adjustment period is appropriately extended to reduce the consumption of system computing resources and balance the system's response performance and resource overhead.

[0075] In some embodiments, the data cache area can be adjusted in a step-by-step manner, gradually adjusting the size of the data cache area in multiple stages according to the changes in device bandwidth allocation, so as to avoid the impact of sudden and large changes in cache space on the stability of data transmission.

[0076] This embodiment achieves dynamic on-demand allocation and efficient transmission of PCIe resources through the coherent execution of full-level initialization of PCIe links, real-time load monitoring and bandwidth prediction model construction, dynamic and refined allocation of bandwidth resources, data transmission process optimization and collaborative management of link energy efficiency. All steps are implemented through existing mature hardware architecture and standard algorithms, and have feasibility and compatibility for implementation.

[0077] This embodiment completes the standardized initialization of PCIe links and the construction of device resource mapping tables during the system startup phase, establishing a unified device information management framework. This framework can clearly and accurately record the resource configuration and operating status of all PCIe devices, providing a foundation for subsequent end-to-end resource management. Through the combined application of real-time load monitoring and bandwidth prediction models, the real-time load status and future load change trends of devices can be obtained synchronously. This allows bandwidth allocation to break free from the limitations of traditional static configuration, enabling proactive adaptation to load changes and achieving forward-looking resource allocation, effectively improving the overall utilization efficiency of PCIe link resources.

[0078] The data transmission optimization stage utilizes multi-channel parallel transmission and hardware-accelerated compression processing to reduce resource consumption during data transmission, lower transmission latency, and alleviate transmission congestion issues when multiple devices share a link. The energy efficiency management stage dynamically switches power consumption modes based on the actual operating status of the devices, effectively reducing link energy consumption when devices are idle and quickly restoring performance when devices have transmission needs, achieving a balance between system transmission performance and energy consumption. The independent operation of the hardware compression and decompression acceleration module removes compression and decompression tasks from the central processing unit (CPU), effectively reducing the CPU's computational load and improving the overall system smoothness. This solution is adaptable to the operational requirements of various PCIe devices, demonstrating positive performance in resource allocation rationality, transmission efficiency, and energy consumption management. It effectively improves the problems of low resource utilization, insufficient transmission efficiency, and crude energy consumption management caused by traditional static resource allocation methods, providing a standardized implementation path for PCIe bus resource management.

[0079] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for dynamic allocation and efficient transmission of PCIe resources, characterized in that, include: S1. After the system starts, it performs initialization operations on the PCIe link, enumerates all PCIe devices connected on the PCIe link, establishes a device resource mapping table, which includes PCIe device identifier, PCIe device allocated bandwidth, PCIe device transmission load status, PCIe device resource priority and PCIe link power consumption mode fields, and allocates initial bandwidth to the PCIe link, which is a preset bandwidth value. S2. Perform real-time monitoring of the data transmission load on the PCIe link, write the monitoring results into the device resource mapping table, determine the device transmission load status on the PCIe link based on the monitoring results, determine the device resource priority based on the device transmission load status and the preset priority scheduling rules, extract the load information from the historical transmission data, build a bandwidth prediction model based on the load information, and determine the future transmission load status through the bandwidth prediction model. S3. Based on the device transmission load status, device resource priority, and future transmission load status, perform dynamic adjustment operations on the bandwidth of the PCIe link, count the idle PCIe link resources, allocate the idle PCIe link resources to devices whose transmission load meets the preset conditions, and update the bandwidth allocation information in the device resource mapping table. Step S3 includes: S3.

1. Extract the device transmission load status from the device resource mapping table, and compare the device transmission load status with the preset load thresholds, which include light load threshold, medium load threshold and heavy load threshold; S3.

2. Filter out devices whose transmission load has reached the heavy load threshold and generate a list of devices to be allocated resources; S3.

3. Calculate the total amount of idle PCIe link resources, which includes the number of unoccupied channels and the total available bandwidth; S3.

4. Allocate idle PCIe link resources to devices in the list of devices to be allocated resources, and update the bandwidth allocation information in the device resource mapping table after the allocation is completed; In step S3, idle PCIe link resources are allocated based on the device resource priority ranking result. The allocation operation is performed in descending order of priority. First, the device with the highest resource priority is allocated bandwidth resources to meet its transmission needs. The remaining idle PCIe link resources are allocated to devices with subsequent priorities in turn. If the remaining resources are insufficient to meet the transmission needs of the next priority device, the allocation operation is stopped and waits for the next bandwidth dynamic adjustment cycle before being re-executed. After the allocation is completed, a bandwidth allocation log is generated and stored in the system storage area. The system storage area is used to record all operation information and status information related to PCIe link resource allocation. S4. Based on the updated device resource mapping table, perform data transmission optimization operations on the PCIe link, perform energy efficiency management operations on the PCIe link, and complete data compression and decompression operations through the hardware acceleration module; The data transmission optimization operation in step S4 includes: S4.

1. Configure a data cache area inside the PCIe controller. The size of the data cache area is dynamically adjusted according to the device bandwidth allocation information in the device resource mapping table. S4.

2. Enable the multi-channel transmission mode of the PCIe link and divide the data to be transmitted into transmission units according to the number of channels currently allocated; S4.

3. Perform compression processing on the transmitted data. The compression processing is performed by the hardware acceleration module, which is a hardware compression and decompression acceleration module integrated inside the PCIe controller. The hardware compression and decompression acceleration module is directly connected to the data transmission channel of the PCIe controller. After the compression processing is completed, compressed data and compression identifier are generated. S4.

4. Append a compression identifier to the header of the transmission data packet and transmit compressed data and transmission data packets through the PCIe link; The energy efficiency management operations in step S4 include: S401. Extract the device transmission load status from the device resource mapping table to determine the working status of the device corresponding to the PCIe link; S402. The power consumption mode of the PCIe link is switched based on the device's working state. The power consumption modes include full power mode, medium power mode and low power mode. S403. Different power consumption modes correspond to different link transmission rates and the number of channels enabled. When switching power consumption modes, non-essential data transmission should be paused first. S404. After completing the power mode switching, resume data transmission and update the power mode information in the device resource mapping table.

2. The method according to claim 1, characterized in that, Step S2 includes: S2.

1. Collect real-time data transmission information on the PCIe link, including link throughput, packet queue length, and transmission delay; S2.

2. Determine the device transmission load status based on real-time data transmission information. The device transmission load status includes unoccupied status, light load status, medium load status, and heavy load status. S2.

3. Prioritize device resources according to the preset task type priority table, and map the task type corresponding to the device to the preset priority level; S2.

4. Extract load characteristic information from historical transmission data. Load characteristic information includes load fluctuations in the time dimension, peak occurrence period, and average transmission rate. S2.

5. A bandwidth prediction model is trained and generated based on load feature information. The bandwidth prediction model adopts a preset time-series prediction neural network structure, which includes an input layer, a hidden layer, and an output layer. The input layer receives load feature information, the hidden layer performs feature extraction and time-series correlation calculation on the load feature information, and the output layer outputs the transmission load status for a future set duration.

3. The method according to claim 1, characterized in that, In step S4, it is determined whether the transmitted data meets the compression conditions. If the compression conditions are met, the transmitted data is compressed. When determining whether the transmitted data meets the compression conditions, the data type information of the transmitted data is extracted first, and the data type information is compared with the preset compressible data type table. If the comparison is consistent, it is determined that the compression conditions are met. The transmitted data that meets the compression conditions is processed by a preset lossless compression algorithm. The preset lossless compression algorithm includes the LZ77 algorithm and the Huffman coding algorithm. The compression ratio is the ratio of the compressed data size to the original data size. If the compression ratio is lower than the preset compression ratio threshold, the current compression process is terminated, and the original data is transmitted directly.

4. The method according to claim 1, characterized in that, In step S4, when the device is in an idle state, the PCIe link is switched to a preset low-power mode. When switched to the preset low-power mode, unused channels in the PCIe link are closed, the transmission rate of the PCIe link is adjusted to the preset low-power transmission rate, and the size of the data buffer area is adjusted to the preset minimum value. When a data transmission request is detected from the device, the closed channels are gradually enabled, the link transmission rate is increased, and the size of the data buffer area is restored to the corresponding bandwidth configuration value.

5. The method according to claim 1, characterized in that, In step S3, the bandwidth dynamic adjustment operation is continuously executed. The execution cycle of the adjustment operation is consistent with the collection cycle of the real-time monitoring operation. Before each bandwidth dynamic adjustment operation, the data transmission load information on the PCIe link is collected again, and the load status information in the device resource mapping table is updated. The bandwidth adjustment is performed based on the updated device transmission load status, device resource priority, and future transmission load status. After the adjustment is completed, the validity of the bandwidth allocation is verified. If the verification is successful, the adjustment operation is completed.

6. The method according to claim 1, characterized in that, In step S4, the transmission data is split into different channels for parallel transmission. When splitting the transmission data, a data block of a corresponding size is allocated to each channel according to the current available bandwidth and transmission delay of each channel. The size of the data block is proportional to the available bandwidth of the channel. The split data blocks are sent to the corresponding channels for transmission. During the transmission process, the transmission status of each channel is monitored in real time. If a transmission abnormality occurs in a certain channel, the remaining data blocks of that channel are redistributed to other normally operating channels to continue transmission.

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