Edge computing-based automatic fatting system data acquisition method

Abstract

This invention relates to the field of industrial data acquisition and edge network technology, and discloses a data acquisition method for an automatic grease-adding system based on edge computing. This method establishes a node mapping table in the edge control unit, generates a global interlocking signal by comparing the real-time current of the main circuit with a threshold, and dynamically switches the polling frequency of the underlying bus. When the value of the underlying status register deviates from the interlocking signal, a time window anti-jitter mechanism based on time difference is introduced to filter out missynchronization caused by physical transmission delay. Furthermore, the edge unit implements read-write decoupling; read requests achieve a through-response based on the mapping table, and write requests are stored in a write buffer queue after acceptance evaluation. When the interlocking signal undergoes a state switch due to a physical abrupt change, the system forcibly locks the queue and suspends writing, prioritizing high-frequency status polling. This invention effectively eliminates read-write collisions caused by network latency, thereby improving the data consistency and operational security of the system under complex operating conditions.

Description

Technical Field

[0001] This invention relates to the field of industrial data acquisition and edge network technology, specifically to a data acquisition method for an automatic grease dispensing system based on edge computing. Background Technology

[0002] Automatic grease dispensing systems are widely used in complex industrial environments such as heavy machinery, wind power generation, and metallurgical equipment. They are primarily responsible for delivering lubricating media to various critical friction pairs at regular intervals and in precise quantities to ensure the continuous and reliable operation of large equipment. With the continuous evolution of industrial internet and automation technologies, existing automatic grease dispensing systems have generally shifted from early stand-alone control to a centralized network architecture based on a host computer or data acquisition and monitoring control system. In this traditional architecture, the control center mainly uses standard industrial low-level buses such as RS485 and CAN to periodically poll controlled nodes in the field, such as the grease pump drive motor, status monitoring sensors, and electromagnetic proportional valves, to complete the acquisition of status data and the dissemination of control parameters.

[0003] However, in real-world heavy-duty industrial environments, the baud rate and communication bandwidth of the underlying bus are typically limited by physical cable length and harsh electromagnetic interference conditions, resulting in extremely limited overall network communication capacity. In existing centralized control methods, every status read or parameter write operation initiated by the upper-level system directly penetrates and is translated into a physical communication action on the underlying bus. This completely synchronous direct interaction mechanism easily leads to the underlying network being in a state of indiscriminate full or overload for extended periods. Especially when facing high-frequency concurrent queries from multiple nodes, the massive number of read requests reduces system response speed. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a data acquisition method for an automatic grease-adding system based on edge computing. This method solves the problems of network read / write concurrency collisions, data loss, and misjudgment caused by limited bus bandwidth and misalignment of physical electrical feedback and digital communication timing when existing centralized industrial control systems face sudden changes in underlying physical anomalies.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a data acquisition method for an automatic fat-adding system based on edge computing, comprising the following steps: First, a node mapping table is established in the edge control unit to correspond to multiple controlled nodes in the underlying network. The table stores the status register values, operating parameter values, update timestamps and communication status identifiers of the controlled nodes. Secondly, the real-time current of the current transformer is compared with a preset threshold to generate a global interlock signal, and the frequency of the controlled node is switched by polling the underlying bus accordingly. Subsequently, during polling, the communication status identifier is updated based on the communication results. The status register value in the node mapping table is compared with the global interlock signal. The current timestamp is obtained and the difference between it and the updated timestamp is calculated to determine whether to send a synchronization broadcast to the underlying bus. The updated timestamp is then updated with the current timestamp. Simultaneously, it receives read requests or write requests carrying write parameters from the upper-layer system; based on the communication status identifier, it responds to the read request according to the node mapping table, or decides whether to store the write parameters in the write buffer queue. Finally, based on the state change event of the global interlock signal, the write buffer queue is locked, the issuance of the write parameters to the underlying bus is paused, and the state polling is performed first.

[0006] This invention establishes an adaptive bus scheduling model driven by underlying physical parameters. The system assesses the overall mechanical load status by real-time acquisition of the current from the current transformers in the power supply circuit. The real-time current... With preset threshold Perform a comparison, output a global interlock signal and map it to the bus polling cycle. Its dynamic switching model satisfies the following relationship: ; in, For the first cycle, It is the second period and satisfies This mechanism enables the system to maintain low-frequency polling under light load conditions: the period is... To free up underlying bus bandwidth; automatically switch to high-frequency polling under heavy load or abnormal conditions: the period is This significantly improves the monitoring accuracy of the edge control unit for the controlled nodes.

[0007] To address the data inconsistency issue caused by inherent communication delays in the underlying industrial bus, this invention designs a debouncing algorithm that combines timestamp comparison. When the controlled node status register value recorded in the edge node mapping table logically deviates from the current global interlock signal, the system does not immediately issue a status synchronization broadcast, but instead extracts the current timestamp. With the record's update timestamp Perform the difference calculation. Define the time difference. The system executes the following anti-shake determination model: ; in, The current inconsistency is determined to be a pseudo-mutation caused by bus delay, and a synchronization broadcast will not be sent for the time being. If the characterization indicates a true state out-of-sync, a state synchronization broadcast is sent to the underlying bus. Given the known underlying bus polling latency, This is the preset system compensation time. This model filters out false positives caused by network physical latency and avoids unnecessary consumption of bus resources by redundant broadcast commands.

[0008] For read commands issued from the upper layer, the edge control unit directly returns the latest data through the memory-level node mapping table, achieving zero-latency response to query commands and completely isolating upper-layer applications from encroaching on the underlying network bandwidth. For write requests, this invention introduces a write buffer queue for asynchronous management. When the system detects a change in the state of the global interlock signal, it triggers a queue locking anti-collision mechanism: the system forcibly locks the write buffer queue, suspends the task issuance of write parameters in the queue, and allocates all bus resources to the status polling tasks of the controlled nodes. The lock is released and write task issuance resumes only after the polling confirms that the status register value of the controlled node is completely consistent with the current interlock signal. This mechanism reduces device malfunctions caused by collisions on the bus due to system state switching and the issuance of control parameters from the underlying communication timing.

[0009] This invention provides a data acquisition method for an automatic fat-adding system based on edge computing. It has the following beneficial effects: 1. This invention compares the real-time current collected by the main circuit transformer with a preset threshold to generate a global interlock signal to dynamically switch the polling frequency of the underlying bus. This allows the system to maintain an extremely low network load for a long period during stable operation, and to instinctively switch to a high-frequency mode to accurately capture underlying details in the event of a sudden physical change such as pipeline blockage.

[0010] 2. When the status register value of the edge-side buffer deviates from the global interlock signal, the system calculates the time difference and compares it with a preset time window that covers the physical delay, thereby filtering out the brief digital synchronization loss caused by the limited bus baud rate and avoiding redundant synchronous broadcasts and channel congestion caused by logical misjudgments.

[0011] 3. This invention creates a node mapping table in the local memory of the edge control unit. When a read request is received from the upper-layer system, the edge side directly extracts the cached data in the mapping table for penetration interception and response, thereby achieving microsecond-level zero-latency data feedback and reserving network bandwidth for core device scheduling and anomaly monitoring.

[0012] 4. The edge control unit of this invention pre-compares and intercepts duplicate write parameters that are redundant with the current operating state, and actively triggers a protection mechanism to refuse enqueueing when the write buffer queue approaches its maximum capacity. This optimization based on memory scheduling mitigates the risk of disordered accumulation of asynchronous write tasks during periods of communication degradation. Attached Figure Description

[0013] Figure 1 This is a topology diagram of the automatic fat-adding system architecture of the present invention; Figure 2 This is the main flowchart of the data acquisition and control method of the present invention; Figure 3 This is a schematic diagram of the internal data structure and memory mapping of the edge control unit of the present invention; Figure 4 This is a logic diagram of the time window anti-shake and state synchronization determination algorithm of the present invention; Figure 5 This is a flowchart of the read / write decoupling and queue acceptance management of the present invention. Detailed Implementation

[0014] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Please see the appendix Figure 1 To be continued Figure 5 This invention provides a data acquisition method for an automatic grease dispensing system based on edge computing. This method is deployed within the edge control unit of the automatic grease dispensing system. An automatic grease dispensing system typically includes an upper-layer system, an edge control unit, and an lower-layer network. The upper-layer system is responsible for overall production scheduling and parameter distribution, such as a SCADA system or an industrial PC. The edge control unit acts as the communication hub between the upper and lower-level machines, communicating with multiple controlled nodes via a lower-layer bus. These controlled nodes include automatic grease dispensing pump drive motors, status monitoring sensors, and electromagnetic proportional valves distributed throughout the industrial site. Furthermore, a current transformer is configured on the power supply circuit for non-contact acquisition of the system's overall operating current.

[0016] The data acquisition method for the edge computing-based automated fat-adding system may include the following steps: S1: Establish a node mapping table for the corresponding underlying controlled node in the edge control unit, which stores the status register value, running parameter value, update timestamp and communication status identifier of the controlled node.

[0017] S2: Compare the real-time current of the current transformer with a preset threshold to generate a global interlock signal, and switch the frequency of the controlled node by polling the underlying bus accordingly.

[0018] S3: During polling, update the communication status identifier based on the communication result, compare the status register value with the global interlock signal, obtain the current timestamp and calculate the difference between it and the updated timestamp to determine whether to send a synchronization broadcast to the underlying bus, and update the updated timestamp with the current timestamp.

[0019] S4: Receive a read request or a write request carrying write parameters from the upper layer system; respond to the read request based on the communication status identifier and the node mapping table, or decide whether to store the write parameters in the write buffer queue.

[0020] S5: Lock the write buffer queue based on the state change event of the global interlock signal, suspend the issuance of the write parameters to the underlying bus, and prioritize the execution of state polling.

[0021] The technical details of steps S1 and S2 will be elaborated below in conjunction with the above system architecture.

[0022] In step S1, after the edge control unit is powered on and initialized, it first performs a low-level network probing task. The edge control unit sends broadcast probe messages through the low-level bus to obtain the total number of controlled nodes on the current low-level bus, thereby establishing a set of controlled nodes.

[0023] After identifying the set of controlled nodes, the edge control unit allocates an independent data mapping area for each controlled node in its local memory. This data mapping area is organized according to a preset byte structure, associating and binding the acquired key data of the controlled nodes to form a node mapping table. Specifically, the bound data includes status register values ​​representing the current physical state of the node, operating parameter values ​​representing the node's settings, an update timestamp used to record the most recent communication time, and a communication status identifier representing the current network connectivity.

[0024] In step S2, the edge control unit acquires the real-time current signal of the current transformer installed on the main power supply circuit of the system through the analog-to-digital conversion circuit.

[0025] The acquired real-time current is compared with a preset threshold to generate a global interlock signal. This global interlock signal directly maps to and regulates the frequency of polling the controlled nodes via the underlying bus. Its dynamic switching model satisfies the following formula: ; in, Defined as the current polling cycle of the underlying bus; Defined as the real-time current collected by the current transformer; Defined as a preset threshold. This preset threshold The rated current of the system is obtained by calibrating it under standard no-load or normal grouting conditions. Defined as the first cycle, representing the regular polling interval when the system is in a normal state; Defined as the second cycle, it represents the high-frequency polling interval after the system detects an overcurrent. Among them, The value is strictly less than .

[0026] when Less than or equal to When the system is determined to be in normal operating condition, the edge control unit sets the global interlock signal to the first state. At this time, the system operates with a relatively long first cycle. The controlled nodes are polled. This mechanism reduces the bus communication frequency when the system is stable, effectively freeing up the underlying bus bandwidth and reducing the resource consumption of invalid communication.

[0027] when Greater than This indicates a potential blockage in the system piping or a sudden increase in motor load. The edge control unit immediately sets the global interlock signal to the second state. Simultaneously, the system switches the polling cycle to the shorter second cycle. The adaptive frequency modulation mechanism ensures that the edge control unit can acquire the latest status data of the underlying controlled nodes at high frequency in the instant when the physical state of the system changes abruptly, thereby improving the accuracy of fault monitoring and status capture.

[0028] In this embodiment, during the process of polling the underlying bus, the edge control unit is not only responsible for collecting real-time data, but also simultaneously performs link status diagnosis and data consistency de-jitter determination. Specifically, for the connectivity diagnosis of the communication link, the system configures an independent continuous timeout counter for each controlled node in the node mapping table.

[0029] The edge control unit sends polling commands to the controlled nodes at the frequency determined in the aforementioned steps. If the polling command times out without a response, the system increments the continuous timeout counter for the corresponding node.

[0030] The system monitors the value of the continuous timeout counter in real time. When the value is greater than or equal to a preset threshold, the edge control unit updates the communication status identifier of the corresponding controlled node in the node mapping table to an abnormal identifier, indicating that the node has gone offline or has experienced a hardware-level failure. Conversely, if the polling command communication is successful, the system immediately resets the continuous timeout counter and updates the communication status identifier to a normal identifier, thereby maintaining the accurate mapping of the link status.

[0031] In this embodiment, the edge control unit extracts the status register value in the node mapping table and compares it with the global interlocking signal generated in step S2.

[0032] If the status register value matches the global interlock signal status, it indicates that the logic state of the underlying device is consistent with the physical current feedback of the main circuit, and polling continues according to the original procedure. If the two are inconsistent, the system determines that a state deviation has occurred. Given the inherent transmission delay of the industrial underlying bus, the speed at which the physical current change signal reaches the controller will inevitably be faster than the speed at which the bus message is uploaded. Directly issuing synchronization commands will lead to unnecessary bus congestion.

[0033] To address this, the system introduces a time-window debouncing mechanism. When an inconsistency is detected, the edge control unit calls the system clock to obtain the current timestamp and calculates the time difference between this current timestamp and the update timestamp of the original record in the node mapping table. Based on this time difference, it determines whether to send a status synchronization broadcast to the underlying bus. The specific debouncing determination model formula is as follows: ; In the above formula, Defined as the trigger flag for state synchronization broadcast; Defined as a time difference, it is calculated by subtracting the updated timestamp from the current timestamp; Defined as a preset time window.

[0034] For this preset time window The value of is strictly equal to the underlying bus polling latency. With preset compensation time The sum of Among them, the underlying bus polling latency time The baud rate, message length, and number of nodes of the underlying bus are statically calculated and calibrated during the system initialization phase; preset compensation time. It is a fixed margin value pre-configured according to the message processing timing of the controlled node microcontroller.

[0035] According to the above model, when the time difference Less than the preset time window When, determine the current result as At this point, the system determines that the inconsistency is caused by a lag due to the inherent physical transmission delay of the underlying bus, which is within the legal error range. Therefore, it does not send a status synchronization broadcast for the time being.

[0036] When time difference Greater than or equal to the preset time window When, determine the current result as At this point, the system determines that the delay has exceeded the reasonable physical transmission window, confirming that the underlying device has lost synchronization or is stuck in logic. The edge control unit immediately sends a status synchronization broadcast to the underlying bus, forcing the underlying nodes to refresh their status.

[0037] After completing the above comparison and anti-jitter judgment logic, regardless of whether a status synchronization broadcast is sent, the edge control unit extracts the current timestamp obtained from this communication and uses it to overwrite the original update timestamp in the update node mapping table to ensure the timeliness of the time difference calculation benchmark. Through this mechanism, the system filters out pseudo-fault mutations caused by network physical latency, ensuring the stability of bus communication and the accuracy of control command issuance.

[0038] In this embodiment, the edge control unit continuously listens to the instructions issued by the upper-layer system. For the received read request or write request carrying write parameters, the system performs differentiated processing through the edge-side read-write decoupling mechanism.

[0039] When a read request is received from the upper-layer system, the edge control unit first queries the communication status identifier of the corresponding controlled node in the node mapping table. If the communication status identifier is an abnormal identifier, it indicates that the underlying device is offline or in a fault state. The edge control unit directly returns an abnormal response message to the upper-layer system.

[0040] If the query result shows a normal communication status, the edge control unit will not forward the read request to the underlying bus. Instead, it will directly extract the operating parameter value from the node mapping table cache. The system encapsulates this operating parameter value into a response message and returns it to the upper-layer system. This read interception mechanism avoids the upper-layer query operation from crowding out the bandwidth of the underlying bus, achieving data penetration and zero-latency response for the query command.

[0041] In this embodiment, the system first checks the communication status identifier. If the communication status identifier is abnormal, the edge control unit refuses to execute the write task and does not cache the write parameters.

[0042] Provided the communication status is normal, the edge control unit compares the write parameters sent from the upper layer with the existing operating parameter values ​​in the node mapping table bit by bit. If the comparison results match, it indicates that the actual operating parameters of the current lower-level controlled node meet the requirements set by the upper layer, and the system actively discards the redundant write request, thereby intercepting invalid bus write operations.

[0043] If the comparison results are inconsistent, the system determines that the write request is a valid control command. At this time, the edge control unit stores the write parameters into a pre-allocated write buffer queue in local memory. The write buffer queue manages write tasks according to the first-in-first-out timing principle, and sends them to the controlled nodes in sequence when the underlying bus is idle.

[0044] To ensure the absolute safety of the system under physical anomalies such as sudden load changes, the daemon process in the edge control unit monitors the state change events of the global interlocking signals in real time.

[0045] When the daemon detects that the global interlock signal has switched from the first state, which indicates normal operation, to the second state, which indicates overload or abnormality, the system determines that a state change event has been triggered. The triggering of this event means that the power supply circuit current has experienced an out-of-limit sudden change, and the underlying physical device may be in a critical state transition period.

[0046] In response to this state change event, the edge control unit immediately locks the write buffer queue. A locked buffer queue forcibly suspends its internal task scheduling for sending write parameters to the underlying bus. The system fully releases the bus time slices originally used for sending write parameters, prioritizing them for high-frequency status polling of controlled nodes.

[0047] This locking mechanism ensures that during critical windows when the system state undergoes physical changes, the underlying bus resources are absolutely prioritized for state capture, thus physically preventing communication packet loss or control disorder caused by collisions between the issued control parameters and the underlying state change messages on the bus.

[0048] After pausing write tasks and prioritizing status polling, the system continuously verifies the underlying feedback. When a round of status polling confirms that the status register value uploaded by the controlled node is consistent with the current global interlock signal, it indicates that the underlying device has completed the state transition and is stabilizing. At this point, the edge control unit sets the write buffer queue to an idle state to release the aforementioned lock.

[0049] After the lock is released, the edge control unit resumes the previously suspended task of sending write parameters to the underlying bus. After successfully sending the write parameters to the underlying controlled node and receiving the execution confirmation message, the system removes the corresponding write parameters from the write buffer queue, thus completing the asynchronous write control process in a closed loop.

[0050] In this embodiment, during a normal automatic grease replenishment cycle, the real-time current collected by the current transformer in the system power supply circuit is... Maintain stability and stay below the preset threshold. Based on the aforementioned dynamic polling mechanism based on physical state coupling, the edge control unit maintains the global interlock signal in the first state and uses a relatively long first cycle. The controlled nodes, such as the automatic grease pump drive motor and the electromagnetic proportional valve, are routinely polled through the underlying bus.

[0051] During this period of stable operation, if the upper-layer SCADA system issues a request to read the operating parameters of a certain node, the edge control unit directly retrieves the operating parameter value of that node from its local node mapping table and returns it promptly. Because the underlying bus maintains a low-frequency polling state and does not need to handle upper-layer query forwarding, the bandwidth utilization of the entire control network remains at an extremely low level.

[0052] When a grease filling line experiences a sudden physical blockage, the grease pump drive motor encounters abnormal mechanical resistance, causing a sudden surge in the main circuit current. The analog-to-digital conversion circuit of the edge control unit captures this real-time current. Greater than the preset threshold .

[0053] Based on the system's frequency control logic, the global interlock signal is immediately toggled to the second state. At this time, the edge control unit forces the underlying bus polling cycle to change from the first cycle. Switch to the second cycle The system enters a high-frequency polling mode to obtain details of the underlying parameters under congested conditions.

[0054] Almost simultaneously with the interlock signal flipping, the internal current loop of the controlled node (motor driver) also detects a congestion overload and attempts to update its local status register value. However, due to the baud rate limitation of the underlying industrial bus, there is a physical delay in uploading the new status message. At this point, because the global interlock signal has abruptly changed to the second state, while the status register value in the edge node's mapping table remains the old value, a logical inconsistency is detected internally by the system.

[0055] In this embodiment, the edge control unit calculates the time difference between the current timestamp and the node's updated timestamp. In the very short initial stage of the inconsistency, It must be less than the preset time window Based on the image stabilization model. The system recognizes that the deviation is due to the slow bus transmission and normal lag, which inhibits the transmission of status synchronization broadcasts.

[0056] Because the global interlock signal abruptly changes from state one to state two, the daemon process of the edge control unit detects this state change event. If the upper-layer system then issues a write request with write parameters for adjusting the grease-adding pressure, the edge control unit intercepts the request. The system forcibly locks the write buffer queue containing the write parameters.

[0057] This locking operation truncates the write task's path, preventing new pressure parameters from being forcibly written to the driver during congestion, which could lead to further mechanical damage or communication channel collisions. The entire time slice of the underlying bus is allocated to high-frequency status polling.

[0058] After a delay of several microseconds or milliseconds, the actual overload alarm message from the driver arrives at the edge control unit via the bus. The system updates the latest status register value in the node mapping table. At this time, the system performs a status comparison to confirm that the status register value in the node mapping table is consistent with the global interlock signal in the second state.

[0059] With the synchronization and confirmation of the underlying state, the edge control unit unlocks the write buffer queue, restoring its idle status. If the upper layer has taken appropriate pressure relief and recovery measures and the communication environment is stable, the system resumes the previously suspended write parameter distribution task, completing the entire closed-loop control.

[0060] This embodiment discloses the underlying memory queue management mechanism and entity execution environment of the edge control unit when processing write requests. When executing the aforementioned logic of storing write parameters into the write buffer queue, the system introduces a queue acceptance evaluation model based on memory depth. After determining that the write parameters are inconsistent with the running parameter values ​​in the node mapping table, the edge control unit synchronously calls the local memory monitoring interface to obtain the real-time queue depth of the current write buffer queue.

[0061] The system combines the real-time queue depth with the pre-allocated maximum queue capacity to perform the final enqueue determination action. Its queue acceptance determination model satisfies the following formula: ; in, Defined as a queue acceptance flag; Defined as the currently acquired real-time queue depth, representing the number of tasks waiting to be dispatched in the current queue; Defined as the pre-allocated maximum queue capacity, which is statically allocated based on the available random access memory size of the edge control unit; Defined as the write parameter carried in the write request issued by the upper-layer system; Defined as the running parameter value of the corresponding controlled node cached in the node mapping table.

[0062] When the calculation result is When the system determines that there is available space in the current queue and that the current write parameter is a valid new instruction, the edge control unit enables memory write protection, pushes the write parameter to the tail of the write buffer queue, and synchronously updates the real-time queue depth. The value.

[0063] When the calculation result is When the system determines that the queue is full or the write parameter is a redundant instruction, a full queue typically occurs when there is a prolonged low-level communication anomaly or when the global interlock signal is in the aforementioned locked state for an extended period. In this case, the system forcibly triggers the bus protection mechanism, refusing to enqueue the write parameter and directly returning a queue overflow or parameter duplication rejection message to the upper-layer system. This memory scheduling layer management mechanism prevents system memory overflow or even kernel crashes caused by the unlimited accumulation of asynchronous write tasks in the edge control unit.

[0064] In this embodiment, the edge control unit hardware that executes the above-described data acquisition and control method mainly includes a processor, a communication interface, and a computer-readable storage medium. The processor is responsible for executing the low-level control instructions and calculation logic embedded in the storage medium, including but not limited to the calculation of dynamic polling frequency switching, the calculation of time window anti-jitter difference, and the monitoring of interlocking status.

[0065] The computer-readable storage medium is used to store the system's main program code and also to create an independent data mapping area in the high-speed memory region containing the aforementioned node mapping table and the write buffer queue, to ensure extremely high memory read / write throughput. The communication interface includes a hardware channel for acquiring analog signals from the current transformer and performing digital conversion, as well as a standard industrial low-level bus transceiver for issuing polling commands.

Claims

1. A data acquisition method for an automatic fat-adding system based on edge computing, characterized in that, include: S1: Establish a node mapping table for the corresponding underlying controlled node in the edge control unit, which stores the status register value, running parameter value, update timestamp and communication status identifier of the controlled node; S2: Compare the real-time current of the current transformer with a preset threshold to generate a global interlocking signal, and switch the frequency of the controlled node by polling the underlying bus accordingly; Specifically, this includes: when the real-time current is less than or equal to the preset threshold, setting the global interlock signal to the first state, and polling the controlled node in a first cycle; When the real-time current is greater than the preset threshold, the global interlock signal is set to the second state, and the controlled node is polled in a second period, wherein the second period is less than the first period. S3: In the polling process, update the communication status identifier based on the communication result, compare the status register value with the global interlock signal, obtain the current timestamp and calculate the difference between it and the updated timestamp to determine whether to send a synchronization broadcast to the underlying bus, and update the updated timestamp with the current timestamp; S4: Receive a read request or a write request carrying write parameters from the upper layer system; respond to the read request based on the communication status identifier and the node mapping table, or decide whether to store the write parameters in the write buffer queue. S5: Lock the write buffer queue based on the state change event of the global interlock signal, suspend the issuance of the write parameters to the underlying bus, and prioritize the execution of state polling.

2. The data acquisition method for an automatic fat-adding system based on edge computing according to claim 1, characterized in that, In step S1, establishing the node mapping table specifically includes: Obtain the total number of controlled nodes on the underlying bus and establish a set of controlled nodes; An independent data mapping area is allocated in the memory area for each controlled node in the set of controlled nodes, and the corresponding status register value, the running parameter value, the update timestamp and the communication status identifier are associated to form the node mapping table.

3. The data acquisition method for an automatic fat-adding system based on edge computing according to claim 1, characterized in that, In step S3, updating the communication status identifier specifically includes: Configure a continuous timeout counter in the node mapping table; A polling command is sent to the controlled node; if a communication timeout occurs, the continuous timeout counter is incremented. When the continuous timeout counter is greater than or equal to a preset number of times threshold, the communication status identifier is updated to an abnormal identifier; if the communication is successful, the continuous timeout counter is reset and the communication status identifier is updated to a normal identifier.

4. The data acquisition method for the automatic fat-adding system based on edge computing according to claim 1, characterized in that, In step S3, calculating the difference to determine whether to send a synchronization broadcast specifically includes: If the status register value is inconsistent with the global interlock signal, calculate the time difference between the current timestamp and the updated timestamp; If the time difference is less than a preset time window, no synchronization broadcast is sent; if the time difference is greater than or equal to the preset time window, a status synchronization broadcast is sent to the underlying bus.

5. The data acquisition method for an automatic fat-adding system based on edge computing according to claim 4, characterized in that, The preset time window is equal to the sum of the underlying bus polling delay time and the preset compensation time.

6. The data acquisition method for an automatic fat-adding system based on edge computing according to claim 3, characterized in that, In step S4, responding to the read request specifically includes: If the communication status identifier is the abnormal identifier, return an abnormal response message to the upper-layer system; If the communication status identifier is the normal identifier, the operating parameter value is extracted and returned as a response message.

7. The data acquisition method for an automatic fat-adding system based on edge computing according to claim 3, characterized in that, In step S4, the write request specifically includes: If the communication status identifier is the abnormal identifier, refuse to store the write parameters into the write buffer queue; If the communication status identifier is the normal identifier, when the write parameter is inconsistent with the running parameter value, the write parameter is stored in the write buffer queue.

8. The data acquisition method for an automatic fat-adding system based on edge computing according to claim 1, characterized in that, In S5, performing the locking action specifically includes: When the global interlock signal is detected to switch from the first state to the second state, it is determined that the state change event is triggered; Set the write buffer queue to a locked state and suspend the task of sending the write parameters to the underlying bus.

9. The data acquisition method for an automatic fat-adding system based on edge computing according to claim 8, characterized in that, Following S5, the following is also included: When the status poll confirms that the status register value of the controlled node is consistent with the current global interlock signal, the write buffer queue is set to an idle state to release the lock. The task of sending the write parameters to the underlying bus is resumed, and the corresponding write parameters are removed from the write buffer queue after the task is completed.

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