A data transmission method and system

Abstract

This invention relates to the field of communication technology and discloses a data transmission method and system, comprising: sending an initialization command sequence to a slave device based on a DDR interface to initialize and calibrate the DDR interface, wherein the initialization command sequence includes multiple initialization commands, and the slave device responds to each initialization command to execute a calibration step; when the master controller's initialization state machine transitions to a ready state, issuing read and write commands to the slave device based on the DDR interface to transmit data with the slave device. The slave device is configured to simulate a DDR chip, enabling the master controller and slave device to adapt to the complex initialization and calibration process of the DDR interface, ensuring the stable operation of the DDR interface, and thereby improving the efficiency of data transmission between the master controller and the slave device.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically to a data transmission method and system. Background Technology

[0002] With the rapid development of artificial intelligence, image processing, and high-performance computing, the demand for high-bandwidth data transmission between Field Programmable Gate Arrays (FPGAs) or between FPGAs and System-on-Chips (SoCs) is increasing. Currently, high-bandwidth data transmission is typically achieved using high-speed serial transceivers integrated within the FPGA or numerous low-voltage differential signal interfaces. However, many SoCs do not integrate high-speed serial transceiver interfaces, making direct high-speed interconnection impossible.

[0003] Double Data Rate (DDR) interfaces, as standard interfaces for SoC chips, feature high data transfer rates and a moderate number of pins, and are typically used to connect external DDR memory chips to expand data storage. However, stable operation of the DDR interface requires a complex initialization calibration process, including impedance calibration, write balancing, and read gating training. These calibration processes necessitate precise bidirectional interaction between the host and the memory. Therefore, establishing a stable and reliable high-bandwidth communication link between the SoC chip and the FPGA is a pressing issue that needs to be addressed. Summary of the Invention

[0004] In view of this, the present invention provides a data transmission method and system to establish a stable and reliable high-bandwidth communication link between a SoC chip and an FPGA.

[0005] In a first aspect, the present invention provides a data transmission method applied to a main controller, wherein the main controller is connected to a slave device via a DDR interface, and the slave device is configured to simulate DDR chips, the method comprising: An initialization command sequence is sent to the slave device based on the DDR interface to perform initialization calibration of the DDR interface; the initialization command sequence includes multiple initialization commands, and the slave device responds to each initialization command to perform each calibration step; When the initialization state machine of the master controller jumps to the ready state, it sends read and write commands to the slave device based on the DDR interface to transmit data with the slave device.

[0006] In one optional implementation, the initialization command includes at least impedance calibration, which includes: A first calibration command is sent to the slave device via the DDR interface. In response to the first calibration command, the slave device reads the resistance value of the reference resistor from the impedance calibration pin, calculates the target resistance value based on the resistance value of the reference resistor, and configures the target resistance value as the terminating resistor of the slave device.

[0007] In one optional implementation, the initialization command includes at least writing a balance calibration, wherein the writing a balance calibration includes: A first data strobe signal is sent to the slave device and the delay of the first data strobe signal relative to the first clock signal is adjusted successively. The slave device samples the first clock signal on the rising edge of the first data strobe signal to obtain a first sampling result. The system receives the first sampling result sent by the slave device and determines the target delay parameter of the first data strobe signal based on the first sampling result.

[0008] In one optional implementation, the initialization command includes at least read gating training, which includes: A read gating training command is sent to the slave device, and the slave device responds to the read gating training command by feeding back a corresponding first data signal; The position of the read data gating is adjusted sequentially, and the first data signal fed back by the slave device is sampled and verified. Based on the sampling and verification results of the first data signal, the first target position of the read data gating is determined, and a valid read data signal is generated.

[0009] In one optional implementation, the initialization command includes at least writing data for training, wherein the writing data for training includes: The position of the second data signal relative to the second data strobe signal is adjusted sequentially, and the adjusted second data signal is sent to the slave device. Based on the first feedback result from the slave device, the second target position of the second data signal relative to the second data strobe signal is determined, so that the second data signal falls at the center position of the edge of the second data strobe signal.

[0010] In one optional implementation, the initialization command includes at least reading data training, wherein the reading data training includes: The position of the third data strobe signal relative to the third data signal is adjusted successively, and a test signal for reading data training is sent to the slave device to trigger feedback; The second feedback result from the device is sampled and verified to determine the third target position of the third data strobe signal relative to the third data signal, so that the third data signal falls at the center position of the edge of the third data strobe signal.

[0011] In a second aspect, the present invention provides a data transmission method applied to a slave device, wherein the slave device is connected to a master controller via a DDR interface, and the slave device is configured to simulate DDR chips, the method comprising: The system receives an initialization command sequence sent by the main controller and executes various calibration steps in response to the initialization command sequence, wherein the initialization command sequence includes multiple initialization commands. When the initialization state machine of the main controller jumps to the ready state, it receives read and write commands sent by the main controller to perform data interaction with the main controller based on the read and write commands.

[0012] In one optional implementation, the initialization command includes at least writing a balance calibration, wherein the writing a balance calibration includes: The system receives a first data strobe signal sent by the main controller, samples the first clock signal on the rising edge of the first data strobe signal, and obtains a first sampling result. The first sampling result is fed back to the main controller through the DDR interface, and the main controller determines the target delay parameter of the first data strobe signal based on the first sampling result.

[0013] In one optional implementation, the initialization command includes at least read gating training, which includes: Receive the read gating training command sent by the main controller, and respond to the read gating training command by feeding back the corresponding first data signal to the main controller; The main controller successively adjusts the position of the read data gating and samples and verifies the first data signal to determine the first target position of the read data gating based on the sampling and verification results of the first data signal, and generates a valid read data signal.

[0014] Thirdly, the present invention provides a data transmission system, comprising: A main controller, which is used to execute the data transmission method of the first aspect or any corresponding embodiment described above; The slave device is connected to the master controller via a DDR interface, the slave device is configured to simulate DDR chips, and the slave device is used to perform the data transmission method of the second aspect above or any corresponding embodiment thereof. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the framework of a data transmission system according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating a data transmission method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the framework of a data transmission system according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This embodiment provides a data transmission system, such as Figure 1 As shown, the system includes at least a master controller and slave devices. The slave devices are connected to the master controller via a DDR interface and are configured to simulate DDR chips. Specifically, the master controller can be a SoC (System-on-a-Chip) as the control core of the entire data transmission system. The master controller sends various commands to the slave devices via the DDR interface to complete system initialization and calibration, and then interacts with the slave devices for data exchange after initialization is complete.

[0019] The slave device can be an FPGA, simulating the hardware behavior and protocol logic of DDR chips. As a passive response end in the system, it cooperates with the main controller to complete all initialization calibrations. By configuring the hardware logic and programming the FPGA slave device, it acquires the core functional characteristics and protocol response logic of DDR memory chips, enabling it to adapt to the DDR interface communication rules of the main controller. This means the slave device does not need to possess the actual storage function of DDR chips; it only needs to simulate the response behavior of DDR chips to various commands sent by the main controller, as well as the hardware interface characteristics of DDR chips (e.g., terminating resistors, signal sampling logic, etc.), allowing the main controller to recognize it as a DDR-compliant memory end, thus achieving bidirectional interaction between the two based on the DDR interface. The slave device receives initialization command sequences, read / write commands, and various signals sent by the main controller through the DDR interface. It responds to the main controller's instructions to execute corresponding calibration coordination operations, including impedance calibration coordination, write balancing calibration coordination, and read gating training coordination. Simultaneously, it feeds back the sampling results and verification results during the calibration process to the main controller, providing a basis for parameter adjustment and target determination, ensuring accurate bidirectional interaction in the initialization calibration process. The design of the device simulating DDR chips enables the master controller and slave device to adapt to the complex initialization calibration process of the DDR interface, including multiple core steps such as impedance calibration, write balance calibration, and read gating training, to ensure that the DDR interface can work stably, thereby improving the data transmission efficiency between the master controller and slave device.

[0020] Furthermore, the transmission of time between the master controller and slave devices is achieved through the DDR interface, eliminating the need for additional high-speed serial transceivers or the occupation of numerous low-voltage differential signal interfaces. This enables high-bandwidth data transmission and is compatible with the hardware interface configurations of most SoC chips.

[0021] According to an embodiment of the present invention, a data transmission method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0022] This embodiment provides a data transmission method that can be used with the aforementioned master controller. The master controller is connected to the slave device via a DDR interface, and the slave device is configured to simulate DDR chips. Figure 2 This is a flowchart of a data transmission method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps: Step S101: Send an initialization command sequence to the slave device based on the DDR interface to perform initialization calibration of the DDR interface.

[0023] The initialization command sequence includes multiple initialization commands, and the slave device responds to each initialization command to execute each calibration step. Initialization commands include impedance calibration, write balance calibration, read gating training, write data training, and read data training.

[0024] After the system is powered on or reset, the clock management module inside the main controller first stabilizes the system clock, and outputs a stable clock signal after the phase-locked loop locks in. When the main controller detects that the power supply is stable, the clock is ready, and the reset signal is released, the internal initialization state machine enters the initialization process from the idle state and begins preparing to send an initialization command sequence to the slave devices. The initialization command sequence is sent serially one by one according to the DDR protocol specification. Each command corresponds to a specific calibration step. Before sending the next command, the main controller must ensure that the current calibration step has been completed or a response has been received from the slave device.

[0025] Step S102: When the master controller's initialization state machine jumps to the ready state, it sends read / write commands to the slave device based on the DDR interface to transmit data with the slave device.

[0026] The initialization state machine of the main controller monitors the execution status of the calibration steps corresponding to each initialization command in real time. When all initialization commands have been sent and the feedback from the device has been received that all calibration steps have been completed, and the controller detects that all parameters of the DDR interface (e.g., impedance, signal delay, gating position, etc.) have reached the preset stable threshold, the initialization state machine jumps from the initialization state to the ready state.

[0027] After the master controller's initialization state machine transitions to the ready state, it generates corresponding read or write commands according to the preset communication protocol and data transmission requirements. The read command instructs the slave device to send data to a specified address to the master controller, while the write command instructs the master controller to write data to a specified address of the slave device. Both read and write commands are strictly encoded in accordance with the DDR protocol specification to ensure that the slave device (simulating DDR chips) can accurately identify them.

[0028] The master controller serially sends encoded read / write commands to the slave device via the command bus of the DDR interface, simultaneously sending corresponding address and control signals. Upon receiving the read / write commands, the slave device, configured to simulate DDR memory, can parse the commands and execute the corresponding operations according to the DDR protocol's response logic. When receiving a write command, it prepares to receive subsequent data sent by the master controller and complete storage. When receiving a read command, it prepares to read the specified data and send it back to the master controller.

[0029] The data transmission method provided in this embodiment includes: sending an initialization command sequence to a slave device based on the DDR interface to perform initialization calibration of the DDR interface, wherein the initialization command sequence includes multiple initialization commands, and the slave device responds to each initialization command to execute each calibration step; when the master controller's initialization state machine jumps to the ready state, it issues read / write commands to the slave device based on the DDR interface to transmit data with the slave device. The slave device is configured to simulate DDR chips, enabling the master controller and slave device to adapt to the complex initialization calibration process of the DDR interface, ensuring the stable operation of the DDR interface, and thereby improving the efficiency of data transmission between the master controller and the slave device.

[0030] In some optional implementations, the initialization command includes at least impedance calibration, which includes: sending a first calibration command to the slave device via the DDR interface; the slave device responding to the first calibration command by reading the resistance value of a reference resistor from the impedance calibration pin; calculating a target resistance value based on the resistance value of the reference resistor; and configuring the target resistance value on the terminating resistor of the slave device.

[0031] When the initialization state machine enters the impedance calibration phase, it sends the first calibration command to the slave device via the DDR interface. The first calibration command follows the DDR protocol format encoding, instructing the slave device to enter impedance calibration mode, and is sent serially via the command bus of the DDR interface. At the same time, the corresponding control signals are sent synchronously to ensure that the slave device can accurately identify the calibration command.

[0032] The slave device, configured as a passive responder to simulate DDR chips, constantly listens for commands on the DDR interface. Upon receiving an impedance calibration command from the master controller, the slave device enters an impedance calibration coordination state in response to the first calibration command, reading the resistance value of the reference resistor via the impedance calibration pin (ZQ pin). The reference resistor is a system-preset standard resistor with a fixed resistance value, used as a benchmark for the slave device's termination resistor calibration to ensure the accuracy of the impedance calibration.

[0033] The slave device calculates the target resistance value based on the resistance value of the reference resistor it reads, using an internally preset calibration algorithm. The calculation logic of the target resistance value conforms to the impedance matching requirements of the DDR interface. The core is to ensure that the terminal resistor value of the slave device is consistent with the output impedance of the DDR interface of the main controller and the transmission line impedance, thereby minimizing interference problems such as reflection and attenuation during signal transmission and ensuring signal transmission quality.

[0034] In some optional implementations, the device internally includes a comparator and an adjustable terminating resistor network. The device sets the initial control code of the adjustable terminating resistor network to an intermediate value, compares the impedance calibration pin voltage with the internal reference voltage using the comparator, and adjusts each bit of the control code successively based on the comparison results. After multiple approximations, the optimal control code is determined to match the terminating resistor value with the external reference resistor value. The resistance value corresponding to the optimal control code is the target resistance value. The optimal control code is latched and applied to the terminating resistor network to complete the impedance matching calibration.

[0035] After determining the target resistance value, the slave device configures the calculated target resistance value onto its own terminating resistor, completing the resistance calibration of the terminating resistor. Upon completion of calibration, the slave device sends an impedance calibration completion signal to the master controller via the DDR interface. Upon receiving this signal, the master controller confirms that the impedance calibration step has been completed and then transitions its initialization state machine to the next calibration stage, preparing to send the next initialization command.

[0036] In some optional implementations, the initialization command includes at least writing a balance calibration, which includes: sending a first data strobe signal to the slave device and successively adjusting the delay of the first data strobe signal relative to the first clock signal, wherein the slave device samples the first clock signal at the rising edge of the first data strobe signal to obtain a first sampling result; receiving the first sampling result sent by the slave device, and determining the target delay parameter of the first data strobe signal based on the first sampling result.

[0037] The write balance calibration technology in this embodiment can be used in the fly-by topology introduced by DDR3 and higher specification DDR interfaces. In this topology, the clock differential signals (CK-CK#, i.e., the first clock signal), command signals, address signals, control signals, etc., of the master controller and slave devices on the printed circuit board are routed in a fly-by manner, while the data mask signal (DM), data signal (DQ), and first data strobe signal (DQS-DQS#) are routed in a point-to-point manner.

[0038] When the initialization state machine inside the master controller enters the write leveling calibration phase, the master controller first sends a write leveling calibration command to the slave device through the address / command bus of the DDR interface, that is, writes a specific configuration to the mode register (for example, sets bit 7 of the DDR3 mode register MR1 to 1) so that the slave device enters the write leveling mode.

[0039] The master controller adjusts the delay of the data strobe signal multiple times, sending a set of data strobe pulses (DQS Pules) to the slave device after each adjustment. The first data strobe signal (DQS) is a bidirectional signal used for synchronous data transmission in the DDR interface, driven by the master controller during write operations. The first clock signal (CK) is the fundamental clock for system synchronization, continuously provided by the master controller. The slave device samples the level of the clock signal on the rising edge of each data strobe pulse, obtaining a first sampling result (e.g., a sample value of 0 or 1), and feeds back the first sampling result to the master controller via the data bus (DQ).

[0040] The master controller receives the first sampling result from the slave device via the data bus and determines whether the first data strobe signal and the first clock signal are aligned based on the first sampling result. Initially, due to the phase difference between the first data strobe signal and the first clock signal, the slave device typically receives a low level (0) when sampling the first clock signal at the rising edge of the first data strobe signal, resulting in a feedback of 0. The master controller gradually increases the delay of the first data strobe signal, repeatedly sending data strobe pulses and receiving feedback until it detects that the sampled value of the first sampling result has jumped from 0 to 1. This jump indicates that the rising edge of the current first data strobe signal is now precisely aligned with the rising edge of the first clock signal, meaning the first data strobe signal and the first clock signal are aligned. At this point, the master controller locks the current delay parameter as the target delay parameter and applies the target delay parameter to all subsequent write operations.

[0041] To ensure calibration accuracy, the master controller can independently perform the above calibration process for each data strobe signal group (each 8 bits of data corresponds to one DQS). After completing the calibration of all groups, the master controller reconfigures the slave device to exit the write-balanced mode via the mode register (e.g., writing bit 7 of MR1 back to 0), thus restoring the slave device to normal operation.

[0042] This step is used to resolve the edge alignment issue between the data strobe differential signal (DQS-DQS#, Data Strobe Signal, differential form, used for synchronous data sampling) and the clock differential signal (CK-CK#, Clock Signal, differential form, used to provide synchronous clock), thereby improving signal integrity.

[0043] In some optional implementations, the initialization command includes at least read gating training, which includes: sending a read gating training instruction to the slave device, the slave device responding to the read gating training instruction by feeding back a corresponding first data signal; successively adjusting the position of the read data gating and sampling and verifying the first data signal fed back by the slave device, determining the first target position of the read data gating based on the sampling and verification results of the first data signal, and generating a valid read data signal.

[0044] When the initialization state machine inside the main controller enters the read gating training phase, the main controller sends a read gating training instruction to the slave device through the address / command bus of the DDR interface. The read gating training instruction uses a standard read command to trigger the slave device to return specific training data.

[0045] The slave device, configured as a passive responder to simulate DDR chips, constantly listens for commands on the DDR interface. When the slave device receives a read-gated training command from the master controller, it reads preset training data from the memory array or a dedicated training data register in response to the read-gated training command, and returns the training data to the master controller via a first data signal.

[0046] After sending a read command, the main controller begins to sequentially adjust the position of the read data gating. The read data gating is a circuit unit within the main controller's physical layer. The main controller scans a series of possible gating positions (e.g., adjusting incrementally over 0 to 7 clock cycles in steps of 10-25 ps) and samples and verifies the training data returned from the device at each gating position. Verification methods include checking whether the sampled data conforms to the expected training pattern, detecting the bit error rate of the data, or evaluating the sampling margin through eye diagram analysis.

[0047] The main controller evaluates the data quality at each gating position based on the sampling verification results of the first data signal. If the gating position is too early, high impedance or noise before the data strobe signal becomes valid may be sampled; if the gating position is too late, a portion of the valid data window may be lost. The main controller determines the optimal gating start time, i.e., the first target position for read data gating, by comparing the sampling correctness and stability at each position. This first target position is configured for the read data gating circuit at the physical layer, and a read data valid signal is generated. The read data valid signal indicates when to open the gating during subsequent normal read operations to capture the read data returned from the device, ensuring that valid data is sampled at the correct time for each read operation.

[0048] During a read operation, when data is returned from the device (simulating DDR chips), a data strobe signal (DQS) is simultaneously activated. The main controller needs to activate the gating circuit within a precise time window to receive this DQS signal, thereby correctly capturing the read data. If the gating position is off, it may result in sampling invalid data or completely missing the read data window. Read gating training scans all possible gating positions through a series of read operations to find the optimal gating activation time, ensuring that the read data can be accurately captured.

[0049] In some optional implementations, the initialization command includes at least writing data training, which includes: successively adjusting the position of the second data signal relative to the second data strobe signal and sending the adjusted second data signal to the slave device; and determining a second target position of the second data signal relative to the second data strobe signal based on the first feedback result from the slave device, so that the second data signal falls at the center position of the edge of the second data strobe signal.

[0050] When the initialization state machine inside the main controller enters the write data training phase, the main controller first sends a write data training command to the slave device through the address / command bus of the DDR interface. The write data training command can be implemented using standard write commands in conjunction with a specific training mode, such as writing a known data pattern to a preset training address, requiring the slave device to receive and store this data.

[0051] The master controller sequentially adjusts the position of the second data signal relative to the second data strobe signal using a delay chain within the physical layer. It changes the transmission time of the second data signal in preset steps (e.g., 10-25 ps), gradually shifting the phase of the second data signal relative to the second data strobe signal. After each adjustment, the master controller sends a set of adjusted second data signals to the slave device.

[0052] The master controller determines the optimal phase position based on the first feedback result from the slave device. The first feedback result can be the bit error rate of the read-back data, the output status of the comparator, or the pass / fail indication provided by the slave device in a specific training mode. By traversing the possible phase offset range and recording the write accuracy at each phase position, the master controller finally determines the phase interval that allows data to be written stably, and selects the center point of this interval as the second target position of the data signal relative to the data strobe signal.

[0053] In some optional implementations, the initialization command includes at least reading data training, which includes: successively adjusting the position of the third data strobe signal relative to the third data signal, and sending a test signal for reading data training to the slave device to trigger feedback; sampling and verifying the second feedback result fed back by the slave device, determining the third target position of the third data strobe signal relative to the third data signal, so that the third data signal falls at the center position of the edge of the third data strobe signal.

[0054] When the initialization state machine inside the main controller enters the read data training phase, the main controller first sends a read data training command to the slave device through the address / command bus of the DDR interface. The read data training command can be implemented using a standard read command combined with a specific training mode, such as initiating a read operation to a preset training address and requesting the slave device to return a known data pattern.

[0055] The main controller begins to sequentially adjust the position of the third data strobe signal relative to the third data signal. Specifically, it changes the sampling timing of the third data strobe signal in preset steps (e.g., 10-25 ps) through a delay chain within the physical layer, gradually shifting its phase relative to the third data signal. It should be noted that this adjustment refers to adjusting the gating timing of the third data strobe signal used for sampling the third data signal within the main controller. That is, the main controller uses the delay chain to phase-shift the received third data strobe signal and samples the third data signal using the edge of the shifted third data strobe signal.

[0056] In response to the test signal for reading training data, the slave device reads preset training data from its internal storage array or dedicated training data register and sends a second feedback result back to the master device. The second feedback result is the read data fed back by the slave device.

[0057] The master device samples and verifies the second feedback result. Under each phase setting, the master controller uses the currently adjusted third data strobe signal to sample the returned second feedback result multiple times. By comparing the sampled results with the expected training data pattern, the sampling accuracy at the current phase position is evaluated. Sampling verification methods may include: checking whether the sampled data matches the expected training pattern, calculating the bit error rate, or statistically calculating the sampling margin through multiple samplings.

[0058] The main controller traverses the possible phase offset range, records the sampling accuracy at each phase position, and finally determines the phase interval that can be stably and correctly sampled. The center point of this interval is selected as the third target position of the data gating signal relative to the data signal.

[0059] This embodiment provides a data transmission method applied to a slave device. The slave device is connected to a master controller via a DDR interface and is configured to simulate DDR chips. The method includes: Step S301: Receive the initialization command sequence sent by the main controller, and execute each calibration step in response to the initialization command sequence.

[0060] The initialization command sequence includes multiple initialization commands. After the system powers on or resets, the clock management module inside the main controller first stabilizes the system clock, and outputs a stable clock signal after the phase-locked loop locks in. When the main controller detects that the power supply is stable, the clock is ready, and the reset signal is released, the internal initialization state machine enters the initialization process from the idle state and begins preparing to send the initialization command sequence to the slave devices. The initialization command sequence is sent serially according to the DDR protocol specification. Each command corresponds to a specific calibration step. Before sending the next command, the main controller must ensure that the current calibration step has been completed or a response has been received from the slave device.

[0061] The device responds to each initialization command and executes the corresponding calibration steps. Initialization commands include impedance calibration, write balance calibration, read gating training, write data training, and read data training.

[0062] Step S302: When the initialization state machine of the main controller jumps to the ready state, it receives the read and write commands sent by the main controller to perform data interaction with the main controller based on the read and write commands.

[0063] The initialization state machine of the main controller monitors the execution status of the calibration steps corresponding to each initialization command in real time. When all initialization commands have been sent and the feedback from the device has been received that all calibration steps have been completed, and the controller detects that all parameters of the DDR interface (e.g., impedance, signal delay, gating position, etc.) have reached the preset stable threshold, the initialization state machine jumps from the initialization state to the ready state.

[0064] After the master controller's initialization state machine transitions to the ready state, it generates corresponding read or write commands according to the preset communication protocol and data transmission requirements. The read command instructs the slave device to send data to a specified address to the master controller, while the write command instructs the master controller to write data to a specified address of the slave device. Both read and write commands are strictly encoded in accordance with the DDR protocol specification to ensure that the slave device (simulating DDR chips) can accurately identify them.

[0065] The master controller serially sends encoded read / write commands to the slave device via the command bus of the DDR interface, simultaneously sending corresponding address and control signals. Upon receiving the read / write commands, the slave device, configured to simulate DDR memory, can parse the commands and execute the corresponding operations according to the DDR protocol's response logic. When receiving a write command, it prepares to receive subsequent data sent by the master controller and complete storage. When receiving a read command, it prepares to read the specified data and send it back to the master controller.

[0066] In some optional implementations, the initialization command includes at least writing a balance calibration, which includes: receiving a first data strobe signal sent by the main controller; sampling a first clock signal on the rising edge of the first data strobe signal to obtain a first sampling result; feeding back the first sampling result to the main controller through the DDR interface; and the main controller determining the target delay parameter of the first data strobe signal based on the first sampling result.

[0067] The write balance calibration technology in this embodiment can be used in the fly-by topology introduced by DDR3 and higher specification DDR interfaces. In this topology, the clock differential signals (CK-CK#, i.e., the first clock signal), command signals, address signals, control signals, etc., of the master controller and slave devices on the printed circuit board are routed in a fly-by manner, while the data mask signal (DM), data signal (DQ), and first data strobe signal (DQS-DQS#) are routed in a point-to-point manner.

[0068] When the initialization state machine inside the master controller enters the write leveling calibration phase, the master controller first sends a write leveling calibration command to the slave device through the address / command bus of the DDR interface, that is, writes a specific configuration to the mode register (for example, sets bit 7 of the DDR3 mode register MR1 to 1) so that the slave device enters the write leveling mode.

[0069] The master controller adjusts the delay of the data strobe signal multiple times, sending a set of data strobe pulses (DQS Pules) to the slave device after each adjustment. The first data strobe signal (DQS) is a bidirectional signal used for synchronous data transmission in the DDR interface, driven by the master controller during write operations. The first clock signal (CK) is the fundamental clock for system synchronization, continuously provided by the master controller. The slave device samples the level of the clock signal on the rising edge of each data strobe pulse, obtaining a first sampling result (e.g., a sample value of 0 or 1), and feeds back the first sampling result to the master controller via the data bus (DQ).

[0070] The master controller receives the first sampling result from the slave device via the data bus and determines whether the first data strobe signal and the first clock signal are aligned based on the first sampling result. Initially, due to the phase difference between the first data strobe signal and the first clock signal, the slave device typically receives a low level (0) when sampling the first clock signal at the rising edge of the first data strobe signal, resulting in a feedback of 0. The master controller gradually increases the delay of the first data strobe signal, repeatedly sending data strobe pulses and receiving feedback until it detects that the sampled value of the first sampling result has jumped from 0 to 1. This jump indicates that the rising edge of the current first data strobe signal is now precisely aligned with the rising edge of the first clock signal, meaning the first data strobe signal and the first clock signal are aligned. At this point, the master controller locks the current delay parameter as the target delay parameter and applies the target delay parameter to all subsequent write operations.

[0071] To ensure calibration accuracy, the master controller can independently perform the above calibration process for each data strobe signal group (each 8 bits of data corresponds to one DQS). After completing the calibration of all groups, the master controller reconfigures the slave device to exit the write-balanced mode via the mode register (e.g., writing bit 7 of MR1 back to 0), thus restoring the slave device to normal operation.

[0072] In some optional implementations, the initialization command includes at least read gating training, which includes: receiving a read gating training instruction sent by the main controller and responding to the read gating training instruction by feeding back a corresponding first data signal to the main controller; the main controller successively adjusts the position of the read data gating and samples and verifies the first data signal to determine the first target position of the read data gating based on the sampling and verification results of the first data signal, and generates a valid read data signal.

[0073] When the initialization state machine inside the main controller enters the read gating training phase, the main controller sends a read gating training instruction to the slave device through the address / command bus of the DDR interface. The read gating training instruction uses a standard read command to trigger the slave device to return specific training data.

[0074] The slave device, configured as a passive responder to simulate DDR chips, constantly listens for commands on the DDR interface. When the slave device receives a read-gated training command from the master controller, it reads preset training data from the memory array or a dedicated training data register in response to the read-gated training command, and returns the training data to the master controller via a first data signal.

[0075] After sending a read command, the main controller begins to sequentially adjust the position of the read data gating. The read data gating is a circuit unit within the main controller's physical layer. The main controller scans a series of possible gating positions (e.g., adjusting incrementally over 0 to 7 clock cycles in steps of 10-25 ps) and samples and verifies the training data returned from the device at each gating position. Verification methods include checking whether the sampled data conforms to the expected training pattern, detecting the bit error rate of the data, or evaluating the sampling margin through eye diagram analysis.

[0076] The main controller evaluates the data quality at each gating position based on the sampling verification results of the first data signal. If the gating position is too early, high impedance or noise before the data strobe signal becomes valid may be sampled; if the gating position is too late, a portion of the valid data window may be lost. The main controller determines the optimal gating start time, i.e., the first target position for read data gating, by comparing the sampling correctness and stability at each position. This first target position is configured for the read data gating circuit at the physical layer, and a read data valid signal is generated. The read data valid signal indicates when to open the gating during subsequent normal read operations to capture the read data returned from the device, ensuring that valid data is sampled at the correct time for each read operation.

[0077] During a read operation, when data is returned from the device (simulating DDR chips), a data strobe signal (DQS) is simultaneously activated. The main controller needs to activate the gating circuit within a precise time window to receive this DQS signal, thereby correctly capturing the read data. If the gating position is off, it may result in sampling invalid data or completely missing the read data window. Read gating training scans all possible gating positions through a series of read operations to find the optimal gating activation time, ensuring that the read data can be accurately captured.

[0078] This embodiment provides a data transmission system, such as Figure 3 As shown, the system includes at least a master controller and a slave device. The slave device is connected to the master controller via a DDR interface and is configured to simulate DDR chips.

[0079] Specifically, the main controller can be a system-on-chip (SoC) as the control core of the entire data transmission system. The main controller internally includes a system clock and reset module to provide the system operating clock and global reset signal. The DDR controller is the core logic unit of the main controller, responsible for generating commands, addresses, and data conforming to the DDR protocol and managing the initialization calibration process. The DDR controller interacts with the DDR physical layer (DDRPHY) through a DFI (DDR Physical Layer Interface) conversion module. DFI is the standard communication interface between the memory controller and the physical layer, and the DFI conversion module converts the internal signals of the DDR controller into signals conforming to the DFI protocol.

[0080] The DDR PHY Control Module is responsible for timing control and signal driving. Internally, it includes an initialization training state machine to perform initialization calibration processes such as impedance calibration, write balance calibration, read gating training, write data training, and read data training. The PHY Control Module also includes a clock generation circuit to generate the clock signal required by the DDR interface and output a clock lock signal indicating clock stability. A 2-to-1 selector switches between normal read / write data and initialization training data. The main controller also has a user interface for data interaction with upper-layer applications or the processor core. The APB (Advanced Peripheral Bus) interface is an optional control interface used to configure the DDR controller's registers.

[0081] The slave device can employ a Field Programmable Gate Array (FPGA). Through hardware logic configuration and programming, it simulates the hardware behavior and protocol logic of DDR chips, acting as a passive response end in the system and cooperating with the main controller to complete all initialization calibrations. The slave device internally contains a DDR command control module, which is the command parsing module mentioned earlier. This module parses commands sent by the main controller through the DDR interface, including impedance calibration commands, write balance calibration commands, read gating training commands, and read / write commands. The DDR command control module is further subdivided into a read control unit and a write control unit, which handle the data streams of read and write operations respectively.

[0082] The slave device also includes a DDR initialization control module, which is the first state machine on the slave side mentioned above. This module responds to the initialization calibration process initiated by the master controller and assists in executing each calibration step. Specifically, during write balance calibration, the DDR initialization control module controls the slave device to sample the clock signal (CK) on the rising edge of the data strobe signal (DQS) and feeds the sampled value back to the master controller via the data bus (DQ). During impedance calibration, the DDR initialization control module uses an external reference resistor connected to the impedance calibration pin and completes the calibration of the terminating resistor through an internal comparator and successive approximation logic.

[0083] The device also includes an internal storage module, namely the data storage module mentioned earlier, which can be implemented using a dual-port RAM (DRAM) to cache data being written or to be read. The storage module is connected to both the read control unit and the write control unit to enable data storage and retrieval.

[0084] After the system powers on or resets, the DDR physical layer control module of the master controller first stabilizes the clock, and outputs a clock lock signal after the phase-locked loop locks the clock. Then, the initialization training state machine starts, sequentially sending impedance calibration commands, write balance calibration commands, read gating training commands, write data training commands, and read data training commands to the slave device via the DDR interface. The slave device's DDR initialization control module responds to each command, simulating the behavior of the DDR chips to complete the calibration. When all calibration steps are successfully completed, the master controller's initialization training state machine jumps to the ready state and generates an initialization completion flag. At this point, the DDR physical link between the master controller and the slave device is established, and normal data read and write operations can be performed.

[0085] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in an optional embodiment of the present invention, such as... Figure 4 As shown, the electronic device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 4 Take a processor 10 as an example.

[0086] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0087] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0088] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0089] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0090] The electronic device also includes a communication interface 30 for communicating with other devices or communication networks.

[0091] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0092] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the invention.

Claims

1. A data transmission method, characterized in that, Applied to a master controller, the master controller being connected to a slave device via a DDR interface, the slave device being configured to simulate DDR chips, the method includes: An initialization command sequence is sent to the slave device based on the DDR interface to perform initialization calibration of the DDR interface; the initialization command sequence includes multiple initialization commands, and the slave device responds to each initialization command to perform each calibration step; When the initialization state machine of the master controller jumps to the ready state, it sends read and write commands to the slave device based on the DDR interface to transmit data with the slave device.

2. The method according to claim 1, characterized in that, The initialization command includes at least impedance calibration, which includes: A first calibration command is sent to the slave device via the DDR interface. In response to the first calibration command, the slave device reads the resistance value of the reference resistor from the impedance calibration pin, calculates the target resistance value based on the resistance value of the reference resistor, and configures the target resistance value as the terminating resistor of the slave device.

3. The method according to claim 1, characterized in that, The initialization command includes at least a write balance calibration, wherein the write balance calibration includes: A first data strobe signal is sent to the slave device and the delay of the first data strobe signal relative to the first clock signal is adjusted successively. The slave device samples the first clock signal on the rising edge of the first data strobe signal to obtain a first sampling result. The system receives the first sampling result sent by the slave device and determines the target delay parameter of the first data strobe signal based on the first sampling result.

4. The method according to claim 1, characterized in that, The initialization command includes at least read gating training, which includes: A read gating training command is sent to the slave device, and the slave device responds to the read gating training command by feeding back a corresponding first data signal; The position of the read data gating is adjusted sequentially, and the first data signal fed back by the slave device is sampled and verified. Based on the sampling and verification results of the first data signal, the first target position of the read data gating is determined, and a valid read data signal is generated.

5. The method according to claim 1, characterized in that, The initialization command includes at least writing data for training, and the writing data for training includes: The position of the second data signal relative to the second data strobe signal is adjusted sequentially, and the adjusted second data signal is sent to the slave device. Based on the first feedback result from the slave device, the second target position of the second data signal relative to the second data strobe signal is determined, so that the second data signal falls at the center position of the edge of the second data strobe signal.

6. The method according to claim 1, characterized in that, The initialization command includes at least reading data training, and the reading data training includes: The position of the third data strobe signal relative to the third data signal is adjusted successively, and a test signal for reading data training is sent to the slave device to trigger feedback; The second feedback result from the device is sampled and verified to determine the third target position of the third data strobe signal relative to the third data signal, so that the third data signal falls at the center position of the edge of the third data strobe signal.

7. A data transmission method, characterized in that, Applied to a slave device connected to a master controller via a DDR interface, the slave device is configured to simulate DDR chips, the method includes: The system receives an initialization command sequence sent by the main controller and executes various calibration steps in response to the initialization command sequence, wherein the initialization command sequence includes multiple initialization commands. When the initialization state machine of the main controller jumps to the ready state, it receives read and write commands sent by the main controller to perform data interaction with the main controller based on the read and write commands.

8. The method according to claim 7, characterized in that, The initialization command includes at least a write balance calibration, wherein the write balance calibration includes: The system receives a first data strobe signal sent by the main controller, samples the first clock signal on the rising edge of the first data strobe signal, and obtains a first sampling result. The first sampling result is fed back to the main controller through the DDR interface, and the main controller determines the target delay parameter of the first data strobe signal based on the first sampling result.

9. The method according to claim 7, characterized in that, The initialization command includes at least read gating training, which includes: Receive the read gating training command sent by the main controller, and respond to the read gating training command by feeding back the corresponding first data signal to the main controller; The main controller successively adjusts the position of the read data gating and samples and verifies the first data signal to determine the first target position of the read data gating based on the sampling and verification results of the first data signal, and generates a valid read data signal.

10. A data transmission system, characterized in that, include: A main controller, wherein the main controller is configured to perform the method according to any one of claims 1 to 6; The slave device is connected to the master controller via a DDR interface, the slave device is configured to simulate DDR chips, and the slave device is used to perform the method according to any one of claims 7 to 9.

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