A method, apparatus, electronic device, storage medium, and program product for probabilistic prediction of RTL cycle power consumption for microcontrollers.

Abstract

This invention discloses a method, apparatus, electronic device, storage medium, and program product for probabilistic prediction of RTL cycle power consumption for microcontrollers. The method includes: dividing the signal sequence output from RTL simulation into samples according to clock cycle indices, and obtaining power consumption labels aligned with each index; generating binary indicators of logic state changes in adjacent cycles based on the logic states of the same multi-channel RTL signals sampled in adjacent clock cycles; concatenating and trimming the logic states and binary indicators of the multi-channel RTL signals in each clock cycle according to a predetermined order; generating a first set of predicted cycle power consumption values ​​and cycle power consumption fluctuation amplitudes corresponding to intermediate random representations based on the standardized effective feature vectors in each clock cycle; and predicting the cycle power consumption and cycle power consumption fluctuation amplitude for each clock cycle based on the standardized effective feature vectors and intermediate random representations in each clock cycle. This invention avoids output instability introduced by random sampling.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit power consumption modeling and electronic design automation technology, and in particular to a method, apparatus, electronic device, storage medium and program product for probabilistic prediction of RTL cycle power consumption for microcontrollers. Background Technology

[0002] As integrated circuits become increasingly complex in function and scale, power consumption has become a key constraint in their architectural design. Especially in high-performance computing and data-intensive tasks, power consumption not only directly affects the energy efficiency of integrated circuits but also relates to system heat dissipation, stability, and the sustainability of applications. Therefore, accurately quantifying processor power consumption is crucial in the early stages of integrated circuit design, particularly at the high-level abstraction stage.

[0003] Integrated circuit-based RTL (Register Transfer Level) cycle power prediction takes the signal activity output from RTL simulation as input and cycle power consumption labeling as output. Cycle power consumption labeling is typically obtained through power consumption simulation or measurement. Existing cycle power consumption models often use deterministic regression to output a single power consumption value and employ a fixed error scale for parameter estimation in the loss function. For scenarios where power consumption fluctuations vary with the cycle's operating state, a fixed error scale leads to inconsistent error handling in the training loss for high-fluctuation and low-fluctuation periods, thus affecting the stability of cycle power consumption assessment. Summary of the Invention

[0004] The purpose of this invention is to provide a method, apparatus, electronic device, storage medium, and program product for probabilistic prediction of RTL cycle power consumption for microcontrollers, to solve the technical problem that existing cycle power consumption models use a fixed error scale during parameter estimation, making it difficult to use the same computational link for consistent error processing between high-fluctuation cycles and low-fluctuation cycles. The various technical effects of the preferred solutions among the many technical solutions provided by this invention are detailed below.

[0005] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a probabilistic prediction method for RTL cycle power consumption in microcontrollers, comprising: Using clock cycles as the sampling unit, the signal sequence output by the RTL simulation is divided into samples according to the index corresponding to the clock cycle, and the power consumption label aligned with each index is obtained. Based on the logic state of the same multi-channel RTL signal sampled in adjacent clock cycles, a binary indicator of the logic state change in adjacent cycles is generated. The logic state of the multiple RTL signals in each clock cycle is concatenated with the binary indicator in a predetermined order to obtain a periodic feature vector, and the periodic feature vector is trimmed to obtain an effective feature vector. Based on the standardized effective feature vector within each clock cycle, generate the first set of cycle power consumption prediction values ​​and cycle power consumption fluctuation amplitude corresponding to the intermediate random representation; Based on the standardized effective feature vector within each clock cycle, and the intermediate random representation obtained by inferring the first set of cycle power consumption predictions and cycle power consumption fluctuation amplitude, the cycle power consumption and cycle power consumption fluctuation amplitude of each clock cycle are predicted.

[0006] In some embodiments, the signals output by the RTL simulation include at least one of register output signals, combinational logic node signals, and bus signals.

[0007] In some embodiments, the power consumption aligned to each index is the average power consumption over the time interval corresponding to each index.

[0008] In some embodiments, cropping the periodic feature vector includes: A fixed number of reserved signal bits at the end of the periodic feature vector are clipped.

[0009] In some embodiments, the intermediate stochastic representation obtained by inferring the first set of generated periodic power consumption predictions and the periodic power consumption fluctuation amplitude includes: During the inference phase, the value of the intermediate random representation is determined based on the predicted periodic power consumption.

[0010] According to another aspect of the present invention, an RTL cycle power consumption probability prediction device for microcontrollers is also provided, comprising: The period-aligned power consumption labeling module uses the clock cycle as the sampling unit, divides the signal sequence output by the RTL simulation into samples according to the index corresponding to the clock cycle, and obtains the power consumption label aligned with each index. The periodic feature construction module generates a binary indicator of the logic state change between adjacent clock cycles based on the logic state of the same multi-channel RTL signal sampled in adjacent clock cycles; it concatenates the logic state and the binary indicator in each clock cycle in a predetermined order to obtain a periodic feature vector, and then trims the periodic feature vector to obtain an effective feature vector. The power consumption standardization module standardizes the effective feature vector and the power consumption label for each clock cycle; The power consumption probability parameter estimation module receives the standardized features and standardized power consumption labels from the power consumption standardization module, and constructs a probability prediction model including a first probability parameter sub-network, a second probability parameter sub-network, and a power consumption probability decoding sub-network. The first probability parameter sub-network generates a second set of periodic power consumption prediction values ​​and periodic power consumption fluctuation amplitudes corresponding to the intermediate random representation based on the standardized effective feature vector and power consumption label of each clock cycle. The second probability parameter sub-network generates the first set of predicted periodic power consumption values ​​and periodic power consumption fluctuation amplitudes corresponding to the intermediate random representation based on the effective feature vector standardized for each clock cycle. The power consumption probability decoding subnetwork predicts the periodic power consumption and periodic power consumption fluctuation amplitude for each clock cycle based on the standardized effective feature vector within each clock cycle and the intermediate random representation obtained by inferring the first set of periodic power consumption prediction values ​​and periodic power consumption fluctuation amplitude. The power consumption prediction output module receives the effective feature vector to be predicted from the periodic feature construction module, the standardized statistics from the power consumption standardization module, and the trained model parameters from the power consumption probability parameter estimation module, and outputs the periodic power consumption prediction value and the numerical value used for subsequent power consumption assessment, periodic screening, or risk judgment.

[0011] In some embodiments, it also includes: A regularization loss term is calculated based on the difference between the intermediate random representation parameters output by the first probability parameter subnetwork and the intermediate random representation parameters output by the second probability parameter subnetwork; a reconstruction loss term is calculated based on a set of first and second statistical parameters output by the power consumption probability decoding subnetwork, and the reconstruction loss term is numerically modulated by the second statistical parameters output by the power consumption probability decoding subnetwork; the loss is trained based on the modulated reconstruction loss term and the generated regularization loss term, and the first probability parameter subnetwork, the second probability parameter subnetwork, and the power consumption probability decoding subnetwork are trained based on the trained loss.

[0012] According to another aspect of the invention, an electronic device is also provided, comprising: at least one processor; at least one memory for storing processor-executable instructions; wherein the at least one processor implements a microcontroller-oriented RTL cycle power consumption probability prediction method as described above by executing the executable instructions.

[0013] According to another aspect of the invention, a computer-readable storage medium is also provided, having stored thereon computer instructions that, when executed by at least one processor, implement the RTL cycle power consumption probability prediction method for a microcontroller as described above.

[0014] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program or instructions that, when executed by a processor, implement the RTL cycle power consumption probability prediction method for microcontrollers as described above.

[0015] Implementing one of the above-described technical solutions of the present invention has the following advantages or beneficial effects: This invention constructs a feature vector from the RTL signal activity of each cycle along the "signal-computation-output" chain, and generates a set of cycle power consumption prediction values ​​and cycle power consumption fluctuation amplitudes for each cycle. When different RTL cycle states correspond to different power consumption fluctuation amplitudes, the cycle power consumption fluctuation amplitude is used as a numerical output for subsequent power consumption assessment, cycle selection, or risk judgment. During the inference phase, without actual power consumption annotations, a determined value based on intermediate random representations is used to output a determined cycle power consumption prediction value, thereby avoiding output instability introduced by random sampling. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a flowchart of an RTL cycle power consumption probability prediction method for microcontrollers according to an embodiment of the present invention; Figure 2 This is a comparison chart of the prediction results of an RTL cycle power consumption probability prediction method for microcontrollers according to an embodiment of the present invention. Figure 3 This is a structural block diagram of a device according to an embodiment of the present invention; Figure 4 This is a schematic diagram of an electronic device structure according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be used to implement the present invention. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of the present invention disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of the present invention.

[0018] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0019] To illustrate the technical solution described in this invention, specific embodiments are described below, showing only the parts related to the embodiments of this invention.

[0020] Example 1: In this example, the test object is designed as a 32-bit Reduced Instruction Set Computer-V (RISC-V) microcontroller based on the open-source PicoRV32 core. The microcontroller includes an instruction fetch unit, register file, arithmetic logic unit, on-chip static random access memory (SRAM) controller, universal asynchronous receiver / transmitter (UART) interface, and general purpose input / output (GPIO) interface, with an operating clock frequency of 50 MHz.

[0021] like Figure 1 As shown in this embodiment, a probabilistic prediction method for RTL cycle power consumption of microcontrollers is provided. This method includes: S100. Using clock cycles as the sampling unit, the signal sequence output by the RTL simulation is divided into samples according to the index corresponding to the clock cycle, and the power consumption label aligned with each index is obtained.

[0022] In a specific embodiment, the sampling unit is the clock cycle, and the clock cycle is set to be... Clock cycle index Corresponding time interval Power consumption label Defined as the average power consumption within that time interval.

[0023] To put it simply, RTL signal activity and power consumption are mapped to the same period index, thus forming a stable input / output interface.

[0024] Specifically, the Verilator register transfer level simulator was used to simulate the above-mentioned PicoRV32 microcontroller register transfer level (RTL) description. Six types of programs were used as test loads: CoreMark benchmark program, Dhrystone benchmark program, 128-bit Advanced Encryption Standard-128 (AES-128) program, Finite Impulse Response (FIR) filtering program, matrix multiplication program, and UART loopback program. A value change dump (VCD) file was exported.

[0025] Furthermore, the gate-level netlist was obtained by synthesizing the RTL using Yosys synthesis tools. Under the conditions of Nangate 45nm standard cell technology library, 1.1V supply voltage and 25 degrees Celsius, the power consumption of each clock cycle was calculated by Synopsys PrimeTime PX power analysis tool in combination with Switching Activity Interchange Format (SAIF).

[0026] S200: Generate a binary indicator of the logic state change in adjacent cycles based on the logic state of the same multi-channel RTL signal sampled in adjacent clock cycles.

[0027] In some implementations, the RTL signals involved in modeling include at least one or more of the following: register output signals, combinational logic node signals, and bus signals.

[0028] The above signals are derived from waveforms or periodic sampling results exported from RTL simulation.

[0029] Based on the above embodiments, the register output signal reflects the state machine or pipeline state, the combinational logic node signal reflects the combinational activity, and the bus signal reflects the data path activity.

[0030] Furthermore, indexing for each clock cycle The logic value of each signal is sampled at the rising (or falling) edge of the clock to form a logic state vector. Define a binary indicator for the change of logic state between adjacent cycles. ,in Used to indicate signals In adjacent cycles and Does a logical change occur between them? When a change occurs... When no change and stipulate hour It is a vector consisting entirely of zeros.

[0031] For ease of understanding, the binary indicator (i.e., the toggle indicator) directly represents the switching activity of adjacent cycles.

[0032] S300: The logic state and binary indication of multiple RTL signals in each clock cycle are concatenated in a predetermined order to obtain a periodic feature vector, and the periodic feature vector is trimmed to obtain an effective feature vector.

[0033] In a specific embodiment, and By concatenating the signals in a fixed order from smallest to largest, a periodic feature vector is obtained. .right A fixed number of reserved signal bits at the end are used to perform pruning to obtain effective feature vectors. The number of consecutive reserved signal bits can be 16.

[0034] To make it easier to understand, the signal bits corresponding to reserved fields that are not involved in storage array control or power consumption modeling are removed to prevent reserved fields from entering the modeling interface.

[0035] S400: Based on the standardized effective feature vector within each clock cycle, generate the first set of predicted periodic power consumption values ​​and periodic power consumption fluctuation amplitudes corresponding to the intermediate random representation.

[0036] In a specific embodiment, the dimension-wise mean of the effective feature vectors can be calculated on the training set. with dimensional standard deviation and the average value of power consumption. with standard deviation Standardize each sample based on its mean and standard deviation to obtain a standardized effective feature vector. With standardized power consumption labels And perform destandardization during the inference phase to obtain .

[0037] To make it easier to understand, scaling the feature and power consumption labels of different dimensions stabilizes the model parameter estimation process.

[0038] In this step, a probabilistic parameter network can be used to generate the first set of predicted periodic power consumption values ​​and the periodic power consumption fluctuation amplitude.

[0039] In some embodiments, the probabilistic parameter network described above can adopt a conditional variational autoencoder network structure. The first probabilistic parameter subnetwork is used to output the posterior distribution parameters obtained by combining the standardized effective feature vector and the power consumption label; the second probabilistic parameter subnetwork is used to output the prior distribution parameters obtained solely based on the standardized effective feature vector; and the power consumption probability decoding subnetwork is used to output the statistical parameters of the conditional probability of periodic power consumption based on the standardized effective feature vector and intermediate random representations.

[0040] In this embodiment, the probabilistic parameter network specifically adopts a Conditional Variational Auto-Encoder (CVAE) model. The first probabilistic parameter sub-network corresponds to the posterior encoding network q_phi(r_t|x'_t,y'_t), the second probabilistic parameter sub-network corresponds to the prior encoding network p_theta(r_t|x'_t), and the power consumption probabilistic decoding sub-network corresponds to the heteroscedastic Gaussian decoding network p_psi(y'_t|x'_t,r_t). In this embodiment, x'_t is the standardized effective feature vector. y'_t is the standardized power consumption specification. r_t represents intermediate randomness. r_t|x'_t represents r_t under x'_t, and so on.

[0041] Specifically, the intermediate random representation r_t is set as a 16-dimensional Gaussian latent variable. The posterior coding network, the prior coding network, and the power probability decoding network all adopt a three-layer fully connected structure with hidden layer dimensions of 256, 128, and 64, respectively. The activation function is the rectified linear unit (ReLU) function.

[0042] Furthermore, each sub-network can be constructed using a multi-layer fully connected network. Adjacent hidden layers are mapped using linear transformations and nonlinear activation functions. The output layers output the predicted periodic power consumption and the statistical parameters corresponding to the periodic power consumption fluctuation amplitude, respectively.

[0043] S500: Based on the standardized effective feature vector within each clock cycle, and the intermediate random representation obtained by reasoning from the first set of predicted cycle power consumption values ​​(first statistical parameter) and cycle power consumption fluctuation amplitude (second statistical parameter), predict the cycle power consumption and cycle power consumption fluctuation amplitude for each clock cycle.

[0044] In some embodiments, intermediate random representations can represent implicit states that are not directly and explicitly observed in the current clock cycle but affect the cycle power consumption. These are used to comprehensively characterize the switching activity intensity, data path occupancy status, and control path operating mode of the cycle.

[0045] In this embodiment, the aforementioned 16-dimensional intermediate random characterization is used to characterize the pipeline occupancy, bus toggle intensity, memory access activity, and control path switching status of the PicoRV32 microcontroller in the current cycle.

[0046] For example, during periods of high bus switching density and frequent combinational logic switching, intermediate random representations can correspond to higher activity levels; during periods of stable registers and idle critical data paths, intermediate random representations can correspond to lower activity levels.

[0047] In some embodiments, the intermediate stochastic characterization is derived by inferring from the generated first set of predicted periodic power consumption values ​​and the periodic power consumption fluctuation amplitude, including: During the inference phase, the values ​​of intermediate random representations are determined based on the predicted periodic power consumption.

[0048] During the training phase, the first probability parameter subnetwork is used as the posterior encoding network to output the posterior mean mu_q,t and the posterior standard deviation sigma_q,t, and the intermediate random representation is determined according to r_t = mu_q,t + sigma_q,t ⊙ epsilon_t, where epsilon_t follows a standard normal distribution N(0,I).

[0049] During the inference phase, the second probability parameter sub-network is used as the prior encoding network to output the prior mean mu_p,t and the prior standard deviation sigma_p,t. The prior mean mu_p,t (the predicted value of periodic power consumption) is directly taken as the determined value of the intermediate random representation, i.e., r_t = mu_q,t, so as to obtain a stable deterministic prediction output.

[0050] In this step, a power consumption probability decoding network can be used to predict the periodic power consumption and the periodic power consumption fluctuation amplitude for each clock cycle.

[0051] In some embodiments, the power consumption probability decoding network receives the concatenation result of the standardized effective feature vector and the intermediate random representation, and outputs the predicted mean y_hat_t and the fluctuation amplitude sigma_t corresponding to the power consumption conditional probability; wherein the predicted mean y_hat_t represents the predicted power consumption value of the period, and the fluctuation amplitude sigma_t represents the power consumption standard deviation of the corresponding period.

[0052] Furthermore, in this embodiment, the fluctuation amplitude sigma_t is constrained to a positive value by the softplus function to avoid invalid negative fluctuation amplitude output.

[0053] To make it easier to understand, this step obtains a deterministic prediction output without a true power consumption label, thus avoiding output instability introduced by random sampling.

[0054] like Figure 2As shown, this figure compares the performance of regression predictions with actual data. The actual data in the figure comes from the periodic power consumption annotations generated by a 32-bit Reduced Instruction Set Computer-V (RISC-V) microcontroller based on the PicoRV32 core under six types of program stimuli: CoreMark benchmark, Dhrystone benchmark, 128-bit Advanced Encryption Standard-128 (AES-128) program, Finite Impulse Response (FIR) filtering program, matrix multiplication program, and UART loopback program. The power consumption annotations were calculated cycle-by-cycle using the Synopsys PrimeTime PX power analysis tool under a 1.1V supply voltage and 25°C operating conditions, combining the gate-level netlist synthesized by Yosys with the Nangate 45nm standard cell technology library and the Switching Activity Interchange Format (SAIF). Figure 2 The test set shows 3600 consecutive periods. As can be seen from the figure, the method in this embodiment can approximate the trend of real data changes well and has high prediction accuracy.

[0055] In summary, in the PicoRV32 microcontroller embodiment, this invention introduces a 16-dimensional intermediate random representation and a heteroscedastic Gaussian decoding network, enabling the residual scale of different RTL cycles to be adaptively modeled in a unified model, and outputting stable cycle power consumption prediction values ​​and cycle power consumption fluctuation amplitudes during the inference stage.

[0056] Example 2: Figure 3 As shown, this embodiment also provides an RTL cycle power consumption probability prediction device for microcontrollers, used to implement the RTL cycle power consumption probability prediction method for microcontrollers described in Embodiment 1. The device in this embodiment includes: The period-aligned power consumption labeling module uses clock cycles as the sampling unit, dividing the signal sequence output from the RTL simulation into samples according to the index corresponding to the clock cycle, and obtaining a power consumption label aligned with each index. This module receives the signal sequence output from the RTL simulation and outputs a periodic signal sequence divided by clock cycle indices, along with a power consumption label sequence corresponding one-to-one with each clock cycle index.

[0057] The periodic feature construction module generates binary indicators of logic state changes between adjacent clock cycles based on the logic states of the same multi-channel RTL signals sampled in adjacent clock cycles. It then concatenates the logic states and binary indicators within each clock cycle in a predetermined order to obtain a periodic feature vector, and trims this vector to obtain an effective feature vector. This module receives a periodic signal sequence from the periodic aligned power consumption labeling module and outputs the effective feature vector corresponding to each clock cycle.

[0058] The power standardization module standardizes the effective feature vector and power label for each clock cycle. This module receives the effective feature vector from the cycle feature construction module and the power label sequence from the cycle-aligned power label module, calculates the statistics of the training samples, performs standardization on the effective feature vector and power label, and outputs the standardized features, standardized power label, and standardized statistics for inference.

[0059] The power consumption probability parameter estimation module receives standardized features and standardized power consumption labels from the power consumption standardization module, and constructs a probabilistic prediction model including a first probability parameter subnetwork, a second probability parameter subnetwork, and a power consumption probability decoding subnetwork. This module outputs the trained model parameters, which also serve as input to the power consumption prediction output module.

[0060] In some embodiments, the first probabilistic parameter subnetwork generates a second set of predicted periodic power consumption values ​​and periodic power consumption fluctuation amplitudes corresponding to intermediate random representations, based on the standardized effective feature vector and power consumption label for each clock cycle. Specifically, the input to the first probabilistic parameter subnetwork is... The output is the first statistical parameter (predicted periodic power consumption value) and the second statistical parameter (periodic power consumption fluctuation amplitude) corresponding to the first set of parameters used to generate the intermediate random representation. For standardized effective feature vectors, For standardized power consumption specifications, please refer to Example 1.

[0061] The second probabilistic parameter subnetwork generates the first set of predicted periodic power consumption values ​​and periodic power consumption fluctuation amplitudes corresponding to the intermediate random representations, based on the standardized effective feature vectors for each clock cycle. Specifically, the second probabilistic parameter subnetwork: input is... The output is the first statistical parameter (predicted periodic power consumption value) and the second statistical parameter (periodic power consumption fluctuation amplitude) corresponding to the first set of parameters used to generate the intermediate random representation.

[0062] The power consumption probabilistic decoding subnetwork predicts the periodic power consumption and periodic power consumption fluctuation amplitude for each clock cycle based on the standardized effective feature vector within each clock cycle and the intermediate random representation obtained through inference from the first set of periodic power consumption predictions and periodic power consumption fluctuation amplitude. Specifically, the input to the power consumption probabilistic decoding subnetwork is... ,in It represents the intermediate randomness (see Example 1); it outputs a set of first and second statistical parameters of the power consumption conditional probability, and constrains the numerical range of the second statistical parameter to avoid invalid output.

[0063] To make it easier to understand, the probability prediction model built by the power consumption probability parameter estimation module explicitly outputs the engineering phenomenon of "different power consumption residual variances under the same characteristic conditions" in the form of power consumption variance parameters, thereby providing a residual scale at the model output.

[0064] The power consumption prediction output module receives the effective feature vector to be predicted from the periodic feature construction module, the standardized statistics from the power consumption standardization module, and the trained model parameters from the power consumption probability parameter estimation module. It outputs the periodic power consumption prediction value and the numerical value used for subsequent power consumption assessment, periodic screening, or risk judgment.

[0065] In some embodiments, it also includes: The regularization loss term is calculated based on the difference between the intermediate random representation parameters output by the first probability parameter subnetwork and the intermediate random representation parameters output by the second probability parameter subnetwork. The reconstruction loss term is calculated based on a set of first and second statistical parameters output by the power consumption probability decoding subnetwork, and the reconstruction loss term is numerically modulated using the second statistical parameters output by the power consumption probability decoding subnetwork. The loss is trained based on the modulated reconstruction loss term and the generated regularization loss term, and the first probability parameter subnetwork, the second probability parameter subnetwork, and the power consumption probability decoding subnetwork are trained using the trained loss.

[0066] In some embodiments, the training dataset consists of 128,000 Register Transfer Level (RTL) cycle samples collected by the six types of programs described in Embodiment 1 under different input data and different working segments, wherein the training set consists of 102,400 cycle samples, the validation set consists of 12,800 cycle samples, and the test set consists of 12,800 cycle samples.

[0067] Furthermore, the model is jointly trained using an Adaptive Moment Estimation (Adam) optimizer with a batch size of 256, an initial learning rate of 0.001, and 120 training epochs. The first probability parameter subnetwork, the second probability parameter subnetwork, and the power consumption probability decoding subnetwork are updated synchronously through backpropagation.

[0068] The aforementioned reconstruction loss term is calculated using a set of first and second statistical parameters based on the power consumption conditional probability, and the error term is numerically modulated by the second statistical parameter. In some embodiments, the first statistical parameter can be represented as the predicted mean of periodic power consumption, the second statistical parameter can be represented as the standard deviation of periodic power consumption, and the error term can be obtained by the square of the difference between the actual power consumption and the predicted mean.

[0069] For example, the reconfiguration loss after modulation can be calculated as L_rec,t = ((y'_t - y_hat_t)^2) / (sigma_t^2 + epsilon) +log(sigma_t^2 + epsilon), where y'_t represents the normalized power consumption label, y_hat_t represents the predicted mean, sigma_t represents the second statistical parameter based on the power consumption conditional probability, and epsilon is 1e-6.

[0070] The above regularization loss term is calculated based on the difference between the intermediate random representation parameters output by the first probability parameter subnetwork and the intermediate random representation parameters output by the second probability parameter subnetwork, so that the parameters of the intermediate random representation remain under control.

[0071] In some embodiments, the intermediate random representation parameters output by the first probability parameter subnetwork can be denoted as (mu1_t, sigma1_t), and the intermediate random representation parameters output by the second probability parameter subnetwork can be denoted as (mu2_t, sigma2_t). A regularized loss term can be constructed based on the difference between the distributions corresponding to the two sets of parameters.

[0072] For example, the regularization loss term can be calculated using the Kullback-Leibler divergence (KL divergence) between two Gaussian distributions to ensure that the posterior distribution during the training phase is consistent with the prior distribution during the inference phase. In this embodiment, the overall training loss is constructed according to L = Σ_t L_rec,t + 0.01×Σ_t L_kl,t.

[0073] For ease of understanding, the two losses mentioned above together form a parameter estimation closed loop: the power consumption variance parameter not only participates in the scaling calculation of the reconstruction loss, but also changes the residual scale under different periodic states as the parameter is updated, thus corresponding to the "heteroscedastic residual" engineering problem.

[0074] Furthermore, the inference phase lacks actual power consumption specifications. The input to the first probability parameter subnetwork does not meet the requirements. During the inference phase, the second probability parameter subnetwork outputs the first and second statistical parameters of the intermediate random representation, and uses the first statistical parameter to determine the definite value of the intermediate random representation. The intermediate random representation is then input into the power consumption probability decoding subnetwork, which outputs the predicted periodic power consumption value and the fluctuation amplitude value. This achieves deterministic prediction output even without real power consumption labeling, avoiding output instability introduced by random sampling.

[0075] In summary, this embodiment uses the output power consumption variance parameter to participate in the training loss, so that the residuals of different periods can be given different numerical weights in the loss.

[0076] Furthermore, when different power consumption fluctuation amplitudes correspond to different RTL cycle states, a set of cycle power consumption fluctuation amplitudes (second statistical parameters) of the output power consumption of each cycle is used as the numerical output for subsequent power consumption assessment, cycle screening or risk judgment. In the inference stage, without the condition of real power consumption labeling, the rate parameter sub-network is used to obtain the determined value of the intermediate random representation and output the determined cycle power consumption prediction value to avoid the output instability introduced by random sampling.

[0077] It should be noted that the specific process of the method involved in this embodiment is the same as that in the embodiment, and please refer to the description in Embodiment 1 for details.

[0078] Example 3: Figure 4 As shown, this embodiment also provides an electronic device, including: One or more processors; One or more memories for storing one or more computer programs, and one or more processors for executing the one or more computer programs stored in the memories to cause the one or more processors to perform the features / steps of a microcontroller-oriented RTL cycle power consumption probability prediction method as described in Embodiment 1.

[0079] Furthermore, at the hardware level, the device includes a processor, an internal bus, a network interface, memory, and non-volatile memory, and may also include other necessary hardware. One or more embodiments of this application can be implemented in software, for example, by the processor reading the corresponding computer program from the non-volatile memory into memory and then running it.

[0080] Of course, in addition to the software implementation, one or more embodiments of this application do not exclude other implementation methods, such as logic devices or a combination of hardware and software. That is to say, the execution subject of the above processing flow is not limited to each logic module, but can also be hardware or logic devices.

[0081] Example 4: As will be understood by those skilled in the art, all or part of the features / steps of the above method embodiments can be implemented by methods, data processing systems, or computer programs. These features can be implemented without hardware, entirely in software, or in a combination of hardware and software. The aforementioned computer program can be stored in one or more computer-readable storage media. When the computer program is executed (e.g., by a processor), it performs the steps of the above-described embodiment of an RTL cycle power consumption probability prediction method for microcontrollers.

[0082] The aforementioned storage media capable of storing program code include: static disks, solid-state drives, random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), optical storage devices, magnetic storage devices, flash memory, magnetic disks or optical disks, and / or combinations of the above devices, that is, they can be implemented by any type of volatile or non-volatile storage devices or combinations thereof.

[0083] Example 5: This example provides a computer program product, including a computer program or instructions, which, when executed by a processor, implements the steps of an RTL cycle power consumption probability prediction method for microcontrollers as described in Example 1.

[0084] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the processes of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0085] The above description is merely a preferred embodiment of the present invention. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A probabilistic prediction method for RTL cycle power consumption in microcontrollers, characterized in that, include: Using clock cycles as the sampling unit, the signal sequence output by RTL simulation is divided into samples according to the index corresponding to the clock cycle, and the power consumption label aligned with each index is obtained, thereby forming a stable input and output interface; Based on the logic state of the same multi-channel RTL signal sampled in adjacent clock cycles, a binary indicator of the logic state change in adjacent cycles is generated. The logic state of the multiple RTL signals in each clock cycle is concatenated with the binary indicator in a predetermined order to obtain a periodic feature vector, and the periodic feature vector is trimmed to obtain an effective feature vector. Based on the standardized effective feature vector within each clock cycle, generate the first set of cycle power consumption prediction values ​​and cycle power consumption fluctuation amplitude corresponding to the intermediate random representation; Based on the standardized effective feature vector within each clock cycle, and the intermediate random representation obtained by inferring the first set of cycle power consumption prediction values ​​and cycle power consumption fluctuation amplitude, the cycle power consumption and cycle power consumption fluctuation amplitude of each clock cycle are predicted; the intermediate random representation includes the pipeline occupancy, bus toggle intensity, memory access activity, and control path switching status of the current cycle. The signals output by the RTL simulation include at least one of register output signals, combinational logic node signals, and bus signals. The power consumption label aligned with each index is the average power consumption over the time interval corresponding to each index.

2. The RTL cycle power consumption probability prediction method for microcontrollers according to claim 1, characterized in that, The periodic feature vector is clipped, including: A fixed number of reserved signal bits at the end of the periodic feature vector are clipped.

3. The RTL cycle power consumption probability prediction method for microcontrollers according to claim 1, characterized in that, The intermediate stochastic representation obtained by reasoning from the first set of predicted periodic power consumption values ​​and the periodic power consumption fluctuation amplitude includes: During the inference phase, the value of the intermediate random representation is determined based on the predicted periodic power consumption.

4. A probabilistic prediction device for RTL cycle power consumption in microcontrollers, characterized in that, include: The period-aligned power consumption labeling module uses the clock cycle as the sampling unit, divides the signal sequence output by the RTL simulation into samples according to the index corresponding to the clock cycle, and obtains the power consumption label aligned with each index. The periodic feature construction module generates a binary indicator of the logic state change between adjacent clock cycles based on the logic state of the same multi-channel RTL signal sampled in adjacent clock cycles; it concatenates the logic state and the binary indicator in each clock cycle in a predetermined order to obtain a periodic feature vector, and then trims the periodic feature vector to obtain an effective feature vector. The power consumption standardization module standardizes the effective feature vector and the power consumption label for each clock cycle; The power consumption probability parameter estimation module receives the standardized features and standardized power consumption labels from the power consumption standardization module, and constructs a probability prediction model including a first probability parameter sub-network, a second probability parameter sub-network, and a power consumption probability decoding sub-network. The first probability parameter sub-network generates a second set of periodic power consumption prediction values ​​and periodic power consumption fluctuation amplitudes corresponding to the intermediate random representation based on the standardized effective feature vector and power consumption label of each clock cycle. The second probability parameter sub-network generates the first set of predicted periodic power consumption values ​​and periodic power consumption fluctuation amplitudes corresponding to the intermediate random representation based on the effective feature vector standardized for each clock cycle. The power consumption probability decoding subnetwork predicts the periodic power consumption and periodic power consumption fluctuation amplitude for each clock cycle based on the standardized effective feature vector within each clock cycle and the intermediate random representation obtained by inferring the first set of periodic power consumption prediction values ​​and periodic power consumption fluctuation amplitude. The power consumption prediction output module receives the effective feature vector to be predicted from the periodic feature construction module, the standardized statistics from the power consumption standardization module, and the trained model parameters from the power consumption probability parameter estimation module, and outputs the periodic power consumption prediction value and the numerical value used for subsequent power consumption assessment, periodic screening, or risk judgment.

5. The RTL cycle power consumption probability prediction device for microcontrollers according to claim 4, characterized in that, Also includes: The regularization loss term is calculated based on the difference between the intermediate random representation parameters output by the first probability parameter subnetwork and the intermediate random representation parameters output by the second probability parameter subnetwork. The reconstruction loss term is calculated based on a set of first and second statistical parameters output by the power consumption probability decoding subnetwork, and the reconstruction loss term is numerically modulated by the second statistical parameters output by the power consumption probability decoding subnetwork. The first probability parameter subnetwork, the second probability parameter subnetwork, and the power consumption probability decoding subnetwork are trained based on the modulation reconstruction loss term and the generated regularization loss term.

6. An electronic device, characterized in that, include: At least one processor; At least one memory used to store processor-executable instructions; The at least one processor implements a microcontroller-oriented RTL cycle power consumption probability prediction method by running the executable instructions as described in any one of claims 1 to 3.

7. A computer-readable storage medium, characterized in that, It stores computer instructions that, when executed by at least one processor, implement a microcontroller-oriented RTL cycle power consumption probability prediction method as described in any one of claims 1 to 3.

8. A computer program product, characterized in that, It includes a computer program or instructions that, when executed by a processor, implement a microcontroller-oriented RTL cycle power consumption probability prediction method as described in any one of claims 1 to 3.

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