Selective triple modular redundancy conversion method and system based on two-stage decoupling
By employing a two-stage decoupled selective triple-mode redundancy conversion method, key signals are dynamically analyzed and converted at the RTL code level. This solves the problems of resource increase and signal mismatch in existing technologies, achieving efficient triple-mode redundancy hardening and improving design flexibility and hardening effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG UNIV
- Filing Date
- 2026-05-09
- Publication Date
- 2026-07-31
AI Technical Summary
Existing triple redundancy technology suffers from excessive hardware resource consumption, increased dynamic power consumption, wiring congestion, difficulty in timing convergence, and signal fan-in/fan-out mismatch issues. Furthermore, its reliance on specific EDA tools results in poor flexibility.
A selective triple-mode redundancy conversion method based on two-stage decoupling is adopted. A whitelist of key signals is generated through dynamic activity analysis, and selective conversion is performed at the RTL code level. Pseudo-TMR processing is used to solve the interface mismatch problem and achieve dynamic selective hardening.
While reducing hardware resources and power consumption, it ensures topology continuity, avoids signal fan-in/fan-out mismatch, improves design flexibility and hardening effect, and shortens the R&D cycle.
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Figure CN122287506B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of triple mode redundancy technology, and particularly relates to a selective triple mode redundancy conversion method and system based on two-stage decoupling. Background Technology
[0002] Digital integrated circuit reliability design hardening technologies are mainly divided into two categories: triple modular redundancy (TMR) circuit design hardening technology in the ASIC front-end design stage, and design hardening technology relying on standard cells at the back-end netlist level.
[0003] TMR hardening currently mainly utilizes EDA (Electronic Design Automation) software, such as Figure 1 As shown, the target module (register, combinational logic, or functional module) is copied three times, and the majority consensus result is output through the majority voter. Figure 1 The diagram illustrates how a single original signal is reinforced with triple mode redundancy to form three circuits: two replica signals and one original signal. If any one of these circuits is subjected to a single-event bombardment causing a level flip and resulting in an error, the outputs of the other two circuits remain correct. Therefore, after passing through a majority voter, if the outputs of the two circuits are identical, then the output is that value, and the result is correct.
[0004] While traditional triple modular redundancy (TMR) technology can effectively mask single points of failure, its basic architecture has significant drawbacks. It requires completely replicating the original circuit three times, resulting in an increase of at least 200% in hardware resources (such as logic units, memory, and power consumption), making it unsuitable for resource-constrained scenarios. In practical applications, the dynamic power consumption increase caused by redundant circuits can reach 200-300%, and large-scale redundancy of circuits leads to wiring congestion and timing convergence difficulties.
[0005] A partial triple modulo redundancy method exists in the prior art. Although it overcomes the complete replication of the original circuit, it still has the following technical problems: (1) It uses netlist parsing to statistically analyze the physical stacking ratio of configuration units to determine whether partial triple redundancy is required. This is essentially a static criterion and cannot distinguish the operating state of the logic. Even if a module has a high proportion of physical units, if it remains silent or dormant for a long time, the risk of it actually interfering with the correct operation of the circuit is relatively low. Using the above static criterion to determine partial triple redundancy can easily lead to a certain degree of blindness.
[0006] (2) In the logic conversion process of partial triple redundancy, topological continuity cannot be achieved, which easily leads to signal fan-in / fan-out mismatch. To correct this, the three redundant branches must converge to a voter at the conversion point. This breaks the original parallel path, causing the three signals to be "squeezed" together in physical space, resulting in asymmetric fan-in delay. The single result after voting often needs to drive the three modules of the next level again. This causes the load (fan-out) of the node to increase by 3 times instantaneously. If the driving capability is mismatched, the signal edges will become blunt, causing timing errors.
[0007] (3) It relies on EDA tools and netlist files generated by back-end layout and routing, and depends on specific EDA vendor tools and standard cells of specific models. This implementation method has certain deficiencies in terms of flexibility. Summary of the Invention
[0008] To overcome the shortcomings of the prior art, this invention provides a selective triple-mode redundancy conversion method and system based on two-stage decoupling. It completely decouples the two stages of dynamic activity analysis of circuit signals and selective conversion of source code. In the dynamic activity analysis stage, a whitelist of critical signals at the logic level is generated based on the dynamic flip frequency. In the selective conversion stage, the code is compared with the list through an automation engine, and true / pseudo-TMR splitting is performed. Through pseudo-TMR interface alignment technology, while ensuring the consistency of the topology of the three signal interfaces of the whole system, the critical path is dynamically selected to implement logic redundancy, and the non-critical path is implemented to implement interface placeholder.
[0009] To achieve the above objectives, one or more embodiments of the present invention provide the following technical solutions: The first aspect of this invention provides a selective triple-mode redundancy conversion method based on two-stage decoupling.
[0010] The selective triple-modulus redundancy conversion method based on two-stage decoupling includes the following steps: Obtain the Verilog design code to be converted and parse out the circuit signals; Calculate the dynamic activity of each circuit signal, combine it with the preset dynamic activity threshold, divide the circuit signals into critical circuit signals and non-critical circuit signals, form a list of critical circuit signals, and complete the analysis of the circuit signals. Read the list of critical circuit signals, traverse each line of assignment statements in the Verilog design code to be converted, and identify whether the current circuit signal is a critical circuit signal; perform triple mode redundancy operation on the identified critical circuit signals, and use logical assignment to make the replica signals track the original signals in real time for the identified non-critical circuit signals, thus completing the selective triple mode redundancy conversion.
[0011] A second aspect of the present invention provides a selective triple-mode redundancy conversion system based on two-stage decoupling.
[0012] Selective triple-mode redundancy conversion system based on two-stage decoupling includes: The circuit signal parsing module is configured to: acquire the Verilog design code to be converted and parse out the circuit signals within it; The dynamic activity analysis module is configured to: calculate the dynamic activity of each circuit signal, combine it with a preset dynamic activity threshold, divide the circuit signals into critical circuit signals and non-critical circuit signals, form a list of critical circuit signals, and complete the analysis of the circuit signals. The selective conversion module is configured to: read the list of critical circuit signals, traverse each line of assignment statements in the Verilog design code to be converted, identify whether the current circuit signal is a critical circuit signal; perform triple-modulus redundancy operation on the identified critical circuit signals, and use logical assignment to make the replica signal track the original signal in real time for the identified non-critical circuit signals, thus completing the selective triple-modulus redundancy conversion.
[0013] The above one or more technical solutions have the following beneficial effects: (1) This invention provides a selective triple-mode redundancy conversion method and system based on two-stage decoupling, which completely decouples the two stages of dynamic activity analysis of circuit signals and selective conversion of source code: The dynamic activity analysis phase generates a whitelist of key signals at the logic level based on the dynamic flip frequency. In the selective conversion phase, processing is performed at the RTL code level (RTL (Register Transfer Level) refers to a logical model described by a hardware description language (such as Verilog or VHDL) that defines how data is transferred and processed between registers). The code is compared with the list by an automation engine, and true / pseudo-TMR splitting is performed. This avoids the blindness of static criteria for statistical configuration units through netlist parsing and the dependence on vendor netlist tools. Furthermore, the placeholder mechanism of pseudo-TMR processing solves the interface mismatch problem caused by some redundancy.
[0014] (2) The advantages of the two-stage decoupling processing mode proposed in this invention are: Design decoupling and flexibility: The list of key signals generated in the first stage can be manually intervened and reviewed. The required signals can be manually added or modified in the list based on human experience, which achieves a perfect combination of automated program analysis and human experience correction.
[0015] Eliminating backend iteration costs: This invention processes at the RTL level. The area overhead after reinforcement can be estimated as soon as the flip rate is calculated in the first step, without waiting for the netlist to be generated before estimating resource overhead, as is the case with traditional methods. If resource consumption exceeds limits, the filtering threshold is immediately adjusted in the list, eliminating the need for repeated, time-consuming layout and routing.
[0016] Code semantic consistency: By constructing a list of key circuit signals and comparing each assignment statement line by line, and classifying them into two categories (true / false) based on the comparison structure, the topology of the source code interface is ensured to be consistent. This solves the problem of not being able to automatically insert most decision switches in some triple-modulus redundancy due to inconsistent signal bit widths.
[0017] The pseudo-TMR processing implemented in this invention through logical assignment is essentially a form of semantic redundancy. It utilizes the equivalence optimization of synthesis tools to automatically eliminate redundant resources, a compiler feature not utilized in existing netlist-level processing. Furthermore, the pseudo-TMR processing of this invention features interface placeholder functionality, ensuring the topological continuity of the hardened link during logical conversion and avoiding the signal fan-in / fan-out mismatch problem commonly found in existing technologies when handling partial redundancy.
[0018] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0019] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.
[0020] Figure 1 This is a schematic diagram of the TMR implementation principle in existing technologies.
[0021] Figure 2 This is a diagram illustrating the method execution steps of Example 1.
[0022] Figure 3 This is a schematic diagram of the selective triple redundancy principle in Example 1.
[0023] Figure 4 This is a flowchart of the overall method in Example 1.
[0024] Figure 5 This is a flowchart of the selective conversion stage in the two-stage decoupling process of Example 1.
[0025] Figure 6 Example 1 Figure 5 TMR processing flowchart.
[0026] Figure 7 Example 1 Figure 5Flowchart of TMR processing in China. Detailed Implementation
[0027] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0028] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations of the present invention.
[0029] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.
[0030] Example 1 like Figure 2 As shown, this embodiment provides a selective triple-mode redundancy conversion method based on two-stage decoupling, including the following steps: Obtain the Verilog design code to be converted and parse out the circuit signals; Calculate the dynamic activity of each circuit signal, combine it with the preset dynamic activity threshold, divide the circuit signals into critical circuit signals and non-critical circuit signals, form a list of critical circuit signals, and complete the analysis of the circuit signals. Read the list of critical circuit signals, traverse each line of assignment statements in the Verilog design code to be converted, and identify whether the current circuit signal is a critical circuit signal; perform triple mode redundancy operation on the identified critical circuit signals, and use logical assignment to make the replica signals track the original signals in real time for the identified non-critical circuit signals, thus completing the selective triple mode redundancy conversion.
[0031] It can be understood that the Verilog design code mentioned in this embodiment refers to text code written in Verilog Hardware Description Language (HDL) to describe the structure and behavior of digital circuit systems.
[0032] Compared to the traditional triple-modulus redundancy (TMR) circuit structure, which requires completely replicating the original circuit three times, this embodiment adopts a novel approach to achieve TMR hardening: selective TMR. Selective TMR only replicates critical circuits three times, while non-critical circuits are not actually replicated logically.
[0033] This embodiment operates directly at the Verilog source code level, achieving automated conversion through front-end syntax parsing to obtain the circuit signals. It does not rely on back-end physical netlist parsing and directly applies to the RTL design stage, avoiding the limitations of specific tools. Furthermore, it assesses the importance of the circuit based on its dynamic activity and then selectively hardens it according to its importance. This approach can significantly reduce the increase in hardware resource area, power consumption, and the difficulty of back-end circuit implementation while maintaining a high level of hardening effect.
[0034] Furthermore, in this embodiment, after obtaining the Verilog design code to be converted, the code needs to be preprocessed, including: Merge multiple distributed Verilog design files; Abstract Syntax Tree (AST) parsing technology is used to identify circuit signal definitions such as module interfaces, registers, and wires in the code.
[0035] After obtaining the circuit signals, this embodiment employs a dynamic analysis method based on the actual workload to calculate the dynamic activity of each circuit signal, specifically including: Insert a counter module to record the number of toggles for each circuit signal in real time; Statistical features are extracted, outlier interference is eliminated using the Z-score algorithm, and the average signal flip rate of the circuit is calculated. The average value of the circuit signal flip rate is used as the dynamic activity of the circuit signal.
[0036] After obtaining the dynamic activity level of the circuit signals, this embodiment, in conjunction with a preset dynamic activity level threshold, divides the circuit signals into critical circuit signals and non-critical circuit signals, specifically including: Circuit signals whose dynamic activity exceeds the dynamic activity threshold are classified as critical circuit signals; Circuit signals whose dynamic activity does not exceed the dynamic activity threshold are classified as non-critical circuit signals.
[0037] Furthermore, in this embodiment, the sum of μ + 2σ is calculated as the dynamic activity threshold, where μ is the average number of flips in the statistical feature and σ is the standard deviation of the number of flips in the statistical feature.
[0038] In this embodiment, the circuit signals to be processed are divided into two categories: critical circuit signals and non-critical circuit signals, based on a preset dynamic activity threshold of the circuit signals. The critical circuit signals are essentially high-activity sensitive signals that have been screened out, while the non-critical circuit signals are essentially low-activity non-sensitive signals that have been screened out.
[0039] Subsequently, this embodiment performs two types of signal splitting processing: true TMR and pseudo TMR splitting processing. Tri-mode redundancy is applied to the identified critical circuit signals, while logical assignment is used to make the replica signals track the original signals in real time for the identified non-critical circuit signals, thus completing the automatic conversion of selective tri-mode redundancy. Specifically: (1) True TMR processing involves physically replicating the sensitive signal and its driving logic in three ways: Identify the original assignment statements in the Verilog design code to be converted, corresponding to the key circuit signals; Triple modular redundancy is applied to the original assignment statements in the Verilog design code corresponding to the critical circuit signals to achieve triple reinforcement.
[0040] (2) The pseudo-TMR processing only performs "definition copying" on non-critical signals, that is, it uses logical assignment to make the copy signal track the original signal in real time to maintain the consistency of the interface: Identify the original assignment statements in the Verilog design code to be converted for the non-critical circuit signals; Remove the original assignment statements from the code block containing the non-critical circuit signals in the Verilog design code to be converted; Create a new code block to handle non-critical circuit signals. Use the signals in the original assignment statements as the original signals and assign the original signals to two copy signals simultaneously. This enables the copy signals to track the original signals in real time without executing the triple redundancy program.
[0041] This embodiment employs a "pseudo-TMR" interface alignment logic: for logic that does not require hardening, the system still defines a port with a width three times that of the top-level module, but in the internal implementation, it is implemented through a non-blocking method of logical assignment, which solves the pain points of interface bit width mismatch between modules and large amount of manual modification work caused by traditional partial redundancy technology.
[0042] Technical value: This approach achieves the appearance of "full redundancy" in the front-end code, ensuring the automatic and unified mounting of most subsequent decision-making modules; however, in the logic synthesis stage, the back-end tools will automatically identify this equivalent logic and optimize away redundant copies, thereby achieving true resource simplification at the underlying level.
[0043] This also includes automatic nesting of most decision-makers, specifically: A majority voter is automatically inserted at the three signal output terminals (original signal and two replica signals) based on the signal attributes, and the single signal after voting is fed back to the original circuit topology.
[0044] This invention introduces dynamic activity as a criterion, enabling precise location of sensitive areas and overcoming the blindness of static criteria. Its core value and difference from existing netlist-level technologies lie in: In existing technologies, the physical stacking ratio of configuration units obtained through netlist analysis is a static criterion that cannot distinguish the operational state of the logic. Even if a module has a high physical unit ratio, if it remains silent or dormant for a long time, the risk of it actually interfering with the correct operation of the circuit is still low. In contrast, this embodiment focuses on high-frequency flip registers, clock networks, and control signals. These nodes have dense state transitions in the time dimension and are sensitive areas for capturing and amplifying single-event flip pulses. Through dynamic analysis, this embodiment can accurately harden the truly changing critical nodes, avoiding blind hardening based on physical stacking.
[0045] Figure 4 The diagram shown is a flowchart of the overall method in this embodiment. Figure 4 As shown, this embodiment includes six steps in its implementation: code standardization, insertion of a flip counter, acquisition of flip frequency, flip frequency processing, selective TMR processing, and TMR post-processing.
[0046] Figure 5 The diagram shown is a flowchart of the selective switching stage in the two-stage decoupling process of this embodiment. Figure 6 and Figure 7 The flowcharts are the TMR processing flowchart and the pseudo-TMR processing flowchart for this embodiment.
[0047] The next step will be based on Figure 4 and combined Figure 5 , Figure 6 and Figure 7 The solution of this embodiment will be explained in detail.
[0048] 1. Code Standardization: The code standardization module mainly formats the Verilog design code to make it conform to the recognition and processing of subsequent modules. The process of standardizing Verilog code is as follows: (1-1) Standardized indentation format: The indentation standard for each line that needs to be indented is four spaces.
[0049] (1-2) Remove redundant spaces or insert spaces in appropriate places: Remove non-standard extra spaces in the original code and add spaces where needed, such as deleting extra spaces from concatenation symbols, deleting extra spaces from bit-width expressions, and requiring a space between the always keyword and the @ keyword in the always block header.
[0050] (1-3) Standardized signal declaration rules: each line declares only the information of one signal.
[0051] (1-4) Add instantiation markers in modules: Add the &instance instantiation marker on the line before the instantiation module in the code to prepare for subsequent programs.
[0052] (1-5) Standardized module signal name instantiation rules: All instantiated module interface signals are triple-modular redundancy interfaces and need to be connected to the corresponding _tmr1 / 2 / 3 suffix signals.
[0053] (1-6) Standardize the begin end procedure code block: Some assignment procedures in the always block are not included in the begin end procedure block. The begin end keyword needs to be added to include these assignment statements in the begin end procedure block.
[0054] 2. Insertion counter: (2-1) Identify signals in the original code: Identify the signal declaration part in the Verilog code using a Python program and record the signal information.
[0055] (2-2) Add counter signal: Add a corresponding flip counter signal for counting the number of flips to each identified signal.
[0056] (2-3) Add counting logic: When a certain original code signal changes, update the counter signal to increment the counter signal by one.
[0057] 3. Acquisition flip frequency: (3-1) Design test cases: Design corresponding test cases according to the application scenario of the reinforced module.
[0058] (3-2) Collect test results: Run enough test programs and output the test results through system functions.
[0059] 4. Flip frequency processing: (4-1) Remove outlier data: The Z-score method based on statistical methods is used to remove outliers that are far from the mean.
[0060] (4-2) Calculate the mean: Calculate the mean of the data after removing outliers.
[0061] (4-3) Determine if it is a critical circuit: Compare the preset threshold and the mean value to determine if it is a critical circuit.
[0062] 5. Selective TMR processing: (5-1) Read the list of key signals obtained in step 4 and modify the original signal declaration to a hardened signal with the suffix _tmr1 / 2 / 3.
[0063] (5-2) Traverse each line of assignment statements in the Verilog file and identify whether it is a key circuit signal that needs to be hardened.
[0064] (5-3) If it is a critical circuit signal that needs to be hardened, the original assignment statement will be hardened by performing triple modulo redundancy, and a majority voter will be inserted at the register output. The code of the triplet part will be marked with corresponding comment lines to support subsequent processing. The circuit structure corresponding to the processed code is as follows: Figure 1 As shown.
[0065] (5-4) If the signal is not a critical circuit signal requiring reinforcement, pseudo-TMR processing is performed. This involves deleting it from the code block containing the assignment statement and creating a new code block to handle non-critical circuit signals. The triple modular redundancy (TMR) procedure is not executed; instead, the signals in the original code's assignment statements are modified to have the 'tmr1' suffix. The 'tmr2' and 'tmr3' signals no longer implement the circuit logic of the 'tmr1' signal separately, but are directly derived from 'tmr1'. This reduces the logic resources of non-critical circuits while retaining the 'tmr1' / 2 / 3 signal form to support the logic of subsequent signals. The circuit structure corresponding to the processed code is as follows: Figure 3 As shown.
[0066] Figure 3 In the diagram, the broken lines at the outputs of most of the switches before the combinational logic circuit, as well as the two broken lines at the output of the combinational logic circuit, all indicate that the two hardened signals of TMR2 / 3 were not replicated by the combinational logic circuit at this point.
[0067] The following is the original circuit code without TMR hardening: reg signal; / / Defines a 1-bit register variable signal; always @(posedge clk ) begin / / Execute the following logic on the rising edge of clock clk; signal<= a&b; / / Assign the bitwise AND result of a and b to signal; end This is after Figure 1 Circuit code after traditional TMR processing: / / Define three redundant output and input registers; reg signal_tmr1; / / Output register for redundant channel 1; reg signal_tmr2; / / Output register for redundant channel 2; reg signal_tmr3; / / Output register for redundant channel 3; reg a_tmr1; / / Input register a for channel 1; reg a_tmr2; / / Input register a for channel 2; reg a_tmr3; / / Input register a for channel 3; reg b_tmr1; / / Input register b for channel 1; reg b_tmr2; / / Input register b for channel 2; reg b_tmr3; / / Input register b for channel 3; / / Independent operation logic for channel 1; always @(posedge clk ) begin / / Clock edge triggered; signal_tmr1<= a_tmr1&b_tmr1; / / AND operation on channel 1; end / / Independent operation logic for channel 2; always @(posedge clk ) begin / / Clock edge triggered; signal_tmr2<= a_tmr2&b_tmr2; / / AND operation on channel 2; end / / Independent operation logic for channel 3; always @(posedge clk ) begin / / Clock edge triggered; signal_tmr3<= a_tmr3&b_tmr3; / / AND operation on channel 3; end This is after Figure 3 The circuit code after pseudo-TMR processing and hardening: / / Define three output registers and input registers (structure is the same as traditional TMR); reg signal_tmr1; / / Output register of the main channel; reg signal_tmr2; / / Placeholder for the output register of channel 2; reg signal_tmr3; / / Placeholder for the output register of channel 3; reg a_tmr1; / / Input register a for the main channel; reg a_tmr2; / / Placeholder for input register a of channel 2; reg a_tmr3; / / Placeholder for input register a of channel 3; reg b_tmr1; / / Input register b of the main channel; reg b_tmr2; / / Placeholder for input register b of channel 2; reg b_tmr3; / / Placeholder input register b for channel 3; / / Main channel: The actual execution of calculations; always @(posedge clk ) begin / / Clock edge triggered; signal_tmr1<= a_tmr1&b_tmr1; / / Perform AND operation on the main channel; end / / Pseudo-redundant channel 2: only used for pass-through connection (no actual computation); always @(*) begin / / Combinational logic, with * as the sensitive signal list; signal_tmr2 = signal_tmr1; / / Directly pass the result from the main channel to channel 2; end / / Pseudo-redundant channel 3: only used for pass-through connection (no actual computation); always @(*) begin / / Combinational logic, with * as the sensitive signal list; signal_tmr3 = signal_tmr1; / / Directly pass the result from the main channel to channel 2; end 6. TMR post-processing: Because blank always blocks will be generated during the execution of the three-modular redundancy program in step 5, that is, there are no valid assignment statements in the always block; or there are duplicate assignment statements in the always block.
[0068] (6-1) Identify whether there is a valid assignment statement using Python regular expressions.
[0069] (6-2) If there is no valid assignment statement, delete this code block.
[0070] (6-3) Identify the tmr marker in step 5 and count all assignment statements in the marked code block into an array.
[0071] (6-4) Use Python's deduplication function to process assignment statements in arrays, thereby merging duplicate assignment statements.
[0072] The selective triple modal redundancy conversion method based on two-stage decoupling provided in this embodiment, compared with the traditional triple modal redundancy TMR technology in the current technology, directly operates at the Verilog source code level (RTL level) and is implemented through abstract syntax tree (AST) parsing. Compared with the existing technology that relies on EDA tools and netlist files generated by back-end placement and routing, this invention is free from the constraints of hardware vendor toolchains and solves the problems of difficult migration and poor versatility of hardened designs across different chip platforms.
[0073] This embodiment employs a "pseudo-TMR" interface alignment technique to dynamically select critical paths for "logical redundancy" and non-critical paths for "interface placeholders" while ensuring the consistency of the three signal interface topologies across the entire system. This not only solves common engineering problems in traditional partial redundancy techniques, such as interface protocol mismatch and unbalanced signal fan-out, but also optimizes resource consumption and power consumption while ensuring radiation resistance.
[0074] This embodiment completes the selective triple-modulus redundancy conversion before logic synthesis, allowing designers to verify the correctness of redundant logic during the RTL simulation stage without going through a lengthy "synthesis-placement-routing-backannotation netlist" cycle. This pre-processing hardening significantly shortens the chip development cycle and substantially reduces the risk of design rework due to excessive backend resources.
[0075] Unlike netlist analysis, which only focuses on the proportion of physical sensitivity, this embodiment filters based on the dynamic activity of the circuit, which is more in line with the logical characteristics of digital circuit operation, and enables redundant resources to be accurately allocated to the nodes that have the greatest impact on system function.
[0076] Example 2 This embodiment discloses a selective triple-mode redundancy conversion system based on two-stage decoupling.
[0077] Selective triple-mode redundancy conversion system based on two-stage decoupling includes: The circuit signal parsing module is configured to: acquire the Verilog design code to be converted and parse out the circuit signals within it; The dynamic activity analysis module is configured to: calculate the dynamic activity of each circuit signal, combine it with a preset dynamic activity threshold, divide the circuit signals into critical circuit signals and non-critical circuit signals, form a list of critical circuit signals, and complete the analysis of the circuit signals. The selective conversion module is configured to: read the list of critical circuit signals, traverse each line of assignment statements in the Verilog design code to be converted, identify whether the current circuit signal is a critical circuit signal; perform triple-modulus redundancy operation on the identified critical circuit signals, and use logical assignment to make the replica signal track the original signal in real time for the identified non-critical circuit signals, thus completing the selective triple-modulus redundancy conversion.
[0078] Those skilled in the art will understand that the modules or steps of the present invention described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computer device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. The present invention is not limited to any particular combination of hardware and software.
[0079] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.
Claims
1. A selective triple-modulus redundancy conversion method based on two-stage decoupling, characterized in that, Includes the following steps: Obtain the Verilog design code to be converted and parse out the circuit signals; Calculate the dynamic activity of each circuit signal, combine it with the preset dynamic activity threshold, divide the circuit signals into critical circuit signals and non-critical circuit signals, form a list of critical circuit signals, and complete the analysis of the circuit signals. Read the list of critical circuit signals, traverse each line of assignment statements in the Verilog design code to be converted, and identify whether the current circuit signal is a critical circuit signal; perform triple mode redundancy operation on the identified critical circuit signals, and use logical assignment to make the replica signal track the original signal in real time for the identified non-critical circuit signals, thus completing the selective triple mode redundancy conversion. For the identified non-critical circuit signals, logical assignment is used to enable the replica signals to track the original signals in real time, specifically including: Identify the original assignment statements in the Verilog design code to be converted for the non-critical circuit signals; Remove the original assignment statements from the code block containing the non-critical circuit signals in the Verilog design code to be converted; Create a new code block to handle non-critical circuit signals. Use the signals in the original assignment statements as the original signals and assign the original signals to two copy signals simultaneously. This enables the copy signals to track the original signals in real time without executing the triple redundancy program.
2. The selective triple-mode redundancy conversion method based on two-stage decoupling as described in claim 1, characterized in that, The abstract syntax tree (AST) parsing technique is used to identify the circuit signals in the Verilog design code to be converted, including module interfaces, registers, and nets.
3. The selective triple-mode redundancy conversion method based on two-stage decoupling as described in claim 1, characterized in that, Calculate the dynamic activity of each circuit signal, specifically including: Insert a counter module to record the number of toggles for each circuit signal in real time; Statistical features are extracted, outlier interference is eliminated using the Z-score algorithm, and the average signal flip rate of the circuit is calculated. The average value of the circuit signal flip rate is used as the dynamic activity of the circuit signal.
4. The selective triple-mode redundancy conversion method based on two-stage decoupling as described in claim 1, characterized in that, Based on a preset dynamic activity threshold, circuit signals are divided into critical circuit signals and non-critical circuit signals, specifically including: Circuit signals whose dynamic activity exceeds the dynamic activity threshold are classified as critical circuit signals; Circuit signals whose dynamic activity does not exceed the dynamic activity threshold are classified as non-critical circuit signals.
5. The selective triple-mode redundancy conversion method based on two-stage decoupling as described in claim 1, characterized in that, Triple modal redundancy operation is performed on the identified critical circuit signals, specifically including: Identify the original assignment statements in the Verilog design code to be converted, corresponding to the key circuit signals; Triple modular redundancy is applied to the original assignment statements in the Verilog design code corresponding to the critical circuit signals to achieve triple reinforcement.
6. The selective triple-mode redundancy conversion method based on two-stage decoupling as described in claim 3, characterized in that, Insert a counter module to record the number of toggles for each circuit signal in real time, specifically including: Add a corresponding counter signal to each circuit signal to count the number of toggles; Determine the counting logic: when a certain original code signal changes, update the counter signal and increment the counter signal by one; Design corresponding test cases based on the application scenario of the reinforced module; Run the test program and output the test results through system functions.
7. The selective triple-mode redundancy conversion method based on two-stage decoupling as described in claim 1, characterized in that, It also includes inserting a majority switch at the output of the three signals (original signal and two replica signals) and feeding the signal output of the majority switch back to the original circuit topology.
8. The selective triple-mode redundancy conversion method based on two-stage decoupling as described in claim 1, characterized in that, After the list of critical circuit signals is formed, it also includes manually adding or modifying critical circuit signals in the list.
9. A selective triple-mode redundancy conversion system based on two-stage decoupling, characterized in that, include: The circuit signal parsing module is configured to: acquire the Verilog design code to be converted and parse out the circuit signals within it; The dynamic activity analysis module is configured to: calculate the dynamic activity of each circuit signal, combine it with a preset dynamic activity threshold, divide the circuit signals into critical circuit signals and non-critical circuit signals, form a list of critical circuit signals, and complete the analysis of the circuit signals. The selective conversion module is configured to: read the list of critical circuit signals, traverse each line of assignment statements in the Verilog design code to be converted, identify whether the current circuit signal is a critical circuit signal; perform triple mode redundancy operation on the identified critical circuit signals, and make the replica signal track the original signal in real time through logical assignment on the identified non-critical circuit signals, thus completing the selective triple mode redundancy conversion; For the identified non-critical circuit signals, logical assignment is used to enable the replica signals to track the original signals in real time, specifically including: Identify the original assignment statements in the Verilog design code to be converted for the non-critical circuit signals; Remove the original assignment statements from the code block containing the non-critical circuit signals in the Verilog design code to be converted; Create a new code block to handle non-critical circuit signals. Use the signals in the original assignment statements as the original signals and assign the original signals to two copy signals simultaneously. This enables the copy signals to track the original signals in real time without executing the triple redundancy program.