A layout structure, design method and system-on-chip of a clock buffer module

Abstract

The application discloses a layout structure of a clock buffer module, a design method and a system-level chip, and belongs to the technical field of integrated circuit design.The layout structure of the clock buffer module comprises a standard buffer unit, a plurality of functional element units, signal pins and power supply pins, and internal connection holes.The plurality of functional element units comprise at least one pre-embedded coupling capacitor unit and at least one pre-embedded charge discharge unit.The plurality of functional element units are arranged in an integrated manner around the standard buffer unit in the layout.The signal pins and the power supply pins are located on different preset high-level metal layers.The signal connection terminals and the power supply connection terminals of the standard buffer unit are respectively electrically connected with the signal pins and the power supply pins through the internal connection holes.The technical scheme provided by the application improves uncontrollable problems such as wire winding, voltage drop and antenna effect caused by directly using large driving force devices provided with a process library, and can also avoid dependence of large driving force devices customized for high-speed long-distance low-delay application scenarios.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit automated design technology, and in particular to a layout structure, design method, and system-on-a-chip for a clock buffer module. Background Technology

[0002] With the continuous evolution of chip design technology, the complexity and computing power requirements of SOC (System on Chip) design are increasing exponentially, directly leading to a significant increase in chip area and performance requirements. Against this backdrop, high-performance, large-area chip designs pose unprecedented challenges to the high-speed transmission and long-distance propagation of global clock signals. To meet the requirements for rapid clock signal response and effectively reduce the impact of on-chip variation (OCV) and clock skew on timing convergence, achieving long-distance, low-latency propagation of high-speed clock signals has become crucial.

[0003] To achieve this goal, a common solution is to lay out the clock signal lines in the chip's RDL (Redistribution Layer). This involves optimizing the routing topology from the clock source signal to each remote destination and using high-drive clock signal buffers or pairs of inverters (collectively referred to as buffers for simplicity) to drive and continue the clock signal. High-drive buffers are fundamental to achieving long-distance, low-latency signal transmission in the RDL layer.

[0004] In the process libraries provided by process manufacturers, there are usually some large drive force buffers. Taking 6nm / 7nm process as an example, the large drive force buffer (X24 device) provided by the process library can drive the clock signal line length in the RDL layer between 500 and 700 micrometers while meeting the clock signal slope requirement of about 2GHz. According to the current performance area of ​​mainstream high-performance large-scale SoCs, such drive force can meet the long-distance transmission of high-speed clock signals for most chips. However, these default buffers have several application bottlenecks. First, because of their large drive force and driving high-speed long-distance clock signals, the voltage drop of large drive force buffers is usually large, resulting in insufficient device voltage. Second, because the device drives RDL metal lines that are 500 to 600 micrometers long, it is prone to antenna effect. Third, its pins are usually located in lower metal layers and cannot be directly connected to the metal lines of the RDL layer. The connection between the metal traces of the RDL layer and the built-in high-drive-force buffer requires the use of an EDA (Electronic Design Automation) tool's wirewound mechanism to create vias (Vertical Interconnect Access, VIAs) during the SOC clock winding process. This process is complex and time-consuming, and it also introduces the uncertainty of how the vias change depending on the device's position, thus causing uncertainty in the clock signal line delay within the RDL layer.

[0005] To address the aforementioned issues and enhance driving force, chip design companies typically opt to purchase custom-designed high-drive-force buffers from third-party IP vendors or perform transistor-level device reconstruction and recharacterization (equivalent to developing their own high-drive-force buffers). However, these methods face challenges such as high cost, long development cycles, and significant risks. Therefore, how to mitigate the numerous uncontrollable problems caused by directly using high-drive-force devices from process libraries, such as wiring, voltage drop, and antenna effects, while simultaneously avoiding the reliance on custom-designed high-drive-force devices for most high-speed, long-distance, low-latency applications, has become a pressing technical challenge in this field. Summary of the Invention

[0006] This invention provides a layout structure, design method, and system-on-a-chip for a clock buffer module, which improves the uncontrollable problems such as wiring, voltage drop, and antenna effect caused by directly using high-power devices provided in the process library. At the same time, it can also avoid the dependence on customized high-power devices in most high-speed, long-distance, low-latency application scenarios.

[0007] According to one aspect of the present invention, a layout structure for a clock buffer module is provided, comprising: Standard buffer unit; Multiple functional element units, each including at least one embedded coupling capacitor unit and at least one embedded charge discharge unit; wherein, the multiple functional element units are integrated in the layout in a manner surrounding the standard buffer unit; Boundary units are located at the edge regions of at least one side of the layout structure; The signal pins and power pins are located on different preset high-layer metal layers; wherein, the standard buffer unit includes signal connection terminals and power connection terminals, which are located on different preset low-layer metal layers; the signal connection terminals and the power connection terminals are electrically connected to the signal pins and the power pins respectively through the internal connection holes of the modular clock buffer.

[0008] Optionally, the signal pins include a clock signal input pin and a clock signal output pin; the signal connection terminals of the standard buffer unit include a clock signal input connection terminal and an output signal connection terminal. The input signal connection terminal is electrically connected to the signal input pin through the first connection hole inside the clock buffer module, and the output signal connection terminal is electrically connected to the signal output pin through the second connection hole inside the clock buffer module; The metal layer containing the signal input pin and the signal output pin is a redistributed metal layer.

[0009] Optionally, the power supply pin includes at least one first power supply pin and at least one ground pin; the first power supply pin is electrically connected to a first power supply trace network inside the clock buffer module, and the ground pin is electrically connected to a ground trace network inside the clock buffer module. The first power supply connection terminal of the standard buffer unit is electrically connected to the first power supply routing network; the grounding terminal of the standard buffer unit is electrically connected to the grounding routing network. The charge discharge unit includes an inverted diode; the first end of the diode is electrically connected to the input signal connection terminal of the standard buffer unit; and the second end of the diode is electrically connected to the grounding network.

[0010] Optionally, the layout structure of the clock buffer module further includes a voltage converter unit, which is located on one side of the standard buffer unit in the layout and is disposed on the coupling path between the signal input pin of the clock signal and the input signal connection terminal of the standard buffer unit. The power supply pin also includes at least one second power supply pin, the power supply voltage input to the second power supply pin is not equal to the voltage input to the first power supply pin; the second power supply pin is arranged on the same layer as the first power supply pin. The voltage converter unit includes a first power connection terminal, a second power connection terminal, and a ground terminal; the first power connection terminal of the voltage converter unit is electrically connected to the first power trace network, and the second power connection terminal of the voltage converter unit is electrically connected to the second power pin through at least one of a trace and a connection hole; the ground terminal of the voltage converter unit is electrically connected to the ground trace network; the clock buffer module is a cross-power island type clock buffer module.

[0011] Optionally, the layout structure of the clock buffer module further includes at least one power switch unit, wherein the at least one power switch unit is located on at least one side of the standard buffer unit in the layout; The power supply pin also includes at least one auxiliary power supply pin, which is located on the same metal layer as the first power supply pin; In this configuration, the first end of each power switch unit is electrically connected to the first power supply pin via the first power supply routing network or directly to the first power supply pin; the second end of each power switch unit is electrically connected to the first power supply connection terminal of the standard buffer unit via the auxiliary power supply pin; the control end of each power switch unit is electrically connected to the control signal line; and the clock buffer module is a turn-off type clock buffer module.

[0012] Optionally, the power connection terminal of the standard buffer unit is located on the first metal layer M1, and the signal connection terminal of the standard buffer unit is located on the second metal layer M2; the second metal layer M2 is located on one side of the first metal layer M1. The power supply pin is located on the eleventh metal layer M11, and the signal pin is located on the twelfth metal layer M12; the eleventh metal layer M11 is located on the side of the second metal layer M2 away from the first metal layer M1; the twelfth metal layer M12 is located on the side of the eleventh metal layer M11 away from the first metal layer M1.

[0013] According to another aspect of the present invention, a design method for a clock buffer module is provided, comprising: Obtain a standard buffer unit and multiple functional element units from the process library, and complete the layout of the standard buffer unit and the multiple functional element units; wherein, the multiple functional element units include at least one embedded coupling capacitor unit and at least one embedded charge discharge unit; the multiple functional element units are integrated and arranged in the layout in a manner surrounding the standard buffer unit; The clock buffer module is configured with signal pins and power pins to achieve a modular physical implementation of the standard buffer unit; wherein the signal pins and power pins are located on different preset high-layer metal layers; the signal connection terminals and power connection terminals of the standard buffer unit are electrically connected to the signal pins and power pins respectively through the internal connection holes of the clock buffer module. Based on the results of the modular physical implementation, an approval model corresponding to the clock buffer module is established. The approval model includes at least an RC parameter file and a circuit netlist. During the chip signing stage, the signing model is read in, and the clock buffer module is treated as a whole unit to perform collaborative signing verification of timing, power consumption, or signal integrity with other functional modules of the chip in the whole chip environment.

[0014] Optionally, before retrieving multiple functional element units from the process library, the following steps are also included: Based on the highest clock frequency of the clock buffer module in the target application scenario, determine the maximum RDL metal line length that it can drive, and calculate the required number of coupling capacitor units and the number of charge discharge units based on the maximum RDL metal line length.

[0015] Optionally, the design method of the clock buffer module further includes: Obtain a voltage converter unit from the process library and arrange the voltage converter unit on one side of the standard buffer unit, and arrange the voltage converter unit on the coupling path between the signal input pin of the clock signal and the input signal connection terminal of the standard buffer unit; Alternatively, at least one power switch unit can be obtained from the process library and the at least one power switch unit can be arranged on at least one side of the standard buffer unit. The first end of the power switch unit is electrically connected to the first power supply pin, the second end of the power switch unit is electrically connected to the first power supply connection terminal of the standard buffer unit through the auxiliary power supply pin, and the control end of the power switch unit is electrically connected to the control signal line.

[0016] According to another aspect of the present invention, a system-on-a-chip is provided, including a clock buffer device, wherein the clock buffer device is arranged according to the layout structure of a clock buffer module according to any embodiment of the present invention.

[0017] Beneficial Effects: The technical solution provided by this invention, based on the large drive force buffer (standard buffer unit) provided by the process library, adopts a modular physical implementation approach to optimize and model the device at the device level, forming a modular device (i.e., clock buffer module). By pre-embedding as many coupling capacitor units and charge discharge units as possible around the standard buffer unit, the coupling capacitor units can improve the voltage drop problem, and the charge discharge units can improve the antenna effect problem. On this basis, the signal pins and power pins are raised from the preset low metal layer to the preset high metal layer of the standard buffer unit provided by the process library through the internal via group and winding of the module. This facilitates the electrical connection between the modular device and the metal lines in the RDL layer, greatly facilitating the construction of the clock signal of the RDL layer by the modular large drive force buffer. It improves the uncertainty of via position caused by the winding tool of EDA tool in the SOC clock winding process to complete the connection by generating new vias, thereby improving the problem of uncertain clock signal line delay in the RDL layer. There is no need to purchase custom-made high-drive-force buffers from third-party manufacturers. This solves the uncontrollable problems such as winding, voltage drop, and antenna effect caused by directly using high-drive-force devices provided in the process library. At the same time, it can also avoid the dependence on custom-made high-drive-force devices in most high-speed, long-distance, low-latency application scenarios.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the layout of each unit in a clock buffer module provided in an embodiment of the present invention; Figure 2 yes Figure 1 The layout diagram of each unit in the clock buffer module shown is shown. Figure 3 yes Figure 1 The layout diagram of each pin of the clock buffer module shown is shown. Figure 4 yes Figure 3 The layout diagram of the pins shown; Figure 5 yes Figure 1The circuit diagram of the layout structure of the clock buffer module shown is partially schematic. Figure 6 This is a schematic diagram of the layout of each unit in another clock buffer module provided in an embodiment of the present invention; Figure 7 yes Figure 6 The layout diagram of each unit in the clock buffer module shown is shown. Figure 8 yes Figure 6 The layout diagram of each pin of the clock buffer module shown is shown. Figure 9 yes Figure 8 The layout diagram of the pins shown; Figure 10 yes Figure 6 The circuit diagram of the layout structure of the clock buffer module shown is partially schematic. Figure 11 This is a schematic diagram of the layout of each unit in another clock buffer module provided in an embodiment of the present invention; Figure 12 yes Figure 11 The layout diagram of each unit in the clock buffer module shown is shown. Figure 13 yes Figure 11 The layout diagram of each pin of the clock buffer module shown is shown. Figure 14 yes Figure 13 The layout diagram of the pins shown; Figure 15 yes Figure 11 The circuit diagram of the layout structure of the clock buffer module shown is partially schematic. Figure 16 This is a flowchart of a design method for a clock buffer module provided in an embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] This invention provides a layout structure for a clock buffer module, including: Standard buffer unit; Multiple functional element units, each including at least one embedded coupling capacitor unit and at least one embedded charge discharge unit; wherein, the multiple functional element units are integrated in the layout in a manner surrounding a standard buffer unit; Boundary units are located at the edge regions of at least one side of the layout structure; The signal pins and power pins are located on different preset high-level metal layers; the standard buffer unit includes signal connection terminals and power connection terminals, which are located on different preset low-level metal layers; the signal connection terminals and power connection terminals are electrically connected to the signal pins and power pins respectively through the internal connection holes of the modular clock buffer.

[0024] The technical solution provided by this invention, based on the large drive force buffer (standard buffer unit) provided by the process library, adopts a modular physical implementation approach to optimize and model the device at the device level, forming a modular device (i.e., a clock buffer module). By pre-embedding as many coupling capacitor units and charge discharge units as possible around the standard buffer unit, the coupling capacitor units can improve the voltage drop problem, and the charge discharge units can improve the antenna effect problem. On this basis, the signal pins and power pins are raised from the preset low metal layer to the preset high metal layer of the standard buffer unit provided by the process library through the internal via group and winding, which facilitates the electrical connection between the modular device and the metal lines in the RDL layer. This greatly facilitates the construction of the clock signal in the RDL layer by the modular large drive force buffer, and improves the uncertainty of via position caused by the creation of new vias to complete the connection during the SOC clock winding process using EDA tools, thereby improving the problem of uncertain clock signal line delay in the RDL layer. There is no need to purchase custom-made high-drive-force buffers from third-party manufacturers. This solves the uncontrollable problems such as winding, voltage drop, and antenna effect caused by directly using high-drive-force devices provided in the process library. At the same time, it can also avoid the dependence on custom-made high-drive-force devices in most high-speed, long-distance, low-latency application scenarios.

[0025] The above are the core inventive points of this invention. The layout structure of the clock buffer module will be described in detail below with reference to the accompanying drawings.

[0026] refer to Figures 1-2 The standard buffer unit region Q10 is the region where the standard buffer unit 10 is located in the layout; the coupling capacitor unit region Q20 is the region where the coupling capacitor unit 20 is located in the layout; each coupling capacitor unit region Q20 may include one or more coupling capacitor units 20; the charge discharge unit region Q30 is the region where the charge discharge unit 30 is located in the layout, and each charge discharge unit region Q30 may include one or more charge discharge units 30. The boundary unit region Q40 is the region where the boundary unit is located in the layout. In this embodiment of the invention, multiple coupling capacitor units 20 are integrated and arranged in the layout in a manner surrounding the standard buffer unit 10, and multiple charge discharge units 30 are arranged between the standard buffer unit region Q10 and the coupling capacitor unit region Q20 on one side.

[0027] The standard buffer unit 10, coupling capacitor unit 20, and charge discharge unit 30 are all basic units included in the process design kit (PDK). The PDK contains design rules, standard cell libraries, device SPICE models, and physical verification rule files for the target process node, provided by the chip manufacturer and widely known and used by designers in the field. During the design of the clock buffer module, as many coupling capacitor units 20 and charge discharge units 30 as possible are configured around the standard buffer unit 10 to ensure high-speed, long-distance clock signal transmission built with this modular device. In SOC sign-off, this reduces the probability of violations such as voltage drop and antenna effects. The charge discharge unit 30 can be an inverted diode. In this embodiment, boundary units are located at the edge regions on opposite sides of the layout structure. These boundary units are dedicated physical fill units formed at the ends of standard cell rows and / or the edges of functional circuit modules. These units do not contain logic circuit functions; their main purpose is to meet the physical design rules of integrated circuit manufacturing, ensuring the uniformity and reliability of the manufacturing process, thereby improving chip yield.

[0028] Further reference Figure 3 and Figure 4 The clock buffer module has signal pins including a clock signal input pin 61 and a clock signal output pin 62. The standard buffer unit 10 has signal connection terminals including an input signal connection terminal and an output signal connection terminal. The input signal connection terminal is electrically connected to the signal input pin 61 through a first connection hole 611 inside the clock buffer module, and the output signal connection terminal is electrically connected to the signal output pin 62 through a second connection hole 621 inside the clock buffer module. The metal layer containing the signal input pin 61 and the signal output pin 62 is a redistributed metal layer, allowing the modular device to be seamlessly connected to the metal lines in the RDL layer, further facilitating the construction of clock signals for the RDL layer using the modular high-drive-force buffer. The metal layers containing the signal input pin 61 and the signal output pin 62 can be the same or different, depending on actual needs.

[0029] Please continue to refer to this. Figure 3 and Figure 4 and combined Figure 5 Optionally, the power supply pins include at least one first power supply pin 51 and at least one ground pin 53; the first power supply pin 51 is electrically connected to the first power supply trace network inside the clock buffer module, and the ground pin 53 is electrically connected to the ground trace network inside the clock buffer module. The first power supply connection terminal of the standard buffer unit 10 is electrically connected to the first power supply routing network; the grounding terminal of the standard buffer unit 10 is electrically connected to the grounding routing network. The charge discharge unit 30 includes an inverted diode; the first end of the diode is electrically connected to the input signal connection terminal of the standard buffer unit 10; and the second end of the diode is electrically connected to the grounding network.

[0030] Specifically, the clock buffer module is integrated inside the chip and is used to receive the original clock signal and drive and shape it to generate a low-jitter, high-drive-capability global or local clock signal, which is then distributed to various timing units within the chip. The clock buffer module has a dedicated power supply pin group for connecting to a stable power supply voltage. This power supply pin group includes: at least one first power supply pin 51 for receiving a first power supply voltage VDD; and at least one ground pin 53 for receiving a ground voltage VSS. The power supply network inside the module is a tree-like or mesh structure to ensure power supply uniformity. The first power supply pin 51 is electrically connected to a first power supply trace network formed inside the module. This first power supply trace network consists of multiple layers of metal wiring and is distributed around the clock buffer circuit, providing it with the first power supply voltage VDD. The ground pin 53 is electrically connected to a ground trace network formed inside the module. This ground trace network also consists of multiple layers of metal wiring and provides the clock buffer circuit with a ground voltage VSS. Therefore, the first power supply trace network can be understood as an interconnected metal network within the clock buffer module for distributing the first power supply voltage VDD. It is used to transmit the first power supply voltage VDD from the pin point to every device within the module that needs this voltage. The ground trace network can be understood as an interconnected metal network within the clock buffer module for distributing the ground voltage VSS. It is used to transmit the ground voltage from the pin point to every device within the module that needs this voltage.

[0031] Figures 1-5 In the structure shown, the clock buffer module is a conventional type, based on the standard buffer unit 10 with high drive force (e.g., X24 and above) provided by the process library. It is configured with coupling capacitor unit 20 and charge discharge unit 30 to meet application requirements, ensuring that the high-speed, long-distance transmission clock signal built with this modular device will not exhibit voltage drop or antenna effect violations during SOC approval. Furthermore, this modular device raises the signal and power pins from the preset low metal layer to the preset high metal layer of the standard buffer unit 10 through internal vias and wiring. This facilitates the electrical connection between the modular device and the metal lines in the RDL, greatly simplifying the construction of clock signals for the RDL layer using the modular high drive force buffer. It also improves upon the problem of uncertain clock signal line delays in the RDL layer caused by uncertain via positions during SOC clock winding using EDA tools.

[0032] Optionally, in another embodiment of this invention, the clock buffer module can be a cross-power island type clock buffer module. (See reference...) Figures 6-10 The layout of the clock buffer module also includes a voltage converter unit 50. The voltage converter unit 50 is located on one side of the standard buffer unit 10 in the layout and is positioned on the coupling path between the clock signal input pin 61 and the input signal connection terminal of the standard buffer unit 10. The voltage converter unit region Q50 is the area where the voltage converter unit 50 is located in the layout. Figure 6 An embodiment is shown where the voltage converter unit region Q50 is located between the charge discharge unit region Q30 and the standard buffer unit region Q10.

[0033] The clock buffer module's power supply pins include at least one first power supply pin 51 and at least one ground pin 53, and also include at least one second power supply pin 52. The second power supply pin 52 is used to receive a second power supply voltage VDDL. The second power supply voltage VDDL input to the second power supply pin 52 is not equal to the first power supply voltage VDD input to the first power supply pin 51. The second power supply pin 52 and the first power supply pin 51 can be arranged on the same layer. The voltage converter unit 50 includes a first power connection terminal, a second power connection terminal, and a ground terminal. The first power connection terminal of the voltage converter unit 50 is electrically connected to a first power supply network to receive a first power supply voltage VDD. The second power connection terminal of the voltage converter unit 50 is electrically connected to a second power supply pin 52 through at least one of a trace and a connection hole to receive a second power supply voltage VDDL. The ground terminal of the voltage converter unit 50 is electrically connected to a ground network to receive a ground voltage VSS.

[0034] Figures 6-10In the structure shown, based on the standard buffer unit 10 with high driving force (e.g., X24 and above) provided by the process library, coupling capacitor unit 20 and charge discharge unit 30 are configured to meet application requirements. This ensures that the high-speed, long-distance transmission clock signal built with this modular device will not exhibit violations such as voltage drop and antenna effect during SOC approval. On the other hand, this modular device raises the signal pins and power pins from the preset low metal layer to the preset high metal layer of the standard buffer unit 10 provided by the process library through internal vias and wiring. This facilitates the electrical connection between the modular device and the metal lines in the RDL, greatly simplifying the construction of the clock signal for the RDL layer using the modular high driving force buffer. It also improves the problem of uncertain RDL clock signal line delay caused by the uncertain via position resulting from the use of EDA tools to complete the connection during SOC clock wiring. Furthermore, whether it is the ground pin 53, the first power supply pin 51, or the second power supply pin 52, the power supply pin of each power supply extends outward in the direction of its respective metal layer, which facilitates the modular device to be connected to the power grid more flexibly and robustly.

[0035] Optionally, in another embodiment of this invention, the clock buffer module can be a turn-off type clock buffer module. (See reference...) Figures 11-15 The layout of the clock buffer module also includes at least one power switch unit 60, which is located on at least one side of the standard buffer unit 10 in the layout. Figure 11 The layout shown exemplarily depicts two power switch unit regions Q60, located on opposite sides of the standard buffer unit region Q10, for reference. Figure 12 One power switch unit area Q60 contains three power switch units 60, and another power switch unit area Q60 contains two power switch units 60. The power supply pins of the clock buffer module include at least one first power supply pin 51 and at least one ground pin 53, and also include at least one auxiliary power supply pin 511. The auxiliary power supply pin 511 and the first power supply pin 51 can be located on the same metal layer. The auxiliary power supply pin 511 is used to transmit the first power supply voltage VDD_SW after passing through the power switch unit 60.

[0036] In this configuration, the first terminal of each power switch unit 60 is electrically connected to the first power supply pin 51 via a first power supply trace network or directly to receive the first power supply voltage VDD. The second terminal of each power switch unit 60 is electrically connected to the first power supply connection terminal of the standard buffer unit 10 via an auxiliary power supply pin 511 to transmit the first power supply voltage VDD to the standard buffer unit 10 when the power switch unit 60 is turned on. The control terminal of each power switch unit 60 is electrically connected to the control signal line inside the module to control the on / off state of the power switch unit 60 via the control signal nsleepin on the control signal line. The signal pins of the clock buffer module may also include a control signal pin 63 for receiving the control signal nsleepin and transmitting it to the control signal line.

[0037] refer to Figures 11-15 Based on the standard buffer unit 10 with high drive force (e.g., X24 and above) provided by the process library, coupling capacitor unit 20 and charge discharge unit 30 are configured to meet application requirements. This ensures that the high-speed, long-distance transmission clock signal built with this modular device will not exhibit voltage drop or antenna effect violations during SOC approval. Furthermore, this modular device raises the signal and power pins from the preset low metal layer to the preset high metal layer of the standard buffer unit 10 through internal vias and wiring. This facilitates the electrical connection between the modular device and the metal lines in the RDL layer, greatly simplifying the construction of the RDL layer clock signal using the modular high drive force buffer. It also improves the problem of uncertain RDL clock trace delay caused by the uncertain via position resulting from the use of EDA tools for winding the SOC clock, which involves creating vias for connection. In addition, both the ground pin 53 and the first power pin 51 extend outwards in the direction of their respective metal layers, allowing the modular device to be connected to the power grid more flexibly and robustly.

[0038] Based on the above embodiments, optionally, the power connection terminal of the standard buffer unit 10 is located in the first metal layer M1, and the signal connection terminal of the standard buffer unit 10 is located in the second metal layer M2; the second metal layer M2 is located on one side of the first metal layer M1. The power supply pin is located on the eleventh metal layer M11, and the signal pin is located on the twelfth metal layer M12; the eleventh metal layer M11 is located on the side of the second metal layer M2 away from the first metal layer M1; the twelfth metal layer M12 is located on the side of the eleventh metal layer M11 away from the first metal layer M1.

[0039] Specifically, the layout structure of each type of clock buffer module raises the signal pins from the second metal layer M2 of the built-in standard buffer unit 10 to the twelfth metal layer M12, and the power pins from the first metal layer M1 of the built-in high-drive-force buffer to the eleventh metal layer M11. This allows the modular devices to be seamlessly connected to the metal traces in the RDL layer, which is beneficial for constructing the clock signal for the RDL layer using the modular high-drive-force buffer. Optionally, the control signal pin 63 can be located on the fourth metal layer M4.

[0040] In summary, the layout structure of the clock buffer module proposed in this invention can be divided into three categories based on the physical structure, according to the requirements of the application scenario; the first category is, such as... Figures 1-5 As shown, the layout structure of the clock buffer module is that of a conventional high-drive modular device; the second type, such as... Figures 6-10 As shown, the layout structure of the clock buffer module is a layout structure of a high-drive modular device across power domains; the third type, such as... Figures 11-15 As shown, the layout structure of the clock buffer module is that of a power-gating, high-drive modular device. Regardless of the type of clock buffer module layout, the required number of coupling capacitor units 20 and charge discharge units 30 can be calculated based on the maximum driveable RDL clock signal line length corresponding to the highest clock frequency in the application scenario, and then placed around the standard buffer unit 10 provided by the process. Furthermore, according to the requirements of the device in SOC clock signal construction, the pins of the process library device are raised to the RDL layer through internal vias and wiring, forming the module's pins on the RDL layer.

[0041] The present invention also provides a design method for a clock buffer module, used for designing the layout structure of the clock buffer module described in any of the above embodiments. Figure 16 This is a flowchart illustrating a design method for a clock buffer module according to an embodiment of the present invention. (Refer to...) Figure 16 The design methodology for clock buffer modules includes: S110. Obtain a standard buffer unit and multiple functional element units from the process library, and complete the layout of the standard buffer unit and multiple functional element units; wherein, the multiple functional element units include at least one pre-embedded coupling capacitor unit and at least one pre-embedded charge discharge unit; the multiple functional element units are integrated and arranged in the layout in a manner surrounding the standard buffer unit.

[0042] S120. Configure the signal pins and power pins of the clock buffer module to complete the modular physical implementation of the standard buffer unit; wherein, the signal pins and power pins are located on different preset high-layer metal layers; the signal connection terminals and power connection terminals of the standard buffer unit are electrically connected to the signal pins and power pins respectively through the internal connection holes of the clock buffer module.

[0043] S130. Based on the results of the modular physical implementation, establish an approval model corresponding to the clock buffer module. The approval model includes at least an RC parameter file and a circuit netlist.

[0044] S140. During the chip signing stage, the signing model is read in, and the clock buffer module is treated as a whole unit. It is then used in conjunction with other functional modules of the chip to perform timing, power consumption, or signal integrity collaborative signing verification in the whole chip environment.

[0045] Specifically, a standard high-drive-force buffer unit is provided, and the standard high-drive-force buffer unit is physically implemented in a modular manner, including device-level optimized layout and routing around it to form an integrated modular buffer device. In this embodiment of the invention, EDA tools can be used to complete the layout of the standard buffer unit, at least one coupling capacitor unit, and at least one charge discharge unit. The multiple functional element units include at least one embedded coupling capacitor unit and at least one embedded charge discharge unit; the multiple functional element units are integrated in the layout in a manner surrounding the standard buffer unit. The signal pins and power pins of the clock buffer module layout structure are located on different preset high-layer metal layers; the signal connection terminals and power connection terminals of the standard buffer unit are electrically connected to the signal pins and power pins respectively through internal connection holes of the clock buffer module.

[0046] In the layout and implementation of the top-level clock signal transmission network of a System-on-a-Chip (SoC), clock buffer modules are invoked and instantiated in a manner similar to standard cells. For example, when it is necessary to transmit the clock signal CLK from point A on the chip to point B at a remote location, a clock buffer module (e.g., named TMAC_BUF24) can be used to construct this path through a multi-level driver structure. Its specific circuit connections are shown in the following netlist: module CLK_spine (CLK_from_A,CLK_to_B); input CLK_from_A; output CLK_to_B; TMAC_BUF24 CLK_spine_buf1(.in(CLK_from_A),.out(CLK_from_A_buf1)); TMAC_BUF24 CLK_spine_buf2(.in(CLK_from_A_buf1),.out(CLK_from_A_buf2)); TMAC_BUF24 CLK_spine_buf3(.in(CLK_from_A_buf2),.out(CLK_to_B)); endmodule; The above netlist can be understood as: Define a module named CLK_spine. It has two ports: CLK_from_A (input) and CLK_to_B (output).

[0047] Declare CLK_from_A as an input port; the external clock signal is passed into the module from here.

[0048] Declare CLK_to_B as the output port; the processed clock signal is sent out of the module from here.

[0049] Instantiate the first buffer (i.e., the clock buffer module), named CLK_spine_buf1, of type TMAC_BUF24. Its input (in) is connected to the external input CLK_from_A, and its output (out) generates an intermediate signal CLK_from_A_buf1.

[0050] Instantiate a second buffer CLK_spine_buf2 (i.e., another clock buffer module). It takes the output of the first buffer (CLK_from_A_buf1) as input, amplifies it again, and generates a second intermediate signal CLK_from_A_buf2.

[0051] Instantiate a third buffer CLK_spine_buf3 (another clock buffer module). It takes the output of the second buffer as input, performs a third amplification, and sends the final output directly to the module's output port CLK_to_B.

[0052] Module definition complete.

[0053] Since this modular device (clock buffer module) does not undergo transistor-level (SPICE) simulation or traditional process library characterization, its RC parasitic parameter information needs to be extracted during the timing verification stage and input into the timing verification tool along with the module's netlist. Based on this data, the timing verification tool will directly calculate key timing information such as signal transmission delay and output slope of the modular high-drive-force buffer under specific load conditions, thereby completing the timing verification of the entire chip.

[0054] The technical solution provided in this invention utilizes a modular physical implementation approach on the high-drive-force buffer provided in the process library to perform device-level optimization and modeling, forming a modular device. This clock buffer module is used to construct a path for high-speed, long-distance, low-latency clock signal transmission. During the approval stage, the RC file and netlist corresponding to this clock buffer module are read in for approval, equivalent to the approval process for other functional modules in the full-chip environment. The layout structure of the clock buffer module proposed in this invention, and the scheme of applying this layout structure to chip physical design and approval, can completely solve many uncontrollable problems such as wiring, voltage drop, and antenna effects caused by directly using the high-drive-force devices provided in the process library. At the same time, it can also avoid the dependence on customized high-drive-force devices in most high-speed, long-distance, low-latency application scenarios.

[0055] Optionally, before retrieving multiple functional element units from the process library, the following steps are also included: Based on the highest clock frequency of the clock buffer module in the target application scenario, the maximum RDL metal line length it can drive is determined. Then, based on this maximum RDL metal line length, the required number of coupling capacitor units and charge discharge units are calculated. This allows for the configuration of coupling capacitor units and charge discharge units to meet application requirements, ensuring that high-speed, long-distance clock signal transmission built with this modular device will not exhibit voltage drop or antenna effect violations during SOC approval.

[0056] Optionally, the design method for the clock buffer module is characterized by further comprising: By acquiring voltage converter units from the technology library and placing them on one side of a standard buffer unit, and positioning them on the coupling path between the clock signal input pin and the input signal connection terminal of the standard buffer unit, a cross-power island type clock buffer module can be constructed.

[0057] Alternatively, at least one power switch unit can be obtained from a process library and positioned on at least one side of a standard buffer unit. The first end of the power switch unit is electrically connected to a first power supply pin, and the second end of the power switch unit is electrically connected to the first power supply terminal of the standard buffer unit via an auxiliary power supply pin. The control end of the power switch unit is electrically connected to a control signal line. This constructs a turn-off type clock buffer module.

[0058] This invention also provides a system-on-a-chip, including a clock buffer device, wherein the clock buffer device is configured according to the layout structure of the clock buffer module described in any embodiment of this invention.

[0059] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A layout structure for a clock buffer module, characterized in that, include; Standard buffer unit; Multiple functional element units, each including at least one embedded coupling capacitor unit and at least one embedded charge discharge unit; wherein, the multiple functional element units are integrated in the layout in a manner surrounding the standard buffer unit; Boundary units are located at the edge regions of at least one side of the layout structure; The signal pins and power pins are located on different preset high-layer metal layers; wherein, the standard buffer unit includes signal connection terminals and power connection terminals, which are located on different preset low-layer metal layers; the signal connection terminals and the power connection terminals are electrically connected to the signal pins and the power pins respectively through the internal connection holes of the modular clock buffer; The signal pins include a clock signal input pin and a clock signal output pin; the signal connection terminals of the standard buffer unit include a clock signal input connection terminal and an output signal connection terminal. The input signal connection terminal is electrically connected to the signal input pin through a first connection hole inside the clock buffer module, and the output signal connection terminal is electrically connected to the signal output pin through a second connection hole inside the clock buffer module; wherein, the metal layer on which the signal input pin and the signal output pin are located is a redistributed metal layer; The power supply pin includes at least one first power supply pin and at least one ground pin; the first power supply pin is electrically connected to a first power supply trace network inside the clock buffer module, and the ground pin is electrically connected to a ground trace network inside the clock buffer module. The first power supply connection terminal of the standard buffer unit is electrically connected to the first power supply routing network; the grounding terminal of the standard buffer unit is electrically connected to the grounding routing network. The charge discharge unit includes an inverted diode; the first end of the diode is electrically connected to the input signal connection terminal of the standard buffer unit; and the second end of the diode is electrically connected to the grounding network.

2. The layout structure of the clock buffer module according to claim 1, characterized in that, It also includes a voltage converter unit, which is located on one side of the standard buffer unit in the layout and is disposed on the coupling path between the signal input pin of the clock signal and the input signal connection terminal of the standard buffer unit; The power supply pin also includes at least one second power supply pin, the power supply voltage input to the second power supply pin is not equal to the voltage input to the first power supply pin; the second power supply pin is arranged on the same layer as the first power supply pin. The voltage converter unit includes a first power connection terminal, a second power connection terminal, and a ground terminal; the first power connection terminal of the voltage converter unit is electrically connected to the first power trace network, and the second power connection terminal of the voltage converter unit is electrically connected to the second power pin through at least one of a trace and a connection hole; the ground terminal of the voltage converter unit is electrically connected to the ground trace network; the clock buffer module is a cross-power island type clock buffer module.

3. The layout structure of the clock buffer module according to claim 2, characterized in that, It also includes at least one power switch unit, which is located on at least one side of the standard buffer unit in the layout; The power supply pin also includes at least one auxiliary power supply pin, which is located on the same metal layer as the first power supply pin; In this configuration, the first end of each power switch unit is electrically connected to the first power supply pin via the first power supply routing network or directly to the first power supply pin; the second end of each power switch unit is electrically connected to the first power supply connection terminal of the standard buffer unit via the auxiliary power supply pin; the control end of each power switch unit is electrically connected to the control signal line; and the clock buffer module is a turn-off type clock buffer module.

4. The layout structure of the clock buffer module according to any one of claims 1 to 3, characterized in that, The power connection terminal of the standard buffer unit is located on the first metal layer M1, and the signal connection terminal of the standard buffer unit is located on the second metal layer M2; the second metal layer M2 is located on one side of the first metal layer M1. The power supply pin is located on the eleventh metal layer M11, and the signal pin is located on the twelfth metal layer M12; the eleventh metal layer M11 is located on the side of the second metal layer M2 away from the first metal layer M1; the twelfth metal layer M12 is located on the side of the eleventh metal layer M11 away from the first metal layer M1.

5. A design method for a clock buffer module, characterized in that, include: Obtain a standard buffer unit and multiple functional element units from the process library, and complete the layout of the standard buffer unit and the multiple functional element units; wherein, the multiple functional element units include at least one embedded coupling capacitor unit and at least one embedded charge discharge unit; the multiple functional element units are integrated and arranged in the layout in a manner surrounding the standard buffer unit; The clock buffer module is configured with signal pins and power pins to achieve a modular physical implementation of the standard buffer unit; wherein the signal pins and power pins are located on different preset high-layer metal layers; the signal connection terminals and power connection terminals of the standard buffer unit are electrically connected to the signal pins and power pins respectively through the internal connection holes of the clock buffer module. Based on the results of the modular physical implementation, an approval model corresponding to the clock buffer module is established. The approval model includes at least an RC parameter file and a circuit netlist. During the chip signing stage, the signing model is read in, and the clock buffer module is treated as a whole unit to perform collaborative signing verification of timing, power consumption, or signal integrity with other functional modules of the chip in the whole chip environment.

6. The design method of the clock buffer module according to claim 5, characterized in that, Before retrieving multiple functional component units from the process library, the following steps are also included: Based on the highest clock frequency of the clock buffer module in the target application scenario, determine the maximum RDL metal line length that it can drive, and calculate the required number of coupling capacitor units and the number of charge discharge units based on the maximum RDL metal line length.

7. The design method of the clock buffer module according to claim 5, characterized in that, Also includes: Obtain a voltage converter unit from the process library and arrange the voltage converter unit on one side of the standard buffer unit, and arrange the voltage converter unit on the coupling path between the signal input pin of the clock signal and the input signal connection terminal of the standard buffer unit; Alternatively, at least one power switch unit can be obtained from the process library and the at least one power switch unit can be arranged on at least one side of the standard buffer unit. The first end of the power switch unit is electrically connected to the first power supply pin, the second end of the power switch unit is electrically connected to the first power supply connection terminal of the standard buffer unit through the auxiliary power supply pin, and the control end of the power switch unit is electrically connected to the control signal line.

8. A system-on-a-chip, characterized in that, It includes a clock buffer device, which is configured according to the layout structure of any one of the clock buffer modules described in claims 1-4.

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