Training acceleration system, training acceleration method, and electronic device

Abstract

The application discloses a kind of training acceleration system, training acceleration method and electronic equipment, especially related to acceleration calculation technical field, including external storage module and acceleration module, acceleration module includes processing module and control module, control module includes storage protocol controller, on-chip storage module and neural network accelerator;External storage module stores training associated data;Processing module issues the training task parameter of neural network to control module;Storage protocol controller generates read instruction for external storage module according to training task parameter, and reads target data from training associated data according to the logical block address specified in read instruction;On-chip storage module stores target data;Neural network accelerator reads target data, and trains neural network based on target data, can solve the problem that data transmission delay is high in prior art, resulting in low training efficiency, to reduce the technical effect of data transmission delay, improve training efficiency.

Description

Technical Field

[0001] This application relates to the field of accelerated computing technology, and in particular to a training acceleration system, training acceleration method and electronic device. Background Technology

[0002] In related graph neural network training acceleration solutions, the central processing unit (CPU) or graphics processing unit (GPU) architecture is usually relied upon. However, the parallel computing capability of CPU is limited and it is difficult to handle the efficient processing of terabyte-level graph data. Although GPU has certain parallel advantages, during data transmission, it is necessary to realize the data interaction between external storage and computing unit through system memory transfer, which involves multiple data transfers, resulting in high data transmission latency and high power consumption, thus leading to low training efficiency. Summary of the Invention

[0003] This application provides a training acceleration system, training acceleration method, and electronic device to at least solve the problem of low training efficiency caused by high data transmission latency and high power consumption in related technologies.

[0004] This application provides a training acceleration system, including at least one external storage module and an acceleration module. The acceleration module is connected to the external storage module via a bus. The acceleration module includes a processing module and a control module. The control module includes a storage protocol controller, an on-chip storage module, and a neural network accelerator. The external storage module is configured to store training association data using logical block addresses; The processing module is configured to initialize the external storage module and send the training task parameters of the neural network to the control module. The storage protocol controller is configured to generate read instructions for the external storage module based on the training task parameters, and to read the target data from the training associated data of the external storage module through direct memory access based on the logical block address specified in the read instructions. The on-chip storage module is configured to store target data read from an external storage module; The neural network accelerator is configured to read target data from an on-chip storage module and train the neural network based on the target data.

[0005] This application also provides a training acceleration method applicable to any training acceleration system, including: The external storage module is initialized and configured, and the training task parameters of the neural network are sent to the control module. The external storage module stores the training-related data in the form of logical block addresses. Based on the training task parameters, a read instruction for the external storage module is generated, and the target data is read from the training associated data of the external storage module through direct memory access according to the logical block address specified in the read instruction. The target data read from the external storage module is stored in the on-chip storage module of the control module; The target data is read from the on-chip storage module, and the neural network is trained based on the target data.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above methods.

[0007] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above methods.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above methods.

[0009] The training acceleration system provided in this application includes at least one external storage module and an acceleration module. The acceleration module is connected to the external storage module via a bus. The acceleration module includes a processing module and a control module. The control module includes a storage protocol controller, an on-chip storage module, and a neural network accelerator. The external storage module is configured to store training-related data in logical block address format. The processing module is configured to initialize the external storage module and send training task parameters of the neural network to the control module. The storage protocol controller is configured to generate read instructions for the external storage module according to the training task parameters, and read target data from the training-related data of the external storage module through direct memory access according to the logical block address specified in the read instructions. The on-chip storage module is configured to store the target data read from the external storage module. The neural network accelerator is configured to read the target data from the on-chip storage module and train the neural network based on the target data. This system can solve the problem of high data transmission latency and low training efficiency in the prior art, and achieve the technical effect of reducing data transmission latency and improving training efficiency. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a training acceleration system provided in an embodiment of this application; Figure 2 This is a schematic diagram of a neural network accelerator provided in an embodiment of this application; Figure 3 A schematic diagram of yet another training acceleration system provided in an embodiment of this application; Figure 4 A flowchart illustrating a training acceleration method provided in an embodiment of this application; Figure 5 This is a flowchart illustrating another training acceleration method provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0013] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] The training acceleration system provided in this disclosure is suitable for application scenarios requiring vertex classification, link prediction, or graph classification on large-scale graphs, including social network analysis (such as user interest prediction and community discovery), academic citation networks (such as paper topic classification and influence prediction), recommendation systems (such as collaborative filtering on user-item bipartite graphs), and knowledge graph embedding (such as entity relationship reasoning). It is particularly suitable for deployment in edge data centers or power-constrained environments, such as real-time graph analysis at base stations and anomaly detection in the Industrial Internet of Things.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] Figure 1 This is a schematic diagram of a training acceleration system provided in an embodiment of this application.

[0017] like Figure 1As shown, the training acceleration system includes at least one external storage module and an acceleration module. The acceleration module is connected to the external storage module via a bus. The acceleration module includes a processing module and a control module. The control module includes a storage protocol controller, an on-chip storage module, and a neural network accelerator. The external storage module is configured to store training association data using logical block addresses; The processing module is configured to initialize the external storage module and send the training task parameters of the neural network to the control module. The storage protocol controller is configured to generate read instructions for the external storage module based on the training task parameters, and to read the target data from the training associated data of the external storage module through direct memory access based on the logical block address specified in the read instructions. The on-chip storage module is configured to store target data read from an external storage module; The neural network accelerator is configured to read target data from an on-chip storage module and train the neural network based on the target data.

[0018] In some embodiments, the external storage module refers to a hardware device used for persistently storing the training association data required for training graph neural networks. In this application, it can be a non-volatile memory express solid state drive (NVMe SSD). The data is organized using logical block addressing (LBA) without a file system, which can avoid the latency overhead caused by file system parsing and adapt to the high-speed data reading requirements. Here, LBA is the addressing unit of data in the external storage module, dividing the storage area into contiguous logical blocks. Each logical block corresponds to a unique LBA address, and the storage location of graph data can be accurately located through LBA.

[0019] In some embodiments, the acceleration module can be a Field Programmable Gate Array (FPGA) accelerator card, used to undertake graph neural network training. The processing module, i.e., the processing system (PS), is a processor unit integrated within the FPGA accelerator card. It runs extremely simplified control logic, does not participate in training data computation, and is only responsible for external storage module initialization, training task parameter distribution, and training status monitoring. The control module (Programmable Logic, PL) is a reconfigurable hardware logic area within the FPGA accelerator card. It implements core functional units such as the storage protocol controller, on-chip storage module, and neural network accelerator through a hardware description language (Verilog / VHDL). The neural network accelerator can be a graph neural network accelerator or a text neural network accelerator, etc.

[0020] In some embodiments, the bus in this application refers to a high-speed data transmission link connecting the acceleration module and the external storage module. Specifically, it can be a high-speed serial computer extended bus standard (Peripheral Component Interconnect Express, PCIe) 4.0 / 5.0 bus, which can provide ultra-high bandwidth, such as PCIe 4.0 x16 up to 32GB / s, to meet the transmission requirements of large-scale graph data.

[0021] In some embodiments, the storage protocol controller is a hardware protocol IP core on the PL side, such as an NVMe controller IP, which conforms to the NVMe protocol specification and is responsible for parsing training task parameters, generating data read instructions, and coordinating the direct memory access module to complete data transmission.

[0022] In some embodiments, the on-chip storage module is a hierarchical cache unit on the PL side, used to cache graph data read from the external storage module to shorten the access latency of the neural network accelerator, and the neural network accelerator is a dedicated hardware acceleration unit on the PL side.

[0023] In some embodiments, the training association data may include at least a graph dataset, a trained graph neural network model file, and intermediate files generated during training. The graph dataset is the source of input data for training the graph neural network and includes graph topology data, such as the connection relationships between vertices, such as adjacency lists, and vertex feature data, such as the attribute information of each vertex.

[0024] In some embodiments, initialization configuration refers to the parameter configuration process for external storage modules and related links before training starts, including but not limited to identifying NVMe SSD devices, creating Admin / I / O queues, configuring PCIe link parameters, and establishing a mapping relationship between LBA and on-chip storage physical addresses.

[0025] In some embodiments, the training task parameters are control parameters that guide the training of the graph neural network, including at least model structure parameters such as the number of layers and feature dimensions, training control parameters such as batch size, sampling strategy, convergence threshold, and data localization parameters such as the target data LBA range. The target data is a subset of graph data required for the current batch during training, which is selected and read by the storage protocol controller from the training associated data of the external storage module according to the training task parameters, and may include the graph topology data and vertex feature data of the corresponding batch.

[0026] In some embodiments, the read command is an I / O command generated by the storage protocol controller that conforms to the NVMe protocol specification and includes information such as the LBA address range of the target data, the data read length, and the transmission channel identifier.

[0027] In some embodiments, by employing Direct Memory Access (DMA), data transfer between the external storage module and the on-chip storage module can be completed directly by the DMA module, without the need for a processing module, thus achieving zero-copy transfer.

[0028] In some embodiments, the external storage module can be initialized by running a bare-metal program. This involves directly accessing the NVMe SSD's controller registers through the PCIe configuration space to sequentially enumerate devices, read device capabilities (such as supported PCIe versions, maximum queue depth, creating one Admin queue and multiple I / O queues with a queue depth of 1024), enable the controller, and wait for it to become ready, thus meeting lightweight, low-latency initialization requirements. Alternatively, a lightweight RTOS can be used for initialization. For example, the processing module can run a lightweight real-time operating system like FreeRTOS, issuing initialization commands through a packaged NVMe driver, supporting batch initialization of multiple NVMe SSDs. Furthermore, before training, initialization parameters, such as queue configuration and LBA mappings, can be written to a designated area of ​​the on-chip storage via a host computer. After power-on, the processing module directly reads these parameters to complete initialization, reducing initialization command interaction overhead and improving startup speed.

[0029] In some embodiments, neural network training parameters can be sent to the control module via the AXI Lite interface. For example, the processing module generates and writes the training parameters one by one into the configuration register group on the PL side through the AXI Lite low-speed control bus inside the FPGA. Each parameter corresponds to an independent register address, and the PL-side module obtains the parameters by reading the registers. Alternatively, neural network training parameters can be sent to the control module in batches via DMA. When there are many training parameters, the processing module packages the parameters into parameter packets and stores them in the on-chip high-bandwidth memory (HBM). The parameter packets are then transferred in batches to the parameter buffer on the PL side via the DMA module, and the PL-side state machine parses the parameter packets, improving the transmission efficiency of large batches of parameters. Neural network training parameters can also be sent to the control module via interrupt triggering. For example, after the processing module completes initialization, it triggers an interrupt to notify the PL side to prepare to receive parameters. After responding to the interrupt, the PL side coordinates with the processing module through a handshake signal to complete the byte-by-byte / word-by-word transmission of parameters, ensuring the reliability of parameter transmission.

[0030] In some embodiments, based on the training task parameters, a hardware-based protocol stack can be used to generate read instructions for external storage modules. For example, the NVMe hardware protocol stack IP core on the PL side can directly parse the LBA range and read length in the training task parameters, fill the read instruction fields according to the NVMe 1.4 protocol specification, such as opcode 0x02, LBA address, transmission length, and Physical Region Page (PRP) pointer, generate a compliant read instruction, and write it to the I / O submission queue.

[0031] In some embodiments, fixed storage areas can be pre-defined for graph topology data, vertex feature data, and intermediate calculation results, and data can be written to fixed addresses and read by the neural network accelerator at fixed addresses; alternatively, the on-chip storage controller can dynamically allocate idle storage resources according to the data volume, allocate temporary storage blocks for each batch of target data, and release the resources after training is completed.

[0032] For example, after the system powers on, the processing module on the PS side runs the bare-metal initialization program. It accesses the controller registers of the two NVMe SSDs through the PCIe configuration space to complete device enumeration, read device capabilities, create one Admin queue and eight I / O queues, configure MSI-X interrupt parameters, and simultaneously establish a static mapping table between LBAs and the physical addresses of the on-chip storage modules. The processing module sends training task parameters to the configuration register on the PL side through the AXI Lite interface, including a training batch size of 256, a 2-hop neighbor sampling strategy, the LBA range of the target data, the 3-layer GCN model structure parameters, a 3×3 convolutional kernel size, and a learning rate of 0.001. The NVMe controller IP core (storage protocol controller) on the PL side parses the training task parameters, generates two read commands conforming to the NVMe 1.4 protocol, and writes them to the I / O submission queue. After the DMA module reads the read commands, it reads the target data in parallel from two SSDs through a PCIe P2P link based on the pre-stored LBA-HBM address mapping relationship. The topology data and feature data are written to different regions of the HBM respectively. After the transfer is completed, the DMA module triggers an interrupt to notify the neural network accelerator. The neural network accelerator reads the target data from on-chip storage and performs training in a pipeline manner: 32 parallel sampling processing units generate a 2-hop target subgraph (i.e., target graph data) in Compressed Sparse Row (CSR) format; the aggregation calculation module completes neighbor feature aggregation using GCN normalization mode; the bidirectional reconfigurable systolic array performs feature transformation and ReLU activation, and outputs the predicted value; the cross-entropy loss function hardware unit calculates the loss value between the predicted value and the true label; the backpropagation module calculates the gradient through chained differentiation and propagates it back along the graph structure, and finally updates the model parameters through the SGD optimization unit. After a single training iteration is completed, the PL side notifies the PS side via an interrupt, and the PS side reads the training status register; if the convergence condition is met, the PS side reports the training results to the host computer.

[0033] In some embodiments, the control module further includes a direct memory access module; The direct memory access module is configured to establish a mapping relationship between the logical block address space of the external storage module and the physical address space of the on-chip storage module; The direct memory access module is also configured to generate a bus transaction layer data packet based on the logical block address and read length in the read instruction of the external storage module, and write the received data to the physical address determined by the mapping relationship through the bus transaction layer data packet.

[0034] In some embodiments, the physical address space is the address range of physical storage units of the on-chip storage module, with each physical address corresponding to a storage unit of the on-chip storage. The mapping relationship between the logical block address space of the external storage module and the physical address space of the on-chip storage module is a mapping table or algorithm rule describing the one-to-one correspondence between the LBA of the external storage module and the physical address of the on-chip storage.

[0035] In some embodiments, the bus transaction layer data packet is a data packet conforming to the bus protocol transaction layer format, which may include address information, data payload, check information, etc. for data transmission.

[0036] In some embodiments, a static mapping table between LBAs and on-chip storage physical addresses can be pre-established by the processing module before training. This mapping table divides continuous address ranges according to graph data types (topology data / feature data), for example, mapping LBA 0x1000-0x2000 to on-chip HBM physical addresses 0x0000-0x1000. The mapping table is stored in the on-chip BRAM, and the DMA module directly obtains the address correspondence by looking up the table. Alternatively, a mapping relationship between the logical block address space of the external storage module and the physical address space of the on-chip storage module can be established based on a preset address mapping algorithm. The DMA module calculates the physical address corresponding to the LBA in real time through the hardware computing unit, such as physical address = base address + (LBA - starting LBA) × data block size, without needing to store the complete mapping table.

[0037] In some embodiments, the DMA module can be used to integrate the bus protocol hardware transaction layer IP core, directly parse the start LBA and read length in the read instruction, fill in the transaction type, address field and data length field of the data packet according to the protocol specification, and generate a standard bus transaction layer data packet. For repeated training batch read instructions, the DMA module can also be used to cache the generated bus transaction layer data packet template. Only the LBA and read length fields in the data packet need to be updated to quickly generate a new data packet, reducing protocol encapsulation overhead.

[0038] In some embodiments, the DMA module can write graph data sequentially into a continuous physical address range determined by the mapping relationship, according to the order in which the bus transaction layer data packets are received. For two different types of data, topology data and vertex feature data, the DMA module can also interleave the received two types of data into adjacent physical address ranges of on-chip storage according to computational requirements, thereby reducing the address jump overhead when the neural network accelerator reads data.

[0039] Direct memory access modules implement address mapping and bus data packet encapsulation in hardware, which can reduce instruction translation latency for data transmission.

[0040] In some embodiments, the on-chip storage module includes primary storage, secondary storage, and tertiary storage; Level 1 storage is configured to store hot data during the current computing phase; Secondary storage is configured to store prefetched data and data accessed more frequently than a preset access frequency threshold. The third-level storage is configured to store the complete data required for training.

[0041] In some embodiments, Level 1 storage is the storage tier with the fastest access speed and smallest capacity in the on-chip storage module, and can be block storage, i.e., BRAM; Level 2 storage has moderate capacity and access speed, and can be ultra-large capacity RAM, i.e., URAM; Level 3 storage is the storage tier with the largest capacity and relatively slow access speed in the on-chip storage module, and can be high bandwidth memory, i.e., HBM.

[0042] In some embodiments, hot data refers to data frequently accessed during the current computational stage of graph neural network training, such as feature aggregation in a single iteration or loss calculation, including aggregated features, model parameters, and predicted values ​​of the current batch. Prefetch data refers to graph data predicted according to the training process and to be used in subsequent computational stages, which is read in advance from external storage modules or tertiary storage to secondary storage to avoid computational units waiting for data. Data with an access frequency higher than a preset access frequency threshold can be graph structure data, which describes the connection relationships between vertices in training-related data, such as adjacency lists and edge lists. This type of data has a high access frequency and a fixed format during training. Taking graph data as an example, complete data, i.e., complete graph data, refers to all input data required for graph neural network training, including feature data of all vertices and full graph structure data, typically reaching the GB level in size.

[0043] In some embodiments, the on-chip storage controller can monitor the data access frequency in real time through hardware logic. When the number of accesses to a certain type of data in the current computation stage exceeds a preset threshold, such as 5 times / iteration, it is automatically migrated to the primary storage. After the computation stage ends, it is automatically cleared or replaced with hot data for the next stage. Alternatively, the address space of the primary storage can be fixed according to the training process, and the hot data types of the current computation stage, such as aggregated features and model weights, can be clearly defined. This type of data can be directly written to a preset address, and the computation unit reads it at a fixed address without dynamic judgment, reducing hardware complexity. Alternatively, the primary storage can be divided into two independent buffers. One buffer provides data for the current computation unit, and the other buffer synchronously receives the migration of hot data for the next stage. After the current computation ends, the two buffers switch quickly, realizing parallel computation and data preparation, further hiding data migration delay.

[0044] In some embodiments, the prefetch controller can predict the data required later based on training task parameters (such as batch size and sampling strategy) and read the prefetch data in advance from the third-level storage or external storage through the DMA module. At the same time, frequently accessed graph structure data (such as fixed adjacency lists) can be permanently stored in the second-level storage, and the computing unit can directly read it from the second-level storage when needed. Alternatively, the second-level storage can be divided into two independent partitions: a prefetch data area and a high-frequency graph structure area. The prefetch data area is dynamically updated according to the training batch, while the high-frequency graph structure area is permanently stored to avoid duplicate loading caused by the two types of data overlapping each other.

[0045] A tiered storage architecture, employing a three-tier storage model, can balance data access latency and storage capacity requirements.

[0046] In some embodiments, the neural network accelerator is a graph neural network accelerator, which includes a graph sampling module, an aggregation calculation module, a feature transformation module, a loss calculation module, and a backpropagation module.

[0047] The image sampling module is configured to read target data from the on-chip storage module and generate target image data; The aggregation calculation module is configured to perform aggregation operations on the features of the neighboring vertices of each vertex in the target graph data to generate aggregated features; The feature transformation module is configured to perform feature transformation processing on the aggregated features to obtain the predicted value; The loss calculation module is configured to determine the loss value based on the predicted value and the actual value; The backpropagation module is configured to backpropagate along the graph structure based on the gradient of the loss value and update the model parameters.

[0048] In some embodiments, the graph sampling module is a front-end data processing unit of the graph neural network accelerator, responsible for filtering local subgraphs from large-scale target data stored on-chip according to a preset strategy; the aggregation calculation module is a graph structure information integration unit, whose core is to fuse the neighbor features of each core vertex in the target graph data to generate aggregated features carrying local context information, providing effective input for subsequent feature transformation; the feature transformation module is a feature dimension transformation and nonlinear expression unit, which transforms the aggregated features to a feature space that adapts to the output dimension of the task through linear mapping (such as matrix multiplication) and nonlinear activation, and outputs the prediction results; the loss calculation module is a training error quantization unit, which calculates the difference between the predicted value and the true value through the loss function, and generates a loss index to guide parameter updates; the backpropagation module is a model parameter optimization unit, responsible for calculating the gradient of the loss value with respect to the parameters of each layer, propagating the gradient back along the graph structure and network layers and updating the parameters to achieve iterative improvement of model accuracy.

[0049] In some embodiments, the target graph data is local graph data adapted to a single training iteration, containing the topological relationships and feature data of core vertices and their associated neighbors. The aggregated features are feature vectors that fuse the information of the core vertex neighbors, which better reflect the position and association attributes of vertices in the graph structure compared to the original vertex features.

[0050] In some embodiments, the graph sampling module includes multiple parallel sampling processing units; The parallel sampling processing unit is configured to perform sampling operations on the target data in parallel according to the sampling strategy in the training task parameters, and generate target map data.

[0051] In some embodiments, 32 / 64 parallel sampling processing units can be deployed, each unit independently responsible for the traversal and filtering of neighbors for one core vertex. Neighbor search and redundant vertex deduplication are completed synchronously according to a 2-hop sampling strategy, and finally, the data is aggregated to generate CSR format target graph data. Alternatively, multiple sets of target graph data can be pre-generated by the processing module before training and stored on-chip HBM. During training, the graph sampling module directly reads the pre-stored target graph data from HBM.

[0052] In some embodiments, dedicated hardware circuits can be used to switch aggregation modes through configuration registers. For example, in GCN normalization mode, the weighted summation of neighbor features and degree normalization calculation are completed simultaneously; in SUM / MEAN mode, it is simplified to summation / mean operation; or the basic aggregation of first-level neighbor features can be performed first, and then the result can be aggregated with second-level neighbor features to gradually deepen the fusion of local structural information.

[0053] In some embodiments, the feature transformation module employs a bidirectional reconfigurable pulsating array.

[0054] In some embodiments, a 128×128 bidirectional reconfigurable pulsating array can be used, configured in matrix multiplication mode during forward propagation to achieve parallel operation of aggregated features and weight matrices; then, nonlinear processing is completed through ReLU / Sigmoid hardware activation units, and the array can dynamically adapt to matrix operations of different dimensions.

[0055] In some embodiments, loss functions such as cross-entropy and mean squared error can be used to determine the loss value between the predicted value and the true value.

[0056] By implementing a fully hardware-based modular architecture to achieve parallel processing of the entire training process, including core steps such as graph sampling and aggregation calculation, the latency of iteration can be reduced. Specifically, the latency of a single training iteration is as low as microseconds.

[0057] In some embodiments, such as Figure 2 As shown, Figure 2This is a schematic diagram of a neural network accelerator provided in an embodiment of this application, including a graph sampling engine (i.e., graph sampling module), an aggregation calculation unit (aggregation calculation module), a feature transformation module, a loss and gradient calculation unit (loss calculation module), a feature transformation unit (backward), a backpropagation engine (backpropagation module), and a gradient aggregation module (corresponding to...). Figure 2 Gradient aggregation unit), parameter updater (corresponding) Figure 2 (1) After receiving the complete data, the graph sampling engine uses sampling algorithms such as m-hop neighbor sampling to extract the neighbor subset within the m-hop range for each target vertex, thereby generating a small batch of subgraphs suitable for batch processing. The subgraphs are output in CSR format, which saves storage space and facilitates subsequent fast traversal. After the sampled subgraph data is parsed, the neighbor vertex ID sequence is extracted and sent to the gradient aggregation unit; at the same time, the neighbor vertex ID sequence is used as the key to read the neighbor vertex features in the on-chip feature cache and send them to the gradient aggregation unit. In view of the bottleneck of low concurrency of traditional CPU sampling, this application proposes a multi-stage pipeline parallel sampling architecture. This architecture is deployed An array of Parallel Sampling Units (PSUs) is used, with each PSU independently executing the complete process of neighbor reading, random sampling, and result caching, achieving spatial parallelism. This includes: ① Each PSU integrates an independent Linear Feedback Shift Register (LFSR), generating high-quality pseudo-random numbers in a single cycle, eliminating the overhead of software random function calls. For a vertex with degree , it can sample 10 neighbors with replacement, reducing the time complexity and latency to 1 cycle / sample. ② A three-level storage hierarchy is constructed: on-chip BRAM / URAM cache (2-8MB), PS-side DDR cache (1-4GB), and NVMe SSD storage (TB level). Hotspot vertices are dynamically loaded based on a prefetch decision function, as follows:

[0058] Where freq(v) represents the vertex Historical access frequency; It is the vertex The normalized degree; recency(v) represents the vertex. The reciprocal of the last access time; All of these are adjustable decay weight parameters.

[0059] ③ For the degree differences in the power-law distribution graph, a global task queue is hierarchically classified by degree. With dynamic task stealing mechanism, the load balancing factor is improved. .in, and These represent the maximum and average task loads allocated to each PSU, respectively. Vertices can be classified into low-degree vertices (e.g., ...) based on their degree. ), medium degree vertex (e.g. ) and low-degree vertices (such as The task is inserted into the global task queue according to the First In First Out (FIFO) rule. The inputs to the dynamic task stealing and allocation algorithm are Queue_L, Queue_M, and Queue_H; the states of each PSU; and the output is the vertex. The allocation results to PSUs can be obtained by establishing a vertex processing time prediction model. A global task scheduler maintains three priority queues to manage high, medium, and low-degree vertices respectively, and dynamically allocates tasks based on the real-time occupancy rate of each aggregation channel. A greedy minimum completion time strategy is used to assign tasks to the channel with the earliest predicted completion time, thus addressing the degree imbalance problem caused by the power-law distribution commonly found in real graph data. The vertex processing time prediction model... , For calibration parameters. ④ The sampling results are converted into a compressed sparse row format after sampling result collection, deduplication and merging, row pointer calculation and column index filling. Through the tree-parallel prefix sum algorithm, the latency can be reduced to O(log2B). Indicates the batch size.

[0060] By leveraging the spatial parallelism and pipeline characteristics of FPGAs, a high-speed and stable graph data stream is provided for subsequent aggregation computing units, thus solving the sampling bottleneck in the training of Graph Neural Networks (GNNs).

[0061] (2) The aggregation computation unit is used to achieve neighbor feature fusion on the graph structure. For vertices... In terms of the GNN model, the first The aggregation operation of the layer is transformed according to the aggregation mode, which can be SUM mode, MEAN mode, or GCN normalization mode. A unified, reconfigurable aggregation engine supports multiple aggregation modes, including SUM, MEAN, GCN normalization, and attention mechanisms. Deployment Several parallel aggregation channels, each containing tiered pipelined adder tree ( For maximum parallelism), each stage is equipped with A floating-point adder ( (for series), total Each adder dynamically skips unnecessary stages using a bypass selector, adapting to different numbers of neighbors. This allows it to maintain high throughput while dynamically adapting to different numbers of neighbors through the bypass selector.

[0062] The pipelined Softmax unit performs attention coefficient normalization calculation through a five-stage pipeline (Stage 1: maximum value calculation; Stage 2: shift and fetch; Stage 3: exponential summation; Stage 4: reciprocal calculation; Stage 5: multiplication), supporting parallel processing of multi-head attention. Stage 1 processes the input vector... Find the maximum value This is used for numerical stability. Phase 2 calculates for each element. Then calculate Phase 3 Calculation This can be implemented using an accumulator or a parallel tree-structured addition. Stage 4 uses the Newton-Raphson iterative inversion method (NR) for iterative calculation. The NR formula is usually as follows: If multiple heads run in parallel and each head... If they arrive at the same time, the NR unit can be deployed individually for each head or shared. Phase 5 for each Multiply get Output value.

[0063] (3) The feature transformation module is responsible for performing feature transformation operations in the GNN. This application proposes a bidirectional reconfigurable systolic array architecture to achieve unified processing of forward propagation and backward propagation on the same hardware structure. In the GNN model... During the layer forward propagation phase, the pulsating array executes... Matrix multiplication, weights Flowing from north to south in rows, input features The data flows column-wise from west to east, with partial products accumulated within each processing element (PE) and output from the south. Backpropagation requires calculating the output gradient, which in turn requires calculating the transpose of the weight matrix. Calculating the weight gradient requires performing matrix multiplication of the output gradient with the transpose of the input features.

[0064] For example, In the two-dimensional pulsating array, each PE contains an FP32 multiplier, two adders, and a mode selector. Seamless switching between forward and backward propagation is achieved by reconstructing the data flow direction. During backpropagation, weights flow column-wise from west to east for transposed access, while the output gradient flows from north to south, with some accumulated gradients output from the east side. To address the transposed access bottleneck in backpropagation, this application employs a block-based transposed storage strategy, dividing the weight matrix into 16×16 sub-blocks. Each sub-block stores data in column-major order, achieving zero-cost transposed access. When accessing a row of weights in the forward propagation, data is read across sub-blocks; when accessing a row of transposed weights in the backward propagation, column-major data can be read directly, eliminating the performance penalty of transposed access.

[0065] In terms of numerical accuracy, the activation values ​​in forward propagation are calculated using FP16 to improve throughput and reduce power consumption, while the error compensation term accumulated by FP32 is maintained to ensure the final accuracy. In contrast, the gradient calculation in backpropagation uses FP32 throughout to ensure numerical stability.

[0066] Online weights are stored in BRAM, organized in a systolic array access mode and supporting simultaneous dual-port reading for transposed access. Offline weights are stored in URAM and loaded in the background. A separate gradient accumulator region stores the weight gradients. While one buffer performs computation, another buffer receives updated parameters, and DMA loads the next batch of data in the background, achieving a triple overlap of computation, communication, and parameter updates. Under conditions where computation time and DMA transfer time are similar, this improves the overall system acceleration.

[0067] By eliminating the DDR access overhead of intermediate data through the aggregation-transformation fusion pipeline, the backpropagation operator fusion design can calculate the weight gradient and input gradient in parallel in the same data scan, which can reduce the intermediate activation storage occupation and reduce the frequency of DDR access.

[0068] (4) The loss and gradient calculation unit receives the predicted value output by the feature transformation module. and the real training labels loaded from DDR By comparing the results, the loss value is obtained. Gradient of the output layer This serves as the starting point for backpropagation.

[0069] This application employs a multi-task fusion pipeline architecture, performing loss calculation, gradient generation, and statistical information collection in parallel within a single data scan. Deployment There are multiple parallel loss calculation channels, each supporting dynamic switching between various loss functions such as cross-entropy, mean squared error, and FocalLoss. Based on the principle of automatic differentiation, the initial gradient calculation is decomposed into a three-stage pipeline, namely... Inverse programming, loss function differentiation, gradient scaling, and regularization. To address the gradient explosion / vanishing problem in deep GNN training, a dynamic gradient clipping unit is designed to monitor the gradient norm in real time.

[0070] Detected At that time, the threshold Configurable, for example, setting it to 5.0 triggers gradient clipping:

[0071] ④Maintain the latest Loss sequence of epochs Real-time calculation of the rate of change of loss:

[0072] When satisfied Furthermore, after q epochs, an early stop signal is issued to avoid overfitting.

[0073] (5) The feature transformation module undertakes the key tasks of gradient calculation and backpropagation during the backpropagation stage, mainly including: activation function gradient calculation, weight gradient calculation, and input feature gradient calculation. Among these, calculating the activation function... The derivative of the loss with respect to the output after activation is transformed into the gradient of the loss with respect to the linear output:

[0074] in, For the derivative of the activation function, when When the function is ReLU, its reciprocal can be obtained using the following formula:

[0075] By element-wise lookup comparison, the data is stored forward. By adding zero, a mask matrix is ​​generated, which implements gradient gating of the activation function.

[0076] The weight gradient is calculated for subsequent parameter updates. It is obtained by reading the input features saved in the previous layer and multiplying them with the output gradient of the current layer.

[0077] The input feature gradient is calculated and used for backpropagation to the previous layer. The output gradient is multiplied by the transpose of the weight matrix to obtain the input gradient.

[0078] (6) The backpropagation engine performs gradient distribution operations, mapping the feature gradients of the center vertex to its neighboring vertices according to the graph structure. It receives the feature gradients of the center vertex from the backpropagation output of the feature transformation module, and these gradients are streamed to the backpropagation engine through an on-chip FIFO buffer. Simultaneously, it needs to read the graph structure information generated by the graph sampling module and cached in the on-chip BRAM, including the adjacency matrix in CSR format. This includes the aggregation pattern metadata recorded by the forward aggregation unit, which contains a 2-bit encoded aggregation type identifier and pre-computed normalization coefficients. These represent the row pointer, column index, and edge weight, respectively.

[0079] A unified approach is used to handle the aforementioned different aggregation modes, with a configurable five-stage pipeline distribution engine. The first stage is responsible for reading the gradient of the central vertex. The second level queries the list of neighbors of that vertex. The third stage loads the corresponding scaling factor (reciprocal of the neighbor count, normalization factor, or attention weight) based on the pattern, and the fourth stage performs gradient scaling operations through a multiplier or divider array. The fifth stage outputs the corresponding aggregation pattern identifier. Key-value pairs, i.e., vertex ID and A 2-dimensional gradient vector. This unified architecture allows modules to dynamically switch computation paths based on 2-bit pattern identifiers, supporting multiple GNN aggregation algorithms within a single hardware framework.

[0080] The output of the backpropagation engine is a series of streams Key-value pairs, the same neighbor vertex may appear multiple times in the output stream because the neighbor may be a neighbor of multiple different center vertices at the same time, and therefore will receive gradient contributions from different center vertices.

[0081] (7) The gradient aggregation module receives the scattered gradient stream generated by the backpropagation engine, performs an accumulation operation on the multiple gradient components received by each vertex, and generates the complete vertex gradient. In forward propagation, the vertex The feature aggregates all its neighbors Information; while in backpropagation, neighboring vertices As neighbors of multiple different central vertices participating in the forward computation, it is necessary to accumulate the gradient contributions from all these central vertices. Specifically, the accumulation operation can be performed based on a hash-based distributed gradient accumulation architecture, and deployed... Each gradient is a completely independent Gradient Accumulation Unit (GAU), and each GAU manages its own hash table and accumulation logic. When a gradient record arrives, the index of the target GAU is calculated using a hash function. After the gradient is distributed to the corresponding GAU, that GAU looks up the index in its local hash table, first calculating the hash slot. If the slot is empty, a new entry is initialized. If the vertex ID in the slot matches, the gradient is accumulated directly. If a hash collision occurs, a collision resolution mechanism is initiated. For the norm of the accumulated gradient, only when the absolute value is greater than the intermediate value... The components are retained, while the rest are set to zero; the intermediate values ​​are typically set to the gradient norm. arrive The sparsified gradient is output in COO (Coordinate) format, where each non-zero element is represented as (vertex_id, feature_dim, ...). The gradient_value triples, such as the original gradient vector of vertex 42 [0.001, 0.523, -0.002, 0.891, 0.0003], are compressed into two triples (42, 1, 0.523) and (42, 3, 0.891) at a threshold of 0.01.

[0082] A configurable dual buffer is used. While buffer A processes the gradient accumulation of the current mini-batch, the gradients already completed in buffer B are being consumed by the downstream feature transformation module. At the same time, the DMA engine asynchronously writes the gradients of the previous mini-batch back to DDR. In the next cycle, the two buffers switch roles: buffer A enters a read-only state for downstream consumption, and buffer B begins to receive new gradients for accumulation, achieving continuous saturation of data transmission.

[0083] (8) The parameter updater is responsible for updating the model parameters based on gradient information, so that the loss function continues to decrease and gradually approaches the optimal solution. In traditional CPU / GPU systems, parameter updates are often constrained by memory access bottlenecks and gradient synchronization delays. This application proposes an on-chip distributed gradient accumulation and asynchronous parameter update architecture, which significantly improves update efficiency while ensuring numerical stability. It includes: The distributed gradient accumulation array (GAA) consists of P parallel accumulation units, each of which is responsible for updating a portion of the weight blocks. The gradient can be stored and calculated using FP16 during the update phase, while the weight parameters are still maintained with FP32 precision. The computation and communication are completely overlapped through computation buffer, write-back buffer, and prefetch buffer. While the current batch is being computed, the previous batch of weights is being written back to DDR, and the next batch of weights is being prefetched from NVMe SSD, which can reduce parameter update latency and improve the overall system throughput and energy efficiency.

[0084] The complete training process includes: At the start of training, the embedded processor first loads the complete graph structure data, feature matrices of all vertices, training labels, and initialized model weight parameters into DDR memory via DMA. The FPGA's weight cache then retrieves the weight parameters from DDR and completes initialization. The graph sampling module extracts a mini-batch of subgraphs from the complete graph, generating a CSR-formatted subgraph topology representation. The aggregation calculation unit, based on the subgraph's topology representation and combined with the feature vectors of corresponding neighboring vertices read from the feature cache, performs aggregation operations to calculate the aggregated features of the center vertex. The feature transformation module then reads the parameters of the current layer from the weight cache, performs fully connected transformations and nonlinear activations on the aggregated features, and obtains the transformed features. Finally, the loss calculation unit calculates the model's predicted output. The model is compared with the true label y, the loss value L is calculated, and the initial gradient is generated. The backpropagation engine receives the initial gradient from the loss unit and begins the chain rule calculation. First, the weight gradient is calculated and temporarily stored in the weight cache for upload. At the same time, the activation gradient is calculated and sent back to the feature transformation module. The backpath of the feature transformation module calculates the gradient of the aggregated features and passes it to the backpath of the aggregation unit. The aggregation unit decomposes the gradient according to the topological relationship of the forward aggregation and calculates the gradient contribution of each neighboring vertex. The gradient is reached through the back traversal of the graph processing engine to the gradient aggregation module, which sums up all gradient components received by each vertex. Finally, the complete gradients and weight gradients of all vertices are uploaded to DDR memory in batches via DMA. The parameter updater reads all gradient data uploaded from FPGA from DDR, calculates the new parameter values, writes the updated weight parameters back to DDR after calculation, and triggers the transfer of DMA to the FPGA weight cache. When the model training is completed and enters the deployment phase, the data flow only executes the forward path of sampling, graph processing, aggregation, and transformation, and directly outputs the prediction results to DDR.

[0085] In some embodiments, the target data is taken as target graph data. The target graph data includes at least graph topology data and vertex feature data. The graph topology data is stored using a hash partitioning strategy, and the vertex feature data is stored using a block partitioning strategy.

[0086] In some embodiments, graph topology data is data describing the connection relationships between vertices in the graph, usually stored in the format of adjacency list, edge list, etc., representing structural information such as the number of neighbors and connected objects of a vertex; vertex feature data is high-dimensional vector data describing the attributes of each vertex in the graph.

[0087] In some embodiments, the hash partitioning strategy calculates the partition identifier by substituting the vertex ID into a preset hash function, so that the topology data corresponding to vertices with the same identifier are stored in the same partition, thereby achieving uniform distribution and fast retrieval of topology data; the block partitioning strategy divides vertex feature data into data blocks of fixed size and stores them continuously in a specified address range of the external storage module.

[0088] In some embodiments, the vertex ID can be selected as the hash key, and the topology data can be divided into N, such as 8, independent partitions using a modulo hash function. Each partition corresponds to a continuous LBA address range of the external storage module. Before training, the processing module establishes a hash mapping table and stores it in the on-chip BRAM. The graph sampling module directly locates the topology data partition of the target vertex by looking up the table. Alternatively, a consistent hashing algorithm can be used to map the vertex ID and partition nodes to a hash ring. When adding / deleting a partition, only the mapping relationship between adjacent nodes needs to be adjusted, without reconstructing all partitions.

[0089] In some embodiments, the feature data block size can be set according to the physical page size of the external storage module. Each data block stores 32 128-dimensional vertex feature vectors, which are stored consecutively in the LBA address range of the NVMe SSD. During training, the DMA module reads multiple consecutive data blocks at once according to the number of target vertices. Alternatively, the data block size can be dynamically adjusted according to the dimension of the vertex feature vectors. For example, higher-dimensional feature vectors correspond to smaller data blocks, and lower-dimensional feature vectors correspond to larger data blocks, thereby balancing the number of data blocks and transmission efficiency.

[0090] In some embodiments, such as Figure 3 As shown, Figure 3 This is a schematic diagram of another training acceleration system provided in the embodiments of this application, which includes two parts: a Processing System (PS) and a Programmable Logic (PL). The PS side includes application management and a minimum system module, and interacts with the PL side through an AXI interface. The PL side integrates modules such as a PCIe AXI Bridge, an NVMe controller IP core, a P2P DMA, an on-chip cache, and a GNN accelerator, and is connected to an external NVMe SSD through PCIe.

[0091] like Figure 4 As shown, Figure 4 A flowchart illustrating a training acceleration method provided in this application embodiment includes: Step 401: Initialize and configure the external storage module, and send the training task parameters of the neural network to the control module. The external storage module stores the training-related data in the form of logical block addresses. Step 402: Based on the training task parameters, generate a read instruction for the external storage module, and read the target data from the training associated data of the external storage module through direct memory access according to the logical block address specified in the read instruction. Step 403: The target data read from the external storage module is stored in the on-chip storage module of the control module; Step 404: Read the target data from the on-chip storage module and train the neural network based on the target data.

[0092] It should be noted that the descriptions of the features in the above training acceleration method embodiments and the related descriptions of the aforementioned training acceleration system embodiments will not be repeated here.

[0093] In some embodiments, based on training task parameters, a read instruction for the external storage module is generated, including: Based on the training batch size and graph sampling strategy determined by the training task parameters, determine the set of target vertices to be accessed during the target training phase. Based on the target vertex set, determine the logical block address range of the corresponding vertex feature data and graph topology data stored in the external storage module; Generate read instructions for a logical block address range.

[0094] In some embodiments, the training batch size refers to the number of sample vertices used in a single training iteration of the graph neural network. For example, when the batch size is configured to 256, 256 vertices and their corresponding neighbor data are selected for computation in a single training iteration. The graph sampling strategy refers to the process of selecting target graph data from large-scale training associated data, which may include 1-hop / 2-hop neighbor sampling, random walk sampling, etc.

[0095] In some embodiments, the training task parameters are directly parsed by a dedicated state machine within the control module, and the selection and determination of the target vertex set are completed in parallel through sampling strategy logic, such as the 2-hop neighbor strategy. Alternatively, a target vertex set list can be generated in advance according to the training batch size and sampling strategy, and written into the configuration register of the control module through the AXI Lite interface, so that it can be directly read and used by the NVMe protocol controller.

[0096] In some embodiments, a static mapping table between vertex IDs and logical block addresses can be pre-established before training and stored in the on-chip BRAM. After determining the target vertex set, the corresponding logical block address range can be directly obtained by looking up the table. Based on the partitioning rules of the external storage module, such as topology data hash partitioning and feature data block partitioning, the logical block address range corresponding to the target vertex set can be calculated in real time without storing the complete mapping table.

[0097] In some embodiments, read commands can be directly generated by the NVMe hardware protocol stack within the control module, and fields such as opcode (0x02), logical block address, and transmission length can be filled according to the NVMe 1.4 specification; alternatively, multiple generated read commands can be stored in the command queue within the control module and issued sequentially by the NVMe protocol controller according to priority.

[0098] Using a hardware state machine to filter the target vertex set and map its addresses can significantly reduce instruction generation latency.

[0099] Training neural networks based on target data includes: Generate target map data based on the target data; Aggregate the features of the neighboring vertices of each vertex in the target graph data to generate aggregated features; The aggregated features are processed by feature transformation to obtain the predicted values; Determine the loss value based on the predicted value and the actual value; The model parameters are updated by backpropagating the gradient of the loss value along the graph structure.

[0100] It should be noted that the descriptions of features in the above training acceleration methods and the related descriptions of the graph sampling module, aggregation calculation module, feature transformation module, loss calculation module and backpropagation module in the graph neural network accelerator of the aforementioned training acceleration system will not be repeated here.

[0101] like Figure 5 As shown, Figure 5 A flowchart illustrating another training acceleration method provided in this application embodiment includes: Step 1, Hardware platform preparation: FPGA accelerator card is used, and the hardware configuration is as follows: quad-core ARM Cortex-A53 processor (PS side), 1968 DSP slices and 32.4 MB on-chip storage (PL side); supports 4-channel DIMM memory slots, up to 256GB DDR4, and a maximum data rate of 2666 MT / s; connected to the host computer via PCIe 3.0 x16 interface; K=4 NVMe SSDs are connected to the MCIO interface (total aggregate bandwidth 27.2 GB / s). (1) Connect K=4 NVMe SSDs to the MCIO expansion interface of the FPGA card. A 1-to-4 PCIe fan-out is achieved through the PCIe switching chip, with the FPGA as the PCIe Root Complex and the four SSDs as PCIe Endpoints. The key configurations are as follows: a) The FPGA PCIe controller is configured in Root Complex mode, supporting Non-Transparent Bridge (NTB); b) Each SSD is allocated an independent PCIe Bus Number and Device Number; c) Peer-to-Peer DMA function is enabled, and Base Address Register (BAR) space mapping is configured; d) The aggregated theoretical bandwidth of the four SSDs reaches 28 GB / s. (2) After the system is powered on, the PS-side ARM processor loads a simplified bare-metal bootloader. This bootloader does not contain any operating system, file system, or network protocol stack. a) PCIe topology enumeration. The PCIe Root Complex register on the PL side is accessed through the AXI GP interface to perform PCIe bus enumeration and identify the four connected NVMe SSD devices. b) NVMe device initialization. An Admin queue and an I / O queue are created for each SSD, and the queue buffer is allocated in the reserved area of ​​the PS-side DDR. c) PL-side bitstream loading: The pre-compiled PL-side bitstream is loaded into the PL through the FPGA Manager. After startup, the PS side outputs logs via serial port to confirm that the four NVMe devices were successfully identified, with a total capacity of 15.36TB and 30,064,771,072 sectors of available LBA address space.

[0102] Step 2, Graph Dataset Preparation: The Papers100M dataset from Open Graph Benchmark (OGB) can be selected. This dataset contains 111,059,956 vertices (representing academic papers) and 1,615,685,872 directed edges (representing citation relationships). Each vertex has a 128-dimensional bag-of-words feature vector. The graph data is not organized through the file system, but is directly written to the raw LBA address space of the SSD. (1) Perform the following preprocessing on the external host: a) CSR format conversion. Convert Papers100M to CSR format, where the row_ptr array stores 111,059,957 64-bit integers; edge_array stores 1,615,685,872 64-bit integers (target vertex IDs); feat_matrix stores a 111,059,956×128 floating-point matrix. b) Hash partitioning strategy. To achieve cross-SSD load balancing, the CSR offset of vertex v is stored in The edge array is stored in a distributed manner; the feature matrix uses block partitioning, with vertices [0, 27.7M) stored on SSD0, [27.7M, 55.5M) stored on SSD1, and so on. c) LBA address layout generation. LBA 0-99 (system configuration area) is written with the magic number 0x474E4E5F4143434C, recording the number of SSDs = 4, the number of vertices = 111,059,956, the number of edges = 1,615,685,872, and the feature dimension = 128. LBA 100-499 (primitive information) records the partitioning strategy = Hash + Block Hybrid, and the number of partitions = 4. LBA 500-999 (partition index table) records the data LBA range on each SSD. LBA 1000-1,776,175 (CSR offset array area) is distributed across 4 SSDs, with each SSD occupying approximately 222MB of LBA space. LBA 1,776,176-27,000,000 (edge ​​data area) distributed storage. LBA 27,000,001-138,000,000 (feature matrix area) storage block partition. (2) Through the NVMe driver of the external host, use the nvmewrite command or custom tool to directly write the preprocessed binary data to the specified LBA address. The writing process adopts multi-threaded parallelism, one thread for each SSD. After the writing is completed, use the nvme flush command to ensure that the data is persisted to NANDFlash. (3) Metadata verification. After the PS side starts up, read the metadata area of ​​LBA 0-999, parse and verify: a) magic number matching to confirm that the data format is correct; b) the number of vertices, the number of edges, and the feature dimension are consistent with expectations; c) write the metadata to the configuration register of the PL side GNN accelerator through the AXI GP interface.

[0103] Step 3, GCN Model Configuration: For example, a 3-layer Graph Convolutional Network (GCN) model is used for vertex classification training, with a 128-dimensional input layer, 256-dimensional hidden layers, and a 172-dimensional output layer. The cross-entropy loss function is used, and the Adam optimizer is employed. The parameters were updated, the learning rate was set to 0.01, and an L2 weight decay of 5e-4 was applied to prevent overfitting. The mini-batch size was set to 256 vertices, and training lasted for 100 epochs until convergence. Weight initialization adopted the Xavier strategy, generating initial weights conforming to a normal distribution on an external host. The standard deviation of these weights was adaptively adjusted according to the input and output dimensions to stabilize the gradient flow in the early stages of training. The generated weight matrix was directly written to the checkpoint region of the SSD via the NVMe Write command. After system startup, the P2P DMA engine on the PL side directly loaded these weights from the SSD to the URAM storage unit on the FPGA chip. The entire process required no intervention from the PS side, achieving true zero-copy weight initialization.

[0104] Step 4, PL-side training accelerator configuration: The PL-side GNN training accelerator is extended based on the inference architecture. The forward path remains unchanged: graph data processing engine (4 parallel CSR parsing units), aggregation computation unit (16 parallel PEs, 128-way vectorization), and feature transformation module (16×16 systolic array, 256 PEs). The newly added backpropagation path includes: a reverse graph data processing engine: loading the reverse CSR format, supporting the search for all source vertices from the target vertex for gradient back aggregation. A gradient back aggregation unit: receiving gradients from downstream vertices. Propagate along the reverse edge to the upstream neighbor and calculate Pulsating array transpose mode: The original array is used for the forward y=Wx, and a transpose mode is added to calculate the reverse. Gradient accumulation buffer: Stores the gradient with respect to the weights. Multiple mini-batches are accumulated and then sent back to the PS side. Activation function derivative unit: calculates the ReLU derivative, Softmax derivative, etc. Loss calculation unit: implements cross-entropy loss. And its gradient with respect to logits; the training bitstream file can be generated using the Vivado 2023.1 tool. The comprehensive report shows improved resource utilization. The bitstream is loaded onto the PL side through the FPGA manager. After configuration, bit[0]=1 in the status register (0x2000) indicates that it is ready, and bit[1]=1 indicates that the training mode is supported.

[0105] Step 5, Start the Epoch Loop: Set the maximum loop count to 100.

[0106] Step 6, Mini-batch sampling: Directly processing the entire graph would lead to memory explosion, therefore a neighbor sampling strategy must be adopted. The system implements GraphSAINT-style hierarchical sampling: First, randomly select vertices from 66.6M training vertices. Use one seed vertex as the center; then sample each seed vertex. First-order neighbors; then sample each first-order neighbor. First, sample the second-order neighbors; finally, sample the second-order neighbors. Alternatively, perform a full graph aggregation using third-order neighbors or directly aggregate the entire graph.

[0107] Step 7, Forward Propagation: The computation of each mini-batch is divided into two stages: forward propagation and back propagation. The forward propagation stage calculates layer by layer starting from the input features: The first GCN layer first reads the 25 neighbor features of each seed vertex through the graph data processing engine, uses 32 aggregation processing units to calculate the mean of the neighbor features in parallel, then performs matrix multiplication of W with its own features using a systolic array, and finally applies the activation function through 32 ReLU units and writes the result (256-dimensional hidden representation) into HBM Bank 0 for back propagation. The second and third layers are processed in a similar manner, the difference being that the input is now the hidden representation instead of the original features, and the second layer introduces Dropout to randomly mask 50% of the neurons, while the third layer outputs 172-dimensional logits and generates a class probability distribution through Softmax activation. The loss function is calculated immediately after forward propagation.

[0108] Step 8, Loss Function and Gradient Calculation: The system implements cross-entropy loss in the PL hardware. For each vertex in the mini-batch, the predicted probability distribution is obtained by Softmax normalization. Then, the predicted probability corresponding to the true label is extracted and the negative logarithm is taken. Finally, the loss of the 256 vertices is averaged to obtain the mini-batch loss scalar.

[0109] Step 9, Backpropagation: In the backpropagation stage, the gradient is propagated in the opposite direction of the computation graph. After the gradient calculation is completed, it is accumulated in the gradient buffer of the URAM.

[0110] Step 10, Model Evaluation and Result Analysis: After 100 epochs of training on the Papers100M dataset, the model achieved a classification accuracy of 64.89% on the test set, 68.42% on the training set, and a best accuracy of 65.31% on the validation set (occurring in the 87th epoch). Compared to the baseline model trained on a GPU using the same hyperparameters, the accuracy difference is less than 0.5%, thus verifying the numerical correctness of the FPGA hardware implementation.

[0111] Step 11, System Cleanup and Resource Release: (1) PS writes a stop command to the control register; (2) The PL-side GNN accelerator stops running and clears the HBM cache; (3) The performance counter is read via AXI GP; (4) The NVMe controller sends a Flush command to ensure the results are persisted; (5) Optional. Key results are transmitted to an external host via Ethernet. Finally, the FPGA card can be powered off or reloaded to its initial state to await the next task.

[0112] The above accelerated training methods eliminate multiple data copies in traditional training architectures: graph data flows directly from the NVMe SSD to the FPGA on-chip storage via P2P DMA. During training, all forward activation, backward gradient, and parameter updates are completed in the BRAM, URAM, and HBM on the PL side, without involving external CPU and system memory. This zero-copy architecture not only reduces latency and power consumption but also avoids frequent CPU wake-ups and repeated read / write operations to DDR memory.

[0113] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described training acceleration method embodiments.

[0114] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described training acceleration method embodiments at runtime.

[0115] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0116] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described training acceleration method embodiments.

[0117] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described training acceleration method embodiments.

[0118] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0119] The training acceleration system, training acceleration method, and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A training acceleration system, characterized by, It includes at least one external storage module and an acceleration module. The acceleration module is connected to the external storage module via a bus. The acceleration module includes a processing module and a control module. The control module includes a storage protocol controller, an on-chip storage module, and a neural network accelerator. The external storage module is configured to store training association data in the form of logical block addresses; The processing module is configured to initialize the external storage module and send training task parameters for the neural network to the control module. The storage protocol controller is configured to generate a read instruction for the external storage module based on the training task parameters, and to read target data from the training associated data of the external storage module through direct memory access based on the logical block address specified in the read instruction. The on-chip storage module is configured to store target data read from the external storage module; wherein, the on-chip storage module includes primary storage, secondary storage and tertiary storage; wherein, the primary storage includes two independent buffers, which are used to provide data for the current computing unit and to synchronously receive the migration of hot data in the next stage; The neural network accelerator is configured to read the target data from the on-chip storage module and train the neural network based on the target data; The control module also includes a direct memory access module; The direct memory access module is configured to establish a mapping relationship between the logical block address space of the external storage module and the physical address space of the on-chip storage module. The direct memory access module is further configured to generate a bus transaction layer data packet based on the logical block address and read length in the read instruction of the external storage module, and to write the received data to the physical address determined by the mapping relationship through the bus transaction layer data packet; The neural network accelerator is a graph neural network accelerator, which includes a graph sampling module, an aggregation calculation module, a feature transformation module, a loss calculation module, and a backpropagation module. The graph sampling module is configured to read the target data from the on-chip storage module and generate target graph data; The aggregation calculation module is configured to perform aggregation operations on the neighbor vertex features of each vertex in the target graph data to generate aggregated features; The feature transformation module is configured to perform feature transformation processing on the aggregated features to obtain predicted values; The loss calculation module is configured to determine the loss value based on the predicted value and the actual value; The backpropagation module is configured to backpropagate along the graph structure based on the gradient of the loss value and update the model parameters.

2. The training acceleration system of claim 1, wherein, The on-chip storage module includes primary storage, secondary storage, and tertiary storage; The primary storage is configured to store hot data for the current computing phase; The secondary storage is configured to store prefetched data and data accessed at a frequency higher than a preset access frequency threshold; The three-tier storage is configured to store the complete data required for training.

3. The training acceleration system of claim 1, wherein, The target graph data includes at least graph topology data and vertex feature data. The graph topology data is stored using a hash partitioning strategy, and the vertex feature data is stored using a block partitioning strategy.

4. The training acceleration system of claim 1, wherein, The graph sampling module includes multiple parallel sampling processing units; The parallel sampling processing unit is configured to perform parallel sampling operations on the target data according to the sampling strategy in the training task parameters to generate target map data.

5. The training acceleration system of claim 1, wherein, The feature transformation module employs a bidirectional reconfigurable pulsating array.

6. A training acceleration method, characterized in that, The training acceleration system applied to any one of claims 1-5 includes: The external storage module is initialized and configured, and the training task parameters of the neural network are sent to the control module. The external storage module stores the training-related data in the form of logical block addresses. Based on the training task parameters, a read instruction for the external storage module is generated, and the target data is read from the training associated data of the external storage module through direct memory access according to the logical block address specified in the read instruction; wherein, the direct memory access method is a method of data transmission between the external storage module and the on-chip storage module by controlling the bus through the direct memory access module. The target data read from the external storage module is stored in the on-chip storage module of the control module; The target data is read from the on-chip storage module, and the neural network is trained based on the target data; wherein, the on-chip storage module includes primary storage, secondary storage and tertiary storage; wherein, the primary storage includes two independent buffers, which are used to provide data for the current computing unit and to synchronously receive the migration of hot data in the next stage.

7. The training acceleration method according to claim 6, characterized in that, The step of generating read instructions for the external storage module based on the training task parameters includes: Based on the training batch size and graph sampling strategy determined by the training task parameters, the set of target vertices to be accessed during the target training phase is determined. Based on the target vertex set, determine the logical block address range of the corresponding vertex feature data and graph topology data stored in the external storage module; Generate a read instruction for the address range of the logical block.

8. The training acceleration method according to claim 6, characterized in that, The training of the neural network based on the target data includes: Based on the target data, generate target map data; Aggregate the features of the neighboring vertices of each vertex in the target graph data to generate aggregated features; The aggregated features are subjected to feature transformation processing to obtain the predicted values; The loss value is determined based on the predicted value and the actual value; The model parameters are updated by backpropagating the gradient of the loss value along the graph structure.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the training acceleration method according to any one of claims 6-8.

Images