A pixel compensation method, device and equipment for splicing of a fantasy lamp tube and a medium

Abstract

This invention discloses a method, apparatus, device, and medium for pixel compensation in splicing of RGB LED tubes. The method includes identifying the breakpoint width and addressing virtual pixels at the splicing tube joints, generating compensation data through equal interpolation in the linear domain based on the color values ​​of the real pixels at both ends, and transmitting the compensation drive signal via serialization encoding and cascaded transmission. In this invention, the problem of dark bands appearing at the splicing points due to the lack of corresponding addressing data filling the physical space of the joints during splicing, causing visual breaks in the image, is addressed by identifying the physical width of the joint breakpoints through a lookup table and calculating the virtual pixel equivalent. The physical space of the joints is then uniformly addressed within a logical address mapping matrix. Furthermore, equal interpolation in the linear domain based on the color values ​​of the real pixels at both ends generates virtual pixel color compensation data, which is then processed and output as a compensation drive signal. This eliminates the dark band breaks at the splicing points, allowing the entire splicing tube to present a visually continuous image.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a pixel compensation method, apparatus, device, and medium for splicing RGB LED tubes. Background Technology

[0002] As a linear light-emitting device integrating multiple independently addressable LED beads, RGB LED tubes are widely used in lighting scenarios such as architectural outlines, stage landscape design, and commercial space decoration due to their rich color expression and controllable individual beads. In actual engineering installations, limited by the fixed length of a single tube, multiple RGB LED tubes are often physically spliced ​​together using connectors to adapt to different sized mounting carriers and form a continuous, extended light-emitting line. Existing RGB LED tube controllers, when generating drive data, typically only use the actual number of LED beads configured inside each tube as the addressing basis, assigning addresses and outputting corresponding color data for each actual pixel. When two RGB LED tubes are spliced ​​together via a connector, the addressing and color data output by the controller still only cover the actual pixel range of each tube itself; as for the physical space occupied by the connector in the splicing structure, since it does not belong to the actual pixel area of ​​any tube, existing controllers do not generate corresponding addressing data and color drive signals for this space.

[0003] However, the connector itself has a certain width in its physical structure, forming a physical discontinuity area between two adjacent RGB LED tubes. Since this area lacks corresponding color data filling and light output, the entire spliced ​​RGB LED tube appears as a dark band without color display at each connector position, causing obvious visual breaks in the overall image at the splicing point, making it difficult to achieve a continuous transition in color and brightness for the entire spliced ​​LED tube. Summary of the Invention

[0004] This invention provides a pixel compensation method, device, equipment, and medium for splicing RGB LED tubes, in order to solve the technical problem that the physical space of the joints in existing RGB LED tube splicing exhibits dark bands due to the lack of corresponding addressing data to fill the gaps, resulting in visual breaks in the image at the splicing point.

[0005] Firstly, a pixel compensation method for splicing multi-color LED tubes is provided, including: The physical topology of the spliced ​​lamp tubes is processed by reading device descriptors and looking up breakpoint widths to obtain the device descriptors of adjacent lamp tubes and match the physical width constants of breakpoints to obtain the topology parameter set. The topology parameter set is subjected to virtual pixel equivalent calculation and logical address continuous expansion processing to continuously number the real pixels and virtual pixels of the connector and bind address attributes to obtain a logical address mapping matrix. Based on the logical address mapping matrix, the pre-extracted video frames are scanned address by address and the breakpoint control point is extracted to locate the real pixels that are closest to the virtual pixel on the left and right and extract their color values ​​to obtain the set of control points at both ends. The set of control points at both ends is subjected to color space linearization and equal division interpolation calculation, so that equal division interpolation is performed in the linear domain according to the virtual pixel position index to obtain the virtual pixel color compensation dataset. The virtual pixel color compensation dataset is subjected to byte-level bitstream encoding and hardware serialization to expand each byte logical bit into SPI bits and output them via DMA to obtain a reconstructed concatenated serial data stream. The recombined cascaded serial data stream is subjected to cascaded transparent transmission processing, so that the cascaded driver chips of the connector are latched and intercepted one by one and mapped to a preset pulse width modulation unit to obtain a compensation drive signal.

[0006] Secondly, a pixel compensation device for splicing multi-color LED tubes is provided, comprising: The data acquisition module is used to read the device descriptor and perform breakpoint width lookup on the physical topology of the spliced ​​lamp tubes to obtain the device descriptors of adjacent lamp tubes and match the breakpoint physical width constant to obtain the topology parameter set. The address mapping module is used to perform virtual pixel equivalent calculation and logical address continuous expansion processing on the topology parameter set, so as to continuously number the real pixels and virtual pixels of the connector and bind address attributes to obtain a logical address mapping matrix. The point extraction module is used to perform address-by-address scanning and breakpoint control point extraction processing on the pre-extracted video frames based on the logical address mapping matrix, so as to locate the real pixels that are closest to the virtual pixel on the left and right and extract their color values ​​to obtain the set of control points at both ends. The color compensation module is used to perform color space linearization and equal division interpolation calculation on the set of control points at both ends, so as to perform equal division interpolation operation in the linear domain according to the virtual pixel position index to obtain the virtual pixel color compensation dataset. The serial processing module is used to perform byte-level bitstream encoding and hardware serialization processing on the virtual pixel color compensation dataset, so as to expand each byte logical bit into SPI bits and output them through DMA to obtain a reconstructed concatenated serial data stream. The cascaded transparent transmission module is used to perform cascaded transparent transmission processing on the recombined cascaded serial data stream, so that the cascaded driver chip of the connector latches and intercepts it one by one and maps it to a preset pulse width modulation unit to obtain a compensation drive signal.

[0007] Thirdly, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the pixel compensation method for splicing the above-mentioned color-changing light tubes.

[0008] Fourthly, a computer-readable storage medium is provided, which stores a computer program that, when executed by a processor, implements the steps of the pixel compensation method for splicing the aforementioned RGB LED tubes.

[0009] The aforementioned method, apparatus, device, and medium for pixel compensation in spliced ​​LED tubes include: reading device descriptors and performing breakpoint width lookup on the physical topology of the spliced ​​LED tubes to obtain adjacent LED tube device descriptors and match breakpoint physical width constants to obtain a topology parameter set; performing virtual pixel equivalent calculation and logical address continuation expansion on the topology parameter set to continuously number and bind address attributes to the real and virtual pixels of the connectors, obtaining a logical address mapping matrix; and performing address-by-address scanning and breakpoint control point extraction on pre-extracted video frames based on the logical address mapping matrix to locate the nearest real pixel to the virtual pixel. Real pixels are analyzed and color values ​​are extracted to obtain a set of control points at both ends. Color space linearization and equal-division interpolation are performed on the control point set at both ends to perform equal-division interpolation operations in the linear domain according to the virtual pixel position index, resulting in a virtual pixel color compensation dataset. Byte-level bitstream encoding and hardware serialization are performed on the virtual pixel color compensation dataset to expand each byte's logical bits into SPI bits and output via DMA, resulting in a reconstructed cascaded serial data stream. The reconstructed cascaded serial data stream is then subjected to cascaded pass-through processing, so that each cascaded driver chip of the connector latches and maps it to a preset pulse width modulation unit to obtain a compensation drive signal. In this invention, to address the problem of dark bands appearing in the physical space of the joints during splicing of existing RGB LED tubes due to the lack of corresponding addressing data to fill them, resulting in visual breaks in the image at the splicing point, the invention addresses this issue by using a lookup table to identify the physical width of the joint break and calculating the virtual pixel equivalent. This allows the physical space of the joint to be uniformly addressed by incorporating it into a logical address mapping matrix. Furthermore, virtual pixel color compensation data is generated by equally dividing and interpolating the color values ​​of the real pixels at both ends in the linear domain. This compensation driving signal is then transmitted through byte-level bitstream encoding and cascaded transmission, thereby achieving color filling and brightness transition in the physical space of the joint, eliminating the dark band breaks at the splicing point, and making the entire spliced ​​LED tube visually present a continuous image. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of an application environment for a pixel compensation method for splicing iridescent light tubes according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of a pixel compensation method for splicing iridescent light tubes according to an embodiment of the present invention; Figure 3 yes Figure 2 A detailed implementation flow diagram of step S10 Figure 1 ; Figure 4 yes Figure 2 A detailed implementation flow diagram of step S20 Figure 2 ; Figure 5 yes Figure 2 A detailed implementation flow diagram of step S30 Figure 3 ; Figure 6 yes Figure 2 A detailed implementation flow diagram of step S40 Figure 4 ; Figure 7 yes Figure 2 A schematic flowchart of a specific implementation method for step S50 Figure 5 ; Figure 8 yes Figure 2 A detailed implementation flow diagram of step S60 Figure 6 ; Figure 9 This is a schematic diagram of a pixel compensation device for splicing iridescent light tubes according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention; Figure 11 This is another structural schematic diagram of a computer device according to one embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] The pixel compensation method for splicing RGB LED tubes provided in this invention can be applied to applications such as... Figure 1 In this application environment, the client communicates with the server via a network. The server can obtain input conditions from the client, namely, read the device descriptor and perform breakpoint width lookup on the physical topology of the spliced ​​light tubes to obtain the device descriptors of adjacent light tubes and match the breakpoint physical width constant to obtain a topology parameter set; perform virtual pixel equivalent calculation and logical address continuous expansion on the topology parameter set to continuously number the real pixels and virtual pixels of the connectors and bind address attributes to obtain a logical address mapping matrix; based on the logical address mapping matrix, perform address-by-address scanning and breakpoint control point extraction on pre-extracted video frames to locate and extract the real pixels that are closest to the virtual pixels. The color value is used to obtain a set of control points at both ends; the set of control points at both ends is processed by color space linearization and equal division interpolation calculation, so as to perform equal division interpolation operation in the linear domain according to the virtual pixel position index to obtain a virtual pixel color compensation dataset; the virtual pixel color compensation dataset is processed by byte-level bit stream encoding and hardware serialization, so as to expand each byte logic bit into SPI bits and output them through DMA transmission to obtain a reconstructed cascaded serial data stream; the reconstructed cascaded serial data stream is processed by cascaded transparent transmission, so that the cascaded driver chip of the connector latches and intercepts them one by one and maps them to a preset pulse width modulation unit to obtain a compensation drive signal. In this invention, the problem of dark bands appearing at the joint physical space due to the lack of corresponding addressing data to fill the gaps in existing RGB LED splicing, causing visual breaks in the image at the splicing point, is addressed by using a lookup table to identify the physical width of the joint break and calculating virtual pixel equivalents. The joint physical space is then incorporated into a logical address mapping matrix for unified addressing. Virtual pixel color compensation data is generated by equally dividing and interpolating the color values ​​of the actual pixels at both ends in the linear domain. This data is then encoded using byte-level bitstream encoding and cascaded transmission to output a compensation drive signal, thereby achieving color filling and brightness transition in the joint physical space, eliminating the dark band breaks at the splicing point, and making the entire spliced ​​LED display a visually continuous image. The client can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. The server can be implemented using a standalone server or a server cluster consisting of multiple servers. The invention will be described in detail below through specific embodiments.

[0014] Please see Figure 2 As shown, Figure 2 A flowchart illustrating a pixel compensation method for splicing multi-color LED tubes according to an embodiment of the present invention includes the following steps: S10: Perform device descriptor reading and breakpoint width lookup on the physical topology of the spliced ​​lamp tubes to obtain the device descriptors of adjacent lamp tubes and match the physical width constant of the breakpoints to obtain the topology parameter set.

[0015] The spliced ​​light tube refers to an extended light-emitting line formed by connecting multiple RGB light tubes end-to-end along a physical direction via connectors. The connectors are located between adjacent RGB light tubes for mechanical fixation and electrical connection. The physical topology refers to the arrangement order and positional relationship of the RGB light tubes and connectors within the spliced ​​light tube. In this step, for each connector, the pre-stored device descriptors in the adjacent light tubes on both sides are read. These device descriptors identify the end-point information such as the light tube model, pixel count, and pixel spacing. Simultaneously, the inherent breakpoint physical width constant of the connector is obtained by looking up a table. This breakpoint physical width constant refers to the physical width value of the connector in the splicing direction, predetermined by the structural components. The device descriptors of the adjacent light tubes read at each connector and the matched breakpoint physical width constants are collected and encapsulated according to the connector sequence number to obtain the topology parameter set.

[0016] Combination Figure 3 As shown, step S10 specifically includes: S101: Identify the chip of the spliced ​​lamp tube and burn the lamp tube description information to obtain the lamp tube end identity data.

[0017] To enable the connector to automatically acquire key attribute parameters of its adjacent LED tubes without relying on on-site manual ranging and data entry, this step pre-integrates a chip carrying the tube's identity information at the end of each LED tube. The chip is preferably a low-cost single-bus identification chip (e.g., DS2411) or an I2C EEPROM (Inter-Integrated Circuit Electrically Erasable Programmable Read-Only Memory, e.g., 24C02). Both types of chips can interact with an external host to read and write identity information via a small number of signal lines and can persistently retain the written content even after power failure. The tube description information includes, but is not limited to, the product model, total number of pixels, pixel pitch P, and end margin lengths used to uniquely identify the physical attributes of the LED tube. The pixel pitch P refers to the center distance between two adjacent real pixels within the LED tube, and the end margin lengths refer to the physical distance from the end face of the LED tube to the center of the nearest real pixel. The lamp tube description information is burned into the chip's storage unit by the production equipment during the product manufacturing stage and stored permanently, thereby ensuring that the end of each of the spliced ​​lamp tubes carries lamp tube end identity data that can be read externally.

[0018] S102: The microprocessor inside the connector reads the lamp end identity data during the power-on initialization phase to obtain the adjacent lamp device descriptor.

[0019] The connector integrates a microprocessor for performing identity information reading and status reporting functions. Upon power-up of the splicing light tube system, the microprocessor immediately enters the power-on initialization phase. During this phase, the microprocessor sequentially accesses the chips located at the ends of adjacent LED tubes on both sides via either a single-bus protocol (applicable to the aforementioned single-bus identity recognition chip) or an I2C protocol (Inter-Integrated Circuit Protocol, i.e., a two-wire serial communication protocol applicable to the aforementioned I2C EEPROM), and reads the previously programmed identity data of the LED tube ends from the chip's storage unit. Through this reading operation, the connector can simultaneously obtain attribute parameters such as the product model, total number of pixels, pixel pitch P, and start and end margin lengths of its left and right adjacent LED tubes. These parameters are recorded internally by the microprocessor as adjacent LED tube device descriptors for direct use in subsequent steps.

[0020] S103: Retrieve the predetermined width of the injection-molded structural component of the joint as the physical width constant of the breakpoint from the table, and match it with the descriptor of the adjacent lamp tube device to obtain the joint parameters.

[0021] The mechanical body of the connector itself is composed of injection-molded structural parts. These parts are molded to millimeter-level tolerances according to the mold dimensions during the production stage. Therefore, the physical distance Wgap between the contacts at both ends of the connector used to mate with adjacent LED tubes is a fixed value that does not change with the installation site. Since the physical distance Wgap can be uniquely determined by the mold dimensions without requiring on-site measurement, this step pre-writes the predetermined width parameter of the injection-molded structural parts into a lookup table and stores it on the microprocessor side. After executing step S102, the microprocessor directly retrieves the predetermined width value corresponding to the connector from the lookup table and records it as the breakpoint physical width constant of the connector. This eliminates the need for on-site distance measurement and avoids errors introduced by manual input. The breakpoint physical width constant characterizes the physical space occupied by the connector in the splicing direction. Subsequently, the microprocessor pairs and binds the retrieved physical width constant of the breakpoint with the adjacent lamp device descriptor obtained in step S102, so that each physical width constant of the breakpoint is clearly associated with the specific lamp model and pixel pitch P on the left and right sides to which it is connected, thereby obtaining a complete connector parameter.

[0022] S104: Based on the current signature modulation during the power-on handshake, assign a link cascading sequence number to the connector and bind it to the connector parameters to obtain cascading sequence number binding data.

[0023] Since multiple connectors can exist on a single link of the splicing lamp tube, in order for the main controller to identify the physical order of each connector within the link, this step assigns a unique link cascading sequence number to each connector during the power-on handshake phase. During the power-on handshake phase, the main controller sequentially applies a handshake signal of a preset waveform to each connector via the cascading link of the splicing lamp tube. The microprocessor within each connector responds to the handshake signal by generating a current fluctuation with identifiable characteristics in its own power circuit, thereby forming a unique current signature for each connector. The main controller samples the total circuit current of the splicing lamp tube and identifies the order in which each current signature appears. Based on this order, it sequentially assigns a link cascading sequence number to the corresponding connector. This link cascading sequence number uniquely identifies the physical arrangement of the connector within the splicing lamp tube. Subsequently, the microprocessor binds the assigned link cascading sequence number with the connector parameters obtained in step S103 to obtain cascading sequence number binding data, ensuring that each connector parameter carries index information reflecting its position within the link.

[0024] S105: Encapsulate the cascade sequence number binding data into a status report frame and report it to the main controller for aggregation to obtain the topology parameter set.

[0025] The microprocessor encapsulates the cascading sequence number binding data obtained in step S104 into a status report frame according to a preset communication frame format. The status report frame carries at least the link cascading sequence number of the connector, the physical width constant Wgap of the breakpoint, and the device descriptors of the adjacent lamp tubes on the left and right sides. The microprocessor reports this to the main controller via the cascading link of the spliced ​​lamp tubes. The main controller receives the status report frames reported sequentially by each connector on the link, sorts and aggregates the content of each frame according to the link cascading sequence number, and finally integrates them into a topology parameter set that completely describes the physical topology of the spliced ​​lamp tubes. The topology parameter set can then be used as the basic data for virtual pixel equivalent calculation and logical address continuous expansion processing in the subsequent step S20.

[0026] In one specific embodiment, on-site construction personnel sequentially splice three SK6812 LED tubes, each with a pixel pitch P=10mm and 100 actual pixels, into a long chain using two standard injection-molded structural parts with a width Wgap=16.5mm. Within approximately 80 milliseconds after system power-on, the main controller sequentially receives status report frames from the two connectors located on this long chain: connector #1 is located after the 100th actual pixel, and the device descriptors of the adjacent LED tubes on its left and right sides both display SK6812-10mm, with a breakpoint physical width constant Wgap=16.5mm; connector #2 is located after the 200th actual pixel, and its parameters are the same as connector #1, thereby completing the aggregation and generation of the topology parameter set for the spliced ​​LED tubes.

[0027] S20: Perform virtual pixel equivalent calculation and logical address continuous expansion processing on the topology parameter set to continuously number the real pixels and virtual pixels of the connector and bind address attributes to obtain a logical address mapping matrix.

[0028] The "real pixel" refers to the independently addressable LED beads actually configured inside each LED tube, while the "virtual pixel" refers to a logical pixel unit that is artificially constructed to fill the physical space occupied by the connector and has the same addressing status as the real pixel. The "virtual pixel equivalent" refers to the number of virtual pixels that need to be compensated at a single connector. In this step, based on the proportional relationship between the physical width constant of the breakpoint and the pixel spacing of adjacent LED tubes in the topology parameter set, the virtual pixel equivalent is calculated for each connector. Then, the real pixels and the virtual pixels are sequentially numbered according to the physical order of the spliced ​​LED tubes to form a unique logical address index, and each logical address index is bound with an attribute identifier and address attribute information such as the LED tube or connector number to which it belongs, thereby integrating to obtain a logical address mapping matrix.

[0029] Combination Figure 4 As shown, step S20 specifically includes: S201: Analyze the physical width constant of the breakpoint of each connector and the pixel spacing parameter of the adjacent lamp tube from the set of topology parameters.

[0030] The topology parameter set is a data set obtained by the main controller in step S10 by aggregating and integrating the status report frames reported by each connector on the splicing lamp tube. It records the physical width constant of each connector's breakpoint and the device descriptors of its adjacent lamp tubes in order of link cascading sequence number. The pixel spacing parameter refers to the center-to-center distance in the physical direction between two adjacent real pixels in the splicing lamp tube, used to characterize the density of real pixels inside the lamp tube, usually represented by P and measured in millimeters. In this step, the main controller accesses each connector entry in the topology parameter set sequentially according to the link cascading sequence number, and performs a parsing operation on each connector entry. On the one hand, it directly reads the physical width constant Wgap of the connector's breakpoint from the entry; on the other hand, it extracts the pixel spacing parameter P of the lamp tubes on both sides of the connector from the device descriptors of the adjacent lamp tubes carried in the entry, thereby providing complete original numerical basis for the subsequent virtual pixel equivalent calculation.

[0031] S202: Take the nearest integer of the ratio between the physical width constant of the breakpoint and the pixel spacing parameter and perform calculations to obtain the virtual pixel equivalent.

[0032] The nearest neighbor integer operation (round operation) refers to a mathematical operation that rounds a non-integer value to the nearest integer. For values ​​with a decimal part greater than or equal to 0.5, the rounding is performed upwards; otherwise, it is performed downwards. This allows continuous physical quantities to be mapped to an enumerable set of discrete integers while minimizing errors. In this step, the main controller calculates for each connector according to the formula Nvirtual = round(Wgap / P). First, the physical width constant Wgap of the connector is divided by the pixel spacing parameter P of the lamps on both sides of the connector to obtain the ratio of the number of pixels that can be accommodated in the physical space occupied by the connector. Then, the nearest neighbor integer operation is applied to the obtained ratio to reduce it to a non-negative integer, which is recorded as the virtual pixel equivalent Nvirtual at the connector. The significance of the virtual pixel equivalent lies in the fact that the physical space occupied by the connector is evenly divided using the pixel spacing parameter P as the basic unit of measurement, resulting in an integer number of virtual pixel positions that are closest in size to the physical space. This allows the compensated virtual pixels to be distributed in a continuous manner with approximately equal spacing from the real pixels on both sides in terms of physical arrangement.

[0033] S203: Based on the virtual pixel equivalent, the real pixels and virtual pixels of the connector are sequentially numbered in physical order to obtain a unique logical address index.

[0034] The physical order refers to the arrangement order of the real pixels and virtual pixels along the physical extension direction of the splicing lamp tube from one end to the other. In this step, the main controller uses one end of the splicing lamp tube as the starting point for numbering and sequentially scans along the physical extension direction. When scanning a lamp tube, it assigns continuously increasing integer numbers to each real pixel according to the physical arrangement order of the real pixels in that lamp tube; when scanning a connector, it continues to assign Nvirtual continuously increasing integer numbers corresponding to the connector based on the virtual pixel equivalent Nvirtual obtained in step S202, and assigns each of the Nvirtual integer numbers to the Nvirtual virtual pixels corresponding to the connector; then when scanning the next lamp tube, it continues to assign integer numbers according to the physical arrangement order of its real pixels, and so on until the other end of the splicing lamp tube. After this continuous numbering operation, each real pixel and each virtual pixel on the splicing lamp tube obtains an integer number that does not repeat throughout the entire link. The integer number serves as the unique logical address index of the pixel, which is used to uniquely locate and address the pixel in subsequent steps.

[0035] S204: Bind the attribute identifier, the lamp or connector number to the unique logical address index and the original physical coordinates to obtain the address attribute entry data.

[0036] Since the unique logical address index obtained in step S203 is merely an integer number reflecting the arrangement order without carrying any additional information about the inherent properties of the address, in order to enable subsequent video frame processing steps to quickly identify the specific type and affiliation of the currently accessed pixel based on the unique logical address index, this step binds three key attribute information to each unique logical address index: first, an attribute identifier, which indicates whether the pixel corresponding to the unique logical address index is a real pixel or a virtual pixel, so that subsequent steps can distinguish whether the address should directly read the color value or trigger interpolation calculation; second, the lamp or connector number, which indicates which lamp or connector the pixel corresponding to the unique logical address index belongs to; and third, the original physical coordinates, which record the specific position coordinates of the pixel corresponding to the unique logical address index in the original physical link of the splicing lamps. The main controller sequentially fills the above three attribute information into each unique logical address index, thereby forming a complete address attribute entry data.

[0037] S205: Expand the address attribute entry data into a one-dimensional structure array in a predetermined order and store it in the main controller's storage area to obtain a logical address mapping matrix.

[0038] The structure array refers to a data set composed of several structure units with the same field definitions arranged in a linear sequence. Each unit contains several predefined fields to carry different attribute values. The one-dimensional structure array refers to the structure array form in which each structure unit is arranged sequentially according to a single index dimension. In this step, the main controller fills all the address attribute entries obtained in step S204 into the corresponding units of the one-dimensional structure array in a predetermined order from smallest to largest according to the unique logical address index, so that a strict one-to-one correspondence is formed between the subscripts of the one-dimensional structure array and the unique logical address index. The one-dimensional structure array is then stored in the storage area of ​​the main controller. The storage area is preferably the SRAM (Static Random Access Memory) inside the main controller to meet the speed requirements of high-frequency random index access during the processing of each subsequent video frame. This results in a logical address mapping matrix, which resides in the storage area in a form that can be directly indexed and accessed, so that subsequent steps S30 and each subsequent video frame processing can directly index and call it without repeated construction.

[0039] In one specific embodiment, based on the topology parameter set obtained in step S10 (i.e., including three SK6812 specifications, pixel pitch P=10mm, each with 100 real pixels, and two connectors with a physical width constant Wgap=16.5mm at the breakpoints), the main controller calculates the virtual pixel equivalent for each connector according to the formula Nvirtual=round(Wgap / P), and obtains Nvirtual=round(16.5 / 10)=round(1.65)=2 at each connector, that is, the number of virtual pixels to be compensated at each connector is 2. The main controller then assigns unique logical address indices to each real pixel and virtual pixel in the physical order of the splicing lamp tubes. The resulting logical address mapping matrix contains a total of 304 pixel addresses, where addresses 0 to 99 belong to the real pixels of lamp tube #1, addresses 100 to 101 belong to the virtual pixels of connector #1, addresses 102 to 201 belong to the real pixels of lamp tube #2, addresses 202 to 203 belong to the virtual pixels of connector #2, and addresses 204 to 303 belong to the real pixels of lamp tube #3. This completes the unified addressing of all real and virtual pixels of the splicing lamp tubes.

[0040] S30: Based on the logical address mapping matrix, perform address-by-address scanning and breakpoint control point extraction processing on the pre-extracted video frames to locate the real pixels that are closest to the virtual pixel on the left and right and extract their color values ​​to obtain a set of control points at both ends.

[0041] The video frame refers to a single frame of image data extracted from the video source in advance and to be output and displayed by the splicing lamp tube; the breakpoint control point refers to the real pixel color reference point located on both sides of the virtual pixel, used to support subsequent interpolation operations. In this step, the video frame is traversed address by address using the logical address mapping matrix as an index: when the logical address belonging to a real pixel is scanned, the color value at the corresponding position of the address is directly retained; when the logical address belonging to a virtual pixel is scanned, the real pixel address closest to the virtual pixel is located to the left and right along the logical address mapping matrix, and the color values ​​of the corresponding positions of the real pixels at the left and right ends are extracted in the current frame; the left and right real pixel color values ​​corresponding to the virtual pixels at each joint are collected together to obtain the set of control points at both ends.

[0042] Combination Figure 5 As shown, step S30 specifically includes: S301: The extracted raw video frame data is decoded and pushed to the frame buffer of the main controller in line order to obtain the video frame data to be processed.

[0043] The raw video frame data refers to the single-frame raw image data output by the video source outside the splicing lamp system that has not undergone any subsequent processing. The image encoding format used by the raw video frame data usually needs to be decoded before it can be accessed by the main controller pixel by pixel. The line sequence mode (also known as raster scanning mode) refers to the data organization method that reads or transmits each pixel of the image in the order of top to bottom and left to right in each line of the image frame. Considering the diverse forms of video sources, this step provides two typical paths for acquiring and pushing the original video frame data: First, the HDMI (High-Definition Multimedia Interface) decoding chip decodes the HDMI video signal from the external signal source and outputs the decoded image data to the DDR (Double Data Rate) frame buffer for temporary storage in the row-order manner described above. Second, the host computer pushes the image data to the internal buffer of the main controller (i.e., the Microcontroller Unit) in the row-order manner via SPI (Serial Peripheral Interface) or UART (Universal Asynchronous Receiver / Transmitter) for temporary storage. Regardless of the path chosen, the original video frame data ultimately falls into the frame buffer of the main controller in row-order arrangement, awaiting subsequent address traversal operations as video frame data to be processed.

[0044] S302: Using the logical address mapping matrix as an index, the video frame data to be processed is traversed address by address to obtain address-by-address scan status data.

[0045] The logical address mapping matrix is ​​a one-dimensional structure array constructed in step S20 and residing in the main controller's storage area. Each unit carries the attribute identifier of the corresponding pixel and address attribute entry data such as the lamp or connector number, which can be directly indexed and accessed by the main controller. The address-by-address traversal refers to the scanning operation of sequentially accessing each unit in the logical address mapping matrix in ascending order of the unique logical address index and reading the address attribute entry data carried by that unit. In this step, the main controller starts the scanning process with the unique logical address index as the loop variable, sequentially accessing each logical address position in the video frame data to be processed. For each address accessed, the attribute identifier of that address is read from the corresponding unit of the logical address mapping matrix. The value indicated by the attribute identifier (i.e., the binary discrimination result indicating whether the current address belongs to a real pixel or a virtual pixel) is used as the address-by-address scan status data and output. The address-by-address scan status data is used to determine the processing branch that should be triggered for the current address in subsequent steps.

[0046] S303: When the address-by-address scan status data indicates that the current address belongs to a real pixel, the color value at the corresponding position is extracted and written into the buffer to be sent to obtain the real pixel color data.

[0047] The buffer to be sent refers to the storage area inside the main controller that is dedicated to temporarily storing the complete color data sequence to be output to the splicing lamp tube after subsequent serialization processing. The storage address order of the buffer to be sent is strictly in one-to-one correspondence with the unique logical address index order of the logical address mapping matrix. In this step, when the address-by-address scan status data output in step S302 indicates that the currently accessed logical address belongs to a real pixel, since the real pixel corresponds to the actual position of an LED bead in a certain RGB light tube, its color value can be directly determined by the image pixel value at the corresponding position in the video frame data to be processed. Therefore, the main controller does not need to perform any interpolation calculations. Instead, it extracts the 24-bit RGB color value (with 8 bits carrying the values ​​of the red, green, and blue components respectively) from the video frame data to be processed based on the original physical coordinates of the real pixel, and writes the extracted 24-bit RGB color value directly into the corresponding position of the buffer to be sent according to the unique logical address index of the real pixel. After the main controller performs the above extraction and writing operations sequentially on all logical addresses belonging to real pixels in the video frame data to be processed, the real pixel color data is collected in the buffer to be sent.

[0048] S304: When the address-by-address scan status data indicates that the current address belongs to a virtual pixel, locate the nearest real pixel address to the left and right of the current address to obtain the breakpoint adjacent address data.

[0049] Since the virtual pixel itself does not correspond to any actual LED beads in the splicing lamp tube, its color value cannot be directly read from the video frame data to be processed. It is necessary to first determine the positions of the two reference points on which its color value depends in the subsequent interpolation operation. Therefore, this step requires locating the address of the nearest real pixel on both sides along the address direction in the logical address mapping matrix for each virtual pixel. In this step, when the address-by-address scan status data output in step S302 indicates that the currently accessed logical address belongs to a virtual pixel, the main controller backtracks along the logical address mapping matrix in the address decreasing direction, using the unique logical address index of the virtual pixel as a reference. When it accesses the first unit whose attribute identifier indicates a real pixel, it records the unique logical address index corresponding to that unit as the nearest real pixel address on the left. At the same time, the main controller advances along the logical address mapping matrix in the address increasing direction, using the unique logical address index of the virtual pixel as a reference. When it accesses the first unit whose attribute identifier indicates a real pixel, it records the unique logical address index corresponding to that unit as the nearest real pixel address on the right. Finally, the main controller combines the recorded nearest real pixel address on the left, the nearest real pixel address on the right, and the unique logical address index of the current virtual pixel itself to form a breakpoint adjacency address data. The breakpoint adjacency address data is used to uniquely represent the adjacency relationship between the current virtual pixel and the real pixels on both sides.

[0050] S305: Extract the color value corresponding to the current frame from the real pixel color data according to the breakpoint adjacency address data and store it in the interpolation task queue, and integrate them to obtain the set of control points at both ends.

[0051] The interpolation task queue refers to a queue-style storage structure within the main controller that is specifically opened for the interpolation calculation stage in the subsequent step S40, and carries interpolation task items to be processed in a first-in-first-out order. Each queue item in the interpolation task queue records all the input parameters required for the interpolation operation of the virtual pixel, with each virtual pixel as a unit. In this step, the main controller processes each of the breakpoint adjacency address data obtained in step S304 as follows: First, based on the address of the nearest real pixel on the left recorded in the breakpoint adjacency address data, the 24-bit RGB color value of the nearest real pixel on the left in the current frame is extracted from the real pixel color data obtained in step S303 as the left-end color control point; then, based on the address of the nearest real pixel on the right recorded in the breakpoint adjacency address data, the 24-bit RGB color value of the nearest real pixel on the right in the current frame is extracted from the real pixel color data as the right-end color control point; finally, the extracted left-end color control point and the right-end color control point, together with the unique logical address index of the current virtual pixel itself, are packaged into an interpolation task item, and pushed into the interpolation task queue in ascending order of the unique logical address index of the virtual pixel. After the main controller sequentially performs the above extraction and push operations on all logical addresses belonging to virtual pixels in the video frame data to be processed, the interpolation task queue gathers the two ends of the real pixel color control points corresponding to all virtual pixels in the current frame, and after integration, the two ends control point set is obtained.

[0052] In one specific embodiment, for a certain frame, the main controller performs the address-by-address traversal operation on all 304 addresses contained in the logical address mapping matrix described in the aforementioned embodiment in 10-millisecond cycles. When the scanning process in this cycle reaches the address with the unique logical address index of 100, the main controller reads the attribute identifier of the address from the logical address mapping matrix, indicating that it belongs to the first virtual pixel at connector #1, and thus triggers a virtual pixel processing branch for this address; then the main controller performs a reverse lookup along the logical address mapping matrix, tracing back from address 100 in the address decreasing direction to address 99, and identifies that address 99 belongs to the real pixel at the end of lamp #1, so address 99 is recorded as the nearest real pixel address on the left; at the same time, it moves forward from address 100 in the address increasing direction, and after skipping address 101, which still belongs to a virtual pixel, it reaches address 102, and identifies that address 102 belongs to the real pixel at the beginning of lamp #2, so address 102 is recorded as the nearest real pixel address on the right. The main controller then extracts the 24-bit RGB color value (255, 128, 0) at address 99 in the current frame from the real pixel color data as the left-end color control point, and the 24-bit RGB color value (0, 128, 255) at address 102 in the current frame as the right-end color control point. The extracted control point pair (255, 128, 0) / (0, 128, 255) along with its corresponding virtual pixel address 100 and address 101 are packaged and pushed into the interpolation task queue, thus completing the extraction operation of the two ends of the control points of the virtual pixel at connector #1.

[0053] S40: Perform color space linearization and equal division interpolation calculation on the set of control points at both ends, so as to perform equal division interpolation operation in the linear domain according to the virtual pixel position index, and obtain the virtual pixel color compensation dataset.

[0054] Since the color values ​​of the real pixels are usually stored in a non-linear color space, and interpolation operations are performed directly in this non-linear color space, color shifts will occur in the intermediate transition areas due to the non-linear relationship between color components and light intensity. Therefore, color space linearization processing is required first. The linear domain refers to the color domain in which the values ​​of each color component have a linear correspondence with the light intensity. In this step, the color values ​​of each pair of left and right real pixels in the set of control points at both ends are first mapped from the non-linear color space to the linear domain. Then, based on the virtual pixel equivalent at each junction, the color interval formed by the control points at both ends in the linear domain is divided equally, and interpolation operations are performed one by one according to the position index of each virtual pixel in the junction to obtain the linear domain color value at the corresponding position. Finally, the linear domain color value is mapped back to the original non-linear color space, and all interpolation results at each junction are integrated to obtain the virtual pixel color compensation dataset.

[0055] Combination Figure 6 As shown, step S40 specifically includes: S401: Extract the actual pixel color values ​​of the left and right ends corresponding to each breakpoint from the set of control points at both ends, and organize them to obtain the endpoint color component data.

[0056] The set of control points at both ends is a data set obtained in step S30 and stored in the form of the interpolation task queue. Each item in the set of control points at both ends records the left and right color control points required for subsequent interpolation operations, with each virtual pixel as a unit. In this step, the main controller sequentially retrieves each interpolation task item in the interpolation task queue according to the first-in-first-out order. For each interpolation task item, the left and right color control points are split into components. That is, the 24-bit RGB color value is decomposed into three independent 8-bit component values ​​according to the red, green, and blue components. The components are then classified and organized according to the breakpoint number, the side (i.e., left or right), and the color channel (i.e., one of red, green, and blue). After this extraction and sorting operation, the color data of the two control points, which were originally stored in a packaged form, are split into a data form in which the values ​​of each component are independent and can be easily processed in parallel for subsequent decoding and mapping operations. This data form is used as the output of the endpoint color component data, providing a structured input for the table lookup decoding process in the subsequent steps.

[0057] S402: Call the sRGB to linear RGB lookup table pre-stored in the memory to decode and map the endpoint color component data to obtain the linear domain endpoint color data.

[0058] The sRGB (standard Red Green Blue) color space is a standard color space that uses a gamma curve to non-linearly encode linear light intensity. There is no simple linear proportional relationship between its components and actual light intensity. Therefore, if arithmetic interpolation is performed directly on the color values ​​of the control points at both ends of this space, the non-uniform compression characteristics of the gamma curve will cause brightness dips or hue shifts in the calculated intermediate transition colors. To eliminate this problem, the endpoint color component data must first be mapped from the sRGB space back to the linear RGB space. The sRGB to linear RGB lookup table is a pre-built data table used to implement this non-linear to linear conversion operation. The sRGB to linear RGB lookup table, abbreviated as LUT (Look-Up Table), pre-calculates and stores the corresponding linear RGB floating-point values ​​for each of the 256 possible values ​​that can be enumerated by an 8-bit integer in the sRGB space. Therefore, the lookup table has 256 entries. The sRGB to linear RGB lookup table is burned into and pre-stored in the Flash (Flash Memory) memory connected to the main controller during the manufacturing stage of the splicing lamp system. The Flash memory is a non-volatile storage medium that retains its stored content even after power failure. In this step, the main controller sequentially performs a lookup operation on each 8-bit component value in the endpoint color component data, that is, using the 8-bit component value as an index, it reads the corresponding linear domain component value from the sRGB to linear RGB lookup table, thereby completing the decoding mapping of the component. After performing the above lookup operation on the red, green, and blue components of the left and right control points, the linear domain endpoint color data is obtained.

[0059] S403: Divide the linear domain endpoint color data into equal interpolation intervals to obtain interpolation interval division data.

[0060] Since the virtual pixel equivalent Nvirtual obtained in step S202 represents the number of virtual pixels that need color compensation at a certain joint, in order to make the Nvirtual virtual pixels at the joint exhibit a uniform gradient characteristic in color transition, this step needs to divide the color value interval formed between the color control points at the left and right ends of the linear domain equally according to the virtual pixel equivalent Nvirtual. In this step, the main controller uses the left linear component value Vleft,linear and the right linear component value Vright,linear of the red, green and blue channels in the linear domain endpoint color data as the start and end points of the color value interval of each channel, respectively. According to the virtual pixel equivalent Nvirtual+1 at this joint, the color value interval is divided into Nvirtual+1 sub-intervals of equal length, so that the Nvirtual virtual pixels correspond exactly to the Nvirtual internal division points between the above-mentioned Nvirtual+1 sub-intervals. After division, each virtual pixel obtains an independent position number i (i=1,2,...,Nvirtual), which uniquely indicates its specific division point position in the equally divided interpolation interval. The position number i, together with the left linear component value Vleft,linear, the right linear component value Vright,linear, and the virtual pixel equivalent Nvirtual, constitute the interpolation interval division data, which serves as the input parameter for subsequent linear equally divided interpolation operations.

[0061] S404: Perform linear interpolation on the interpolation interval data according to the virtual pixel position number of each connector to obtain the linear domain virtual pixel color data.

[0062] The linear equidistant interpolation operation refers to an arithmetic operation within the linear domain that weights and mixes the linear component values ​​at both ends based on the position index of the virtual pixel in the equidistant interpolation interval to obtain the intermediate transition component value. In this step, the main controller calculates the linear domain component values ​​of the red, green, and blue channels for each virtual pixel position index i at each connector according to the following formula: Vlinear,i=Vleft,linear+(Vright,linear−Vleft,linear)×i / (Nvirtual+1); Where Vlinear,i represents the linear domain component value of the virtual pixel at position i in the color channel, Vleft,linear and Vright,linear represent the left and right linear component values ​​in the color channel, respectively, and i / (Nvirtual+1) represents the normalized interpolation weight corresponding to the position number within the linearly divided interpolation interval. After the main controller performs the above operation sequentially on all Nvirtual virtual pixel position numbers at the connector, it obtains the red, green, and blue channel component values ​​of each virtual pixel at the connector in the linear domain. After performing the above operation sequentially on each connector on the splicing lamp tube, it integrates to obtain the color data of the virtual pixels in the linear domain. Since the above operation process only involves basic arithmetic operations such as table lookup, subtraction, multiplication, and division, the computational overhead is significantly reduced compared to the multiple matrix multiplications and cube root operations required for interpolation in the perceptual color space. Therefore, the compensation calculation of all virtual pixels of a single connector can be completed in microseconds on a general-purpose MCU, which can meet the requirements of real-time video frame processing for computational latency.

[0063] S405: Call the reverse lookup table to re-encode and map the linear domain virtual pixel color data back to the sRGB domain to obtain the virtual pixel color compensation dataset.

[0064] Since the color values ​​of each real pixel in the splicing lamp tube are carried in 8-bit integer form in sRGB space in the video frame data to be processed and the buffer to be sent, in order to ensure that the virtual pixel color and the real pixel color are consistent in data format and can participate in the bit stream encoding and serialization processing of subsequent steps without difference, the linear domain virtual pixel color data obtained in step S404 must be converted back to sRGB space. The reverse lookup table is a pre-made data table used to implement the linear RGB to sRGB conversion operation. The reverse lookup table and the sRGB to linear RGB lookup table in step S402 are inverse operations of each other. It is also pre-calculated and pre-stored in the Flash memory during the manufacturing stage of the splicing lamp tube system. In this step, the main controller sequentially performs a lookup operation on the red, green, and blue linear component values ​​of each virtual pixel in the linear domain virtual pixel color data. That is, it reads the corresponding 8-bit sRGB component value from the reverse lookup table using the linear component value as an input parameter, thereby re-encoding the linear domain color of each virtual pixel into a 24-bit RGB sRGB color value that can be directly recognized by subsequent hardware circuits. After performing the above re-encoding and mapping operation on all virtual pixels on the splicing lamp tube, a virtual pixel color compensation dataset is obtained. Each item in the virtual pixel color compensation dataset carries its calculated 24-bit RGB compensation color value, identified by the unique logical address index of a single virtual pixel.

[0065] In one specific embodiment, taking the breakpoints corresponding to virtual pixel addresses 100 and 101 at connector #1 located by step S30 in the aforementioned embodiment as an example, the left-end color control point of the breakpoint is extracted from the set of control points at both ends as (255, 128, 0) and the right-end color control point is (0, 128, 255). After calling the sRGB to linear RGB lookup table to perform decoding mapping, the linear domain endpoint color data corresponding to the left-end color control point in the linear domain is (1.000, 0.216, 0.000) and the linear domain endpoint color data corresponding to the right-end color control point in the linear domain is (0.000, 0.216, 1.000). Then, based on the virtual pixel equivalent Nvirtual=2 at this connector, the color value interval on the linear domain is divided equally, and the virtual pixel position numbers i at address 100 and address 101 are 1 and 2 respectively, and the corresponding normalized interpolation weights i / (Nvirtual+1) are 1 / 3 and 2 / 3 respectively. The main controller performs linear interpolation on the red, green, and blue channels according to the formula Vlinear,i=Vleft,linear+(Vright,linear−Vleft,linear)×i / (Nvirtual+1), resulting in the following: the linear domain virtual pixel color data for address 100 is (0.667,0.216,0.333), and the linear domain virtual pixel color data for address 101 is (0.333,0.216,0.667). Finally, the reverse lookup table is called to re-encode and map the linear domain results back to the sRGB domain, resulting in the final compensated color for address 100 as (217,128,153) and the final compensated color for address 101 as (153,128,217). This result is then written into the corresponding virtual pixel address in the pending transmission buffer as the corresponding item in the virtual pixel color compensation dataset.

[0066] S50: Perform byte-level bitstream encoding and hardware serialization processing on the virtual pixel color compensation dataset to expand each byte logical bit into SPI bits and output them via DMA to obtain a reconstructed concatenated serial data stream.

[0067] SPI (Serial Peripheral Interface) is a peripheral interface used for high-speed synchronous serial communication between a host controller and peripheral devices. The SPI bit refers to the serial bit stream unit output by the SPI peripheral. DMA (Direct Memory Access) is a hardware transfer mechanism that allows direct data transfer between memory and peripherals without occupying the CPU. In this step, according to the address order determined by the logical address mapping matrix, the virtual pixel color compensation dataset and the corresponding real pixel color values ​​are integrated into a complete byte sequence to be sent. For each byte in this byte sequence, each logical bit is expanded into the corresponding number of SPI bits according to a preset bit encoding rule, resulting in a bit stream that meets the timing requirements of the downstream cascaded driver chip. Then, DMA transfer is initiated to move the source buffer of the bit stream autonomous controller to the SPI peripheral and serially output it through its data output pin, thereby obtaining the reconstructed cascaded serial data stream.

[0068] Combination Figure 7 As shown, step S50 specifically includes: S501: Write the virtual pixel color compensation dataset and the real pixel color data into the send buffer according to the address order of the logical address mapping matrix to obtain complete send buffer data.

[0069] The real pixel color data obtained in step S30 carries the 24-bit RGB color value of each real pixel on the splicing lamp tube in the current frame. The virtual pixel color compensation dataset obtained in step S40 carries the 24-bit RGB compensation color value of each virtual pixel on the splicing lamp tube obtained by interpolation. The two only cover part of the logical address of the splicing lamp tube and have not yet formed a continuous and complete color data sequence in the buffer to be sent. In this step, the main controller traverses the unique logical address indices in the logical address mapping matrix in ascending order, performing the following write operations on each unique logical address index: when the attribute identifier corresponding to the unique logical address index indicates that the corresponding pixel is a real pixel, the 24-bit RGB color value of the real pixel is retrieved from the real pixel color data and written to the storage location corresponding to the unique logical address index in the buffer to be sent; when the attribute identifier corresponding to the unique logical address index indicates that the corresponding pixel is a virtual pixel, the 24-bit RGB compensation color value calculated for the virtual pixel is retrieved from the virtual pixel color compensation dataset and written to the storage location corresponding to the unique logical address index in the buffer to be sent. After this alternating write operation, the buffer to be sent is compiled into a byte sequence without address breaks, without attribute distinctions, and continuously carrying all real pixel colors and all virtual pixel colors, according to the physical arrangement order of the splicing lamps. This byte sequence serves as the complete buffer data to be sent, providing a single continuous data source for subsequent bitstream encoding processing.

[0070] S502: Configure the baud rate of the SPI peripheral so that each non-return-to-zero code bit corresponds to a preset number of SPI byte bits, and obtain SPI encoded configuration data.

[0071] The non-return-to-zero code, abbreviated as NZR code, is a serial encoding method that distinguishes logic 0 from logic 1 by the ratio of the duration of high and low levels on a single signal line. The cascaded driver chips in the splicing lamp tube (such as WS2812B, SK6812 and other industry-standard cascaded driver chips) use the NZR code as the protocol timing for their data input terminals. However, the NZR code has strict requirements on the duration accuracy of the high and low levels within a single bit (typical protocols specify that its timing tolerance must be controlled within ±150 nanoseconds). If the main controller directly generates the NZR code waveform bit by bit using software delay, it will be difficult to stably meet the above timing tolerance requirements due to software interrupt jitter. Therefore, this solution adopts the industry-mature SPI simulation NZR code scheme, that is, by using the hardware-level clock and shift register of the SPI peripheral to simulate the waveform of a single NZR code bit by concatenating the first and last bits of multiple SPI bytes, the timing generation task of the NZR code is migrated from software to hardware, so that its timing accuracy is locked by the hardware clock of the SPI peripheral, thereby stably meeting the ±150 nanosecond timing tolerance requirement and avoiding the interrupt jitter problem inherent in software delay. In this step, the main controller configures the baud rate of the SPI peripheral to a value range of approximately 2.4MHz to 3MHz, so that the time required for the SPI peripheral to output one SPI byte is exactly one-third to one-quarter of the single bit period of the NZR code. Thus, each NZR code bit corresponds to a preset number (i.e., 3 to 4) of SPI bytes. The baud rate value and the corresponding number and other parameters together constitute the SPI encoding configuration data, which serves as the configuration basis for subsequent byte-by-byte bit stream unfolding operations.

[0072] S503: Based on the SPI encoding configuration data, expand the logical bits of each byte in the complete buffer data to be transmitted into corresponding SPI bits according to a preset high-low ratio rule to obtain byte-by-byte expanded bit stream data.

[0073] The preset high-low ratio rule refers to the encoding rule used to specify the ratio of the number of bytes occupied by the high level to the number of bytes occupied by the low level when a single NZR code logic bit is expanded into multiple SPI byte bits. In this step, the preset high-low ratio rule is specifically defined as follows: For the logic 0 bit in the complete buffer data to be transmitted, it is encoded into an SPI byte with a high-low ratio of approximately 1:2. That is, the front part of the expanded SPI byte maintains a high level with a small number of bytes and the back part maintains a low level with a large number of bytes. Thus, the waveform presented by the SPI byte on the SPI main output pin is equivalent to an NZR code logic 0 bit (i.e., short duration of high level and long duration of low level). For the logic 1 bit in the complete buffer data to be transmitted, it is encoded into an SPI byte with a high-low ratio of approximately 2:1. That is, the front part of the expanded SPI byte maintains a high level with a large number of bytes and the back part maintains a low level with a small number of bytes. Thus, the waveform presented by the SPI byte on the SPI main output pin is equivalent to an NZR code logic 1 bit (i.e., long duration of high level and short duration of low level). The main controller performs an expansion encoding operation on each of the eight logical bits of each byte in the complete buffer data to be sent, according to the expansion ratio specified in the SPI encoding configuration data, and sequentially according to the preset high-low ratio rule. That is, each logical bit is converted into a corresponding SPI byte, thereby expanding each 3 bytes that originally carried 24-bit RGB color values ​​into 24 bit stream segments corresponding to the SPI bytes. The bit stream segments are then output as byte-by-byte expanded bit stream data.

[0074] S504: Concatenate the byte-by-byte expanded bitstream data according to the address order of the logical address mapping matrix and store it in the DMA source buffer to obtain DMA source bitstream data.

[0075] The DMA source buffer refers to the source storage area within the main controller, dedicated to the DMA controller (Direct Memory Access Controller) for data transfer operations. The DMA controller can read the data to be transferred byte by byte from the DMA source buffer in a preset address incrementing manner and send it directly to the data register of the target peripheral. The entire transfer process does not require the computing resources of the main controller's CPU core. In this step, the main controller uses the unique logical address index in the logical address mapping matrix in ascending order as the splicing basis, and splices all the byte-by-byte expanded bitstream data obtained in step S503 sequentially according to the physical arrangement order of the splicing lamp tubes, so that the 24 SPI bytes corresponding to each pixel are closely connected according to the unique logical address index order of their respective pixels; then, the complete SPI byte sequence obtained by splicing is sequentially stored in the DMA source buffer, thereby ensuring that the byte sequence carried in the DMA source buffer is strictly consistent with the physical arrangement order of each pixel on the splicing lamp tube in terms of address arrangement. The byte sequence serves as the DMA source bitstream data waiting to be transferred.

[0076] S505: Initiate DMA transfer to send the DMA source bitstream data to a predetermined SPI data register and output it constantly on the main output pin to obtain a reassembled cascaded serial data stream.

[0077] The SPI data register refers to the hardware register inside the SPI peripheral used to temporarily store the byte data to be serially shifted and output. After completing the serial shift output of each byte, the SPI peripheral loads the next byte from the SPI data register and continues the shift output operation. The master output pin is the MOSI (Master Output Slave Input) pin of the SPI peripheral, which is the physical pin used by the SPI peripheral to serially output the byte bit stream in master mode. In this step, the main controller configures the DMA controller's source address to point to the DMA source buffer and the destination address to point to the SPI data register. Then, DMA transfer is initiated. The DMA controller reads the DMA source bitstream data byte by byte from the DMA source buffer in auto-incrementing address order and writes it into the SPI data register. The SPI peripheral performs hardware-level shifting of the byte data in the SPI data register based on the main controller's internal clock, and stably outputs the shifted SPI byte bitstream on the MOSI pin. Since the timing accuracy of the SPI byte bitstream is completely locked by the hardware clock of the SPI peripheral throughout the entire transfer process, the CPU core of the main controller does not need to intervene in any byte loading or timing generation operations during the entire process of the DMA controller's transfer. Therefore, the interrupt jitter problem inherent in software delay can be completely avoided, ensuring that the final output bitstream waveform stably meets the ±150 nanosecond timing tolerance requirement specified by the cascade driver chip protocol. This bitstream waveform serves as the reassembled cascaded serial data stream output from the MOSI pin to the cascaded link of the splicing lamp.

[0078] In one specific embodiment, an STM32F411 general-purpose MCU is selected as the main controller. The SPI1 peripheral of the MCU is configured to operate in a 3MHz master mode, 8-bit frame, MSB (Most Significant Bit) priority mode. Correspondingly, the logic 0 of the NZR code is encoded as byte 0xC0 (its binary form is 11000000, that is, the first 2 bytes are high level and the last 6 bytes are low level, with a high-low ratio of approximately 1:3), and the logic 1 of the NZR code is encoded as byte 0xF8 (its binary form is 11111000, that is, the first 5 bytes are high level and the last 3 bytes are low level, with a high-low ratio of approximately 5:3). At this baud rate, each NZR code bit occupies an output duration of approximately 2.667 microseconds. Based on the 304-pixel link scale of the splicing lamp tube described in the foregoing embodiment, the total capacity of the SPI buffer is 304 pixels × 24 bits × 1 byte = 7296 bytes. The outputs from steps S10 to S40 are filled in the address order of the logical address mapping matrix. The DMA controller moves the DMA source bit stream data from the SPI buffer to the SPI data register in a single-pass mode. The complete transmission time of a single frame bit stream is about 7.5 milliseconds, which can support a screen refresh rate higher than 60Hz. The CPU core of the main controller is only responsible for updating the contents of the SPI buffer between two adjacent frames, thereby completing the stable generation and output of the reassembled cascaded serial data stream.

[0079] Furthermore, in a specific embodiment, step S505 further includes several configuration and execution steps to ensure the timing stability and data integrity of the reassembled cascaded serial data stream on the MOSI (Master Output Slave Input) pin.

[0080] Before the DMA transfer is initiated, the main controller needs to initialize the DMA controller by setting the transfer direction of the DMA data stream or DMA channel used for this transfer to memory-to-peripheral (MEM2PERIPH), configuring its source address register to the starting address of the DMA source buffer, configuring its destination address register to the physical address of the SPI data register, configuring its transfer width to be aligned and moved in units of bytes (i.e., 8 bits), enabling its source address auto-increment mode (Memory Increment Mode) and disabling its destination address auto-increment mode (Peripheral Increment Mode). This ensures that after each byte is moved, the DMA controller automatically increments the source address pointer to the next byte position in the DMA source buffer, keeping the destination address pointing to the SPI data register. At the same time, its total transfer register is configured to the total number of bytes of the DMA source bitstream data in the DMA source buffer, so that the DMA controller automatically terminates the current transfer when the number of bytes moved reaches the total number of bytes.

[0081] Furthermore, to establish a stable handshake relationship between the SPI peripheral and the DMA controller, the master controller enables the DMA request line corresponding to the Transmit Buffer Empty (TXE) flag of the SPI peripheral. This causes the SPI peripheral to automatically send a DMA request to the DMA controller every time it completes a serial shift output of one byte and clears the SPI data register. The DMA controller responds to the request by reading the next byte from the DMA source buffer and writing it into the SPI data register. Since this handshake process is entirely triggered by hardware signals without the intervention of the CPU core of the master controller, it can be ensured that the SPI data register is immediately filled with the next byte after the previous byte is shifted and output. This ensures that the byte shift process of the SPI peripheral maintains a gapless continuous output on the MOSI pin, avoiding disruption of the continuous timing of the NZR code due to idle level intervals between adjacent bytes. In addition, to prevent the DMA transfer from being interrupted due to other peripherals preempting the bus, the main controller configures the DMA data stream corresponding to this transfer to high priority, so that the DMA controller can prioritize the real-time performance of this bit stream transfer in a working scenario where multiple peripherals share the bus bandwidth.

[0082] Furthermore, to ensure the MOSI pin can stably output the reassembled cascaded serial data stream and possess sufficient driving capability, the main controller configures the GPIO (General-Purpose Input / Output) pin corresponding to the MOSI pin in Alternate Function Push-Pull Output Mode and points it to the multiplexing function of the SPI peripheral. Simultaneously, it configures the output speed level to HighSpeed, so that the rise and fall edge transition times of the pin's output are significantly lower than the tolerance range of a single bit period of the NZR code. This ensures steep waveform edges on the MOSI pin, facilitating accurate identification of high and low level transitions by the downstream cascaded driver chip. At the same time, the main controller configures the SPI peripheral's slave selection management mode to Software-managed Slave Select (NSS) mode to disable the chip select signal's influence on the MOSI pin output, and configures the SPI peripheral's clock polarity (CPOL) to 0 and clock phase (CPHA) to... The Phase is configured to 0, so that the clock pin of the SPI peripheral is kept at an idle low level and the first and second byte are sampled in rising edge alignment, so that the byte waveform of this SPI simulated NZR code scheme is consistent with the bit start timing specified by the downstream cascaded driver chip protocol.

[0083] After completing the above initialization configuration, the main controller sequentially sets the enable bit of the DMA controller and the DMA send request enable bit of the SPI peripheral to officially start the DMA transfer. The DMA controller then reads the DMA source bit stream data byte by byte from the DMA source buffer in the configured source address auto-increment mode, and writes the read bytes into the SPI data register in real time in response to each TXE request of the SPI peripheral. The SPI peripheral shifts each byte in the SPI data register to the MOSI pin in MSB (Most Significant Bit) priority mode. The MOSI pin continuously outputs a bit stream waveform composed of the first and last SPI bytes connected together under the lock of the SPI peripheral hardware clock. The bit stream waveform is the constant output of the reassembled concatenated serial data stream on the MOSI pin.

[0084] To support continuous output of multiple frames and enable the downstream cascaded driver chip to correctly perform data latching between frames, the main controller further enables the DMA controller's Transfer Complete Interrupt (TCIF). After all the DMA source bitstream data corresponding to this frame has been shifted and output by the SPI peripheral, the DMA controller automatically triggers the transmission completion interrupt. Upon responding to the interrupt, the main controller immediately switches the MOSI pin to GPIO general output mode and pulls it low, maintaining the low level for a duration not less than the reset low level duration specified by the cascade driver chip protocol (typically not less than 50 microseconds, and not less than 280 microseconds for some new cascade driver chips). This forms a clear and identifiable inter-frame reset interval on the cascade link of the splicing lamps, allowing each cascade driver chip to synchronously complete the internal latching of the data of this frame and prepare to receive the next frame bitstream at the end of the reset interval. After the reset low level duration ends, the main controller switches the MOSI pin back to push-pull output mode and starts the DMA transmission corresponding to the next frame, thereby achieving seamless connection between frames.

[0085] Furthermore, to ensure that the preparation process of the DMA source bitstream data corresponding to the next frame overlaps with the execution process of the DMA transfer corresponding to the current frame in time, thereby further compressing the overall processing time of a single frame, the main controller internally sets up two physical storage areas of the same capacity and non-adjacent addresses as a ping-pong buffer for the DMA source buffer. One ping-pong buffer is read in real time as the transfer source of the DMA controller during the execution of the current frame, while the other ping-pong buffer is used as the filling target of the bitstream of the next frame, and the CPU core of the main controller synchronously executes the data filling operations from steps S501 to S504 during this period. When the DMA transfer corresponding to the current frame is completed and after the inter-frame reset interval, the main controller only needs to switch the source address register of the DMA controller to the first address of the other ping-pong buffer to immediately start the DMA transfer corresponding to the next frame. This avoids the additional waiting delay introduced by the inter-frame data preparation and can stably support a screen refresh rate of 60Hz or even higher under the limited computing resources of the main controller.

[0086] Finally, in cases where the output level of the MOSI pin may differ from the data input level required by the cascaded driver chip in the video wall (e.g., the main controller outputs at 3.3V while the cascaded driver chip uses 5V as the logic high determination benchmark), a level shifter can optionally be connected between the main controller and the cascaded link input of the video wall. This level shifter boosts the 3.3V logic level output by the MOSI pin to a 5V logic level while maintaining the original timing before connecting it to the cascaded link input of the video wall. This further improves the reliability of the recombined cascaded serial data stream being correctly identified by the downstream cascaded driver chip and ensures that the cascaded link of the video wall maintains sufficient signal integrity and anti-interference capability in long-distance transmission scenarios.

[0087] S60: Perform cascaded transparent transmission processing on the recombined cascaded serial data stream so that each cascaded driver chip of the connector is latched and intercepted and mapped to a preset pulse width modulation unit to obtain a compensation drive signal.

[0088] The cascaded driver chip refers to a driver chip with self-addressing latching function built into the connector and connected in series in a cascade manner. Each cascaded driver chip corresponds to one virtual pixel. The pulse width modulation unit refers to a hardware unit inside the cascaded driver chip used to control the brightness and color components of the light-emitting device by adjusting the output duty cycle. In this step, the recombined cascaded serial data stream is connected to the data input terminal of the first cascaded driver chip in the connector. The first cascaded driver chip automatically latches and extracts the color data of the virtual pixel corresponding to itself, and transmits the remaining bit stream through the built-in shaping circuit to the subsequent cascaded driver chips one by one, thus completing the latching and extraction of the color data of the virtual pixel corresponding to each cascaded driver chip in sequence. Then, the color data extracted by each cascaded driver chip is mapped to the internal pulse width modulation unit according to the red, green, and blue components. The pulse width modulation unit outputs a driving signal according to the corresponding duty cycle, thereby obtaining a compensation driving signal for lighting up the light-emitting device corresponding to the virtual pixel.

[0089] Combination Figure 8 As shown, step S60 specifically includes: S601: The recombined cascaded serial data is connected to the data input terminal of the first cascaded driver chip in the connector to obtain the connector inlet data stream.

[0090] In this solution, the connector no longer relies on a self-developed ASIC (Application-Specific Integrated Circuit) for color data capture and emission control. Instead, it pre-integrates Nvirtual standard cascading driver chips (such as the industry-standard WS2812B cascading driver IC, or an equivalent solution using an external WS2811 driver with a micro RGB SMD LED) with cascading functionality, according to the virtual pixel equivalent Nvirtual at the connector. These Nvirtual cascading driver chips are connected end-to-end within the connector to form a micro cascading sub-link, which is then connected in series to the main link of the splicing lamp tube. Each of the cascading driver chips has two data transceiver pins: a data input (DIN) and a data output (DOUT). The data input receives the serial bit stream from upstream, while the data output forwards the remaining bit stream processed by the chip to downstream. Regarding the connection relationship between this connector and the main link of the splicing light tube, the upstream side of this connector is led out from the data output terminal of the cascaded driver device corresponding to the actual pixel at the end of the previous RGB light tube, and the main link bit stream is connected to the data input terminal of the first cascaded driver chip on the micro cascaded sub-link within this connector via the electrical contact between the end face of the light tube and the end face of the connector; the downstream side of this connector is led out from the data output terminal of the last cascaded driver chip in the micro cascaded sub-link within this connector, and connected to the data input terminal of the cascaded driver device corresponding to the first actual pixel of the next RGB light tube via the opposite electrical contact. In this step, the recombined cascaded serial data output in step S50 is continuously transmitted downstream along the main link of the splicing light tube, and when it reaches the position of this connector, it is automatically sent to the data input terminal of the first cascaded driver chip via the above-mentioned upstream access path. Thus, from the perspective of the first cascaded driver chip, the received bit stream is used as the connector inlet data stream.

[0091] S602: Control the first cascaded driver chip to perform latching and interception of the preset bit width data at the beginning of the connector inlet data stream, and obtain the first chip latched color data.

[0092] The latching and interception refers to a hardware-level operation in which the cascaded driver chip, using its built-in hardware latch, intercepts and stores a fixed-length data segment at the very beginning of the received serial bit stream and removes this data segment from the bit stream being forwarded downstream. This latching and interception function is inherent to the cascaded working mechanism of the cascaded driver chip itself and requires no additional external timing intervention. The preset bit-width data refers to 24 consecutive bits that are strictly equal in length to the 24-bit RGB (Red, Green, Blue) color value of a single pixel. In this step, the first cascaded driver chip counts bits in the connector entry data stream from its very beginning. When the counted number of bits reaches the preset bit-width, i.e., 24 bits, the first cascaded driver chip automatically triggers its built-in latch to intercept the aforementioned 24 bits of data from the connector entry data stream and store them in its internal register. This makes the 24 bits of data the exclusive color data of this cascaded driver chip and prevents it from flowing downstream. Since the recombined cascaded serial data obtained in step S50 has placed the virtual pixel color compensation data of this connector strictly in the byte segment corresponding to the physical location of this connector according to the address order of the logical address mapping matrix, the 24-bit data at the very beginning of the connector's input data stream exactly corresponds to the 24-bit RGB compensation color value calculated by the first virtual pixel in this connector in step S40. Therefore, the 24-bit data latched and intercepted by the first cascaded driver chip is output as the color data latched by the first chip.

[0093] S603: The remaining bit stream of the connector inlet data stream is forwarded one by one to the subsequent cascaded driver chips in the connector through the built-in shaping circuit to obtain the color data latched by each chip.

[0094] The built-in shaping circuit refers to the hardware circuit unit integrated inside the cascaded driver chip, which is used to steepen the edge and calibrate the level of the bit stream waveform before forwarding it downstream. The built-in shaping circuit can perform waveform recovery on the received bit stream inside each of the cascaded driver chips, so that the waveform quality of the bit stream will not deteriorate to the point that the downstream cascaded driver chip cannot recognize it after being transmitted one by one through multiple cascaded driver chips due to edge passivation and level attenuation introduced by long link transmission. In this step, after the first cascaded driver chip completes the latching and truncation of the 24-bit preset width data in step S602, it sends the remaining bit stream in the connector inlet data stream to its own built-in shaping circuit for waveform recovery processing, and forwards the shaped remaining bit stream from the data output terminal of the first cascaded driver chip to the data input terminal of the next cascaded driver chip in this connector; the next cascaded driver chip then truncates the first 24 bits of the received remaining bit stream in the same way as its own color data, and forwards the remaining bit stream to the next cascaded driver chip after shaping it through its own built-in shaping circuit, and so on in a cyclical manner until the last cascaded driver chip in this connector completes its own 24-bit data latching. Since the Nvirtual×24-bit compensation color data corresponding to this connector in the recombined cascaded serial data is arranged strictly in sequence according to the virtual pixel position number, the 24-bit data successively latched and extracted by the Nvirtual cascaded driver chips from the first to the last in this connector exactly corresponds one-to-one to the 24-bit RGB compensation color value of the first to Nvirtual virtual pixels in this connector. The color data latched by each cascaded driver chip is output as chip-by-chip latched color data. At the same time, the remaining bit stream forwarded by the data output terminal of the last cascaded driver chip in this connector has had its Nvirtual×24-bit compensation color data consumed by this connector itself removed, and its byte order is completely aligned with the physical position of the real pixels of the downstream RGB LED tube. Therefore, the downstream RGB LED tube can continue to be decoded and lit normally in the conventional cascaded manner from its first real pixel without additional processing.

[0095] S604: Collect the color data latched by the first chip and the color data latched by each chip, and map them to the pulse width modulation unit according to the red, green and blue components to obtain the compensation drive signal.

[0096] The pulse width modulation unit refers to the hardware unit inside the cascaded driver chip used to adjust the high-level duty cycle of its output pin according to the input digital color component value. The pulse width modulation unit is abbreviated as PWM unit (Pulse Width Modulation Unit). Its output duty cycle has a linear proportional relationship with the input color component value. Therefore, by taking advantage of the visual integral effect of the human eye on rapidly changing light intensity signals, the visual brightness of the driven light-emitting device can be made equivalent to a state that is continuously adjustable according to the digital value of the color component. In this step, the first cascaded driver chip and each subsequent cascaded driver chip in the connector perform component splitting on the 24-bit RGB color value they latch, dividing it into three color channels: red, green, and blue. This involves dividing the 24-bit RGB color value into three 8-bit values ​​carrying the red, green, and blue components respectively, and mapping these three 8-bit component values ​​to three independent pulse width modulation (PWM) units within the cascaded driver chip. These three PWM units independently adjust the high-level duty cycle of their respective output pins according to the magnitude of the mapped component values, and provide driving current from their output pins in the form of a PWM waveform to the red, green, and blue light-emitting subunits of the miniature RGB light-emitting device corresponding to the cascaded driver chip. This enables the miniature RGB light-emitting device to emit mixed-color light according to the color and brightness indicated by the 24-bit RGB color value. The pulse width modulation waveform synchronously output by the pulse width modulation unit of the Nvirtual cascaded driver chip within this connector serves as the compensation drive signal. This compensation drive signal is converted into visible light by the corresponding micro RGB light-emitting devices to achieve the physical illumination of the virtual pixels. Furthermore, the outer shell of the connector is made of a semi-transparent uniform light-emitting material. When the light emitted by the micro RGB light-emitting devices passes through the semi-transparent uniform light-emitting material, it undergoes multiple diffuse reflections, transforming from the original dotted light spots into uniform and soft continuous light spots. This visually fills in the physical dark band originally occupied by the injection-molded structure of the connector, creating a continuous light-emitting section indistinguishable from the actual pixel light-emitting areas of the two side RGB LED tubes.

[0097] In one specific embodiment, the connector #1 described in the previous embodiment integrates two WS2812B cascaded driver chips (corresponding to the virtual pixel equivalent Nvirtual=2 at this connector) and is equipped with two 0603 packaged miniature RGB SMD (Surface Mounted Device) LEDs as the miniature RGB light-emitting devices. The two WS2812B cascaded driver chips are connected end to end in this connector to form the miniature cascaded sub-link. When the recombined cascaded serial data generated in step S50 reaches connector #1 along the main link, the connector inlet data stream is accessed from the data input terminal of the first WS2812B cascaded driver chip. The first WS2812B cascaded driver chip latches and extracts the first 24 bits of data in the connector inlet data stream. The extracted 24-bit RGB color value is (217, 128, 153) calculated in step S40. The first WS2812B cascaded driver chip maps this color value to its three pulse width modulation units according to the red, green, and blue components, and drives the first 0603 packaged micro RGB SMD connected to it. The LED emits orange-red light; the subsequent 24-bit RGB color value (153,128,217) is shaped by the built-in shaping circuit of the first WS2812B cascade driver chip and forwarded to the second WS2812B cascade driver chip. The second WS2812B cascade driver chip performs latching on the 24-bit data and maps it component-wise to its own pulse width modulation unit in the same way, driving the second 0603 packaged miniature RGB SMD LED connected to it to emit purple-red light; then, the data output terminal of the last WS2812B cascade driver chip in connector #1 pushes the remaining 280 pixel × 24-bit byte stream after being consumed by this connector to the downstream lamp tube #2 through the electrical contact of the other end. The lamp tube #2 decodes and lights up normally according to the physical position of its internal pixels. After these six steps are executed in tandem, the physical dark band at the connector #1, which was originally defined by the physical width constant Wgap=16.5mm of the breakpoint, is filled by a continuous light spot emitted by the two miniature RGB SMD LEDs and formed by the diffuse reflection of the semi-transparent uniform light material, which smoothly connects with the colors of the real pixels at both ends. This makes the physical link, which was originally composed of only 300 real pixels, appear as a continuous and seamless iridescent light band composed of 304 pixels in the final visual effect.

[0098] In addition, in a specific embodiment, step S604 further includes several hardware configuration and execution steps to ensure that the compensation drive signal can be synchronously activated among the Nvirtual cascaded drive chips in the connector and that the micro RGB light-emitting device presents a stable and uniform light-emitting effect visually.

[0099] Specifically, after the first cascaded driver chip and subsequent cascaded driver chips within the connector complete their respective latching operations, each cascaded driver chip within the connector has a two-level register structure to temporarily store the captured 24-bit RGB color value: the first level register is a receive shift register, used to receive and temporarily store the first 24 consecutive bits of the connector's input data stream bit by bit during the latching process; the second level register is an output latch register, used to load the temporarily stored 24 bits of data from the receive shift register at once at the reset low-level interval trigger time at the end of the frame, and to stably maintain the 24 bits of data in its own storage unit throughout the next frame cycle for continuous reading by the pulse width modulation unit. All Nvirtual cascaded driver chips within the connector synchronously trigger their respective output latch registers to load data at the end of the same reset low-level interval. This enables the color data corresponding to all virtual pixels within the connector to switch synchronously at the frame-level time scale, avoiding color switching misalignments that can be perceived by the human eye between virtual pixels due to inconsistent loading times of each chip.

[0100] Furthermore, each of the cascaded driver chips within the connector integrates three independent pulse width modulation units, corresponding to the red, green, and blue color channels respectively. After loading the data into the output latch register, each cascaded driver chip sequentially divides the 24-bit RGB color value into three 8-bit components (R, G, and B) according to the red, green, and blue components, and loads these three 8-bit components into the corresponding duty cycle comparison registers within the three pulse width modulation units. The three pulse width modulation units share the same reference clock output by the same internal oscillator integrated within the cascaded driver chip. The reference clock is divided to form a modulation period signal. The modulation period signal corresponds to an 8-bit counting range (i.e., 256 levels from 0 to 255) within each modulation period. At the beginning of its modulation period, each pulse width modulation unit sets its output pin to a high level and its internal counter increments from 0. When the count value of the internal counter is equal to the 8-bit component value loaded in the duty cycle comparison register of this channel, the pulse width modulation unit immediately flips its output pin to a low level. When the internal counter accumulates to the maximum value of the 8-bit counting range, it enters the next modulation period cycle. This ensures that the high-level duty cycle of the pulse width modulation waveform formed on the output pin of the pulse width modulation unit has a strictly linear proportional relationship with the value of the 8-bit component. The larger the value of the 8-bit component, the higher the high-level duty cycle and the stronger the visual luminous brightness of the corresponding color subunit of the micro RGB light-emitting device. Furthermore, since the frequency of the modulation period signal is usually set to a range of several hundred hertz or higher after frequency division (typically not less than 400Hz), which is much higher than the visual persistence threshold frequency of the human eye, the luminous brightness of the micro RGB light-emitting device perceived by the human eye is equivalent to a stable visual brightness that is continuously adjustable according to the value of the 8-bit component, without any perceptible flickering phenomenon.

[0101] Furthermore, the output pin of the pulse width modulation unit does not directly drive the light-emitting sub-unit of the miniature RGB light-emitting device, but rather via a constant current output stage integrated within the cascaded driver chip. After current shaping by the stage, the driving current is provided to the light-emitting sub-unit. The constant current drive output stage has independent constant current output ports (OUTR, OUTG, OUTB) for the red, green, and blue color channels respectively. Each constant current output port provides a constant driving current of a preset amplitude (typically 12mA to 20mA per channel) to the light-emitting sub-unit during the high level output of the corresponding pulse width modulation unit, and cuts off the driving current in the light-emitting sub-unit to zero during the low level output of the corresponding pulse width modulation unit. This makes the visual brightness of the red, green, and blue light-emitting sub-units in the miniature RGB light-emitting device depend only on the duty cycle of the pulse width modulation unit and is not affected by factors such as the forward voltage difference of the light-emitting sub-units, power supply voltage fluctuations, and changes in ambient temperature. This avoids the problem of inconsistent color and brightness between the Nvirtual miniature RGB light-emitting devices in the connector due to the individual discreteness of the devices. At the same time, the constant current amplitude is uniformly limited by the reference current source inside the cascaded drive chip, so that the miniature RGB light-emitting device can still avoid overcurrent damage when it is continuously lit for a long time.

[0102] Furthermore, the Nvirtual micro RGB light-emitting devices corresponding to the Nvirtual cascaded driver chips within the connector are arranged sequentially along the splicing direction inside the connector according to the unique logical address index order of the virtual pixels at this connector. The center distance between two adjacent micro RGB light-emitting devices is set to be strictly consistent with or nearly consistent with the pixel spacing parameter P, thereby enabling the Nvirtual micro RGB light-emitting devices to form a continuous and equally spaced light-emitting dot matrix with the actual pixels of the two sides of the spliced ​​light tube in terms of physical arrangement. The outer shell of the connector is made of a semi-transparent light-diffusing material, which is preferably a milky white polycarbonate (PC) material or acrylic (PMMA, Polymethyl methacrylate) material with a preset haze parameter. The light emitted by the micro RGB light-emitting devices in the Nvirtual unit needs to pass through the translucent uniform light-emitting material and undergo multiple diffuse reflections and scatterings before being uniformly radiated from the entire surface of the connector. This causes the original dot-shaped light spots emitted by each micro RGB light-emitting device to be merged into a uniform, soft, and continuous light spot without obvious boundaries on the surface of the connector shell. Finally, visually, the physical dark band at the connector defined by the physical width constant Wgap of the breakpoint is filled into a continuous light band that is indistinguishable from the actual pixel light-emitting areas of the two side RGB LED tubes in terms of brightness uniformity and color continuity.

[0103] Finally, the compensation drive signal output by the Nvirtual cascaded drive chips in the connector is mixed at the red, green, and blue light-emitting sub-units inside the micro RGB light-emitting device using additive color mixing to form a mixed color light that strictly corresponds to the 24-bit RGB compensation color value digital content, and is emitted through diffuse reflection by the semi-transparent uniform light material. While completing its own latching and pulse width modulation unit loading operations, the data output terminal of the last cascaded drive chip in this connector continues to forward the remaining bit stream after being consumed by this connector to the data input terminal of the downstream RGB lamp tube according to the timing specified by the cascaded drive chip protocol. This allows the virtual pixel light emission process at this connector and the real pixel light emission process of the downstream RGB lamp tube to be carried out in parallel within the same frame period without interfering with each other. Finally, the pulse width modulation waveform synchronously output by all the pulse width modulation units in the connector serves as the compensation drive signal, driving the micro RGB light-emitting device to emit light according to the 24-bit RGB compensation color value calculated in step S40, thus completing the physical light emission process of the virtual pixel.

[0104] As can be seen, compared to the existing RGB LED controllers that only use the actual number of LEDs inside each tube as the addressing basis, resulting in dark bands in the physical space of the connector due to the lack of corresponding addressing data, this application automatically obtains the physical width constant of the breakpoint and the device descriptors of adjacent tubes by reading the device descriptor of the connector and performing breakpoint width lookup table processing. This eliminates the need for on-site distance measurement and manual input, and avoids parameter errors introduced by manual input. Then, the virtual pixel equivalent is obtained by calculating the nearest integer between the ratio of the physical width constant of the breakpoint and the pixel spacing parameter. This allows the physical space occupied by the connector to be included in the unified addressing range of the spliced ​​LED tubes, thus obtaining the same addressing status as real pixels. The logical position is determined; then, through virtual pixel equivalent calculation and logical address continuous expansion processing, a logical address mapping matrix covering real pixels and virtual pixels is constructed, so that subsequent video frame processing can directly complete the unified addressing of each pixel with a single index without maintaining additional attribute flag bits in the data stream; furthermore, by performing color space linearization and equal division interpolation calculation processing on the set of control points at both ends, the color value of the virtual pixel transitions evenly according to the position index in the linear domain, avoiding the brightness dip and hue shift problems inherent in interpolation in the nonlinear color space, and because it only involves basic operations such as table lookup, subtraction, multiplication and division, the compensation calculation of a single connector can be completed on a general-purpose MCU with a microsecond delay. This avoids the high computational overhead of multiple matrix multiplications and cube root operations required for color space perception. Furthermore, through byte-level bitstream encoding and hardware serialization, the virtual pixel color compensation dataset and the real pixel color data are uniformly expanded into a bitstream conforming to the timing requirements of the cascaded driver chip protocol according to the address order of the logical address mapping matrix. The SPI peripheral and the DMA controller use hardware-level clock locking of the bitstream timing and hardware-level handshaking to maintain continuous byte output, ensuring that the reconstituted cascaded serial data stream is constantly output on the main output pin while completely avoiding the interrupt jitter inherent in software delays and stably meeting the ±150 nanosecond timing tolerance requirement. Finally, by executing the reconstituted cascaded serial data stream... The cascaded transparent transmission process allows the standard cascaded driver chip integrated within the connector to perform latching, interception, and pulse width modulation of the corresponding virtual pixel color data one by one through its inherent cascaded working mechanism. This eliminates the need for a self-developed ASIC to achieve physical light emission of the virtual pixels. Furthermore, because the connector shell is made of a semi-transparent uniform light material, the light emitted by the micro RGB light-emitting device is diffusely reflected to form a continuous light spot that smoothly connects with the colors of the real pixels on both sides. Ultimately, the physical dark band that the splicing light tube originally presented at each connector is visually filled in as a continuous light-emitting section indistinguishable from the real pixel light-emitting area of ​​the iridescent light tubes on both sides, making the entire splicing light tube appear as a iridescent light band with continuous and seamless color and brightness.

[0105] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0106] In one embodiment, a pixel compensation device for splicing RGB LED tubes is provided, which corresponds one-to-one with the pixel compensation method for splicing RGB LED tubes in the above embodiments. For example... Figure 9 As shown, the pixel compensation device for splicing the colorful light tubes includes: a data acquisition module 100, an address mapping module 200, a point extraction module 300, a color compensation module 400, a serial processing module 500, and a cascaded transparent transmission module 600.

[0107] Detailed descriptions of each functional module are as follows: The data acquisition module 100 is used to read the device descriptor and perform breakpoint width lookup on the physical topology of the spliced ​​lamp tubes to obtain the device descriptor of adjacent lamp tubes and match the breakpoint physical width constant to obtain the topology parameter set. Address mapping module 200 is used to perform virtual pixel equivalent calculation and logical address continuous expansion processing on the topology parameter set, so as to continuously number the real pixels and virtual pixels of the connector and bind address attributes to obtain a logical address mapping matrix. The point extraction module 300 is used to perform address-by-address scanning and breakpoint control point extraction processing on the pre-extracted video frames based on the logical address mapping matrix, so as to locate the real pixels that are closest to the virtual pixel on the left and right and extract their color values ​​to obtain a set of control points at both ends. Color compensation module 400 is used to perform color space linearization and equal division interpolation calculation on the set of control points at both ends, so as to perform equal division interpolation operation in the linear domain according to the virtual pixel position index to obtain virtual pixel color compensation dataset. The serial processing module 500 is used to perform byte-level bitstream encoding and hardware serialization processing on the virtual pixel color compensation dataset, so as to expand each byte logical bit into SPI bits and output them through DMA to obtain a reconstructed concatenated serial data stream. The cascaded transparent transmission module 600 is used to perform cascaded transparent transmission processing on the recombined cascaded serial data stream, so that the cascaded driver chip of the connector latches and intercepts it one by one and maps it to a preset pulse width modulation unit to obtain a compensation drive signal.

[0108] In one embodiment, the data acquisition module 100 is specifically used for: The chip of the spliced ​​light tube is identified and the light tube description information is burned to obtain the identification data of the end of the light tube; During the power-on initialization phase, the microprocessor inside the connector reads the lamp end identity data to obtain the adjacent lamp device descriptor. The predetermined width of the injection-molded structural component of the joint is retrieved from a table as the physical width constant of the breakpoint, and matched with the descriptor of the adjacent lamp tube device to obtain the joint parameters; Based on the current signature modulation during the power-on handshake, a link cascading sequence number is assigned to the connector and bound to the connector parameters to obtain cascading sequence number binding data; The cascade sequence number binding data is encapsulated into a status report frame and reported to the main controller for aggregation to obtain the topology parameter set.

[0109] In one embodiment, the address mapping module 200 is specifically used for: The physical width constant of each connector breakpoint and the pixel spacing parameter of adjacent lamp tubes are analyzed from the set of topology parameters. The virtual pixel equivalent is obtained by taking the nearest integer of the ratio between the physical width constant of the breakpoint and the pixel spacing parameter; Based on the virtual pixel equivalent, the real pixels and virtual pixels of the connector are sequentially numbered according to the physical order to obtain a unique logical address index; The unique logical address index is bound to the attribute identifier, the corresponding light tube or connector number, and the original physical coordinates to obtain address attribute entry data; The address attribute entry data is expanded into a one-dimensional structure array in a predetermined order and stored in the main controller's storage area to obtain a logical address mapping matrix.

[0110] In one embodiment, the point extraction module 300 is specifically used for: The extracted raw video frame data is decoded and pushed to the frame buffer of the main controller in line order to obtain the video frame data to be processed. The video frame data to be processed is traversed address by address using the logical address mapping matrix as an index to obtain address-by-address scan status data. When the address-by-address scan status data indicates that the current address belongs to a real pixel, the color value at the corresponding position is extracted and written into the buffer to be sent to obtain the real pixel color data; When the address-by-address scan status data indicates that the current address belongs to a virtual pixel, locate the nearest real pixel address to the left and right of the current address to obtain the breakpoint adjacent address data; Based on the breakpoint adjacency address data, the color value corresponding to the current frame is extracted from the real pixel color data and stored in the interpolation task queue, and integrated to obtain the set of control points at both ends.

[0111] In one embodiment, the color compensation module 400 is specifically used for: Extract the actual pixel color values ​​of the left and right ends corresponding to each breakpoint from the set of control points at both ends, and organize them to obtain the endpoint color component data; The endpoint color component data is decoded and mapped by calling the sRGB to linear RGB lookup table pre-stored in memory to obtain the linear domain endpoint color data; Divide the linear domain endpoint color data into equal interpolation intervals to obtain interpolation interval division data; The interpolation interval data is divided into linear equal parts according to the virtual pixel position number of each connector to obtain the linear domain virtual pixel color data. The virtual pixel color data in the linear domain is re-encoded and mapped back to the sRGB domain by calling the reverse lookup table to obtain the virtual pixel color compensation dataset.

[0112] In one embodiment, the serial processing module 500 is specifically used for: The virtual pixel color compensation dataset and the real pixel color data are written into the buffer to be sent according to the address order of the logical address mapping matrix to obtain complete buffer data to be sent. Configure the baud rate of the SPI peripheral so that each non-return-to-zero code bit corresponds to a preset number of SPI byte bits, and obtain the SPI encoded configuration data; According to the SPI encoding configuration data, the logical bits of each byte in the complete buffer data to be sent are expanded into corresponding SPI bits according to a preset high-low ratio rule to obtain byte-by-byte expanded bit stream data; The byte-by-byte expanded bitstream data is concatenated according to the address order of the logical address mapping matrix and stored in the DMA source buffer to obtain DMA source bitstream data; Initiate DMA transfer to send the DMA source bitstream data to a predetermined SPI data register, and output it constantly on the main output pin to obtain a reassembled cascaded serial data stream.

[0113] In one embodiment, the cascaded transparent transmission module 600 is specifically used for: The recombined cascaded serial data is connected to the data input terminal of the first cascaded driver chip in the connector to obtain the connector inlet data stream; The first cascaded driver chip is controlled to perform latching and interception of the preset bit width data at the beginning of the connector inlet data stream to obtain the first chip latched color data; The remaining bit stream of the connector inlet data stream is forwarded one by one to the subsequent cascaded driver chips in the connector through the built-in shaping circuit, so as to obtain the color data latched by each chip. The color data latched by the first chip and the color data latched by each subsequent chip are collected and mapped to the pulse width modulation unit according to the red, green and blue components to obtain the compensation drive signal.

[0114] Specific limitations regarding the pixel compensation device for splicing RGB LED tubes can be found in the limitations of the pixel compensation method for splicing RGB LED tubes mentioned above, and will not be repeated here. Each module in the aforementioned pixel compensation device for splicing RGB LED tubes can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0115] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used to communicate with external clients via a network connection. When the computer program is executed by the processor, it implements the functions or steps of a pixel compensation method for splicing iridescent LED lights on the server side.

[0116] In one embodiment, a computer device is provided, which may be a client, and its internal structure diagram may be as follows: Figure 11 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used to communicate with an external server via a network connection. When the computer program is executed by the processor, it implements the client-side functions or steps of a pixel compensation method for splicing iridescent LED lights.

[0117] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed, can perform the steps provided in the above embodiments.

[0118] It should be noted that the functions or steps that can be implemented by the computer-readable storage medium or computer device described above can be referred to the relevant descriptions on the server side and client side in the foregoing method embodiments. To avoid repetition, they will not be described one by one here.

[0119] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0120] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0121] It should be noted that any AI models, software tools, or components not belonging to this company appearing in the embodiments of this application are merely illustrative examples and do not represent actual use. All user personal information involved in the embodiments of this application has been authorized (with the knowledge and consent) by the relevant parties or has been fully authorized by all parties, and the executing entity may obtain it through various legal and compliant means. The collection, storage, use, processing, transmission, provision, and disclosure of the information, data, and signals involved all comply with relevant laws and regulations and do not violate public order and good morals.

[0122] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A pixel compensation method for splicing multi-color LED tubes, characterized in that, include: The physical topology of the spliced ​​lamp tubes is processed by reading device descriptors and looking up breakpoint widths to obtain the device descriptors of adjacent lamp tubes and match the physical width constants of breakpoints to obtain the topology parameter set. The topology parameter set is subjected to virtual pixel equivalent calculation and logical address continuous expansion processing to continuously number the real pixels and virtual pixels of the connector and bind address attributes to obtain a logical address mapping matrix. Based on the logical address mapping matrix, the pre-extracted video frames are scanned address by address and the breakpoint control point is extracted to locate the real pixels that are closest to the virtual pixel on the left and right and extract their color values ​​to obtain the set of control points at both ends. The set of control points at both ends is subjected to color space linearization and equal division interpolation calculation, so that equal division interpolation is performed in the linear domain according to the virtual pixel position index to obtain the virtual pixel color compensation dataset. The virtual pixel color compensation dataset is subjected to byte-level bitstream encoding and hardware serialization to expand each byte logical bit into SPI bits and output them via DMA to obtain a reconstructed concatenated serial data stream. The recombined cascaded serial data stream is subjected to cascaded transparent transmission processing, so that the cascaded driver chips of the connector are latched and intercepted one by one and mapped to a preset pulse width modulation unit to obtain a compensation drive signal.

2. The pixel compensation method for splicing multi-color LED tubes according to claim 1, characterized in that, The physical topology of the spliced ​​lamp tubes is processed by reading device descriptors and looking up breakpoint widths in a table to obtain the device descriptors of adjacent lamp tubes and match the breakpoint physical width constants, thus obtaining a set of topology parameters, including: The chip of the spliced ​​light tube is identified and the light tube description information is burned to obtain the identification data of the end of the light tube; During the power-on initialization phase, the microprocessor inside the connector reads the lamp end identity data to obtain the adjacent lamp device descriptor. The predetermined width of the injection-molded structural component of the joint is retrieved from a table as the physical width constant of the breakpoint, and matched with the descriptor of the adjacent lamp tube device to obtain the joint parameters; Based on the current signature modulation during the power-on handshake, a link cascading sequence number is assigned to the connector and bound to the connector parameters to obtain cascading sequence number binding data; The cascade sequence number binding data is encapsulated into a status report frame and reported to the main controller for aggregation to obtain the topology parameter set.

3. The pixel compensation method for splicing multi-color LED tubes according to claim 1, characterized in that, The process of performing virtual pixel equivalent calculation and logical address continuation expansion on the topology parameter set to continuously number and bind address attributes to the real and virtual pixels of the connector, resulting in a logical address mapping matrix, includes: The physical width constant of each connector breakpoint and the pixel spacing parameter of adjacent lamp tubes are analyzed from the set of topology parameters. The virtual pixel equivalent is obtained by taking the nearest integer of the ratio between the physical width constant of the breakpoint and the pixel spacing parameter; Based on the virtual pixel equivalent, the real pixels and virtual pixels of the connector are sequentially numbered according to the physical order to obtain a unique logical address index; The unique logical address index is bound to the attribute identifier, the corresponding light tube or connector number, and the original physical coordinates to obtain address attribute entry data; The address attribute entry data is expanded into a one-dimensional structure array in a predetermined order and stored in the main controller's storage area to obtain a logical address mapping matrix.

4. The pixel compensation method for splicing multi-color LED tubes according to claim 1, characterized in that, The process of performing address-by-address scanning and breakpoint control point extraction on pre-extracted video frames based on the logical address mapping matrix, in order to locate the nearest real pixels to the left and right of the virtual pixel and extract their color values, yields a set of control points at both ends, including: The extracted raw video frame data is decoded and pushed to the frame buffer of the main controller in line order to obtain the video frame data to be processed. The video frame data to be processed is traversed address by address using the logical address mapping matrix as an index to obtain address-by-address scan status data. When the address-by-address scan status data indicates that the current address belongs to a real pixel, the color value at the corresponding position is extracted and written into the buffer to be sent to obtain the real pixel color data; When the address-by-address scan status data indicates that the current address belongs to a virtual pixel, locate the nearest real pixel address to the left and right of the current address to obtain the breakpoint adjacent address data; Based on the breakpoint adjacency address data, the color value corresponding to the current frame is extracted from the real pixel color data and stored in the interpolation task queue, and integrated to obtain the set of control points at both ends.

5. The pixel compensation method for splicing multi-color LED tubes according to claim 1, characterized in that, The step of performing color space linearization and equal-division interpolation on the set of control points at both ends, to perform equal-division interpolation in the linear domain according to the virtual pixel position index, yields a virtual pixel color compensation dataset, including: Extract the actual pixel color values ​​of the left and right ends corresponding to each breakpoint from the set of control points at both ends, and organize them to obtain the endpoint color component data; The endpoint color component data is decoded and mapped by calling the sRGB to linear RGB lookup table pre-stored in memory to obtain the linear domain endpoint color data; Divide the linear domain endpoint color data into equal interpolation intervals to obtain interpolation interval division data; The interpolation interval data is divided into linear equal parts according to the virtual pixel position number of each connector to obtain the linear domain virtual pixel color data. The virtual pixel color data in the linear domain is re-encoded and mapped back to the sRGB domain by calling the reverse lookup table to obtain the virtual pixel color compensation dataset.

6. The pixel compensation method for splicing multi-color LED tubes according to claim 4, characterized in that, The step of performing byte-level bitstream encoding and hardware serialization on the virtual pixel color compensation dataset to expand each byte logical bit into SPI bits and output them via DMA to obtain a reassembled concatenated serial data stream includes: The virtual pixel color compensation dataset and the real pixel color data are written into the buffer to be sent according to the address order of the logical address mapping matrix to obtain complete buffer data to be sent. Configure the baud rate of the SPI peripheral so that each non-return-to-zero code bit corresponds to a preset number of SPI byte bits, and obtain the SPI encoded configuration data; According to the SPI encoding configuration data, the logical bits of each byte in the complete buffer data to be sent are expanded into corresponding SPI bits according to a preset high-low ratio rule to obtain byte-by-byte expanded bit stream data; The byte-by-byte expanded bitstream data is concatenated according to the address order of the logical address mapping matrix and stored in the DMA source buffer to obtain DMA source bitstream data; Initiate DMA transfer to send the DMA source bitstream data to a predetermined SPI data register, and output it constantly on the main output pin to obtain a reassembled cascaded serial data stream.

7. The pixel compensation method for splicing multi-color LED tubes according to claim 1, characterized in that, The cascaded transparent transmission processing of the recombined cascaded serial data stream, wherein each cascaded driver chip of the connector is latched, intercepted, and mapped to a preset pulse width modulation unit to obtain a compensation drive signal, includes: The recombined cascaded serial data is connected to the data input terminal of the first cascaded driver chip in the connector to obtain the connector inlet data stream; The first cascaded driver chip is controlled to perform latching and interception of the preset bit width data at the beginning of the connector inlet data stream to obtain the first chip latched color data; The remaining bit stream of the connector inlet data stream is forwarded one by one to the subsequent cascaded driver chips in the connector through the built-in shaping circuit, so as to obtain the color data latched by each chip. The color data latched by the first chip and the color data latched by each subsequent chip are collected and mapped to the pulse width modulation unit according to the red, green and blue components to obtain the compensation drive signal.

8. A pixel compensation device for splicing iridescent light tubes, characterized in that, include: The data acquisition module is used to read the device descriptor and perform breakpoint width lookup on the physical topology of the spliced ​​lamp tubes to obtain the device descriptors of adjacent lamp tubes and match the breakpoint physical width constant to obtain the topology parameter set. The address mapping module is used to perform virtual pixel equivalent calculation and logical address continuous expansion processing on the topology parameter set, so as to continuously number the real pixels and virtual pixels of the connector and bind address attributes to obtain a logical address mapping matrix. The point extraction module is used to perform address-by-address scanning and breakpoint control point extraction processing on the pre-extracted video frames based on the logical address mapping matrix, so as to locate the real pixels that are closest to the virtual pixel on the left and right and extract their color values ​​to obtain the set of control points at both ends. The color compensation module is used to perform color space linearization and equal division interpolation calculation on the set of control points at both ends, so as to perform equal division interpolation operation in the linear domain according to the virtual pixel position index to obtain the virtual pixel color compensation dataset. The serial processing module is used to perform byte-level bitstream encoding and hardware serialization processing on the virtual pixel color compensation dataset, so as to expand each byte logical bit into SPI bits and output them through DMA to obtain a reconstructed concatenated serial data stream. The cascaded transparent transmission module is used to perform cascaded transparent transmission processing on the recombined cascaded serial data stream, so that the cascaded driver chip of the connector latches and intercepts it one by one and maps it to a preset pulse width modulation unit to obtain a compensation drive signal.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the pixel compensation method for splicing RGB LED tubes as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the pixel compensation method for splicing RGB LED tubes as described in any one of claims 1 to 7.

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