In-memory logic sensing circuit of magnetic random access memory and driving control method thereof
By designing an in-memory logic sensing circuit for magnetic random access memory (MRAM) and utilizing a complementary latch structure composed of a reference resistor and transistors, the logic operation results can be directly sensed, thus solving the problems of write errors and area overhead in the STT-MRAM in-memory computing platform and improving the computing speed and efficiency.
CN122290656APending Publication Date: 2026-06-26BEIJING SUPERSTRING ACAD OF MEMORY TECH +1
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2026-03-03
- Publication Date
- 2026-06-26
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Figure CN122290656A_ABST
Abstract
This disclosure provides an in-memory logic sensing circuit for a magnetic random access memory (RAM). The circuit includes a reference resistor, a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, and a fourth N-type transistor. This disclosure, through the design and implementation of the in-memory logic sensing circuit, utilizes fewer components to sense the logic operation results of two parallel magnetic tunnel junctions. The output of the in-memory logic sensing circuit directly represents the logic operation result, eliminating the need for external logic operations. This reduces on-chip area while increasing processing speed. Furthermore, the current during the sensing process does not directly pass through the magnetic tunnel junctions, avoiding the problem of erroneous writing to the magnetic tunnel junctions during output.
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