A write voltage regulation circuit for ferroelectric memory

Abstract

This invention provides a write voltage regulation circuit for ferroelectric memory, comprising: a main array unit for performing read and write operations on the ferroelectric memory; a monitoring array unit for performing a pre-read / write operation using an external monitoring voltage before the formal read / write operation to determine the writable voltage; a row and column decoder for decoding input address data, determining the rows and columns for read / write operations, and activating the decoder; a latch for latching the read data; an error detection unit for detecting whether the read data read from the monitoring array unit is erroneous based on the write data of the fixed write monitoring array unit; a boost charge pump for boosting the external monitoring voltage; and a drive control unit for driving control such that the pre-read / write operation is performed after the row and column decoder activates the rows and columns to be read / written by the main array unit, and in the pre-read / write operation, the main array unit also performs read / write operations simultaneously with the monitoring array unit using the external monitoring voltage.

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