Memory device and operating method of the memory device

Abstract

This application relates to a memory device and a method of operating the memory device. A memory device includes: a memory block comprising a first sub-block and a second sub-block located between a source line and a bit line; peripheral circuitry configured to perform an erase operation on the memory block and, prior to the erase operation, sequentially perform pre-programming operations on the first and second sub-blocks; and control circuitry configured to control the peripheral circuitry, wherein each of the first and second sub-blocks includes a first selection transistor, a memory cell, and a second selection transistor disposed between the source line and the bit line, and wherein the control circuitry is configured to control the peripheral circuitry to apply a first pre-programming voltage to a word line coupled to a memory cell during the pre-programming operation of the first sub-block, and to apply a second pre-programming voltage lower than the first pre-programming voltage to the word line during the pre-programming operation of the second sub-block.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method of operating the memory device, and more specifically, to a memory device configured to perform pre-programmed operations prior to an erase operation and a method of operating the memory device. Background Technology

[0002] A memory device configured to store data may include a memory cell array, peripheral circuitry, and control circuitry. The memory cell array may include memory blocks, and each memory block may include memory cells in which data is stored. The peripheral circuitry may program, read, or erase the memory cells under the control of the control circuitry. The control circuitry may, in response to commands, control the peripheral circuitry to perform programming, reading, or erasing operations.

[0003] The memory block can be implemented as a three-dimensional (3D) structure. In a memory block implemented as a 3D structure, memory cells are stacked in a direction perpendicular to the substrate. For example, in a memory block implemented as a 3D structure, memory cells can be stacked along plugs extending vertically from the substrate.

[0004] Due to the nature of the manufacturing process of memory devices, memory cells can have different sizes depending on their location. Memory cells of different sizes can have different electrical characteristics due to physical differences. For example, a memory cell positioned closer to the outer edge of the memory block can have a larger size than a memory cell positioned in the central region of the memory block, and the size of an upper memory cell in a stacked memory cell may be larger than the size of a lower memory cell.

[0005] The size differences of memory cells can increase the time required for both erase and programming operations within a memory device. For example, during a block erase operation, while memory cells with relatively slower erase rates are erased, memory cells with relatively faster erase rates may be over-erased. Over-erased memory cells can increase the time required for subsequent programming operations. Summary of the Invention

[0006] According to an embodiment, a memory device may include: a memory block comprising a first sub-block and a second sub-block located between a source line and a bit line; peripheral circuitry configured to perform an erase operation on the memory block and, prior to the erase operation, sequentially perform pre-programming operations on the first sub-block and the second sub-block; and control circuitry configured to control the peripheral circuitry. Each of the first sub-block and the second sub-block includes a first selection transistor, a memory cell, and a second selection transistor disposed between the source line and the bit line. The control circuitry is configured to control the peripheral circuitry to apply a first pre-programming voltage to a word line coupled to the memory cell during a pre-programming operation on the first sub-block, and to apply a second pre-programming voltage lower than the first pre-programming voltage to the word line during a pre-programming operation on the second sub-block.

[0007] According to an embodiment, a method of operating a memory device includes the steps of: performing a first pre-programming operation on the first sub-block by applying a first pre-programming voltage to word lines connected to the first sub-block and the second sub-block before an erase operation on a memory block including a first sub-block and a second sub-block located between the first sub-block; and performing a second pre-programming operation on the second sub-block by applying a second pre-programming voltage lower than the first pre-programming voltage to the word lines after performing the first pre-programming operation on the first sub-block. Attached Figure Description

[0008] Figure 1 It is a diagram used to describe a memory system.

[0009] Figure 2 It is a diagram used to describe a memory device.

[0010] Figure 3 It is a diagram used to describe an array of memory cells.

[0011] Figure 4 It is a circuit diagram used to describe a memory block;

[0012] Figure 5 It is a cross-sectional diagram used to describe the structure of the string;

[0013] Figure 6 It is a planar diagram used to describe the structure of a string;

[0014] Figure 7 It is a diagram used to describe storage blocks that have defined isolated regions;

[0015] Figure 8 It is a cross-sectional view used to describe a storage block including an isolation pattern;

[0016] Figure 9This is a diagram illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0017] Figure 10 It is a diagram used to describe the threshold voltage distribution of a memory cell according to an embodiment of the present disclosure;

[0018] Figure 11A and Figure 11B It is a diagram used to describe the pre-programmed operations according to the first embodiment of this disclosure;

[0019] Figure 12 This is a diagram used to describe the pre-programmed operations according to the second embodiment of this disclosure;

[0020] Figure 13 This is a diagram used to describe the pre-programmed operations according to the third embodiment of this disclosure;

[0021] Figure 14 This is a diagram used to describe the pre-programmed operations according to the fourth embodiment of this disclosure;

[0022] Figure 15 This is a diagram used to describe the pre-programmed operations according to the fifth embodiment of this disclosure;

[0023] Figure 16 This is a diagram used to describe the pre-programmed operations according to the sixth embodiment of this disclosure;

[0024] Figure 17 This is a diagram illustrating a memory card system employing a memory device according to an embodiment of the present disclosure; and

[0025] Figure 18 This is a diagram illustrating a solid-state drive (SSD) system for a memory device applied according to an embodiment of the present disclosure. Detailed Implementation

[0026] Specific structural or functional descriptions of examples of embodiments based on the concepts disclosed in this specification are shown only to describe embodiments based on the concepts disclosed herein. Examples of embodiments based on the concepts may be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0027] While terms such as “first” and “second” may be used to identify various components, these components should not be construed as being limited by these terms. These terms are used to distinguish one component from another and are not intended to indicate the number or order of components.

[0028] According to some embodiments of the present disclosure, the memory device and the method of operating the memory device improve the threshold voltage distribution of the memory cells during an erase operation, thereby reducing the time required for a programming operation.

[0029] Figure 1 This is a diagram used to describe memory system 1000.

[0030] Reference Figure 1 The memory system 1000 may include a memory device 100, a controller 200, and a host 300.

[0031] The memory device 100 can store data. The memory device 100 can be a non-volatile memory device. A non-volatile memory device is a device that retains stored data even when power is cut off.

[0032] The controller 200 can communicate between the host 300 and the memory device 100. The controller 200 can control the memory device 100 based on requests (RQs) received from the host 300. For example, upon receiving a request (RQ) for a programming operation from the host 300, the controller 200 can generate a command (CMD) for the programming operation and transmit the generated command (CMD) to the memory device 100. Upon receiving a request (RQ) for a read operation from the host 300, the controller 200 can generate a command (CMD) for the read operation and transmit the generated command (CMD) to the memory device 100. Upon receiving a request (RQ) for an erase operation from the host 300, the controller 200 can generate a command (CMD) for the erase operation and transmit the generated command (CMD) to the memory device 100.

[0033] The host 300 can communicate with the storage device 100 via the controller 200 using interface protocols such as Fast Peripheral Component Interconnect (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). The interface protocols are not limited to the examples above and may include various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Digital Disk Interface (ESDI), Integrated Drive Electronics (IDE), etc.

[0034] The memory device 100 according to the embodiment can adjust the pre-programming operation performed before the erase operation to shorten the time spent on the programming operation. For example, in the pre-programming operation, the memory device can adjust the programming voltage applied to the word line according to the position of the string included in the memory block. In addition to the programming voltage, the memory device can also adjust the voltage applied to at least one of the source line, bit line, drain select line, and source select line.

[0035] Figure 2 It is a diagram used to describe a memory device.

[0036] Reference Figure 2The memory device 100 may include a memory cell array 110 for storing data and peripheral circuitry 180 for performing programming, reading and erasing operations.

[0037] The memory cell array 110 may include first memory blocks BLK1 to j-th memory blocks BLKj for storing data. Each of the first memory blocks BLK1 to j-th memory blocks BLKj includes a plurality of memory cells, and the memory cells may be implemented in a two-dimensional structure in which the memory cells are arranged parallel to the substrate or in a three-dimensional structure in which the memory cells are stacked in a direction perpendicular to the substrate. According to this embodiment, the first memory blocks BLK1 to j-th memory blocks BLKj may be implemented in a three-dimensional structure. Drain select line DSL, word line WL, and source select line SSL may be connected to each of the first memory blocks BLK1 to j-th memory blocks BLKj. Source line SL may be collectively connected to the first memory blocks BLK1 to j-th memory blocks BLKj. The memory cell may store at least one bit of data according to the programming method. For example, when programming is performed in a single-level cell (SLC) manner, one bit of data may be stored in one memory cell. When programming is performed in a multi-level cell (MLC) manner, two or more bits of data may be stored in one memory cell. For example, when programming in a three-level cell (TLC) manner, three bits of data can be stored in one memory cell, and four bits of data can be stored in a four-level cell (QLC) manner in one memory cell. Furthermore, depending on the programming method, five or more bits of data can be stored in one memory cell.

[0038] The peripheral circuitry 180 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuitry 160, and a control circuitry 170. In some embodiments, the control circuitry 170 is separate from and not included in the peripheral circuitry 180.

[0039] Voltage generator 120 can generate and output operating voltages Vop for various operations in response to operation code OPCD. For example, voltage generator 120 can generate and output programming voltage, verification voltage, read voltage, pass voltage, erase voltage, conduction voltage, negative voltage, etc. Voltage generator 120 can change the level of each of the operating voltages Vop in response to operation code OPCD, and can adjust the output time of each of the operating voltages Vof.

[0040] The row decoder 130 can select one of the first memory blocks BLK1 to j-th memory blocks BLKj included in the memory cell array 110 according to the row address RADD, and the row decoder 130 can transmit the operating voltage Vop to the selected memory block.

[0041] Page buffer group 140 can be coupled to memory cell array 110 via bit line BL. For example, page buffer group 140 may include page buffers (not shown) coupled to bit line BL. Page buffers can operate in parallel in response to page buffer control signal PBSIG and can temporarily store data during programming or read operations. For this purpose, each of the page buffers may include multiple latches for temporary data storage. The number of latches may vary depending on the programming method.

[0042] The column decoder 150 can transfer data DATA between the input / output circuit 160 and the page buffer group 140 according to the column address CADD.

[0043] Input / output circuit 160 can be connected to controller 200 via input / output line I / O. Input / output circuit 160 can input / output commands (CMD), addresses (ADD), and data (DATA) via input / output line I / O. For example, input / output circuit 160 can transmit commands (CMD) and addresses (ADD) received via input / output line I / O to control circuit 170, and can transmit data (DATA) received via input / output line I / O to column decoder 150. Input / output circuit 160 can output data (DATA) received from column decoder 150 to an external device via input / output line I / O.

[0044] Control circuit 170 can output operation code OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD in response to command CMD and address ADD. For example, control circuit 170 may include software for performing programming, reading, or erasing operations in response to command CMD and address ADD, and control circuit 170 may include hardware for outputting operation code OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD under software control. For different implementations, control circuit 170 may be configured with firmware that controls control circuit 170 to perform the operations described herein. Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 The described operation.

[0045] Control circuit 170 can control peripheral circuit 180 to initiate pre-programming operations for the selected memory block to be performed prior to the erase operation of the selected memory block. For example, control circuit 170 can control peripheral circuit 180 to perform pre-programming operations for selected sub-blocks included in the selected memory block and pre-programming operations for unselected sub-blocks at different times. For example, during the pre-programming operation of a sub-block included in and located outside the selected memory block, control circuit 170 can control peripheral circuit 180 to apply a first pre-programming voltage to the word line connected to the selected memory block. During the pre-programming operation of a sub-block within the selected memory block located in the inner or central region of the selected memory block, control circuit 170 can control peripheral circuit 180 to apply a second pre-programming voltage lower than the first pre-programming voltage to the word line connected to the selected memory block. Control circuit 170 can modify the operation code OPCD to adjust the level of the pre-programming voltage applied to the word line WL according to the selected sub-blocks of the selected memory block. During the pre-programming operation, the control circuit 170 can change the operation code OPCD so that the level and duration of the voltages applied to the drain select line, source select line, bit line, and source line, in addition to the pre-programming voltage, are also adjusted.

[0046] Figure 3 This is a diagram used to describe the memory cell array 110.

[0047] Reference Figure 3 The memory cell array 110 may include first memory blocks BLK1 to j-th memory blocks BLKj, where "j" is a positive integer. The first memory blocks BLK1 to j-th memory blocks BLKj may be spaced apart from each other in the Y direction, and they may be located between the source line SL and the first bit line BL1 to the i-th bit line BLi, where "i" is a positive integer. The drain select line DSL, the word line WL, and the source select line SSL may be connected to each of the first memory blocks BLK1 to j-th memory blocks BLKj. Figure 2 The operating voltage Vop shown can be applied through the drain select line DSL, word line WL, source select line SSL, and source line SL of the selected memory blocks from the first memory block BLK1 to the j-th memory block BLKj, and the drain select line DSL, word line WL, and source select line SSL connected to the remaining unselected memory blocks can be floated. Pre-programming operations according to this embodiment can be performed on the selected memory blocks from the first memory block BLK1 to the j-th memory block BLKj.

[0048] Figure 4 It is a circuit diagram used to describe a memory block.

[0049] Reference Figure 4Since memory blocks can be configured identically to each other, the j-th memory block BLKj is shown as an example. The j-th memory block BLKj may include a string ST connected between the source line SL and the first bit lines BL1 to ith bit lines BLi. The string ST may be connected to the source line SL. The first bit lines BL1 to ith bit lines BLi may be arranged spaced apart from each other in the X direction, and each bit line among the first bit lines BL1 to ith bit lines BLi may extend in the Y direction. The strings arranged in the Y direction may be connected to each bit line among the first bit lines BL1 to ith bit lines BLi, and the strings arranged in the X direction may be connected to different bit lines among the first bit lines BL1 to ith bit lines BLi.

[0050] The number of source selection transistors SST, first memory cells M1 to nth memory cells Mn, and drain selection transistors DST included in each of the strings ST can vary depending on the memory device. For example, although Figure 4 The diagram shows that each of the strings ST includes a source select transistor SST and a drain select transistor DST, but each string ST may also include multiple source select transistors SST and multiple drain select transistors DST arranged along the Z direction.

[0051] The gates of the source select transistors SST in different strings ST can be connected to the source select line SSL, the gates of the first memory cell M1 to the nth memory cell Mn can be connected to the first word line WL1 to the nth word line WLn, and the gates of the drain select transistors DST can be connected to the first drain select line DSL1 to the fourth drain select line DSL4, where "n" is a positive integer. The number of drain select lines can vary depending on the memory device and is therefore not limited to... Figure 4 The quantity shown.

[0052] Source select lines SSL can be connected together to source select transistors SST arranged along the X and Y directions. However, some source select lines SSL arranged along the Y direction can be spaced apart. Each of the first word lines WL1 to the nth word line WLn can be connected together to memory cells arranged along the X and Y directions. For example, the nth memory cell Mn arranged along the X and Y directions can be connected together to the nth word line WLn, and the nth word lines WLn can be connected to each other. For example, the (n-1)th memory cell M(n-1) arranged along the X and Y directions can be connected together to the (n-1)th word line WL(n-1), and the (n-1)th word lines WL(n-1) can be connected to each other. The nth word line WLn and the (n-1)th word line WL(n-1) are spaced apart. The group of memory cells that are connected together to one of the word lines from the first word line WL1 to the nth word line WLn is a page PG. For example, the fourth memory cell M4, which is connected to the fourth word line WL4, is grouped into a page PG. Programming and read operations can be performed on a page (PG) basis. When the fourth word line WL4 is the selected word line, the remaining word lines are unselected word lines.

[0053] The first drain select lines DSL1 to the fourth drain select lines DSL4 are spaced apart from each other. Each of the first drain select lines DSL1 to the fourth drain select lines DSL4 can be connected together to a drain select transistor DST arranged along the X direction. Therefore, during programming or reading operations, the memory cells included in the string ST connected to the selected drain select line of the first drain select lines DSL1 to the fourth drain select lines DSL4 can be selected.

[0054] When the source select transistor SST is turned on, the voltage supplied to the source line SL can be applied to the channel of the series ST. When the source select transistor SST is turned off, the source line SL and the series ST can be electrically disconnected. The source select transistor SST can be turned on when a turn-on voltage is applied to the first source select line SSL1 or the second source select line SSL2, and turned off when a cut-off voltage is applied. For example, when a turn-on voltage is applied to the first source select line SSL1 and a cut-off voltage is applied to the second source select line SSL2, the source select transistor connected to the first source select line SSL1 is turned on, and the source select transistor SST connected to the second source select line SSL2 is turned off. The turn-on voltage can be a positive voltage higher than 0V, and the cut-off voltage can be ground voltage or a negative voltage lower than 0V.

[0055] When the drain select transistor DST is turned on, the voltage supplied to the first bit line BL1 to the i-th bit line BLi can be applied to the channel of the series ST. When the drain select transistor DST is turned off, the first bit line BL1 to the i-th bit line Bli and the series ST can be electrically disconnected. As an example, referring to the drain select transistor DST connected to the first drain select line DSL1, when an on-state voltage is applied to the first drain select line DSL1, the drain select transistor DST can be turned on, and when an off-state voltage is applied, the drain select transistor DST can be turned off. The on-state voltage applied to the first drain select line DSL1 can also be a positive voltage higher than 0V, and the off-state voltage can also be a ground voltage or a negative voltage lower than 0V.

[0056] Figure 5 It is a cross-sectional view used to describe the structure of the string ST, and Figure 6 It is a planar diagram used to describe the structure of the string ST.

[0057] Reference Figure 5 and Figure 6 The string ST may include a plug PL that passes through the source select line SSL, the first word line WL1 to the nth word line WLn, and the drain select line DSL, which are stacked at a certain distance from each other. The source select line SSL, the first word line WL1 to the nth word line WLn, and the drain select line DSL may include, but are not limited to, metallic materials such as tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), or semiconductor materials such as silicon (Si) or polysilicon (Poly-Si). The plug PL may extend in the Z direction between the source line SL and the i-th bit line BLi. The bit line contact Cb may be located between the plug PL and the i-th bit line BLi.

[0058] The plug PL may include a core post CP, a channel layer CH, a tunnel isolation layer TX, a charge trapping layer CTL, and a barrier layer BX. The core post CP may be in the form of a cylinder, square post, or polygonal post, and may include insulating or conductive materials. The channel layer CH may surround the core post CP and include polysilicon. The tunnel isolation layer TX may surround the channel layer CH and include an oxide layer. The charge trapping layer CTL may surround the tunnel isolation layer TX and include a nitride film. The barrier layer BX may surround the charge trapping layer CTL and include an oxide layer. The lower portion of the channel layer CH may contact the source line SL, while the upper portion of the channel layer CH may contact the bit line contact Cb. The bit line contact Cb may be located between the i-th bit line BLi and the plug PL.

[0059] Due to the characteristics of the manufacturing process, the plug PL extending in the Z direction can have a width that varies with its height. Specifically, the width of the plug PL can increase as the height in the Z direction increases. In other words, the width of the plug PL can narrow from the top to the bottom. For example, when the first word line WL1 to the nth word line WLn connected to the string ST is at its lowest position and the nth word line WLn is at its highest position, assuming that the portion of the plug PL that contacts the nth word line WLn has a first width W1, then the portion of the plug PL that contacts the first word line WL1 can have a second width W2 that is smaller than the first width W1.

[0060] Figure 6 The planar structure of the plug PL, cut along the A1-A2 direction, is shown.

[0061] Reference Figure 6 The plug PL may include a core post CP, a channel layer CH, a tunnel isolation layer TX, a charge trapping layer CTL, and a barrier layer BX. The channel layer CH may surround the core post CP. The tunnel isolation layer TX may surround the channel layer CH. The charge trapping layer CTL may surround the tunnel isolation layer TX. The barrier layer BX may surround the charge trapping layer CTL. The word line WL may surround the barrier layer BX.

[0062] Figure 7 It is a diagram used to describe storage blocks that have defined isolated regions.

[0063] Reference Figure 7 The (N-1)th storage block BLK(N-1), the Nth storage block BLKN, and the (N+1)th storage block BLK(N+1) can be spaced apart from each other in the Y direction, where "N" is a positive integer. The (N-1)th storage block BLK(N-1), the Nth storage block BLKN, and the (N+1)th storage block BLK(N+1) can be spaced apart from each other by a first slit 1SLT and a second slit 2SLT. For example, the (N-1)th storage block BLK(N-1) and the Nth storage block BLKN can be spaced apart from each other by the first slit 1SLT, and the Nth storage block BLKN and the (N+1)th storage block BLK(N+1) can be spaced apart from each other by the second slit 2SLT. The (N-1)th storage block BLK(N-1), the Nth storage block BLKN, and the (N+1)th storage block BLK(N+1) can be configured to be identical; therefore, the Nth storage block BLKN is described below as a representative example.

[0064] In the Nth memory block BLKN, a first upper isolation region 1UDR to a third upper isolation region 3UDR and a lower isolation region DDR can be defined. Each of the first upper isolation regions 1UDR to the third upper isolation region 3UDR extends along the X direction on the top of the Nth memory block BLKN. The drain select lines included in the Nth memory block BLKN are separated by the first upper isolation regions 1UDR to the third upper isolation regions 3UDR. The lower isolation region DDR of the Nth memory block BLKN also extends in the X direction. The source select lines included in the Nth memory block BLKN are separated by the lower isolation region DDR. For example, the Nth memory block BLKN may include multiple sub-blocks 1SB and 2SB divided by the first upper isolation regions 1UDR to the third upper isolation regions 3UDR. The first sub-block 1SB may be located on the outer edge of the Nth memory block BLKN, and the second sub-block 2SB may be located in the middle of the Nth memory block BLKN between the first sub-blocks 1SB. For example, one of the first sub-blocks 1SB may be adjacent to the first slit 1SLT, while the other first sub-block 1SB may be adjacent to the second slit 2SLT. Therefore, the second sub-block 2SB may be located between the first sub-blocks 1SB. Although the strings included in each of the first sub-blocks 1SB and the second sub-block 2SB have substantially the same size, due to limitations in the manufacturing process of the memory device, the strings may have different sizes depending on their location. For example, the size of the string included in the first sub-block 1SB may be larger than the size of the string included in the second sub-block 2SB. When the string sizes differ, the sizes of the memory cells may also differ. When memory cells have different sizes, even if the same voltage is applied to the memory cells, the memory cells may be programmed or erased at different speeds. When memory cells are programmed or erased at different speeds, the time required for programming or erasing operations may increase, and the distribution of the threshold voltage of the memory cells may widen. Therefore, embodiments of this disclosure provide a technique to prevent or mitigate the degradation of the threshold voltage distribution due to differences in the size of the memory cells, thereby reducing the time required for programming operations.

[0065] Figure 8 This is a cross-sectional view used to describe a storage block including an isolation pattern, and it shows how by... Figure 7 The cross-section is obtained by cutting the Nth storage block BLKN into the YZ plane, as shown in the figure.

[0066] Reference Figure 8The memory block may include a stacked structure STA located between source line SL and bit line BL, and the memory block may include a plug PL located in the stacked structure STA. Bit line contacts Cb may be located between the stacked structure STA and the bit line BL. The plug PL may extend to the bottom or top of the stacked structure STA, or the plug PL may extend to both the bottom and top of the stacked structure STA. The bottom of the plug PL may be adjacent to or extend into the source line SL, while the top of the plug PL may be adjacent to the bit line contact Cb. The plug PL may be adjacent to the bit line contact Cb individually, and the bit line contact Cb may collectively be adjacent to the bit line BL. The plug PL may include memory cells, and refers to... Figure 6 This describes the structure of each plug in the PL. A plug PL containing memory cells can be located within a stacked structure STA. A plug PL can extend in the Z direction.

[0067] The stacked structure STA may include an interlayer insulating layer ISL, a first source select line SSL1 and a second source select line SSL2, a word line WL, and first drain select lines DSL1 to fourth drain select lines DSL4. The interlayer insulating layer ISL may include a silicon oxide layer. The first source select lines SSL1 and SSL2, the word line WL, and the first drain select lines DSL1 to fourth drain select lines DSL4 may include the same conductive film. For example, the first source select lines SSL1 and SSL2, the word line WL, and the first drain select lines DSL1 to fourth drain select lines DSL4 may include metallic materials such as tungsten (W), molybdenum (Mo), cobalt (Co), and nickel (Ni), or semiconductor materials such as silicon (Si) or polysilicon (Poly-Si).

[0068] The first source select line SSL1 and the second source select line SSL2 can be separated from each other by the lower isolation pattern DDP. The lower isolation pattern DDP is formed in the lower isolation region ( Figure 7 The insulating pattern in the DDR (DDR) is as follows. The first source select line SSL1 can be stacked on top of each other, and the second source select line SSL2 can be stacked on top of each other. The number of stacks of the first source select line SSL1 and the second source select line SSL2 can vary depending on the memory device. Word lines WL can be located above the first source select line SSL1 and the second source select line SSL2. Each word line WL extends in the XY plane and is spaced apart from other word lines WL in the Z direction. The first drain select line DSL1 to the fourth drain select line DSL4 can be separated from each other by the first upper isolation pattern 1UDP to the third upper isolation pattern 3UDP. The first upper isolation pattern 1UDP to the third upper isolation pattern 3UDP are formed on... Figure 7The insulating patterns shown are in the first upper isolation region 1UDR to the third upper isolation region 3UDR. For example, the first upper isolation pattern 1UDP is formed in... Figure 7 The isolation pattern shown is in the first upper isolation region 1UDR, and the second upper isolation pattern 2UDP is formed in... Figure 7 The isolation pattern in the second upper isolation region 2UDR, and the third upper isolation pattern 3UDP are formed in Figure 7 The isolation patterns in the third upper isolation region 3UDR are shown. The first upper isolation pattern 1UDP separates the first drain select line DSL1 and the second drain select line DSL2 from each other, the second upper isolation pattern 2UDP separates the second drain select line DSL2 and the third drain select line DSL3 from each other, and the third upper isolation pattern 3UDP separates the third drain select line DSL3 and the fourth drain select line DSL4 from each other.

[0069] The first drain select line DSL1 can be stacked on top of each other, the second drain select line DSL2 can be stacked on top of each other, the third drain select line DSL3 can be stacked on top of each other, and the fourth drain select line DSL4 can be stacked on top of each other. The number of stacked first drain select lines DSL1 to fourth drain select lines DSL4 can vary depending on the memory device.

[0070] The first subblock 1SB and the second subblock 2SB can be distinguished by the first upper isolation pattern 1UDP to the third upper isolation pattern 3UDP. Therefore, the plug PL connected to the first drain select line DSL1 is included in the first subblock 1SB, the plug PL connected to the second drain select line DSL2 is included in the second subblock 2SB, the plug PL connected to the third drain select line DLS3 is included in the second subblock 2SB, and the plug PL connected to the fourth drain select line DSL4 is included in the first subblock 1SB.

[0071] Figure 9 This is a diagram illustrating a method of operating a memory device according to an embodiment of the present disclosure, and Figure 10 This is a diagram showing the threshold voltage distribution of a memory cell according to an embodiment.

[0072] Reference Figure 9 and Figure 10The erase operation of a memory block is an operation that reduces the threshold voltage distribution of a memory cell to an erase state. Therefore, the memory block selected for the erase operation can be a memory block that has already undergone a master programming operation (101). When the master programming operation is performed in a multi-level cell (MLC) manner instead of a single-level cell (SLC) manner, the programmed memory cell can have two or more threshold voltage distributions. In the embodiments described below, the master programming operation is performed in a three-level cell (TLC) manner, but this teaching is not limited to the three-level cell (TLC) manner. When the programming operation is performed in the three-level cell (TLC) manner, the memory cell can be in an erase state ER or in one of the first programming states P1 to the seventh programming states P7 (101).

[0073] Before performing an erase operation on a previously programmed (101) memory block, a pre-programming operation (S91) is performed. The pre-programming operation can be performed to reduce the threshold voltage difference of the memory cells included in the selected memory block. The memory cells included in the selected memory block can be programmed with various threshold voltage distributions (ER or P1 to P7). Therefore, the relatively low threshold voltage of the memory cells can be increased through the pre-programming operation. The memory cells that have undergone the pre-programming operation can have a threshold voltage distribution corresponding to the pre-programming state PP. That is, the memory cells included in the selected memory block can be pre-programmed to be in the pre-programming state PP. Thus, the pre-programming operation to increase the relatively low threshold voltage of the memory cells can be performed by applying a pre-programming voltage to all word lines connected to the selected memory block. Alternatively, the pre-programming operation can be performed by applying a pre-programming voltage to the word lines connected to the selected memory block at different times. The method of applying a pre-programming voltage to all word lines connected to the selected memory block is described below.

[0074] Preprogramming operations can be performed without verification operations. For example, a preprogramming operation can be performed by applying at least one preprogramming pulse to all word lines connected to the selected memory block. The level of the preprogramming voltage used for the preprogramming operation can be set between the average level and the maximum level of the programming voltage used in the main programming operation.

[0075] The preprogramming operation according to the implementation can be performed at different times on a per-sub-block basis within the selected memory block to mitigate or prevent preprogramming performance degradation based on the location of the memory cells included in the memory block. Preprogramming performance degradation refers to threshold voltage variations that occur depending on the location of the memory cells. For example, among the sub-blocks included in the selected memory block, the preprogramming speed of the first sub-block adjacent to the slit may be slower than the preprogramming speed of the second sub-block located between the first sub-blocks. Therefore, the preprogramming operation can reduce the difference in preprogramming speed between sub-blocks whose preprogramming speeds may differ from each other.

[0076] For example, among the sub-blocks included in the selected memory block, a first sub-block adjacent to the slit and a second sub-block located between the first sub-blocks can be pre-programmed at different times. For example, when the first sub-block is the selected sub-block, the second sub-block is an unselected sub-block. When the second sub-block is the selected sub-block, the first sub-block is an unselected sub-block. After the pre-programming operation of the selected sub-block is completed, the pre-programming operation of the unselected sub-block can be performed. That is, when the pre-programming operation of the selected sub-block is completed, the unselected sub-block is designated as the selected sub-block, and then the pre-programming operation of the newly designated selected sub-block can be performed. In the pre-programming operation according to the embodiment, the level of the pre-programming voltage can be adjusted according to each sub-block. When performing the pre-programming operation on a sub-block with a relatively fast pre-programming speed, the level of the pre-programming voltage applied to the word line can be set below a reference level. For example, when the level of the pre-programming voltage applied during the pre-programming operation of the first sub-block is set to the reference level, the level of the pre-programming voltage applied during the pre-programming operation of the second sub-block can be set below the reference level and above 0V.

[0077] Furthermore, in the pre-programming operation according to the embodiment, the voltage applied to at least one of the bit line and the source line can be changed. For example, in the pre-programming operation, the voltage applied to the bit line can be lower than the reference bit line voltage, thereby increasing the threshold voltage of the memory cells in the selected memory block that are positioned closer to the bit line than the source line. During the pre-programming operation, the voltage applied to the source line can be higher than the reference source line voltage, thereby decreasing the threshold voltage of the memory cells in the selected memory block that are positioned closer to the source line than the bit line.

[0078] Alternatively, the voltage applied to the bit line can be increased before applying the pre-programming voltage to the word line to rapidly increase the pre-programming speed of memory cells located at the upper part of the selected memory block. Alternatively, the voltage applied to the source line can be increased before applying the pre-programming voltage to the word line, or the voltage applied to the source line can be increased and then decreased again to increase the pre-programming speed of memory cells located at the lower part of the selected memory block.

[0079] According to the above implementation, the memory cells included in the selected memory block are in a pre-programmed state PP, and are related to the... Figure 10 Compared to the previous programming state shown at point 101, the width of the threshold voltage distribution corresponding to the pre-programmed state PP can be narrower.

[0080] When the pre-programming operation (S91) of the selected memory block is completed, the erase operation (S92) of the selected memory block is performed. Erasure operations can be performed in parallel on the sub-blocks included in the selected memory block. The erase operation can be performed in a gate-induced drain leakage (GIDL) manner. When an erase voltage is applied to the bit line, GIDL may appear in the region where the drain selection transistor is located. When an erase voltage is applied to the source line, GIDL may appear in the region where the source selection transistor is located. When erase voltages are applied to both the bit line and the source line, GIDL may appear in the regions where both the drain selection transistor and the source selection transistor are located. When an erase operation is performed on the selected memory block, the memory cells in the pre-programmed state PP are changed to the erased state ER. Because the threshold voltage distribution of the pre-programmed memory cell in the pre-programming operation S91 is narrower than the distribution shown at 101, the memory cell can be erased to the erase state ER faster than if the pre-programming operation S91 were omitted, and the width of the threshold voltage distribution corresponding to the erase state ER can be narrower than if the pre-programming operation S91 were omitted.

[0081] When a programming command is input to the memory device after the erase operation (S92) is completed, the memory device can execute the main programming operation (S93) of the selected memory block. When the main programming operation is performed in a three-level cell (TLC) manner, the memory cell can be programmed into an erase state ER or one of the first programming states P1 to the seventh programming states P7. Because the threshold voltage distribution of the memory cell erased in step S92 is narrower than that of omitting step S91, the speed of the main programming operation performed in step S93 can be increased. That is, because the number of memory cells that have been over-erased in step S92 may be reduced, the time spent on the main programming operation in step S93 can be shortened.

[0082] The various implementations of the pre-programming operation performed in step S91 as described above will now be described in detail.

[0083] Figure 11A and Figure 11B This is a diagram used to describe the pre-programmed operations according to the first embodiment of this disclosure.

[0084] Reference Figure 11A and Figure 11B The pre-programming operation according to the first embodiment can be performed sequentially on the first sub-block 1SB and the second sub-block 2SB included in the selected memory block. The first sub-block 1SB and the second sub-block 2SB can be as follows: Figure 7 and Figure 8The first subblock 1SB and the second subblock 2SB are shown. For example, the first subblock 1SB can be located at both ends of the selected memory block, while the second subblock 2SB can be located between the first subblock 1SB. Preprogramming operations can be performed on the second subblock 2SB after preprogramming operations are performed on the first subblock 1SB, or vice versa.

[0085] Figure 11A It is a diagram used to describe the pre-programmed operations performed on the first subblock 1SB, and Figure 11B It is a diagram used to describe the pre-programmed operations performed on the second sub-block 2SB.

[0086] Reference Figure 11A At the first moment T1 after the pre-programming operation begins, a turn-on voltage Von can be applied to the drain select line DSL connected to the first sub-block 1SB, and a ground voltage GND can be applied to the drain select line DSL connected to the second sub-block 2SB. That is, assuming the first sub-block 1SB is the selected sub-block and the second sub-block 2SB is the unselected sub-block, a turn-on voltage Von can be applied to the drain select line DSL connected to the selected sub-block, and a ground voltage GND can be applied to the drain select line DSL connected to the unselected sub-block. The turn-on voltage Von applied to the drain select line DSL connected to the first sub-block 1SB can be set to a positive voltage to turn on the drain select transistor. The ground voltage GND applied to the drain select line DSL connected to the second sub-block 2SB is a voltage to turn off the drain select transistor included in the second sub-block 2SB. The ground voltage GND can be applied to the source select line SSL connected to the first sub-block 1SB and the second sub-block 2SB.

[0087] Ground voltage GND can be applied to bit line BL. Because the drain select transistor of the first sub-block 1SB is turned on and the source select transistor of the first sub-block 1SB is turned off, the channel of the plug included in the first sub-block 1SB can be electrically connected to bit line BL. Therefore, the potential of the channel of the first sub-block 1SB can be reduced to the ground voltage GND level. Because the drain select transistor and source select transistor of the second sub-block 2SB are turned off, the channel of the plug included in the second sub-block 2SB is in a floating state.

[0088] Ground voltage GND can be applied to the source line SL. At the first time T1, ground voltage GND can be applied to the word line WL.

[0089] At the second time T2, a first pass voltage 1Vpass higher than the ground voltage GND can be applied to the word line WL. The first pass voltage 1Vpass can be applied to all word lines WL to turn on all memory cells included in the selected memory block.

[0090] At the third time T3, a second pass voltage 2Vpass, higher than the first pass voltage 1Vpass, can be applied to the word line WL. Before applying the first pre-programmed voltage 1pVpgm to the word line WL, the second pass voltage 2Vpass can be applied to gradually increase the potential of the word line WL. For some embodiments, gradually increasing or decreasing the potential means that the potential changes from the first potential to the second potential through an intermediate potential having a level between the first and second potentials. For example, the potential of the word line WL can gradually change upwards from the first pass voltage 1Vpass through the second pass voltage 2Vpass to the first pre-programmed voltage 1pVpgm. The potential of the word line WL can also gradually change downwards from the first pre-programmed voltage 1pVpgm through the second pass voltage 2Vpass to the ground voltage GND.

[0091] At time T4, a first pre-programming voltage of 1pVpgm can be applied to the word line WL. Because the channel potential of the first sub-block 1SB has a ground voltage GND level, the threshold voltage of the memory cells included in the first sub-block 1SB can be increased. Because the channel of the second sub-block 2SB is in a floating state, its channel potential may be boosted due to the potential of the word line WL. Therefore, the memory cells included in the second sub-block 2SB can remain erased. The threshold voltage of the memory cells included in the first sub-block 1SB can be increased from time T4 to time T5.

[0092] At the fifth time point T5, the potential of the word line WL can be gradually reduced. For example, a second pass voltage of 2Vpass, lower than the first pre-programmed voltage of 1pVpgm, can be applied to the word line WL. Although Figure 11A It is not shown in the figure, but the potential of word line WL can gradually or progressively decrease between the fifth time T5 and the sixth time T6.

[0093] At time T6, word line WL can be discharged. For example, ground voltage GND can be applied to word line WL.

[0094] At time T7, the drain selection line DSL connected to the first sub-block 1SB can be discharged.

[0095] Reference Figure 11B The pre-programming operations for the second sub-block 2SB can be similar to those described in reference [reference]. Figure 11AThe preprogramming operation of the first subblock 1SB is described. However, in the preprogramming operation of the second subblock 2SB, a second preprogramming voltage of 2pVpgm, lower than the first preprogramming voltage of 1pVpgm, is applied to the word line WL. That is, since the preprogramming speed of the second subblock 2SB included in the selected memory block can be faster than the preprogramming speed of the first subblock 1SB, the level of the preprogramming voltage applied to the word line WL can be adjusted differently for each subblock to similarly match the preprogramming speed of the first subblock 1SB and the second subblock 2SB. Except for applying the second preprogramming voltage of 2pVpgm to the word line WL between the fourth time T4 and the fifth time T5, the operation at the remaining intervals is the same as the operation in the preprogramming operation performed in the first subblock 1SB, and therefore its redundant description is omitted.

[0096] The preprogramming operation can be performed on the second subblock 2SB after the preprogramming operation is performed on the first subblock 1SB, or the preprogramming operation can be performed on the first subblock 1SB after the preprogramming operation is performed on the second subblock 2SB.

[0097] Figure 12 This is a diagram used to describe the pre-programmed operations according to the second embodiment of this disclosure.

[0098] Reference Figure 12 At the first time T1, when the pre-programming operation begins, a conduction voltage Von can be applied to the drain selection line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain selection line DSL connected to the unselected sub-block Unsel_SB. When the selected sub-block Sel_SB is Figure 7 and Figure 8 When the first sub-block 1SB is shown, the unselected sub-block Unsel_SB is... Figure 7 and Figure 8 The second sub-block 2SB is shown. When the selected sub-block Sel_SB is the second sub-block 2SB, the unselected sub-block Unsel_SB is the first sub-block 1SB.

[0099] A turn-on voltage Von can be applied to the drain select line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain select line DSL connected to the unselected sub-block Unsel_SB. The turn-on voltage Von applied to the drain select line DSL connected to the selected sub-block Sel_SB can be set to a positive voltage to turn on the drain select transistor. The ground voltage GND applied to the drain select line DSL connected to the unselected sub-block Unsel_SB is a voltage to turn off the drain select transistor included in the unselected sub-block Unsel_SB. The ground voltage GND can be applied to the source select line SSL connected to both the selected sub-block Sel_SB and the unselected sub-block Unsel_SB.

[0100] A negative voltage Vn, lower than the ground voltage GND, can be applied to the bit line BL. As the potential of the bit line BL decreases, the threshold voltage of the memory cells included in the selected sub-block Sel_SB can increase more quickly, thereby reducing the time spent on pre-programming operations. Because the drain select transistor of the selected sub-block Sel_SB is turned on and the source select transistor is turned off, the channel of the plug included in the selected sub-block Sel_SB can be electrically connected to the bit line BL. Therefore, the potential of the channel of the selected sub-block Sel_SB can decrease to the negative voltage Vn level. Because the drain select transistor and the source select transistor of the unselected sub-block Unsel_SB are turned off, the channel of the plug included in the unselected sub-block Unsel_SB is in a floating state.

[0101] Ground voltage GND can be applied to the source line SL. At the first time T1, ground voltage GND can be applied to the word line WL.

[0102] At the second time T2, a first pass voltage 1Vpass higher than the ground voltage GND can be applied to the word line WL. The first pass voltage 1Vpass can be applied to all word lines WL to turn on all memory cells included in the selected memory block.

[0103] At the third time T3, a second pass voltage of 2Vpass, higher than the first pass voltage of 1Vpass, can be applied to the word line WL. Before applying the first preprogramming voltage of 1pVpgm or the second preprogramming voltage of 2pVpgm to the word line WL, the second pass voltage of 2Vpass can be applied to the word line WL to gradually increase the potential of the word line WL.

[0104] At time T4, a first preprogrammed voltage of 1pVpgm or a second preprogrammed voltage of 2pVpgm can be applied to the word line WL. For example, when the first subblock 1SB is the selected subblock Sel_SB, the first preprogrammed voltage of 1pVpgm can be applied to the word line WL. When the second subblock 2SB is the selected subblock Sel_SB, the second preprogrammed voltage of 2pVpgm can be applied to the word line WL.

[0105] Because the channel potential of the selected sub-block Sel_SB has a negative voltage level Vn, the threshold voltage of the memory cells included in the selected sub-block Sel_SB can be increased by the first preprogramming voltage 1pVpgm or the second preprogramming voltage 2pVpgm. Because the channel of the unselected sub-block Unsel_SB is in a floating state, its channel may be boosted by the potential of the word line WL. Therefore, the memory cells included in the unselected sub-block Unsel_SB can remain erased. The threshold voltage of the memory cells included in the first sub-block 1SB can be increased from the fourth time T4 to the fifth time T5.

[0106] At the fifth time T5, the potential of the word line WL can be gradually reduced. For example, a second pass voltage of 2Vpass, lower than the first preprogrammed voltage of 1pVpgm or the second preprogrammed voltage of 2pVpgm, can be applied to the word line WL. Although Figure 12 It is not shown in the figure, but the potential of word line WL can gradually or progressively decrease between the fifth time T5 and the sixth time T6.

[0107] At time T6, word line WL can be discharged. For example, ground voltage GND can be applied to word line WL.

[0108] At time T7, the drain selection line DSL connected to the first sub-block 1SB can be discharged.

[0109] Figure 13 This is a diagram used to describe the pre-programmed operations according to the third embodiment of this disclosure.

[0110] Reference Figure 13 At the first time T1, when the pre-programming operation begins, a conduction voltage Von can be applied to the drain selection line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain selection line DSL connected to the unselected sub-block Unsel_SB. When the selected sub-block Sel_SB is Figure 7 and Figure 8 When the first sub-block 1SB is shown, the unselected sub-block Unsel_SB is... Figure 7 and Figure 8 The second sub-block 2SB is shown. When the selected sub-block Sel_SB is the second sub-block 2SB, the unselected sub-block Unsel_SB is the first sub-block 1SB.

[0111] A turn-on voltage Von can be applied to the drain select line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain select line DSL connected to the unselected sub-block Unsel_SB. The turn-on voltage Von applied to the drain select line DSL connected to the selected sub-block Sel_SB can be set to a positive voltage to turn on the drain select transistor. The ground voltage GND applied to the drain select line DSL connected to the unselected sub-block Unsel_SB is a voltage to turn off the drain select transistor included in the unselected sub-block Unsel_SB. The ground voltage GND can be applied to the source select line SSL connected to both the selected sub-block Sel_SB and the unselected sub-block Unsel_SB.

[0112] Ground voltage GND can be applied to bit line BL. Because the drain select transistor of the selected sub-block Sel_SB is turned on and the source select transistor is turned off, the channel of the plug included in the selected sub-block Sel_SB can be electrically connected to bit line BL. Therefore, the potential of the channel of the selected sub-block Sel_SB can be reduced to the ground voltage GND level. Because the drain select transistor and source select transistor of the unselected sub-block Unsel_SB are turned off, the channel of the plug included in the unselected sub-block Unsel_SB is in a floating state.

[0113] A positive voltage Vp higher than the ground voltage GND can be applied to the source line SL. In this way, during the pre-programming operation of the memory cells included in the selected sub-block Sel_SB, the threshold voltage of the memory cells included in the unselected sub-block Unsel_SB can be more effectively resisted or prevented from increasing. At the first time T1, the ground voltage GND can be applied to the word line WL.

[0114] At the second time T2, a first pass voltage 1Vpass higher than the ground voltage GND can be applied to the word line WL. The first pass voltage 1Vpass can be applied to all word lines WL to turn on all memory cells included in the selected memory block.

[0115] At the third time T3, a second pass voltage of 2Vpass, higher than the first pass voltage of 1Vpass, can be applied to the word line WL. Before applying the first preprogramming voltage of 1pVpgm or the second preprogramming voltage of 2pVpgm to the word line WL, the second pass voltage of 2Vpass can be applied to the word line WL to gradually increase the potential of the word line WL.

[0116] At time T4, a first preprogrammed voltage of 1pVpgm or a second preprogrammed voltage of 2pVpgm can be applied to the word line WL. For example, when the first subblock 1SB is the selected subblock Sel_SB, the first preprogrammed voltage of 1pVpgm can be applied to the word line WL. When the second subblock 2SB is the selected subblock Sel_SB, the second preprogrammed voltage of 2pVpgm can be applied to the word line WL.

[0117] Because the channel potential of the selected sub-block Sel_SB has a negative voltage level Vn, the threshold voltage of the memory cells included in the selected sub-block Sel_SB can be increased by the first preprogramming voltage 1pVpgm or the second preprogramming voltage 2pVpgm. Because the channel of the unselected sub-block Unsel_SB is in a floating state, its channel may be boosted by the potential of the word line WL. Therefore, the memory cells included in the unselected sub-block Unsel_SB can remain erased. The threshold voltage of the memory cells included in the first sub-block 1SB can be increased from the fourth time T4 to the fifth time T5.

[0118] At the fifth time T5, the potential of the word line WL can be gradually reduced. For example, a second pass voltage of 2Vpass, lower than the first preprogrammed voltage of 1pVpgm or the second preprogrammed voltage of 2pVpgm, can be applied to the word line WL. Although Figure 13 It is not shown in the figure, but the potential of word line WL can gradually or progressively decrease between the fifth time T5 and the sixth time T6.

[0119] At time T6, word line WL can be discharged. For example, ground voltage GND can be applied to word line WL.

[0120] At time T7, the drain selection line DSL connected to the first sub-block 1SB can be discharged.

[0121] Figure 14 This is a diagram used to describe the pre-programmed operations according to the fourth embodiment of this disclosure.

[0122] Reference Figure 14 At the first time T1, when the pre-programming operation begins, a conduction voltage Von can be applied to the drain selection line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain selection line DSL connected to the unselected sub-block Unsel_SB. When the selected sub-block Sel_SB is Figure 7 and Figure 8 When the first sub-block 1SB is shown, the unselected sub-block Unsel_SB is... Figure 7 and Figure 8 The second sub-block 2SB is shown. When the selected sub-block Sel_SB is the second sub-block 2SB, the unselected sub-block Unsel_SB is the first sub-block 1SB.

[0123] A turn-on voltage Von can be applied to the drain select line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain select line DSL connected to the unselected sub-block Unsel_SB. The turn-on voltage Von applied to the drain select line DSL connected to the selected sub-block Sel_SB can be set to a positive voltage to turn on the drain select transistor. The ground voltage GND applied to the drain select line DSL connected to the unselected sub-block Unsel_SB is a voltage to turn off the drain select transistor included in the unselected sub-block Unsel_SB. The ground voltage GND can be applied to the source select line SSL connected to both the selected sub-block Sel_SB and the unselected sub-block Unsel_SB.

[0124] A negative voltage Vn, lower than the ground voltage GND, can be applied to the bit line BL. As the potential of the bit line BL decreases, the threshold voltage of the memory cells included in the selected sub-block Sel_SB can increase more quickly, thereby reducing the time spent on pre-programming operations. Because the drain select transistor of the selected sub-block Sel_SB is turned on and the source select transistor is turned off, the channel of the plug included in the selected sub-block Sel_SB can be electrically connected to the bit line BL. Therefore, the potential of the channel of the selected sub-block Sel_SB can decrease to the negative voltage Vn level. Because the drain select transistor and the source select transistor of the unselected sub-block Unsel_SB are turned off, the channel of the plug included in the unselected sub-block Unsel_SB is in a floating state.

[0125] A positive voltage Vp higher than the ground voltage GND can be applied to the source line SL. In this way, during the pre-programming operation of the memory cells included in the selected sub-block Sel_SB, the threshold voltage of the memory cells included in the unselected sub-block Unsel_SB can be more effectively resisted or prevented from increasing. At the first time T1, the ground voltage GND can be applied to the word line WL.

[0126] At the second time T2, a first pass voltage 1Vpass higher than the ground voltage GND can be applied to the word line WL. The first pass voltage 1Vpass can be applied to all word lines WL to turn on all memory cells included in the selected memory block.

[0127] At the third time T3, a second pass voltage of 2Vpass, higher than the first pass voltage of 1Vpass, can be applied to the word line WL. Before applying the first preprogramming voltage of 1pVpgm or the second preprogramming voltage of 2pVpgm to the word line WL, the second pass voltage of 2Vpass can be applied to the word line WL to gradually increase the potential of the word line WL.

[0128] At time T4, a first preprogrammed voltage of 1pVpgm or a second preprogrammed voltage of 2pVpgm can be applied to the word line WL. For example, when the first subblock 1SB is the selected subblock Sel_SB, the first preprogrammed voltage of 1pVpgm can be applied to the word line WL. When the second subblock 2SB is the selected subblock Sel_SB, the second preprogrammed voltage of 2pVpgm can be applied to the word line WL.

[0129] Because the channel potential of the selected sub-block Sel_SB has a negative voltage level Vn, the threshold voltage of the memory cells included in the selected sub-block Sel_SB can be increased by the first preprogramming voltage 1pVpgm or the second preprogramming voltage 2pVpgm. Because the channel of the unselected sub-block Unsel_SB is in a floating state, its channel may be boosted by the potential of the word line WL. Therefore, the memory cells included in the unselected sub-block Unsel_SB can remain erased. The threshold voltage of the memory cells included in the first sub-block 1SB can be increased from the fourth time T4 to the fifth time T5.

[0130] At the fifth time T5, the potential of the word line WL can be gradually reduced. For example, a second pass voltage of 2Vpass, lower than the first preprogrammed voltage of 1pVpgm or the second preprogrammed voltage of 2pVpgm, can be applied to the word line WL. Although Figure 14 It is not shown in the figure, but the potential of word line WL can gradually or progressively decrease between the fifth time T5 and the sixth time T6.

[0131] At time T6, word line WL can be discharged. For example, ground voltage GND can be applied to word line WL.

[0132] At time T7, the drain selection line DSL connected to the first sub-block 1SB can be discharged.

[0133] Figure 15 This is a diagram used to describe the pre-programmed operations according to the fifth embodiment of this disclosure.

[0134] Reference Figure 15 At the first time T1, when the pre-programming operation begins, a conduction voltage Von can be applied to the drain selection line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain selection line DSL connected to the unselected sub-block Unsel_SB. When the selected sub-block Sel_SB is Figure 7 and Figure 8 When the first sub-block 1SB is shown, the unselected sub-block Unsel_SB is... Figure 7 and Figure 8 The second sub-block 2SB is shown. When the selected sub-block Sel_SB is the second sub-block 2SB, the unselected sub-block Unsel_SB is the first sub-block 1SB.

[0135] A turn-on voltage Von can be applied to the drain select line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain select line DSL connected to the unselected sub-block Unsel_SB. The turn-on voltage Von applied to the drain select line DSL connected to the selected sub-block Sel_SB can be set to a positive voltage to turn on the drain select transistor. The ground voltage GND applied to the drain select line DSL connected to the unselected sub-block Unsel_SB is a voltage to turn off the drain select transistor included in the unselected sub-block Unsel_SB. The ground voltage GND can be applied to the source select line SSL connected to both the selected sub-block Sel_SB and the unselected sub-block Unsel_SB.

[0136] A negative voltage Vn, lower than the ground voltage GND, can be applied to the bit line BL. As the potential of the bit line BL decreases, the threshold voltage of the memory cells included in the selected sub-block Sel_SB can increase more quickly, thereby reducing the time spent on pre-programming operations. Because the drain select transistor of the selected sub-block Sel_SB is turned on and the source select transistor is turned off, the channel of the plug included in the selected sub-block Sel_SB can be electrically connected to the bit line BL. Therefore, the potential of the channel of the selected sub-block Sel_SB can decrease to the negative voltage Vn level. Because the drain select transistor and the source select transistor of the unselected sub-block Unsel_SB are turned off, the channel of the plug included in the unselected sub-block Unsel_SB is in a floating state.

[0137] Ground voltage GND can be applied to the source line SL. At the first time T1, ground voltage GND can be applied to the word line WL.

[0138] At the second time T2, a first pass voltage 1Vpass higher than the ground voltage GND can be applied to the word line WL. The first pass voltage 1Vpass can be applied to all word lines WL to turn on all memory cells included in the selected memory block.

[0139] At the third time T3, a second pass voltage of 2Vpass, higher than the first pass voltage 1Vpass, can be applied to the word line WL. Before applying the first preprogramming voltage 1pVpgm or the second preprogramming voltage 2pVpgm to the word line WL, the second pass voltage 2Vpass can be applied to gradually increase the potential of the word line WL. Between the third time T3 and the fourth time T4, the potential of the bit line BL can rise to the ground voltage GND level. Between the third time T3 and the fourth time T4, there may be a third time T3' where the potential of the bit line BL rises from the negative voltage Vn level to the ground voltage GND level.

[0140] At time T4, a first preprogrammed voltage of 1pVpgm or a second preprogrammed voltage of 2pVpgm can be applied to the word line WL. For example, when the first subblock 1SB is the selected subblock Sel_SB, the first preprogrammed voltage of 1pVpgm can be applied to the word line WL. When the second subblock 2SB is the selected subblock Sel_SB, the second preprogrammed voltage of 2pVpgm can be applied to the word line WL.

[0141] Because the channel potential of the selected sub-block Sel_SB has a negative voltage level Vn, the threshold voltage of the memory cells included in the selected sub-block Sel_SB can be increased by the first preprogramming voltage 1pVpgm or the second preprogramming voltage 2pVpgm. Because the channel of the unselected sub-block Unsel_SB is in a floating state, its channel may be boosted by the potential of the word line WL. Therefore, the memory cells included in the unselected sub-block Unsel_SB can remain erased. The threshold voltage of the memory cells included in the first sub-block 1SB can be increased from the fourth time T4 to the fifth time T5.

[0142] At the fifth time T5, the potential of the word line WL can be gradually reduced. For example, a second pass voltage of 2Vpass, lower than the first preprogrammed voltage of 1pVpgm or the second preprogrammed voltage of 2pVpgm, can be applied to the word line WL. Although Figure 15 It is not shown in the figure, but the potential of word line WL can gradually or progressively decrease between the fifth time T5 and the sixth time T6.

[0143] At time T6, word line WL can be discharged. For example, ground voltage GND can be applied to word line WL.

[0144] At time T7, the drain selection line DSL connected to the first sub-block 1SB can be discharged.

[0145] Figure 16 This is a diagram used to describe the pre-programmed operations according to the sixth embodiment of this disclosure.

[0146] Reference Figure 16 At the first time T1, when the pre-programming operation begins, a conduction voltage Von can be applied to the drain selection line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain selection line DSL connected to the unselected sub-block Unsel_SB. When the selected sub-block Sel_SB is Figure 7 and Figure 8 When the first sub-block 1SB is shown, the unselected sub-block Unsel_SB is... Figure 7 and Figure 8 The second sub-block 2SB is shown. When the selected sub-block Sel_SB is the second sub-block 2SB, the unselected sub-block Unsel_SB is the first sub-block 1SB.

[0147] A turn-on voltage Von can be applied to the drain select line DSL connected to the selected sub-block Sel_SB, and a ground voltage GND can be applied to the drain select line DSL connected to the unselected sub-block Unsel_SB. The turn-on voltage Von applied to the drain select line DSL connected to the selected sub-block Sel_SB can be set to a positive voltage to turn on the drain select transistor. The ground voltage GND applied to the drain select line DSL connected to the unselected sub-block Unsel_SB is a voltage to turn off the drain select transistor included in the unselected sub-block Unsel_SB. A positive voltage Vp higher than the ground voltage GND can be applied to the source select line SSL connected to both the selected sub-block Sel_SB and the unselected sub-block Unsel_SB.

[0148] Ground voltage GND can be applied to bit line BL. Because the drain select transistor and source select transistor of the selected sub-block Sel_SB are turned on, the channel of the plug included in the selected sub-block Sel_SB can be electrically connected to bit line BL and source line SL. Because the drain select transistor of the unselected sub-block Unsel_SB is turned off and the source select transistor is turned on, the channel of the plug included in the unselected sub-block Unsel_SB can be electrically connected to source line SL.

[0149] A positive voltage Vp higher than the ground voltage GND can be applied to the source line SL. In this way, during the pre-programming operation of the memory cells included in the selected sub-block Sel_SB, the threshold voltage of the memory cells included in the unselected sub-block Unsel_SB can be more effectively resisted or prevented from increasing. At the first time T1, the ground voltage GND can be applied to the word line WL.

[0150] At the second time T2, a first pass voltage 1Vpass higher than the ground voltage GND can be applied to the word line WL. The first pass voltage 1Vpass can be applied to all word lines WL to turn on all memory cells included in the selected memory block.

[0151] Because the drain and source selection transistors of the selected sub-block Sel_SB are turned on, the potential of the channel of the plug included in the selected sub-block Sel_SB can be maintained at a level below the positive voltage Vp. Because the drain selection transistor of the unselected sub-block Unsel_SB is turned off and the source selection transistor is turned on, the potential of the channel of the plug included in the unselected sub-block Unsel_SB can be increased by applying a positive voltage Vp to the source line SL.

[0152] At the third time T3, a second through voltage of 2Vpass, higher than the first through voltage 1Vpass, can be applied to the word line WL. Before applying the first preprogramming voltage 1pVpgm or the second preprogramming voltage 2pVpgm to the word line WL, the second through voltage 2Vpass can be applied to the word line WL to gradually increase its potential. The on-state voltage Von applied to the source select line SSL and the positive voltage Vp applied to the source line SL can be reduced to the ground voltage GND level between the third time T3 and the fourth time T4. The third time T3' for the discharge of the source select line SSL and the source line SL can be varied between the third time T3 and the fourth time T4.

[0153] At time T4, a first preprogrammed voltage of 1pVpgm or a second preprogrammed voltage of 2pVpgm can be applied to the word line WL. For example, when the first subblock 1SB is the selected subblock Sel_SB, the first preprogrammed voltage of 1pVpgm can be applied to the word line WL. When the second subblock 2SB is the selected subblock Sel_SB, the second preprogrammed voltage of 2pVpgm can be applied to the word line WL.

[0154] Because the channel potential of the selected sub-block Sel_SB has a negative voltage level Vn, the threshold voltage of the memory cells included in the selected sub-block Sel_SB can be increased by the first preprogramming voltage 1pVpgm or the second preprogramming voltage 2pVpgm. Because the channel of the unselected sub-block Unsel_SB is in a floating state, its channel may be boosted by the potential of the word line WL. Therefore, the memory cells included in the unselected sub-block Unsel_SB can remain erased. The threshold voltage of the memory cells included in the first sub-block 1SB can be increased from the fourth time T4 to the fifth time T5.

[0155] At the fifth time T5, the potential of the word line WL can be gradually reduced. For example, a second pass voltage of 2Vpass, lower than the first preprogrammed voltage of 1pVpgm or the second preprogrammed voltage of 2pVpgm, can be applied to the word line WL. Although Figure 16 It is not shown in the figure, but the potential of word line WL can gradually or progressively decrease between the fifth time T5 and the sixth time T6.

[0156] At time T6, word line WL can be discharged. For example, ground voltage GND can be applied to word line WL.

[0157] At time T7, the drain selection line DSL connected to the first sub-block 1SB can be discharged.

[0158] Figure 17 This is a diagram illustrating a memory card system 3000 using a memory device according to an embodiment of the present disclosure.

[0159] Reference Figure 17 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0160] The controller 3100 can be connected to the memory device 3200. In some embodiments, the controller 3100 can represent... Figure 1 Controller 200 or Figure 2 The controller 3100 can be configured to access the memory device 3200. For example, the controller 3100 can control programming operations, read operations, erase operations, or background operations of the memory device 3200. The controller 3100 can be configured to provide an interface between the memory device 3200 and the host. The controller 3100 can be configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0161] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, controller 3100 can be configured to communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0162] Memory device 3200 may include a plurality of memory cells and can be coupled with Figure 2 The memory device 100 shown is configured in the same manner. For example, the memory device 3200 may perform a pre-programming operation before an erase operation. During the pre-programming operation, the memory device 3200 may adjust the level of the pre-programming voltage applied to the word line according to the selected sub-blocks included in the selected memory block. In addition to the programming voltage, the memory device 3200 may also adjust the voltage applied to at least one of the source line, bit line, drain select line, and source select line.

[0163] To reduce the time required for programming operations and mitigate or prevent interference, the channel precharge time can be adjusted based on the size of the memory cells included in the selected page during the programming operation of the selected page of the selected memory block.

[0164] The controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and memory device 3200 can form memory cards such as: personal computer (PC) cards (PCMCIA), compact flash memory (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), and universal flash memory (UFS).

[0165] Figure 18 This is a diagram illustrating a solid-state drive (SSD) system 4000 to which an embodiment of the memory device according to the present disclosure is applied.

[0166] Reference Figure 18 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0167] Controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from host 4100. For example, the signals can be based on the interface between host 4100 and SSD 4200. For example, the signals can be defined via at least one interface such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe interface. In some implementations, controller 4210 may represent... Figure 1 Controller 200 or Figure 2 The control circuit.

[0168] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n can be coupled with... Figure 1 The memory device 100 shown is configured in the same manner. Multiple memory devices 4221 to 422n can communicate with the controller 4210 via channels CH1 to CHn.

[0169] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive and charge power from host 4100. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power to SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and can provide auxiliary power to SSD 4200.

[0170] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0171] According to this disclosure, the phenomenon of excessive reduction of the threshold voltage of memory cells during erase operations can be mitigated or prevented, and the time spent on programming operations can be shortened.

[0172] It will be apparent to those skilled in the art that various modifications may be made to the embodiments disclosed herein without departing from the spirit or scope of this teaching. Therefore, this teaching is intended to cover all such modifications, provided that they fall within the scope of the appended claims and their equivalents.

[0173] Cross-reference to related applications

[0174] This application claims priority to Korean Patent Application No. 10-2024-0197170, filed with the Korean Intellectual Property Office on December 26, 2024, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A memory block comprising a first sub-block and a second sub-block located between the source line and the bit line; The peripheral circuitry performs the erase operation on the memory block and sequentially performs pre-programming operations on the first sub-block and the second sub-block prior to the erase operation. as well as Control circuit, which controls the peripheral circuit. Each of the first sub-block and the second sub-block includes a first selection transistor, a memory cell, and a second selection transistor disposed between the source line and the bit line. The control circuit controls the peripheral circuit to apply a first preprogramming voltage to the word line connected to the memory cell during the preprogramming operation of the first sub-block, and to apply a second preprogramming voltage lower than the first preprogramming voltage to the word line during the preprogramming operation of the second sub-block.

2. The memory device according to claim 1, wherein, The second sub-block is located between the first sub-blocks.

3. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit so that the potential of the word line gradually increases before the first pre-programming voltage or the second pre-programming voltage is applied to the word line.

4. The memory device according to claim 3, wherein, The control circuit controls the peripheral circuit to gradually apply a pass voltage lower than the first preprogramming voltage or the second preprogramming voltage to the word line before applying the first preprogramming voltage or the second preprogramming voltage to the word line.

5. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit such that when the pre-programming operation is performed on the first sub-block, the second selection transistor included in the first sub-block is turned on and the second selection transistor included in the second sub-block is turned off.

6. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit such that when the pre-programming operation is performed on the second sub-block, the second selection transistor included in the second sub-block is turned on and the second selection transistor included in the first sub-block is turned off.

7. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit to apply a ground voltage to the first selection line connected to the first selection transistor.

8. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit to apply a positive voltage higher than the ground voltage to the first selection line connected to the first selection transistor.

9. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit to apply a ground voltage to the bit line.

10. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit to apply a negative voltage lower than the ground voltage to the bit line.

11. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit to apply a ground voltage to the source line.

12. The memory device according to claim 1, wherein, The control circuit controls the peripheral circuit to apply a positive voltage higher than the ground voltage to the source line.

13. The memory device according to claim 12, wherein, The control circuit controls the peripheral circuit to discharge the source line to which the positive voltage is applied before applying the first preprogrammed voltage or the second preprogrammed voltage to the word line.

14. The memory device according to claim 13, wherein, The control circuit controls the peripheral circuit to turn on the first selection transistor when the positive voltage is applied to the source line.

15. A method of operating a memory device, the method comprising the steps of: Prior to the erase operation of the memory block including the first sub-block and the second sub-block located between the first sub-block, a first pre-programming operation of the first sub-block is performed by applying a first pre-programming voltage to the word line connected to the first sub-block and the second sub-block; as well as The second preprogramming operation of the second subblock is performed by applying a second preprogramming voltage lower than the first preprogramming voltage to the word line.

16. The method according to claim 15, wherein, Before applying the first preprogramming voltage or the second preprogramming voltage to the word line, the potential of the word line is gradually increased to the first preprogramming voltage or the second preprogramming voltage.

17. The method according to claim 15, wherein, When the first preprogramming operation or the second preprogramming operation is performed, a ground voltage is applied to the bit line connected to the memory block.

18. The method according to claim 15, wherein, When the first preprogramming operation or the second preprogramming operation is performed, a negative voltage lower than the ground voltage is applied to the bit line connected to the memory block.

19. The method according to claim 15, wherein, When the first preprogramming operation or the second preprogramming operation is performed, a ground voltage is applied to the source line connected to the memory block.

20. The method of claim 15, wherein, When the first preprogramming operation or the second preprogramming operation is performed, a positive voltage higher than the ground voltage is applied to the source line connected to the memory block.

21. The method according to claim 20, wherein, Before applying the first preprogrammed voltage or the second preprogrammed voltage to the word line, the source line to which the positive voltage is applied is discharged.

22. The method according to claim 20, wherein, When the positive voltage is applied to the source line, the channel of the plug included in the first sub-block and the second sub-block is disconnected from the source line resistance.

23. The method according to claim 15, wherein, When the first preprogramming operation is performed: The channel of the plug included in the first sub-block is electrically connected to the wire, and The channel of the plug included in the second sub-block is disconnected from the bit line resistor.

24. The method according to claim 15, wherein, When the second pre-programming operation is performed: The second sub-block includes a plug whose channel is electrically connected to the wire, and The channel of the plug included in the first sub-block is disconnected from the bit line resistor.

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