A packaging process method of NPO light engine

Abstract

This application provides a packaging process method for an NPO optical engine. The method includes: preparing a silicon interposer and pre-treating the silicon interposer; mounting an AWG chip to the silicon interposer and curing the mounted workpiece; mounting a VCSEL array to the silicon interposer and curing the mounted workpiece; aligning and coupling a silicon lens array to the silicon interposer and curing the coupled workpiece; aligning and assembling an FA fiber array to the silicon interposer and curing the assembled workpiece; and performing bonding and heat dissipation packaging on the assembled workpiece to obtain the NPO optical engine. This application integrates an AWG chip and a VCSEL array within the same NPO, thereby reducing hardware costs, minimizing PCB layout space requirements, and lowering the deployment complexity of the computing cluster.

Description

Technical Field

[0001] This application relates to the field of optical technology, and in particular to a packaging process method for an NPO optical engine. Background Technology

[0002] The core of existing near-package optics (NPO) fabrication processes lies in high density, short interconnects, low power consumption, and efficient heat dissipation to meet the signal integrity and thermal management requirements of ultra-high speed scenarios.

[0003] However, existing NPO optical engine packaging processes only support the integration of a single path for either an Arrayed Waveguide Grating (AWG) chip or a Vertical-Cavity Surface-Emitting Laser (VCSEL) array. They cannot simultaneously integrate an AWG chip and a VCSEL array within the same NPO to achieve hybrid transmission of "short-distance VCSEL direct drive and long-distance AWG wavelength division multiplexing." To achieve this hybrid transmission functionality, two independent NPO optical engines need to be deployed, which increases hardware costs and printed circuit board (PCB) layout space, and also raises the deployment complexity of the computing cluster. Summary of the Invention

[0004] This application provides a packaging process method for an NPO optical engine, which aims to solve the technical problem that existing NPO optical engine packaging processes cannot simultaneously integrate an AWG chip and a VCSEL array in the same NPO.

[0005] In a first aspect, embodiments of this application provide a packaging process method for an NPO optical engine, the method comprising:

[0006] A silicon interposer layer is prepared, and the silicon interposer layer is pretreated.

[0007] The AWG chip is mounted to the silicon interposer, and the mounted workpiece is then cured.

[0008] The VCSEL array is mounted to the silicon interposer, and the mounted workpiece is then cured.

[0009] The silicon lens array is aligned and coupled to the silicon interposer, and the coupled workpiece is then cured.

[0010] The FA fiber array is aligned and assembled with the silicon interposer, and the assembled workpiece is then cured.

[0011] The assembled workpiece is then bonded and heat-dissipated and packaged to obtain the NPO optical engine.

[0012] Optionally, the preparation of the silicon interposer and the pretreatment of the silicon interposer include:

[0013] A silicon wafer substrate is selected and cleaned to obtain a silicon interposer layer;

[0014] Deep reactive ion etching (DRIE) is used to etch microchannels and copper pillar holes on the surface of the silicon interlayer using photoresist as a mask.

[0015] The copper pillar holes are filled with copper sulfate by electroplating and the surface is smoothed.

[0016] A titanium-platinum-gold three-layer metal layer was deposited on the surface of the silicon interlayer using a magnetron sputtering process.

[0017] Through photolithography and etching processes, optical path positioning marks corresponding to the AWG chip mounting positions, chip pads corresponding to the VCSEL array mounting positions, and gold wire bonding pads are formed on the metal layer.

[0018] The silicon interposer is baked.

[0019] The silicon interlayer is cleaned after baking.

[0020] Optionally, the step of mounting the AWG chip to the silicon interposer and curing the mounted workpiece includes:

[0021] Preprocess the AWG chip;

[0022] Epoxy silver paste is applied to the pre-mounted area of ​​the AWG chip in the silicon interposer layer.

[0023] The pre-processed AWG chip is placed on a pick-and-place machine, and the AWG chip is mounted to the silicon interposer with the optical path positioning mark of the silicon interposer as a reference.

[0024] The assembled workpieces are then subjected to segmented curing.

[0025] Optionally, the step of mounting the VCSEL array to the silicon interposer and curing the mounted workpiece includes:

[0026] Preprocess the VCSEL array;

[0027] A flip-chip bonding device is used to flip the VCSEL array so that the solder surface of the VCSEL array is aligned with the chip pads of the silicon interposer.

[0028] The VCSEL array is attached to the silicon interposer;

[0029] The mounted workpiece is then cured.

[0030] A gold wire bonding machine is used to perform gold wire bonding between the auxiliary electrode of the VCSEL array and the gold wire bonding pad of the silicon interposer.

[0031] Optionally, the step of aligning and coupling the silicon lens array with the silicon interposer, and then curing the coupled workpiece, includes:

[0032] Preprocessing of the silicon lens array;

[0033] The silicon interposer is fixed to the vacuum stage of the coupling device;

[0034] A high-speed signal source is connected to the driver end of the VCSEL array, and an optical power meter is connected to the output end of the AWG chip.

[0035] Start the coupling device and adjust the position of the silicon lens array using the six-axis fine-tuning frame on the coupling device;

[0036] When the optical power reaches its maximum value, the position of the six-axis fine-tuning frame is locked to complete the alignment and coupling of the silicon lens array and the silicon interposer.

[0037] The coupled workpiece is then subjected to UV curing.

[0038] The workpiece after UV curing is subjected to heat curing treatment.

[0039] Optionally, aligning and assembling the FA fiber array with the silicon interposer, and then curing the assembled workpiece, includes:

[0040] Preprocessing of FA fiber array;

[0041] The FA fiber array and the silicon lens array of the silicon interposer are aligned and assembled using a manual fine-tuning frame.

[0042] Apply epoxy adhesive in spots at the contact points between the FA fiber array and the silicon interposer;

[0043] After the epoxy adhesive has cured, a buffer adhesive is applied at the connection between the FA fiber array and the silicon interlayer.

[0044] After the buffer adhesive has cured, the output end face of the FA fiber array is flattened using a fiber optic cleaver.

[0045] Optionally, the bonding and heat dissipation encapsulation of the assembled workpiece to obtain the NPO optical engine includes:

[0046] The three-layer bonding interface of the assembled workpiece is bonded, and a stress buffer layer is prepared.

[0047] The microchannels of the silicon interposer are sealed and encapsulated, and then filled with a thermally conductive liquid.

[0048] Optionally, the bonding treatment of the three-layer bonding interface of the assembled workpiece and the preparation of the stress buffer layer include:

[0049] The three-layer bonding interface is cleaned. The three-layer bonding interface includes a first bonding interface composed of an AWG chip and a silicon interposer, a second bonding interface composed of a VCSEL array and a silicon interposer, and a third bonding interface composed of a silicon interposer and a PCBLGA interface.

[0050] Epoxy resin is coated on the first bonding interface and the second bonding interface;

[0051] Solder paste is applied to the pads of the PCB LGA interface at the first bonding interface.

[0052] A bonding machine is used to perform a three-layer stepped bonding of the first bonding interface, the second bonding interface, and the third bonding interface;

[0053] At the edge of the bonding interface between the silicon interposer and the PCB LGA interface, polyimide resin is applied using a dispensing machine to form a stress buffer layer.

[0054] The assembled workpiece is cured to allow the polyimide resin to form a buffer film.

[0055] Optionally, the sealing and encapsulation of the microchannels of the silicon interposer and the filling of thermally conductive fluid includes:

[0056] Laser sealing technology is used to seal the microchannels on the surface of the silicon interposer.

[0057] Vacuum the microchannels;

[0058] A piezoelectric micropump is used to slowly inject insulating thermally conductive fluid into the microchannel;

[0059] Connect the inlet and outlet of the microchannel to the liquid-cooled circulating pump.

[0060] Optionally, after performing bonding and heat dissipation encapsulation on the assembled workpiece to obtain the NPO optical engine, the method further includes:

[0061] The NPO optical engine was subjected to optical performance testing, electrical performance testing, thermal performance testing, and reliability testing.

[0062] Based on the optical performance test results, electrical performance test results, thermal performance test results, and reliability test results, the corresponding level of the NPO optical engine is determined.

[0063] This application provides a packaging process method for an NPO optical engine. The method includes: preparing a silicon interposer and pre-treating the silicon interposer; mounting an AWG chip to the silicon interposer and curing the mounted workpiece; mounting a VCSEL array to the silicon interposer and curing the mounted workpiece; aligning and coupling a silicon lens array to the silicon interposer and curing the coupled workpiece; aligning and assembling an FA fiber array to the silicon interposer and curing the assembled workpiece; and performing bonding and heat dissipation packaging on the assembled workpiece to obtain the NPO optical engine. In this application, by mounting the AWG chip to the silicon interposer and curing the mounted workpiece, and mounting the VCSEL array to the silicon interposer and curing the mounted workpiece, the AWG chip and VCSEL array are integrated into the same NPO, thereby reducing hardware costs, reducing PCB layout space occupation, and reducing the deployment complexity of the computing cluster. Attached Figure Description

[0064] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0065] Figure 1 This is a flowchart of a packaging process method for an NPO optical engine provided in an embodiment of this application. Detailed Implementation

[0066] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0067] See Figure 1 , Figure 1 This is a flowchart of a packaging process method for an NPO optical engine provided in an embodiment of this application, as shown below. Figure 1 As shown, the method includes the following steps:

[0068] Step 101: Prepare a silicon interposer and pretreat the silicon interposer.

[0069] Step 102: The AWG chip is attached to the silicon interposer, and the attached workpiece is cured.

[0070] Step 103: Mount the VCSEL array to the silicon interposer and cure the mounted workpiece.

[0071] Step 104: Align and couple the silicon lens array with the silicon interposer, and then perform a curing process on the coupled workpiece.

[0072] Step 105: Align and assemble the FA fiber array with the silicon interposer, and then cure the assembled workpiece.

[0073] Step 106: Perform bonding and heat dissipation encapsulation on the assembled workpiece to obtain the NPO optical engine.

[0074] In this embodiment, a silicon interposer is prepared and pretreated. An AWG chip is then mounted onto the pretreated silicon interposer, and the mounted workpiece is cured. A VCSEL array is then mounted onto the silicon interposer, and the mounted workpiece is cured.

[0075] Furthermore, the silicon lens array is aligned and coupled to the silicon interposer, and the coupled workpiece is then cured. The FA fiber array is then aligned and assembled to the silicon interposer, and the assembled workpiece is then cured.

[0076] By mounting the AWG chip and VCSEL array onto the silicon interposer, coupling the silicon lens array to the silicon interposer, and assembling the FA fiber array onto the silicon interposer, the above-mentioned components are bonded and heat-dissipated to obtain the NPO optical engine.

[0077] In this embodiment, by mounting the AWG chip to the silicon interposer and curing the mounted workpiece, and by mounting the VCSEL array to the silicon interposer and curing the mounted workpiece, the AWG chip and VCSEL array are integrated into the same NPO, thereby reducing hardware costs, reducing the space occupied by the PCB layout, and reducing the deployment complexity of the computing cluster.

[0078] Optionally, the preparation of the silicon interposer and the pretreatment of the silicon interposer include:

[0079] A silicon wafer substrate is selected and cleaned to obtain a silicon interposer layer;

[0080] Deep reactive ion etching (DRIE) is used to etch microchannels and copper pillar holes on the surface of the silicon interlayer using photoresist as a mask.

[0081] The copper pillar holes are filled with copper sulfate by electroplating and the surface is smoothed.

[0082] A titanium-platinum-gold three-layer metal layer was deposited on the surface of the silicon interlayer using a magnetron sputtering process.

[0083] Through photolithography and etching processes, optical path positioning marks corresponding to the AWG chip mounting positions, chip pads corresponding to the VCSEL array mounting positions, and gold wire bonding pads are formed on the metal layer.

[0084] The silicon interposer is baked.

[0085] The silicon interlayer is cleaned after baking.

[0086] In this embodiment, optionally, a 4-inch high-resistivity silicon wafer is cut into silicon wafer substrates of a preset size according to the wafer dicing line, and a three-stage cleaning process of "deionized water ultrasonic cleaning → anhydrous ethanol rinsing → nitrogen drying" is adopted to remove cutting debris, oil and oxide layer on the surface of the silicon wafer. The ultrasonic cleaning power is 150W and the time is 10min.

[0087] After cleaning, the silicon substrate surface is free of visible impurities, and the contact angle is ≤10° to ensure adhesion for subsequent etching and metallization processes. If the contact angle is >10°, ultrasonic cleaning is performed again, and a plasma cleaning step is added.

[0088] A deep reactive ion etching (DRIE) process is employed, using photoresist as a mask to etch spiral microchannels and vertical thermally conductive copper pillars onto the surface of the silicon interposer. Optionally, the microchannel width is 150μm±5μm, the depth is 200μm±5μm, and the pitch is 500μm, with each microchannel covering the core heat-generating area of ​​the AWG chip and VCSEL array. Optionally, the copper pillars have a diameter of 50μm±2μm, a depth of 300μm, and a spacing of 200μm, penetrating the silicon interposer and arranged in a matrix beneath the chip mounting area.

[0089] The etching depth and width are measured using a profilometer, with a deviation within ±5μm. The verticality of the etched sidewalls is checked using a microscope; a verticality ≥89.5° is required, with no lateral etching defects. If insufficient etching occurs, the etching time is extended by 5-10 minutes; if over-etching occurs, the photoresist mask thickness or etching power is adjusted. The copper pillar holes are filled with copper sulfate electroplating and the surface is smoothed. Specifically:

[0090] Before electroplating, the copper pillar holes are subjected to plasma cleaning to remove residual polymer from the etching process. The plasma cleaning power is 100W and the time is 15 minutes. Subsequently, chemical copper plating is performed as a base layer with a thickness of 5μm to ensure the conductivity of the inner wall of the copper pillar holes.

[0091] The process employs pulse electroplating with a current density of 2A / dm², a pulse frequency of 1kHz, a duty cycle of 50%, and an electroplating time of 60min±5min to ensure that the copper pillar holes are completely filled without any gaps or shrinkage cavities.

[0092] The excess copper layer on the surface of the silicon interposer is removed by chemical mechanical polishing, so that the surface of the copper pillar is flush with the surface of the silicon interposer, with a flatness of ≤0.2μm.

[0093] X-ray inspection is used to check the copper column filling rate, which must reach 100%. A roughness tester is used to check the surface flatness of the copper column, with a deviation ≤0.2μm. If filling voids are found, chemical copper plating is performed again as a base coat, followed by electroplating. If the flatness does not meet the standard, the polishing time is extended by 5-10 minutes.

[0094] Furthermore, a titanium-platinum-gold three-layer metal layer is deposited on the surface of the silicon interposer using magnetron sputtering. Specific parameters are: titanium layer 10nm, platinum layer 50nm, and gold layer 200nm. The titanium layer enhances adhesion, the platinum layer acts as an anti-corrosion and barrier layer, and the gold layer improves electrical connectivity and thermal conductivity. Through photolithography and etching processes, optical path positioning marks corresponding to the AWG chip mounting positions, chip pads corresponding to the VCSEL array mounting positions, and gold wire bonding pads are formed on the metal layers. Optionally, the optical path positioning marks are cross-shaped with a dimensional accuracy of ±0.5μm.

[0095] The metal layer thickness was measured using a film thickness gauge, with a deviation of ≤ ±5 nm; the positioning mark accuracy was measured using an image measuring instrument, with a deviation of ≤ ±0.5 μm. If the metal layer thickness did not meet the standard, the sputtering power and time were adjusted; if the positioning mark deviation exceeded the tolerance, photolithography and etching were repeated.

[0096] Furthermore, the prepared silicon interposer was placed in a vacuum oven and baked at 80℃±5℃ for 2 hours to remove surface moisture; then it was placed in a plasma cleaner and cleaned with argon plasma to improve surface wettability and subsequent bonding strength. The argon plasma cleaning power was 100W and the time was 15 minutes.

[0097] After cleaning, the silicon interposer surface shows no oxidation or discoloration, and the metal pad resistance is ≤0.01Ω. If the pad resistance exceeds the standard, perform plasma cleaning again to remove the surface oxide layer.

[0098] Optionally, the step of mounting the AWG chip to the silicon interposer and curing the mounted workpiece includes:

[0099] Preprocess the AWG chip;

[0100] Epoxy silver paste is applied to the pre-mounted area of ​​the AWG chip in the silicon interposer layer.

[0101] The pre-processed AWG chip is placed on a pick-and-place machine, and the AWG chip is mounted to the silicon interposer with the optical path positioning mark of the silicon interposer as a reference.

[0102] The assembled workpieces are then subjected to segmented curing.

[0103] In this embodiment, a 16 / 32-channel heatless AWG chip is selected. The input / output end faces of the AWG chip are ground to a 0.5°±0.1° bevel angle to avoid reflection of the optical signal at the end face and the generation of crosstalk. A coating is then applied to the ground end face. A composite antireflection membrane, with wavelengths covering 1260 to 1625 nm and an antireflection rate ≥99.5%, was used. An ultrasonic cleaner was employed, using a mixture of anhydrous ethanol and deionized water (volume ratio 1:1) as the cleaning solution, with a cleaning power of 100W and a time of 10 minutes, to remove dust and oil from the surface of the AWG chip. Subsequently, the chip was dried under a nitrogen atmosphere (60℃, 30 minutes).

[0104] The antireflection coating's transmittance was measured using a spectrophotometer to ensure it was ≥99.5%. The AWG chip's end face was inspected using a microscope for scratches and chipping. If the transmittance did not meet the standard, the antireflection coating was re-deposited; if chipping was found on the end face, the AWG chip was discarded. An epoxy silver paste was applied to the pre-set mounting area of ​​the AWG chip with a silicon interposer using a dispensing machine. The epoxy silver paste thickness was controlled at 20μm ± 2μm, and the application area matched the bottom dimensions of the AWG chip to prevent paste overflow and contamination of the optical path.

[0105] The adhesive layer thickness was measured using an adhesive thickness gauge, with a deviation of ≤ ±2μm; the adhesive was free of bubbles and agglomerates. If the adhesive layer was too thick, it was wiped clean and reapplied; if bubbles were present, it was allowed to stand for 10 minutes to dissipate before installation.

[0106] The pre-treated AWG chip is placed on the nozzle of a high-precision pick-and-place machine. Using the optical path positioning marks on the silicon interposer as a reference, precise alignment is achieved through a machine vision system, with placement accuracy controlled within ±1μm. Uniform pressure is applied during placement to ensure full contact between the bottom of the AWG chip and the epoxy silver paste; optionally, the pressure is 2N.

[0107] A video measuring instrument is used to monitor the placement position in real time to ensure that the X / Y direction deviation of the AWG chip is ≤±1μm and the angle deviation is ≤±0.1°. If the deviation exceeds the tolerance, the automatic correction function of the pick-and-place machine is activated and the chip is re-placed.

[0108] The mounted workpiece is placed in a temperature-controlled curing oven and cured in stages under a nitrogen atmosphere to prevent chip deformation caused by high temperatures. The oxygen content in the temperature-controlled curing oven is ≤100ppm. The temperature of the temperature-controlled curing oven is first controlled at 120℃±5℃, and the holding time is 30 minutes for primary curing to ensure complete curing of the epoxy silver paste.

[0109] After curing, the chip mounting strength is tested using a push-pull force tester, with a shear force ≥10N; the adhesive layer is inspected under a microscope, with no cracks or overflow. If the shear force is insufficient, extend the main curing time by 10-15 minutes; if adhesive overflows, gently wipe it with a lint-free cotton swab dipped in anhydrous ethanol.

[0110] After curing is completed, positional accuracy and conductivity are checked. Positional accuracy is checked using an image measuring instrument to detect the final mounting deviation of the AWG chip, which must be ≤±1μm. Conductivity is checked using a conductivity tester to detect the conductivity between the electrodes of the AWG chip and the metal pads of the silicon interposer, ensuring that there are no open circuits or short circuits.

[0111] Only after both tests meet the standards can the next process begin; unqualified products are rejected and reworked.

[0112] Optionally, the step of mounting the VCSEL array to the silicon interposer and curing the mounted workpiece includes:

[0113] Preprocess the VCSEL array;

[0114] A flip-chip bonding device is used to flip the VCSEL array so that the solder surface of the VCSEL array is aligned with the chip pads of the silicon interposer.

[0115] The VCSEL array is attached to the silicon interposer;

[0116] The mounted workpiece is then cured.

[0117] A gold wire bonding machine is used to perform gold wire bonding between the auxiliary electrode of the VCSEL array and the gold wire bonding pad of the silicon interposer.

[0118] In this embodiment, an 8 / 16-channel 200G PAM4 VCSEL array chip can be selected, with its light emission direction parallel to the chip surface. First, the VCSEL array is cleaned using a plasma cleaner (80W power, 10min) to remove the oxide layer and impurities from the chip surface. If the chip surface is not pre-deposited with gold-tin eutectic solder, a 15μm thick Au80Sn20 eutectic solder is deposited using a vapor deposition process.

[0119] Microscopic examination of the chip surface revealed no scratches or oxide spots; the solder layer thickness was uniform, with a deviation of ≤±1μm. If oxide spots were present on the surface, the plasma cleaning time was extended; if the solder thickness was uneven, re-deposit.

[0120] A flip-chip bonding system is used to flip the VCSEL array, aligning the solder surface of the chip with the chip pads of the silicon interposer. During the mounting process, a dual-field-of-view microscope is used for real-time monitoring to ensure that each output port of the VCSEL array is coaxially aligned with the corresponding input waveguide of the AWG chip, with an alignment accuracy controlled within ±0.8μm. A pressure of 5N is applied during mounting to initially bond the solder to the pads.

[0121] The alignment accuracy is monitored in real time to ensure that the X / Y direction deviation is ≤ ±0.8μm and the angle deviation is ≤ ±0.1°. If the alignment deviation exceeds the tolerance, the equipment will automatically reset and re-attach.

[0122] The mounted workpiece is placed in a eutectic furnace and eutectic curing is performed in a nitrogen atmosphere (oxygen content ≤50ppm). The temperature profile is strictly controlled to avoid high-temperature damage to the chip. During the heating phase: the temperature is increased to 280℃±5℃ at a rate of 5℃ / s; during the holding phase: 280℃ for 10s to ensure that the Au80Sn20 solder is completely melted into a eutectic alloy; during the cooling phase: the temperature is reduced to room temperature at a rate of 2℃ / s to form a dense alloy bonding layer.

[0123] After curing, the bonding layer was inspected under a microscope and found to be free of voids, cracks, and segregation. The bonding strength was tested using a push-pull force tester, with a shear force ≥15N. If solder voids were found, the heating rate of the eutectic furnace was adjusted; if the bonding strength was insufficient, the original solder was removed and eutectic curing was repeated.

[0124] A fully automated gold wire bonding machine was used to bond the auxiliary electrodes of the VCSEL array to the gold wire bonding pads of the silicon interposer. The gold wire parameters were: diameter 25μm, bonding point spacing 50μm, and wire length controlled within 2mm to reduce high-speed signal transmission loss. The bonding pressure was controlled at 150g, and the ultrasonic power at 80W to ensure a strong bond without detachment.

[0125] After bonding, the electrical connection performance is tested using a network analyzer with a frequency range of 0-110GHz. The single-channel signal insertion loss is ≤0.5dB, and the return loss is ≥15dB. If the signal loss exceeds the standard, check if the gold wire length exceeds the standard, and rebond if necessary; if the bonding point falls off, adjust the bonding pressure and ultrasonic power.

[0126] In this embodiment, the limitations of existing single-path integration are overcome, and a hybrid optical path collaborative process with "horizontal waveguide as the main component and 45° reflection steering as the auxiliary component" is innovatively designed. By precisely controlling the horizontal waveguide layout of the AWG chip, the light output direction positioning of the VCSEL array, and the etching accuracy of the 45° total reflection surface, conflict-free transmission of short-distance optical signals from the VCSEL array and long-distance wavelength division multiplexing (WDM) optical signals from the AWG chip is achieved on the same silicon interposer. This allows a single NPO optical engine to simultaneously support both short-distance direct drive and long-distance WDM transmission, and is compatible with 1.6T / 3.2T / 6.4T multi-rate configurations.

[0127] Optionally, the step of aligning and coupling the silicon lens array with the silicon interposer, and then curing the coupled workpiece, includes:

[0128] Preprocessing of the silicon lens array;

[0129] The silicon interposer is fixed to the vacuum stage of the coupling device;

[0130] A high-speed signal source is connected to the driver end of the VCSEL array, and an optical power meter is connected to the output end of the AWG chip.

[0131] Start the coupling device and adjust the position of the silicon lens array using the six-axis fine-tuning frame on the coupling device;

[0132] When the optical power reaches its maximum value, the position of the six-axis fine-tuning frame is locked to complete the alignment and coupling of the silicon lens array and the silicon interposer.

[0133] The coupled workpiece is then subjected to UV curing.

[0134] The workpiece after UV curing is subjected to heat curing treatment.

[0135] A wafer-level silicon lens array is selected, with its lens spacing perfectly matching the channel spacing of the VCSEL array and AWG chip. A 45° total reflection surface is integrated into the lens surface, fabricated using photolithography and etching processes, achieving a surface roughness ≤5nm. An anti-reflection coating with an anti-reflection rate ≥99.5% is deposited on both the lens surface and the 45° reflection surface. Dust and oil are removed by gently wiping the lens surface with a lint-free cloth dampened with anhydrous ethanol.

[0136] The surface roughness of the lens is measured using a laser interferometer to ensure it is ≤5nm; the anti-reflection rate is measured using a spectrophotometer to ensure it is ≥99.5%. If the roughness of the reflective surface exceeds the standard, it is repolished; if the anti-reflection rate does not meet the standard, it is re-coated.

[0137] A silicon interposer is fixed to the vacuum stage of a six-axis automated coupling device, ensuring no workpiece movement. The silicon lens array is placed on the device's six-axis fine-tuning frame, with a motion accuracy of 0.1 μm / step. A high-speed signal source is connected to the driver of the VCSEL array, and an optical power meter is connected to the output of the AWG chip, establishing a closed-loop test link of "signal transmission-coupling-reception". The coupling device is started, and the six-axis fine-tuning frame moves the silicon lens array in the X / Y / Z axes while rotating it around the X / Y axes, adjusting the lens position in real time. The optical power meter continuously monitors the optical power at the AWG output; when the optical power reaches its maximum value (coupling efficiency ≥ 85%), the position of the six-axis fine-tuning frame is locked.

[0138] After alignment, ensure that single-channel coupling insertion loss is ≤2.2dB, inter-channel crosstalk is ≤-35dB, and alignment accuracy is ≤0.3μm. If the optical power cannot reach the maximum value, check whether the lens and chip channels are aligned, and readjust the fixture positioning if necessary; if the insertion loss exceeds the standard, check whether there are stains on the lens surface and clean it again.

[0139] To ensure long-term stability of the coupling position, a dual curing process of "UV pre-curing + thermal curing" is employed. UV adhesive is applied to the contact gap between the silicon lens array and the silicon interposer, and then irradiated with a 365nm UV lamp (intensity 100mW / cm², time 30s) to rapidly cure the UV adhesive, temporarily locking the lens position—this is UV pre-curing. The workpiece is then placed in a constant-temperature curing oven and cured at 100℃±5℃ for 1 hour to fully cure the UV adhesive, forming a permanent fixation—this is thermal curing. During the curing process, the six-axis fine-tuning frame of the coupling device is kept locked to prevent lens position displacement.

[0140] After curing, the coupled light power is tested again to ensure that the power attenuation is ≤0.1dB. The UV adhesive is inspected under a microscope to ensure there is no overflow or bubbles. If the power attenuation exceeds the standard, it indicates that the lens has shifted during the curing process, and the UV adhesive needs to be removed and the coupling re-aligned. If the UV adhesive overflows, it should be gently wiped away with a lint-free cotton swab dipped in acetone.

[0141] In this embodiment, an active alignment coupling process with closed-loop optical power feedback and six-axis submicron level linkage is employed, based on automated coupling equipment. The coupling process of the silicon lens array, VCSEL array, and AWG chip is linked to real-time optical power monitoring, achieving an alignment accuracy of ≤0.3μm. Simultaneously, combined with the 45° total internal reflection surface integration process of wafer-level silicon lenses, the average insertion loss of multiple channels is controlled to ≤2.2dB, and inter-channel crosstalk is ≤-35dB, effectively reducing losses.

[0142] Optionally, aligning and assembling the FA fiber array with the silicon interposer, and then curing the assembled workpiece, includes:

[0143] Preprocessing of FA fiber array;

[0144] The FA fiber array and the silicon lens array of the silicon interposer are aligned and assembled using a manual fine-tuning frame.

[0145] Apply epoxy adhesive in spots at the contact points between the FA fiber array and the silicon interposer;

[0146] After the epoxy adhesive has cured, a buffer adhesive is applied at the connection between the FA fiber array and the silicon interlayer.

[0147] After the buffer adhesive has cured, the output end face of the FA fiber array is flattened using a fiber optic cleaver.

[0148] A high-precision V-groove FA fiber array with a core spacing of 250μm is selected, perfectly matching the channel spacing of the silicon lens array. The input end face of the FA fiber array is ground to 42.5°±0.1° to match the 45° total reflection surface of the silicon lens array, preventing optical signal reflection. A 10μm thick abrasion-resistant protective layer is coated on the ground end face to enhance its abrasion and corrosion resistance. The output end of the FA fiber array is cut to a length of 1m, ensuring that the fiber is free from bending and breakage.

[0149] An angle meter was used to check the end-face grinding angle, ensuring the deviation was ≤ ±0.1°. A microscope was used to inspect the fiber end face, ensuring no chipping or contamination. If the angle deviation exceeded the tolerance, the fiber was re-ground; if the fiber was bent, the FA fiber array was discarded. The pre-treated FA fiber array was placed at the preset position at the output end of the silicon lens array. Using the edge positioning marks of the silicon lens array as a reference, passive alignment was performed using a manual fine-tuning frame. During alignment, the alignment of the FA fiber core and the lens was observed under a microscope, ensuring an alignment accuracy of ≤ ±1μm. Assembly was performed gently to avoid subjecting the fiber to tension or bending forces.

[0150] After alignment, the optical power at the output of the FA fiber array is measured using an optical power meter. Compared with the optical power at the output of the AWG chip, the loss should be ≤0.3dB. If the loss exceeds the standard, the position of the FA fiber array is fine-tuned until the loss meets the standard; if the fiber is bent, it is reassembled.

[0151] Low-modulus epoxy adhesive was applied in spots at the contact points between the FA fiber array and the silicon interposer, with the adhesive layer thickness controlled at 30 μm ± 2 μm. The mixture was allowed to stand at room temperature for 30 minutes to allow initial curing. A 50 μm thick elastic buffer adhesive was then applied to the junction between the FA fiber array and the silicon interposer, covering the root of the FA fiber array to buffer thermal stress caused by temperature changes. The workpiece was then left at room temperature for 2 hours to ensure complete curing of both adhesive layers.

[0152] After curing, the fixing strength of the FA fiber array is tested using a push-pull force tester to ensure that the tensile force is ≥5N and that the FA is not loose or bent. If the fixing strength is insufficient, the curing time is extended; if the FA fiber array is loose, the adhesive is reapplied for fixing.

[0153] A high-precision fiber optic cleaver is used to smoothly cut the output end face of the FA fiber array, with a flatness of ≤1μm. After cutting, a lint-free cloth dampened with anhydrous ethanol is used to gently wipe the end face to remove cutting debris.

[0154] Microscopic inspection of the cut end face revealed a smooth, burr-free surface and no damage to the fiber core. Handling of anomalies: If burrs are present on the end face, recut; if the fiber core is damaged, discard the entire FA fiber array.

[0155] Optionally, the bonding and heat dissipation encapsulation of the assembled workpiece to obtain the NPO optical engine includes:

[0156] The three-layer bonding interface of the assembled workpiece is bonded, and a stress buffer layer is prepared.

[0157] The microchannels of the silicon interposer are sealed and encapsulated, and then filled with a thermally conductive liquid.

[0158] Optionally, the bonding treatment of the three-layer bonding interface of the assembled workpiece and the preparation of the stress buffer layer include:

[0159] The three-layer bonding interface is cleaned. The three-layer bonding interface includes a first bonding interface composed of an AWG chip and a silicon interposer, a second bonding interface composed of a VCSEL array and a silicon interposer, and a third bonding interface composed of a silicon interposer and a PCBLGA interface.

[0160] Epoxy resin is coated on the first bonding interface and the second bonding interface;

[0161] Solder paste is applied to the pads of the PCB LGA interface at the first bonding interface.

[0162] A bonding machine is used to perform a three-layer stepped bonding of the first bonding interface, the second bonding interface, and the third bonding interface;

[0163] At the edge of the bonding interface between the silicon interposer and the PCB LGA interface, polyimide resin is applied using a dispensing machine to form a stress buffer layer.

[0164] The assembled workpiece is cured to allow the polyimide resin to form a buffer film.

[0165] In this embodiment, the three bonding interfaces are meticulously cleaned. For the first bonding interface, plasma cleaning (80W power, 10min) is used to remove residual adhesive residue after mounting and curing. For the second bonding interface, anhydrous ethanol is used to wipe away residual flux after gold wire bonding. For the third bonding interface, sandblasting is used to treat the PCB pad surface to remove the oxide layer, followed by plasma cleaning.

[0166] Ensure that all bonding interfaces are free of impurities and oxide layers, and have good surface wettability. If there are stubborn stains on the interfaces, clean them again using ultrasonic cleaning.

[0167] Different bonding materials are applied based on the material properties of each bonding interface. For the first and second bonding interfaces, epoxy adhesive is applied, with a thickness of 20μm±2μm, and it is only applied to the bonding area at the chip edge to avoid contaminating the optical path and electrical connection points. For the third bonding interface, solder paste is applied to the pads of the PCB LGA interface, with a thickness of 15μm±2μm, and the pads correspond one-to-one with the metal pads of the silicon interposer.

[0168] Ensure the bonding material is applied evenly, free of bubbles and agglomerates, and does not contaminate non-bonded areas. If the coating is uneven, gently smooth it with a scraper; if non-bonded areas are contaminated, wipe them with a lint-free cotton swab dipped in anhydrous ethanol.

[0169] A high-precision bonding machine is used for three-layer stepped bonding, with different process parameters for each layer to suit the bonding characteristics of different materials, as shown in Table 1: Table 1:

[0170]

[0171] After each bonding layer is completed, an image measuring instrument is used to check the alignment accuracy. Only after the accuracy is met can the next bonding layer be performed. The third bonding layer must be performed in a nitrogen atmosphere to avoid solder paste oxidation. If the alignment deviation of any layer exceeds the tolerance, bonding must be stopped immediately, the bonding material removed, and the components remounted. If the solder paste is oxidized, new solder paste must be replaced and the pads cleaned again.

[0172] At the bonding interface edge between the silicon interposer and the PCB LGA interface, polyimide resin is applied using a dispensing machine to form a ring-shaped stress buffer layer with a thickness of 30μm±2μm, completely covering the connection gap between the two layers. After coating, the workpiece is placed in a curing oven and cured at 150℃±5℃ for 1 hour, allowing the polyimide resin to form a highly elastic buffer film.

[0173] Ensure the buffer layer is free of cracks and peeling, and completely covers the joint gaps; its elastic modulus should be ≤5GPa, providing good stress release capability. If the buffer layer cracks, extend the curing time; if it does not cover the gaps, reapply adhesive.

[0174] A helium mass spectrometer leak detector was used to perform an overall airtightness test on the bonded photoengine. The workpiece was placed in a leak detection chamber, filled with helium, and the helium leakage rate was measured.

[0175] Ensure helium leakage rate ≤ This ensures that the internal components of the light engine are protected from external moisture and dust. If the leakage rate exceeds the standard, use a microscope to check for leaks, apply epoxy adhesive to the gaps, and retest until the standard is met.

[0176] In this embodiment, an innovative process scheme of "three-layer stepped bonding + polyimide stress buffer" is designed. Following the sequence of "silicon photonic chip - silicon interposer", "VCSEL array - silicon interposer", and "silicon interposer - PCB LGA interface", differentiated bonding temperatures, pressures and materials are used, combined with a polyimide buffer layer to release thermal stress, solving the cracking and detachment problems of heterogeneous material bonding and meeting reliability requirements.

[0177] Optionally, the sealing and encapsulation of the microchannels of the silicon interposer and the filling of thermally conductive fluid includes:

[0178] Laser sealing technology is used to seal the microchannels on the surface of the silicon interposer.

[0179] Vacuum the microchannels;

[0180] A piezoelectric micropump is used to slowly inject insulating thermally conductive fluid into the microchannel;

[0181] Connect the inlet and outlet of the microchannel to the liquid-cooled circulating pump.

[0182] In this embodiment, laser sealing is used to seal the spiral microchannels on the surface of the silicon interposer. The sealing material is an ultrathin silicon capping plate (50μm thick). During sealing, the laser power is controlled at 50W and the scanning speed is 10mm / s to ensure that a dense weld seam is formed between the silicon capping plate and the edge of the microchannel, without leakage.

[0183] After the sealing is completed, deionized water is introduced into the microchannel for a pressure test (0.5 MPa) for 30 minutes. No leakage or seepage is observed. If leakage occurs, laser welding is applied to the leak point, and the pressure test is repeated.

[0184] The microchannels of the light engine are evacuated (vacuum degree ≤10Pa) to prevent air bubbles from forming during filling, thus achieving air venting before filling. A piezoelectric micropump is used to slowly inject insulating thermally conductive fluid into the microchannels at a filling rate of 1mL / min, ensuring the microchannels are completely filled with thermally conductive fluid without any residual air bubbles, thus achieving thermally conductive fluid filling. The inlet and outlet of the microchannels are connected to a micro liquid-cooled circulation pump, and air-cooled heat sink fins are installed on the top of the light engine, with a pre-installed interface for connection to the rack's air-cooling system.

[0185] After filling, X-ray inspection of the microchannels is used to ensure there are no air bubbles; the liquid cooling circulation system should operate without blockages or leaks. If air bubbles are found, vacuum the system again and fill the system again; if the system is blocked, check the microchannels for weld slag residue, clean it, and reconnect it.

[0186] The light engine was connected to the test platform to simulate high-power conditions (single light engine power consumption 40W). Three modes, namely "pure air cooling", "pure liquid cooling" and "composite heat dissipation", were turned on to test the temperature of the chip surface.

[0187] In pure air-cooling mode: chip temperature ≤75℃;

[0188] Pure liquid cooling mode: chip temperature ≤65℃;

[0189] Composite heat dissipation mode: chip temperature ≤ 60℃.

[0190] In all three modes, the chip temperature met the preset specifications; and after high and low temperature cycling tests (-40℃-85℃, 10 cycles), the heat dissipation system showed no leaks or malfunctions. If the temperature exceeds the limit, adjust the flow rate of the liquid cooling circulation pump (≥5mL / min), or clean the dust from the air-cooled heat sink fins.

[0191] In this embodiment, an innovative integrated heat dissipation process of "silicon interposer integrated microchannel + thermally conductive copper pillar" is developed. A spiral microchannel is constructed inside the silicon interposer using the DRIE etching process, which, combined with vertically conductive copper pillars, forms a composite heat dissipation path of "lateral liquid cooling + vertical heat conduction," with a thermal resistance ≤0.5℃ / W. Simultaneously, a pre-reserved air-cooling interface is provided to enable adaptive switching between liquid cooling (high power) and air cooling (low power), with a coupling position offset ≤0.5μm within a wide temperature range of -40℃ to 85℃.

[0192] Optionally, after performing bonding and heat dissipation encapsulation on the assembled workpiece to obtain the NPO optical engine, the method further includes:

[0193] The NPO optical engine was subjected to optical performance testing, electrical performance testing, thermal performance testing, and reliability testing.

[0194] Based on the optical performance test results, electrical performance test results, thermal performance test results, and reliability test results, the corresponding level of the NPO optical engine is determined.

[0195] The test items and test standards mentioned above are shown in Table 2:

[0196] Table 2:

[0197]

[0198] Only products that pass all tests can proceed to the cutting process; defective products are marked and processed centrally later.

[0199] A wafer dicing machine is used to dice the wafers with high precision. During dicing, the dicing blade rotates at 30,000 rpm, and the dicing speed is 5 mm / s. Water cooling is used to prevent heat damage to the devices during dicing.

[0200] Ensure that the dimensional deviation of the finished light engine after cutting is ≤±0.1mm, and that there are no chips or burrs on the edges. If the dimensional deviation exceeds the tolerance, adjust the positioning parameters of the cutting machine; if there are chips on the edges, replace the cutting blade.

[0201] Based on the performance test results, NPO optical engines were categorized into three levels: "Superior," "Qualified," and "Unqualified." Superior engines are used in high-end AI computing clusters, qualified engines are used in mid-to-low-end scenarios, and unqualified engines are dismantled and recycled for raw materials. Superior and qualified engines were packaged using anti-static methods, with each NPO optical engine placed individually in an anti-static bag, along with desiccant and cushioning foam, to ensure no damage during transportation. After packaging, a second visual inspection was conducted; no scratches or damage were found, and the packaging labels were clear.

[0202] The packaging process of the NPO optical engine provided in this application has significant advantages in terms of performance, reliability, and mass production. A comparison with existing processes is shown in Table 3.

[0203] Table 3:

[0204]

[0205] In an optional embodiment, the performance test results of the NPO optical engine prepared using the packaging process method provided in this application are as follows:

[0206] Optical performance: 32-channel average insertion loss of 2.05dB, maximum crosstalk of -37.2dB, meeting the performance requirements of 6.4T expansion.

[0207] Thermal performance: Under 40W high power conditions, the chip operates at a temperature of 62℃. After high and low temperature cycling from -40℃ to 85℃, the coupling offset is 0.38μm.

[0208] Reliability: It has completed 1,000 high and low temperature cycles and 500 thermal shock tests without bond cracking or fiber detachment, and the performance degradation is ≤0.1dB.

[0209] Mass production capability: The pilot production line achieved a yield rate of 87.5%, and the manufacturing cost of a single optical engine was reduced by 50%.

[0210] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0211] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0212] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A packaging process method of NPO light engine, characterized in that, The method includes: A silicon interposer layer is prepared, and the silicon interposer layer is pretreated. The AWG chip is mounted to the silicon interposer, and the mounted workpiece is then cured. The VCSEL array is mounted to the silicon interposer, and the mounted workpiece is then cured. The silicon lens array is aligned and coupled to the silicon interposer, and the coupled workpiece is then cured. The FA fiber array is aligned and assembled with the silicon interposer, and the assembled workpiece is then cured. The assembled workpiece is then bonded and heat-dissipated and packaged to obtain the NPO optical engine; The preparation of the silicon interposer and the pretreatment of the silicon interposer include: A silicon wafer substrate is selected and cleaned to obtain a silicon interposer layer; Deep reactive ion etching (DRIE) is used to etch microchannels and copper pillar holes on the surface of the silicon interlayer using photoresist as a mask. The copper pillar holes are filled with copper sulfate by electroplating and the surface is smoothed. A titanium-platinum-gold three-layer metal layer was deposited on the surface of the silicon interlayer using a magnetron sputtering process. Through photolithography and etching processes, optical path positioning marks corresponding to the AWG chip mounting positions, chip pads corresponding to the VCSEL array mounting positions, and gold wire bonding pads are formed on the metal layer. The silicon interposer is baked. Clean the silicon interlayer after baking; The process of bonding and heat dissipation encapsulation of the assembled workpiece to obtain the NPO optical engine includes: The three-layer bonding interface of the assembled workpiece is bonded, and a stress buffer layer is prepared. The microchannels of the silicon interposer are sealed and encapsulated, and then filled with a thermally conductive liquid. The bonding process for the three-layer bonding interfaces of the assembled workpiece and the preparation of the stress buffer layer include: The three-layer bonding interface is cleaned. The three-layer bonding interface includes a first bonding interface composed of an AWG chip and a silicon interposer, a second bonding interface composed of a VCSEL array and a silicon interposer, and a third bonding interface composed of a silicon interposer and a PCB LGA interface. Epoxy resin is coated on the first bonding interface and the second bonding interface; Solder paste is applied to the pads of the PCB LGA interface at the third bonding interface. A bonding machine is used to sequentially perform three-layer stepped bonding on the first bonding interface, the second bonding interface, and the third bonding interface. The bonding temperature for the first bonding interface is 120℃±5℃, the pressure is 3N, and the time is 20s; the bonding temperature for the second bonding interface is 130℃±5℃, the pressure is 4N, and the time is 25s; and the bonding temperature for the third bonding interface is 260℃±5℃, the pressure is 5N, and the time is 30s. At the edge of the bonding interface between the silicon interposer and the PCB LGA interface, polyimide resin is applied using a dispensing machine to form a stress buffer layer. The assembled workpiece is cured to allow the polyimide resin to form a buffer film.

2. The method according to claim 1, characterized in that, The process of mounting the AWG chip to the silicon interposer and curing the mounted workpiece includes: Preprocess the AWG chip; Epoxy silver paste is applied to the pre-mounted area of ​​the AWG chip in the silicon interposer layer. The pre-processed AWG chip is placed on a pick-and-place machine, and the AWG chip is mounted to the silicon interposer with the optical path positioning mark of the silicon interposer as a reference. The assembled workpieces are then subjected to segmented curing.

3. The method according to claim 1, characterized in that, The process of mounting the VCSEL array to the silicon interposer and curing the mounted workpiece includes: Preprocess the VCSEL array; A flip-chip bonding device is used to flip the VCSEL array so that the solder surface of the VCSEL array is aligned with the chip pads of the silicon interposer. The VCSEL array is attached to the silicon interposer; The mounted workpiece is then cured. A gold wire bonding machine is used to perform gold wire bonding between the auxiliary electrode of the VCSEL array and the gold wire bonding pad of the silicon interposer.

4. The method according to claim 1, characterized in that, The step of aligning and coupling the silicon lens array with the silicon interposer, and then curing the coupled workpiece, includes: Preprocessing of the silicon lens array; The silicon interposer is fixed to the vacuum stage of the coupling device; A high-speed signal source is connected to the driver end of the VCSEL array, and an optical power meter is connected to the output end of the AWG chip. Start the coupling device and adjust the position of the silicon lens array using the six-axis fine-tuning frame on the coupling device; When the optical power reaches its maximum value, the position of the six-axis fine-tuning frame is locked to complete the alignment and coupling of the silicon lens array and the silicon interposer. The coupled workpiece is then subjected to UV curing. The workpiece after UV curing is subjected to heat curing treatment.

5. The method according to claim 1, characterized in that, The process of aligning and assembling the FA fiber array with the silicon interposer, and then curing the assembled workpiece, includes: Preprocessing of FA fiber array; The FA fiber array and the silicon lens array of the silicon interposer are aligned and assembled using a manual fine-tuning frame. Apply epoxy adhesive in spots at the contact points between the FA fiber array and the silicon interposer; After the epoxy adhesive has cured, a buffer adhesive is applied at the connection between the FA fiber array and the silicon interlayer. After the buffer adhesive has cured, the output end face of the FA fiber array is flattened using a fiber optic cleaver.

6. The method according to claim 1, characterized in that, The process of sealing and encapsulating the microchannels of the silicon interposer and filling them with thermally conductive fluid includes: Laser sealing technology is used to seal the microchannels on the surface of the silicon interposer. Vacuum the microchannels; A piezoelectric micropump is used to slowly inject insulating thermally conductive fluid into the microchannel; Connect the inlet and outlet of the microchannel to a liquid-cooled circulating pump.

7. The method according to claim 1, characterized in that, After performing bonding and heat dissipation encapsulation on the assembled workpiece to obtain the NPO optical engine, the method further includes: The NPO optical engine was subjected to optical performance testing, electrical performance testing, thermal performance testing, and reliability testing. Based on the optical performance test results, electrical performance test results, thermal performance test results, and reliability test results, the corresponding level of the NPO optical engine is determined.

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