A method for suppressing inrush current of a staggered parallel soft-switching single-phase inverter

Abstract

The application discloses a starting inrush current suppression method for a staggered parallel soft-switching single-phase inverter, and belongs to the technical field of soft-switching control of power electronic converters. The application is used for solving the starting inrush current problem caused by the asymmetric first switching cycle conduction pulse width due to the carrier phase shift of the fixed frequency staggered parallel soft-switching single-phase inverter in the starting process. The application comprises the following steps: step one, zero phase shift synchronous starting, the controller forces the carrier of all corresponding units in all power modules to be synchronous, so that the initial conduction duty ratio of all units in the first cycle is 0.25; step two, transient self-current sharing, the zero phase shift synchronous state is maintained for several cycles, the inherent equivalent duty ratio negative feedback current sharing mechanism of the system is utilized to make the initial disturbance decay in an exponential law; step three, optimal trajectory phase shift, the carrier phase of the power module to be phase shifted is smoothly shifted from the synchronous state to a preset staggered angle at a constant angular velocity, the switch tube current does not exceed the safety limit value in the phase shift process, and the stable state closed loop control is switched after the phase shift is completed.

Description

Technical Field

[0001] This invention relates to a method for suppressing inrush current during startup of an interleaved parallel soft-switching single-phase inverter, specifically a soft-start method based on Zero Phase-Shift Synchronization and Optimal Trajectory (ZPS-OT), belonging to the field of soft-switching control technology for power electronic converters. Background Technology

[0002] Driven by distributed energy storage, electrified transportation, and high-precision industrial applications, single-phase inverters are evolving towards higher frequencies and higher power densities. To achieve zero-voltage switching (ZVS) across the entire load range, some single-phase inverters force the switching transistor current to cross zero and reverse in each switching cycle to drain the parasitic output capacitor charge. While this mechanism effectively achieves ZVS, it generates significant high-frequency current ripple. In engineering, this ripple is typically suppressed through multiphase interleaved parallel connection. Typical topologies include sinusoidal current mode (S-TCM), quadrilateral current mode (QCM), and auxiliary resonant commutator (ACRP) fixed-frequency ZVS inverters.

[0003] However, such interleaved parallel soft-switching inverters generally face a severe inrush current problem during startup. At startup, the inherent carrier phase shift of the interleaved parallel structure causes asymmetry in the conduction pulse width of each module during the first switching cycle. This asymmetry directly causes a unidirectional surge in the switching transistor current and inductor current within the inverter bridge arm within a very short time, forming an inrush current several times higher than the steady-state peak value. This inrush current not only threatens the safe operating area (SOA) of wide-bandgap (WBG) devices but also easily leads to transient saturation of magnetic components, severely restricting system reliability.

[0004] Existing soft-start methods (such as Pulse Frequency Modulation (PFM), Pulse Width Modulation (PWM), and Phase Shift Modulation (PSM)) are mainly designed for DC-DC converters. Their core idea is to maintain an extremely narrow initial conduction pulse during startup to limit the voltage rise rate and prevent inrush current caused by rapid energy accumulation. However, these methods have limited effectiveness in interleaved parallel inverters because the modulation command during startup typically increases slowly from zero, resulting in a gradual energy accumulation. The root cause of inrush current is not rapid energy accumulation, but rather the asymmetry in the initial conduction pulse width caused by carrier phase shift. Furthermore, while traditional optimal trajectory control (OTC) strategies can achieve precise current boundary constraints, their computational complexity is too high, making real-time deployment on high-frequency digital controllers difficult.

[0005] In summary, for fixed-frequency interleaved parallel soft-switching single-phase inverters, there is an urgent need for a soft-start strategy that can fundamentally eliminate the asymmetry caused by carrier phase shift and achieve smooth, overshoot-free startup. Summary of the Invention

[0006] To address the startup inrush current problem in fixed-frequency interleaved parallel soft-switching single-phase inverters caused by asymmetric conduction pulse width during the first switching cycle due to carrier phase shift, this invention provides a startup inrush current suppression method for interleaved parallel soft-switching single-phase inverters.

[0007] The present invention discloses a method for suppressing inrush current during startup in an interleaved parallel soft-switching single-phase inverter, wherein the inverter comprises... Each power module consists of two basic units connected in an interleaved parallel configuration. The carrier phases of the two basic units within the same power module differ by 180°. During steady-state interleaved operation, the carrier phase difference between corresponding basic units in adjacent power modules is... This inverter achieves zero-voltage switching by forcing the switching transistor current to reverse; it includes the following steps:

[0008] Step 1, Zero Phase Shift Synchronization Start-up Step: After receiving the enable signal, the controller temporarily cancels the steady-state interleaved phase shift between adjacent power modules, synchronizes the carrier phase of the corresponding basic unit in each power module, and makes the initial conduction duty cycle of all units in the first switching cycle 0.25.

[0009] Step 2, Transient Self-Synchronization Step: Maintain zero phase shift synchronization state for a duration of... By utilizing the system's inherent equivalent duty cycle negative feedback current sharing mechanism, the initial non-ideal disturbance decays exponentially. It is a time constant;

[0010] Step 3, Optimal Trajectory Phase Shifting Step: The carrier phase of each power module is smoothly shifted from the synchronous state to the preset interleaving angle at a constant angular velocity. During the phase shifting process, the switching current does not exceed the safety limit. After the phase shifting is completed, the system switches to steady-state closed-loop control.

[0011] Preferably, the number of interleaved parallel power modules =2, the inverter is a Δ-type inductor-assisted resonant commutator ACRP type single-phase inverter; the inverter includes a first power module and a second power module, the first power module is composed of unit A and unit B, and the second power module is composed of unit C and unit D;

[0012] Each unit contains four switching transistors, forming two half-bridge arms. The DC input terminals of the two half-bridge arms are connected in parallel, and an auxiliary inductor is connected between the midpoints of the two arms. The midpoints of the two arms are connected to the AC output terminals through filter inductors, forming a Δ-type inductor connection structure.

[0013] The output sides of each unit are connected in parallel to the common output terminal, and the auxiliary inductor in each unit is used to force the current to reverse cycle by cycle in order to achieve zero-voltage switching.

[0014] Preferably, step one specifically includes: after receiving the enable signal, the controller temporarily blocks the preset carrier phase shift angles of units C and D in the second power module, and forces the triangular carriers of units C and D to be synchronized and aligned with the triangular carriers of units A and B in the first power module, that is, the carrier phase shift angle satisfies =0°, =180°, so that the conduction angle of the first switch of all units is 90° and the initial conduction duty cycle is 0.25; These are the carrier phase shift angles for units A, B, C, and D, respectively.

[0015] Preferably, the time constant mentioned in step two Determined by the following formula:

[0016]

[0017] In the formula, The equivalent inductance of a delta-type inductor. This is the equivalent output capacitance of the switching transistor. For the switching cycle, For the parasitic resistance of the loop, This is the DC bus voltage. This represents the peak value of the steady-state switching transistor current.

[0018] Preferably, in step three, the controller linearly slides the carrier phase of unit C from 0° to 90° at a constant angular velocity, and linearly slides the carrier phase of unit D from 180° to 270°, so that the second power module as a whole restores a steady-state staggered phase shift of 90° relative to the first power module; during the sliding process, the system's inherent equivalent duty cycle negative feedback current sharing mechanism continuously suppresses the equivalent disturbance introduced by the phase shift; when the carrier phase transitions to the preset staggered angle, that is, unit C is 90° and unit D is 270°, the system switches from soft-start control to steady-state closed-loop control.

[0019] Preferably, the constant angular velocity in step three is Minimum phase shift time satisfy:

[0020]

[0021] In the formula, For the switching cycle, This is the DC bus voltage. For the parasitic resistance of the loop, Feedback gain coefficient: For the safety limit of the switching transistor current, This represents the peak value of the steady-state switching transistor current.

[0022] Preferably, the feedback gain coefficient Determined by the following formula:

[0023]

[0024] In the formula, This is the equivalent output capacitance of the switching transistor. This is the bias current.

[0025] Preferably, the switching current in step three does not exceed the safety limit, specifically satisfying the following conditions: ,in This represents the peak value of the steady-state switching transistor current. The dynamic bias current introduced for phase shifting. This refers to the safe current limit for the switching transistor.

[0026] Preferably, the dynamic bias current With phase shift angular velocity satisfy:

[0027]

[0028] in, This is the DC bus voltage. For the switching cycle, For feedback gain coefficient, This is the parasitic resistance of the circuit.

[0029] The beneficial effects of this invention are:

[0030] 1. Eliminate startup inrush current and improve device reliability

[0031] This invention, through zero-phase-shift synchronous startup in step one, forces all parallel units to have the same conduction pulse width (duty cycle of 0.25) in the first switching cycle, completely eliminating the asymmetry in the first-cycle conduction pulse width caused by the inherent carrier phase shift of the interleaved parallel structure. Experimental results show that, after adopting this invention, the peak value of the first-cycle switching transistor current in the unit with the most severe inrush current (carrier phase shift of 90°) is reduced from twice the steady-state peak value (approximately 20A) to less than the steady-state peak value (10A), completely eliminating the threat to the safe operating area of ​​wide bandgap devices such as SiCMOSFETs and avoiding transient saturation of magnetic components.

[0032] 2. Utilizing the system's inherent current sharing mechanism, no additional hardware or complex calculations are required.

[0033] Step two of this invention fully utilizes the inherent equivalent duty cycle negative feedback current sharing mechanism in fixed-frequency soft-switching inverters, without introducing any active control variables, relying entirely on the system's passive self-current sharing capability to dissipate the initial small bias. The experimentally measured time constant (29.87 μs) has a relative error of only 2.38% compared to the theoretically calculated value (30.6 μs), verifying the accuracy of the established first-order inertial model. This mechanism requires no additional hardware circuitry or complex online calculations, resulting in low implementation cost and high reliability.

[0034] 3. Achieve optimal trajectory phase shift, balancing safety margin and speed.

[0035] Step three of this invention, under the constraint of the current sharing mechanism, derives the analytical relationship between the dynamic bias current and the phase shift angular velocity during the phase shift process, and determines the optimal trajectory for linear sliding at a constant angular velocity based on this relationship. This strategy ensures that the switching current is always limited within a safe boundary throughout the entire phase shift process. = 15A) within the range, with the shortest phase shift time ( = 100μs), achieving an optimal balance between safety and speed.

[0036] 4. Suitable for various load types, with smooth and seamless transition.

[0037] This invention was experimentally verified under both resistive loads (18Ω) and inductive loads (4.8mH + 0.9Ω). The results show that under both load conditions, all current waveforms are smoothly established within the steady-state peak envelope, with the average value strictly maintaining zero bias, and no transient current overshoot or waveform abrupt changes. The switching process from open-loop soft start to high-frequency steady-state closed-loop control is smooth and seamless, verifying the universal applicability of this invention to different load types.

[0038] 5. Highly versatile, it can be extended to similar fixed-frequency ZVS inverters.

[0039] The core mechanism of this invention (zero phase shift synchronization → transient self-current sharing → optimal trajectory phase shift) does not depend on specific topology details and is applicable to any fixed-frequency ZVS single-phase inverter (such as S-TCM, QCM, ACRP, etc.) with periodic current reversal mechanism and interleaved parallel characteristics, and has good universality and engineering promotion value. Attached Figure Description

[0040] Figure 1 A schematic diagram of a single power module consisting of units A and B;

[0041] Figure 2 The diagram shows the carrier signal and modulation wave signal of each bridge arm when two power modules are connected in staggered parallel configuration.

[0042] Figure 3 The topology of a delta-type inductor ACRP converter with two power modules connected in staggered parallel configuration is shown.

[0043] Figure 4 This is a waveform diagram of the inverter's operation during the first switching cycle at startup.

[0044] Figure 5 This is a state-plane trajectory diagram of one unit of the inverter during startup, where Figure 5 (a) in the figure represents the current. The trajectory diagram, where 5(b) represents the current. The trajectory diagram;

[0045] Figure 6 A comparison of the transient waveforms of unit A and unit C during traditional startup, for resistive loads.

[0046] Figure 7 For a resistive load, the typical waveform of unit C during traditional startup is shown.

[0047] Figure 8 for Figure 7 A magnified view of a typical waveform;

[0048] Figure 9 Typical waveform diagram of unit C during ZPS-OT startup, for resistive load;

[0049] Figure 10 for Figure 9 A magnified view of a typical waveform;

[0050] Figure 11 For a resistive-inductive load, the typical waveform of unit C during traditional startup is shown.

[0051] Figure 12 for Figure 11 A magnified view of a typical waveform;

[0052] Figure 13 For a resistive-inductive load, the typical waveform of unit C during ZPS-OT startup;

[0053] Figure 14 for Figure 13 A magnified view of a typical waveform;

[0054] Figure 15 For a resistive load, the transient waveform of the switching current of unit C during conventional startup is shown.

[0055] Figure 16 This is the complete load current waveform of the inverter under the ZPS-OT soft-start strategy, where... Figure 16 (a) in the diagram represents a resistive load. Figure 16 (b) in the diagram represents an inductive load;

[0056] Figure 17 This is a flowchart of the overall process of the method of the present invention. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0059] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0060] Specific Implementation Method 1: The following is combined with... Figures 1 to 17 This embodiment describes a method for suppressing inrush current during startup in an interleaved parallel soft-switching single-phase inverter.

[0061] The following is based on A specific embodiment of the invention is a Δ-type inductor-assisted resonant commutator ACRP single-phase inverter with two power modules (interleaved parallel connection). The specific implementation of the invention is described in detail with reference to the accompanying drawings. It should be noted that the scope of protection of this invention is not limited to this specific embodiment; any fixed-frequency ZVS single-phase inverter with a periodic current reversal mechanism and interleaved parallel connection characteristics can adopt this method.

[0062] like Figure 1 As shown, a single power module comprises two basic units, Unit A and Unit B. Each unit consists of two half-bridge arms interconnected by an auxiliary inductor, and includes four SiC MOSFET switches and one auxiliary inductor. and two filter inductors Auxiliary inductor Zero-voltage switching (ZVS) is achieved across the entire load range by forcing cycle-by-cycle reverse discharge of the parasitic output capacitor. Taking unit A as an example, the switching transistor... and The first bridge arm is formed by connecting the nodes. Midpoint of bridge arm; switch transistor and The second bridge arm is formed by connecting the nodes. The midpoint of the bridge arm. Auxiliary inductor. Following and Between, filter inductor connect To the AC output terminal, filter inductor catch Connect to the AC output terminal. The positive terminal of the DC power supply is connected to the drain of each upper transistor, and the negative terminal is connected to the source of each lower transistor. Unit B has the same structure as Unit A, but its filter inductor... , and auxiliary inductor The parameters are the same as those of Unit A. Unit A has two filter inductors. The other end is connected to one end of the load, and the two filter inductors of unit B are connected together. The other end is connected to the other end of the load, and each end of the load is connected to an output filter capacitor. Grounding.

[0063] When two power modules are included, the system topology is as follows: Figure 3 As shown. Figure 3 In this inverter, units A and B constitute the first power module, and units C and D constitute the second power module. The output sides of each unit are connected in parallel to a common output terminal through filter inductors. Units C and D have the same structure as units A and B, and their auxiliary inductors and filter inductors have the same parameters. This inverter uses sinusoidal pulse width modulation (SPWM). Figure 2 The carrier signal and modulation signal of each arm are given when two power modules are connected in interleaved parallel. In the figure, and The triangular carriers corresponding to the two bridge arms of units A and B in the first power module. and The triangular carriers corresponding to the two bridge arms of units C and D in the second power module. For a common sinusoidal modulation wave. During steady-state interleaved operation, adjacent carriers are 90° out of phase to cancel out high-frequency output ripple. For [the following]... The general configuration of the power modules is as follows: the system has a total of 2 Each unit, the carrier phase shift angle difference between corresponding basic units in adjacent power modules During steady-state operation, the nominal carrier phase shift angle between adjacent power modules is denoted as... , abbreviated as carrier phase shift angle.

[0064] For ease of subsequent explanation, the main variables and symbols involved in this embodiment are uniformly defined as follows. Wherein, When the phase angle is 2, the system consists of units A and B forming the first power module, and units C and D forming the second power module. The steady-state values ​​of the carrier phase angle of the four units A, B, C, and D satisfy: =0°、 =180° =90° =270°. During the ZPS-OT soft boot process... The value will be adjusted temporarily according to the control strategy and will not be constant equal to the steady-state value.

[0065] definition This is a general term for auxiliary inductors; all auxiliary inductors use this value, i.e. ;definition This is a general term for filter inductors; all filter inductors use this value, i.e. ;definition This refers to the current output at the midpoint of the two bridge arms of Unit A, flowing through the corresponding switching transistors, where... Corresponding to the upper tube of the first bridge arm , Corresponding to the upper tube of the second bridge arm .definition For flow through the auxiliary inductor The current, For the flow through the filter inductor The current. The switching period is defined as... DC bus voltage is The parasitic resistance of the circuit is The equivalent output capacitance of the switching transistor is .definition This represents the peak value of the steady-state switching transistor current. This represents the peak value of the steady-state auxiliary inductor current. This represents the peak value of the steady-state filter inductor current. (Definition) This refers to the safe current limit for the switching transistor. (Definition) This is the equivalent characteristic impedance during the resonant commutation process. ω is the angular frequency at resonance. (Definition) This refers to the voltage at the inverter output or across the load. This is the output load current of the inverter.

[0066] To describe the transient process during the first switching cycle of startup, define ( () represents the boundary time of each operating mode within the first switching cycle, where The start time of the cycle, This is the end of the cycle. Figure 4 middle The time corresponding to the next cycle position is outside the scope of this definition. for Flow through the switching transistor at all times current The value, for Flow through the switching transistor at all times current The value. Definition. and They are respectively and The corresponding point in the state plane trajectory diagram. Definition For current Trajectory in the state plane Figure 5 The centers of the two resonant circles in (a) are For current Trajectory in the state plane Figure 5 The centers of the two resonant circles in (b) are; correspondingly, for The radii of the two resonant circles in the trajectory. for The radii of the two harmonic circles in the trajectory. Definition The initial duty cycle for initiating the first switching cycle; To account for the actual equivalent duty cycle after the dead zone and resonant commutation process; The digital control duty cycle command given to the controller; The duty cycle of the disturbance injected as an equivalent of continuous phase slip of the carrier.

[0067] The specific execution process of the ZPS-OT soft-start method of the present invention will be described in detail below with reference to the accompanying drawings. The method consists of three sequentially executed steps.

[0068] Step 1: Perform zero-phase-shift synchronous startup to reconstruct the initial transient boundary conditions and eliminate the inrush current in the first cycle. After the controller receives the enable signal, it temporarily masks the preset carrier phase shift angles of 90° and 270° for units C and D. During the initial few cycles, the triangular carriers of units C and D are forcibly synchronized with the triangular carriers of units A and B, i.e., the carrier phase shift angles satisfy... =0°, =180°. This ensures that the first switching transistor in all units has a conduction angle of 90°, and the initial conduction duty cycle is 180°. =0.25, the current in each unit rises smoothly and synchronously from zero to the steady-state peak value. In the state plane trajectory diagram, each state variable will directly enter the steady-state trajectory loop from the origin. To more clearly understand the necessity of step one, the generation mechanism of the inrush current is quantitatively analyzed below.

[0069] Start-up time ( The boundary conditions for this state differ from those for steady state, specifically in four aspects: all energy storage elements have zero initial energy; the output filter capacitor is not fully charged, and the voltage across the load is extremely low, approximating zero; the voltage across the filter inductor is approximately equal to the DC bus voltage during conduction. The inductor current rise rate is much higher than in steady state; modulation command The initial conduction pulse width of the switching transistor gradually increases from zero, determined solely by the carrier phase shift angle. The decision was made that the duty cycle would subsequently approach 0.5.

[0070] Under the above boundary conditions, the initial duty cycle of each unit during the first switching cycle. phase shift angle with carrier The relationship is:

[0071] ;

[0072] Taking unit A as an example, analysis of the first switching cycle of startup shows that the first switching cycle contains 4 working modes, which are divided into 2 resonant stages and 2 non-resonant stages. Figure 4 The waveforms of inverter unit A during startup are shown. Figure 5 The corresponding state plane trajectory diagram is given, where Figure 5 (a) in the figure represents the current. The trajectory diagram, Figure 5 (b) in the figure represents the current. The trajectory diagram. The switching cycle is set to... At the end of the first non-resonant phase, the switching current... Reaching a positive peak value, for :

[0073] ;

[0074] At the end of the second non-resonant phase, the switching current... Reaching a negative peak, for :

[0075] ;

[0076] Figure 4 The waveforms include the triangular carrier waves corresponding to the two bridge arms of unit A. and Corresponding switching transistor drive signal Auxiliary inductor current Filter inductor current and switching transistor current The waveform. (From) Figure 4 It can be seen that the first switching cycle can be divided into two non-resonant stages and two resonant stages: in the non-resonant stage, the inductor current rises or falls approximately linearly; in the resonant stage, the auxiliary inductor and the output capacitor of the switching transistor resonate and commutate to achieve zero-voltage turn-on of the switching transistor.

[0077] Figure 5 To and Figure 4 The corresponding state plane trajectory diagram is used to describe the change process of the current state during the first switching cycle of startup. Figure 5 The horizontal and vertical axes in the diagram represent the two state variables labeled in the figure. Figure 5 In (a), the x and y coordinates represent the switching transistors in unit A. voltage across the two ends and the equivalent characteristic impedance during the resonant commutation process With the current flowing through the switching transistor The product; Figure 5 In (b), the x and y coordinates represent the switching transistors in unit A. voltage across the two ends and the equivalent characteristic impedance during the resonant commutation process With the current flowing through the switching transistor The product of. Figure 5 Points in trajectory (a) correspond Moment as well as , Figure 5 Points in trajectory (b) correspond Moment as well as . Figure 5 In This represents the equivalent voltage bias of the center of the resonant circle relative to the horizontal axis in the state-plane trajectory diagram. Further analysis reveals that... Figure 5 The corresponding straight line segment Figure 4 In the non-resonant phase, the inductor current changes linearly under an approximately constant voltage; the circular arc segment in the trajectory corresponds to... Figure 4 During the resonant phase, energy exchange occurs between the auxiliary inductor and the output capacitor of the switching transistor. Whether the trajectory is symmetrical about the horizontal axis can be used to determine whether there is unidirectional current bias and inrush current during the startup process.

[0078] Therefore, during the non-resonant phase, each current (auxiliary inductor current) ; Filter inductor current The current output at the midpoint of the two bridge arms of Unit A, flowing through the switching transistor. ) and the first conduction duty cycle of the switching transistor The relationship is linear, depending on the carrier phase shift angle. It is also a linear relationship, corresponding to the straight line part in the state trajectory; the resonance stage corresponds to the circular arc part in the state trajectory. Due to the short time, the current values ​​remain basically unchanged.

[0079] by Taking the interleaved parallel connection as an example, we can obtain the phase shift angles of units A and B. =0°、 =180°, conduction ratio =0.25, the conduction angle of the first switching transistor is exactly 90°, at this time , Each current smoothly rises to its steady-state peak during the first non-resonant phase, and then transitions smoothly thereafter. Its state plane trajectory is symmetrical around the x-axis, without inrush current. Meanwhile, the phase shift angles of elements C and D... =90° =270°, its =0.5, the first conduction angle is 180°, causing the current to rise from zero to twice the steady-state peak value in the first switching cycle. ).

[0080] In summary, the inrush current amplitude and carrier phase shift angle are related. They exhibit a strictly linear relationship: Inside, The larger the initial flow, the more severe the initial inrush; when At 90°, the inrush reaches This poses a threat to the SOA of the switching transistor and may lead to deep saturation of the magnetic components.

[0081] After step one is completed, the process proceeds to step two, the transient self-current sharing stage. After ZPS synchronous startup, the large inrush current bias has been eliminated, but due to non-ideal factors such as parasitic parameter mismatch, dead-time effect, and the initial low-frequency impedance of the output filter capacitor, a small transient bias still exists between the phase currents. The dynamic phase-shifting operation in step three will also continuously inject equivalent disturbances. Therefore, before entering the phase-shifting stage, it is necessary to fully understand and utilize the system's inherent passive current sharing capability.

[0082] This current-sharing capability is commonly found in soft-switching inverters where the switching current reverses after crossing zero in each cycle. It primarily stems from the negative feedback mechanism of the equivalent duty cycle during the resonant commutation process. Due to the resonant charging and discharging of the inductor and the equivalent junction capacitance of the switching transistor during the dead time, the drain-source voltage of the switching transistor exhibits rising and falling edges with distinct slopes, thus affecting the actual equivalent duty cycle. Deviation from digital control instructions :

[0083] ;

[0084] in, Dead time, rising edge duration and duration of falling edge They are respectively:

[0085] ;

[0086] In the formula, for The negative trough value, for The positive peak value, The characteristic impedance at resonance. ω is the angular frequency at resonance.

[0087] Suppose a positive DC bias current appears in a certain branch. At this point, it is moving towards the peak. Get bigger The absolute value of the negative valley decreases; Increase. Equivalent duty cycle The current decreases, causing it to drop until it converges back to a steady state. The change process when a negative DC bias current appears is similar to that of the positive one. Therefore, the changes in the resonant current and the equivalent duty cycle form a negative feedback current-sharing mechanism, causing the equivalent duty cycle of all parallel bridge arms to naturally converge to a steady-state value.

[0088] To quantify this convergence process at a macroscopic, low-frequency scale, a nonlinear dynamic model is established using the switching period averaging method. The compensation duty cycle is defined. and feedback gain coefficient :

[0089] ;

[0090] At this point, the differential equation describing the decay of the bias current is as follows:

[0091] ;

[0092] Since the initial bias is extremely small at this time ( The differential equation is a first-order homogeneous linear differential equation, and its solution shows that the small starting bias current follows an exponential decay law:

[0093] ;

[0094] In the formula, This represents the switching transistor current bias that varies over time. This represents the initial bias current at the start of the transient current sharing phase.

[0095] Where the time constant for:

[0096] ;

[0097] After eliminating the large inrush current in step one, the system proceeds to step two. In this stage, the system maintains the zero-phase-shift synchronization state from step one and continues a transient self-current sharing process to eliminate initial minor disturbances in the actual circuit. The duration is set to... According to classical system control theory, this duration is sufficient to allow the initial disturbance to decay to a negligible level. This step does not introduce any active control variables and relies entirely on the system's inherent current-sharing capability to converge naturally, thus neither increasing control complexity nor hindering the provision of a clean initial state for step three.

[0098] After step two is completed, step three is performed, which involves executing the optimal trajectory phase shift based on the safe current boundary to restore the interleaved parallel operation state. The system needs to smoothly shift the carrier phases of units C and D from the synchronous state (0° / 180°) to the preset interleaved state (90° / 270°), with a total phase shift of 90° (corresponding to 0.25). ).from Initially, the controller linearly shifts the carrier phase of unit C from 0° to 90° at a constant angular velocity, and linearly shifts the carrier phase of unit D from 180° to 270°. Simultaneously, the inherent current sharing mechanism described in step two continuously suppresses the equivalent disturbance introduced by the phase shift, ensuring a smooth and symmetrical establishment of the current envelope. When the carrier phase has fully transitioned to the preset interleaving angle (90° for unit C, 270° for unit D), the system switches from the active soft-start algorithm to the steady-state closed-loop control algorithm.

[0099] Continuous phase shift of the carrier is equivalent to continuously injecting a perturbation duty cycle into the switching signal. Its relationship with phase slip angular velocity The relationship is:

[0100] ;

[0101] In the formula, The carrier phase angle is expressed in degrees; if radians are used, the denominator should be changed accordingly. .

[0102] This continuous disturbance is also suppressed by the self-current sharing mechanism. Therefore, substituting this disturbance into the first-order inertial model established in step two, we obtain the differential equation of the bias current containing the disturbance:

[0103] ;

[0104] Under the dynamic equilibrium boundary, the rate of change of the bias current tends to zero, i.e. The dynamic bias current excited by the phase shift is obtained. for:

[0105] ;

[0106] To fully utilize the device's current safety margin while ensuring that the current does not exceed the safety limit throughout the entire phase shift process. The dynamic bias constraint is set as follows:

[0107] ;

[0108] Under this constraint, in order to complete the phase shifting step as quickly as possible, It should be maintained at the maximum value. ,at this time Since the phase shift is constant, the optimal trajectory for phase slip is a linear ramp function of time. This maximizes the phase shift speed while precisely controlling the dynamic bias within a safe boundary, representing the optimal phase shift strategy. Based on this, the phase shift time in step three... satisfy:

[0109] ;

[0110] when When the carrier phase fully transitions to the preset interleaving angle, the system completes the soft-start process and switches to steady-state closed-loop control. This is the end time.

[0111] The present invention was experimentally verified on a 300V / 250kHz Δ-type inductor ACRP single-phase inverter prototype. The main parameters are as follows: =300V =250kHz =10A、 =15μH, =60μH =2、 =0.4Ω =15A、 =200pF, the power device is a SiC MOSFET. The calculated value is... =0.0003, ≈30.6μs. Therefore, the duration of step two is taken. =100μs, Step 3 sliding time =100μs, at which point the soft start ends. =200μs.

[0112] (1) Comparative verification of start-up transient under resistive load (18Ω):

[0113] like Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 As shown, under the traditional direct startup method, There is no inrush flow in cell A at 0°. The peak current of the C-cell at 90° in the first cycle is approximately twice that of the steady state (about 20A). The inductor waveform shows distortion, reflecting local core saturation, verifying the relationship between the inrush current amplitude and... The linear relationship. After adopting the ZPS-OT strategy, the peak switching current of cell C is completely constrained to within the steady-state value of 10A, and the inrush current is completely eliminated. The status flag signal indicates three steps: Step 1 ( Step 1 (0~100μs) is a zero-phase-shift synchronous start-up, with the current smoothly rising to the steady-state peak value; Step 2 (0~100μs) maintains synchronization and enters transient self-current sharing; Step 3 (100~200μs) is a linear phase shift, with the current envelope smoothly and symmetrically established without overshoot.

[0114] Figure 6 This is used to compare the startup current of different carrier phase units during traditional direct startup. In the figure, The control signals measured in the experiment correspond to the drive signals of the upper switch transistors of the first bridge arm in units A and C, respectively. The auxiliary inductor currents in units A and C, as measured experimentally; The currents of the two filter inductors in Unit A, measured in the experiment, correspond to the first and second bridge arm filter inductors in Unit A, respectively. The experimentally measured currents of the two filter inductors in Unit C correspond to the first and second bridge arm filter inductors in Unit C, respectively. The experimentally measured switching transistor currents correspond to the switching transistor currents output at the midpoint of the first bridge arm and the midpoint of the second bridge arm in Unit A, respectively. The experimentally measured switching currents correspond to the switching currents output at the midpoint of the first bridge arm and the midpoint of the second bridge arm in unit C, respectively. (The figure shows...) , and These represent the peak values ​​of the auxiliary inductor current, filter inductor current, and switching transistor current in steady state, respectively, and are used as reference boundaries to determine whether overcurrent occurs during startup. The carrier phase shift angle of the first bridge arm of unit A is... =0°, its first conduction pulse width is relatively small at 90°, therefore The peak value is the same as the steady-state current peak value, and no obvious inrush current is observed; the carrier phase shift angle of unit C is... =90°, its first conduction pulse width increases to 180°, resulting in A significant current surge occurs during the first switching cycle, with a value approximately twice the steady-state peak current. This comparison indicates that the inrush current during conventional direct startup is primarily caused by the asymmetry in the first-cycle conduction pulse width due to the phase shift of the interleaved carrier.

[0115] Figure 7 and Figure 8 The figure shows a typical waveform and a magnified view of the C unit during conventional startup under resistive load. This indicates the drive signal for the switching transistor on the first bridge arm in Unit C; This represents the auxiliary inductor current of unit C; This represents the filter inductor current of unit C; This represents the current output at the midpoint of the two bridge arms in unit C, flowing through the switching transistor. Figure 7 It can be seen that, under the traditional direct start-up method, the C unit retains the steady-state interleaved phase, resulting in better performance during the initial start-up phase. , and Both exhibited significant transient shocks, and the system gradually transitioned to a steady state only after approximately one output fundamental frequency cycle. Figure 8 A magnified view of the portion further reveals that during the first switching cycle... The corresponding conduction pulse widths are significantly asymmetrical, making , and Initiation inrush currents, approximately twice the steady-state peak value, appeared in the first switching cycle.

[0116] Figure 9 and Figure 10 This image shows a typical waveform and a magnified view of the C unit when using the ZPS-OT soft-start method under resistive load. Status flag signals are used to identify the soft-start stages. The first stage involves synchronous startup of the C unit and the A unit; the second stage involves maintaining a zero-phase-shift state for transient self-current sharing; and the third stage involves recovering to the preset staggered phase according to the linear optimal trajectory. Figure 9 and Figure 10 As can be seen, after adopting the ZPS-OT soft-start method, unit C no longer operates directly according to the steady-state interleaved phase during the initial startup phase, but instead starts synchronously with unit A. Therefore, , and All are at the corresponding steady-state peak boundaries , and Inner smoothing was established, and no abnormalities were observed. Figure 7 and Figure 8 The first cycle inrush flow during a conventional startup is shown.

[0117] (2) Comparative verification of startup transient under resistive-inductive load (4.8mH + 0.9Ω):

[0118] like Figure 11 , Figure 12 , Figure 13 and Figure 14 As shown, under resistive-inductive loads, the ZPS-OT strategy also completely eliminates inrush current, with all currents within the steady-state peak envelope and the average value strictly maintaining zero bias. The soft-start process is continuous and smooth, verifying the general applicability of the strategy to different load types.

[0119] Figures 11 to 14 This is used to verify the applicability of the method of the present invention under resistive-inductive loads. Figure 11 and Figure 12 The traditional startup waveform, Figure 13 and Figure 14The waveform is shown after using the ZPS-OT soft-start method. Figure 11 and Figure 12 It is evident that under traditional direct-start conditions, even with an inductive load, unit C will still experience significant start-up overcurrent due to the asymmetrical pulse width during the first switching cycle. The peak value exceeds the peak value of the steady-state switching transistor current. .Depend on Figure 13 and Figure 14 It is evident that after adopting the ZPS-OT soft-boot method, , and All values ​​are confined within the corresponding steady-state peak envelope, indicating that this method is applicable not only to resistive loads but also to inductive loads.

[0120] (3) Verification of the first-order inertial model of the passive self-equalizing flow mechanism:

[0121] During the natural decay process of traditional inrush current, the measured time constant of the switching current of cell C is obtained using the envelope extraction algorithm. =29.87μs, compared with the theoretically calculated value The relative error of 30.6 μs is only 2.38%, which verifies the accuracy of the passive self-averaging flow model in step two.

[0122] Figure 15 A first-order inertial model was used to verify the transient self-flow averaging mechanism. (See figure) The measured switching current corresponds to the switching current output at the midpoint of the first bridge arm in unit C. The envelope curve represents the decay process of its peak inrush current over time. The measured time constant obtained from the envelope extraction is denoted as... The time constant calculated based on the theoretical model is denoted as .Depend on Figure 15 It is evident that the inrush current generated during traditional startup is not sustained indefinitely, but rather gradually decays over time. Its envelope curve largely conforms to the first-order exponential decay law, and... and The relatively small error indicates that the passive self-current equalization first-order model established in step two can accurately describe the natural decay process of the starting bias current.

[0123] (4) Verification of steady-state transition smoothness:

[0124] The measured complete load current waveform shows that there is no transient current overshoot or waveform change during the transition from standby zero state to steady-state sinusoidal output, realizing a seamless switch from open-loop soft start to high-frequency closed-loop control.

[0125] Figure 16 This is the complete load current waveform after adopting the ZPS-OT soft-start strategy, where Figure 16 (a) in the text corresponds to a resistive load. Figure 16 (b) in the diagram corresponds to a resistive-inductive load. The figure represents the inverter output load current. As can be seen from the figure, the load current gradually transitions from zero to a steady-state sine wave. No obvious abrupt changes, oscillations, or overcurrents occur during the transition, indicating that the method of the present invention can achieve a smooth switch from soft-start control to steady-state closed-loop control.

[0126] In summary, step one eliminates the inrush current caused by the asymmetry of the first-cycle conduction pulse width through forced synchronization; step two dissipates the initial disturbance using the system's inherent current sharing capability and provides a clean initial state for step three; step three, under the constraint of current sharing capability, completes the restoration of the interleaved parallel state with the optimal trajectory. The entire soft-start process requires no additional hardware circuitry and is entirely implemented through digital controller software. The scope of protection of this invention is not limited to the above-described N=2 delta-type inductor ACRP inverter embodiment. Any fixed-frequency ZVS single-phase inverter with a periodic current reversal mechanism and interleaved parallel characteristics, including sinusoidal delta current mode S-TCM, quadrilateral current mode QCM, etc., can use this method to achieve inrush-free smooth start-up.

[0127] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A method for suppressing inrush current during startup in an interleaved parallel soft-switching single-phase inverter, the inverter comprising... Each power module consists of two basic units connected in an interleaved parallel configuration. The carrier phases of the two basic units within the same power module differ by 180°. During steady-state interleaved operation, the carrier phase difference between corresponding basic units in adjacent power modules is... ; This inverter achieves zero-voltage switching by forcing the current of the switching transistors to reverse; it is characterized by including the following steps: Step 1, Zero Phase Shift Synchronization Start-up Step: After receiving the enable signal, the controller forces the carriers of the corresponding basic units in all power modules to synchronize to the same phase, so that the initial conduction duty cycle of all units in the first switching cycle is 0.

25. Step 2, Transient Self-Synchronization Step: Maintain zero phase shift synchronization state for a duration of... By utilizing the system's inherent equivalent duty cycle negative feedback current sharing mechanism, the initial non-ideal disturbance decays exponentially. It is a time constant; Step 3, Optimal Trajectory Phase Shifting Step: The carrier phase of each power module is smoothly shifted from the synchronous state to the preset interleaving angle at a constant angular velocity. During the phase shifting process, the switching current does not exceed the safety limit. After the phase shifting is completed, the system switches to steady-state closed-loop control. The number of interleaved parallel power modules =2, the inverter is a Δ-type inductor-assisted resonant commutator ACRP type single-phase inverter; the inverter includes a first power module and a second power module. The first power module is composed of two basic units, A unit and B unit, and the second power module is composed of two basic units, C unit and D unit. The first power module and the second power module are adjacent power modules, wherein A unit and C unit are corresponding basic units, and B unit and D unit are corresponding basic units; Each basic unit contains four switching transistors, forming two half-bridge arms. The DC input terminals of the two half-bridge arms are connected in parallel, and an auxiliary inductor is connected between the midpoints of the two arms. The midpoints of the two arms are connected to the AC output terminals through filter inductors, forming a Δ-type inductor connection structure. The output sides of each basic unit are connected in parallel to a common output terminal, and the auxiliary inductor in each basic unit is used to force the current to reverse cycle by cycle in order to achieve zero-voltage switching.

2. The inrush current suppression method for an interleaved parallel soft-switching single-phase inverter according to claim 1, characterized in that, Step one specifically includes: After receiving the enable signal, the controller temporarily blocks the preset carrier phase shift angles of units C and D in the second power module, forcibly aligns the triangular carrier of unit C with the triangular carrier of unit A in the first power module, and aligns the triangular carrier of unit D with the triangular carrier of unit B in the first power module, that is, the carrier phase shift angle satisfies =0°, =180°, so that the conduction angle of the first switch of all units is 90° and the initial conduction duty cycle is 0.25; These are the carrier phase shift angles for units A, B, C, and D, respectively.

3. The inrush current suppression method for an interleaved parallel soft-switching single-phase inverter according to claim 1, characterized in that, The time constant mentioned in step two Determined by the following formula: In the formula, The equivalent inductance of a delta-type inductor. This is the equivalent output capacitance of the switching transistor. For the switching cycle, For the parasitic resistance of the loop, This is the DC bus voltage. This represents the peak value of the steady-state switching transistor current.

4. The inrush current suppression method for an interleaved parallel soft-switching single-phase inverter according to claim 1, characterized in that, In step three, the controller linearly slides the carrier phase of unit C from 0° to 90° at a constant angular velocity, and linearly slides the carrier phase of unit D from 180° to 270°, so that the second power module as a whole restores a steady-state staggered phase shift of 90° relative to the first power module. During the sliding process, the system's inherent equivalent duty cycle negative feedback current sharing mechanism continuously suppresses the equivalent disturbance introduced by the phase shift. When the carrier phase transitions to the preset staggered angle, that is, unit C is 90° and unit D is 270°, the system switches from soft-start control to steady-state closed-loop control.

5. The inrush current suppression method for an interleaved parallel soft-switching single-phase inverter according to claim 4, characterized in that, The constant angular velocity mentioned in step three is Minimum phase shift time satisfy: In the formula, For the switching cycle, This is the DC bus voltage. For the parasitic resistance of the loop, Feedback gain coefficient: For the safety limit of the switching transistor current, This represents the peak value of the steady-state switching transistor current.

6. The inrush current suppression method for an interleaved parallel soft-switching single-phase inverter according to claim 5, characterized in that, The feedback gain coefficient Determined by the following formula: In the formula, This is the equivalent output capacitance of the switching transistor. This is the bias current.

7. The inrush current suppression method for an interleaved parallel soft-switching single-phase inverter according to claim 4, characterized in that, In step three, the switching current does not exceed the safety limit, specifically satisfying the following conditions: ,in This represents the peak value of the steady-state switching transistor current. The dynamic bias current introduced for phase shifting. This refers to the safe limit for the switching transistor current.

8. The inrush current suppression method for an interleaved parallel soft-switching single-phase inverter according to claim 7, characterized in that, The dynamic bias current With phase shift angular velocity satisfy: in, This is the DC bus voltage. For the switching cycle, For feedback gain coefficient, This is the parasitic resistance of the circuit.

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