A positive and negative high voltage dual charge pump circuit based on a single power supply system

Abstract

The present application belongs to the technical field of power supply circuit, and particularly relates to a positive and negative high-voltage double charge pump circuit based on a single power supply system. The positive and negative high-voltage double charge pump circuit comprises an oscillator, a loop composed of three inverters; a clock frequency division and non-overlapping clock generation unit for dividing the clock signal output by the oscillator by four and generating four non-overlapping clock signals; a level conversion driving unit; and a charge pump unit. Based on the principle of Dickson structure, the charge pump unit controls the charging and discharging of the capacitor by the clock signal converted by the level conversion driving unit, so as to realize voltage multiplication and reverse action on the single power supply voltage, and generate positive and negative high-voltage signals. The present application can provide positive and negative high-voltage outputs under the working voltage of the single power supply system, and can be used as a power supply. Meanwhile, the improved non-overlapping clock control design can effectively avoid the charge backflow problem caused by the simultaneous conduction of the transmission tube in the charge pump, and improve the system working efficiency.

Description

Technical Field

[0001] This invention belongs to the field of power supply circuit technology, and specifically relates to a positive and negative high voltage dual charge pump circuit based on a single power supply system. Background Technology

[0002] A charge pump circuit is a circuit that uses the accumulation effect of charge in a capacitor to generate a voltage higher than or negative than the power supply. They are commonly used in non-volatile memories such as EEPROM and flash memory for programming and operating storage cells; they can also serve as high-voltage generation components for switching drives in switched-capacitor circuit systems; or they can act as positive and negative voltage power supplies to power other circuits in the system. They can also be applied in bus driver circuits, where high-voltage drive output is required in single-supply systems, such as ARINC429 bus and RS485 bus driver circuits.

[0003] In practical applications, single Dickson-structured positive or negative charge pumps are quite common. However, charge pump circuits that simultaneously provide positive and negative high voltages in the same system are relatively rare. Alternatively, the positive and negative charge pump structures used in the same system may be independent, each generating a positive or negative high voltage output.

[0004] However, existing technologies still have the following drawbacks: the positive and negative charge pump structures used in the same system are independent, generating positive and negative high voltages separately, which increases the layout area and reduces circuit efficiency. Furthermore, using a multi-power supply system increases the power requirements of the system, unnecessarily increasing the complexity of the application system.

[0005] Therefore, there is an urgent need for this invention to propose a positive and negative high-voltage dual charge pump circuit based on a single power supply system to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this invention is to provide a positive and negative high-voltage dual charge pump circuit based on a single-power supply system. Based on the traditional Dickson structure, this invention designs a dual charge pump circuit structure. By multiplying and reversing the voltage of the single power supply, positive and negative high-voltage signals are generated respectively, achieving the purpose of generating positive and negative high-voltage outputs in a single-power supply system, which can then be used as a power source. Simultaneously, the circuit employs an improved non-overlapping clock control design, which effectively avoids the charge backflow problem caused by the simultaneous conduction of the transfer transistors in the charge pump, thus improving system efficiency.

[0007] To solve the above technical problems, the present invention provides a positive and negative high-voltage dual charge pump circuit based on a single power supply system, comprising: The oscillator, consisting of a loop of three inverters, is used to generate the clock signal CLK0. The frequency of the clock signal CLK0 can be effectively adjusted by adjusting the capacitor. The oscillator is turned on or off by the enable signal EN. The clock division and non-overlapping clock generation unit is used to divide the clock signal CLK0 output by the oscillator by four and generate four non-overlapping clock signals CLK1~CLK4; wherein clock signals CLK1~CLK2 are a set of high-level non-overlapping clock signals; and non-overlapping clock signals CLK3~CLK4 are a set of low-level non-overlapping clock signals. The level conversion driver unit has four groups, which are used to convert clock signals CLK1~CLK4 into two clock signals CLK1A~CLK1B, two clock signals CLK2A~CLK2B, two clock signals CLK3A~CLK3B, and two clock signals CLK4A~CLK4B respectively; and the clock signals converted by the level conversion driver unit have a wider range of high and low signal amplitudes to enhance the driving capability. The charge pump unit includes a positive high-voltage charge pump module and a negative high-voltage charge pump module with a two-stage Dickson structure. Based on the Dickson structure principle, the clock signal converted by the level conversion drive unit controls the transmission tube to charge and discharge the capacitor, so as to realize the voltage multiplication and reverse action of the single power supply voltage, and generate positive and negative high-voltage signals respectively for use as positive and negative power supplies. The positive high voltage charge pump module uses PMOS transistor MP41 and NMOS transistor MN41 to alternately switch the node M connected to the drain of the PMOS transistor MP42 and NMOS transistor MN41 between ground GND and power supply VDD. The node N connected to the source and drain of PMOS transistor MP42 and PMOS transistor MP43 is boosted through the coupling of capacitor C41. The boosted voltage is output through PMOS transistor MP43 to generate power supply VDD2P. The negative high-voltage charge pump module uses PMOS transistor MP44 and NMOS transistor MN42 to alternately switch the node E connected to their drain between ground GND and power supply VDD2P. Through capacitor C40, the node F connected to the source and drain of NMOS transistors MN43 and MN44 is pulled low to a negative voltage. The negative voltage is then output through NMOS transistor MN44 to generate power supply VDD2N.

[0008] Preferably, the oscillator includes: PMOS transistors MP0~MP8, NMOS transistors MN0~MN8, and capacitor C0; the source of PMOS transistor MP0 is connected to power supply VDD, and its gate and drain are connected to the drain of NMOS transistor MN0; the gate of NMOS transistor MN0 is connected to enable signal EN, and its source is connected to the gate and drain of NMOS transistor MN1, the gate of NMOS transistor MN2, and the gate of NMOS transistor MN3; the source of NMOS transistor MN1 is grounded to GND; the source of NMOS transistor MN2 is grounded, and its drain is connected to the gate and drain of PMOS transistor MP1 and the gate of PMOS transistor MP2; the source of PMOS transistor MP1 is connected to power supply VDD; the source of PMOS transistor MP2 is connected to power supply VDD, and its drain is connected to the source of PMOS transistor MP3; the gate of PMOS transistor MP3 is connected to the gate of NMOS transistor MN5, and the drains of PMOS transistors MP7 and MN8, and outputs a clock signal CLK0; its drain is connected to the drain of NMOS transistor MN5 and the drain of PMOS transistor MP8. The gates of MP4~MP5, and the gates of NMOS transistors MN6 and MN4; the source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3, and the source of NMOS transistor MN3 is grounded to GND; the source of PMOS transistor MP4 is connected to power supply VDD, and the drain is connected to the source of PMOS transistors MP5~MP6; the drain of PMOS transistor MP5 is connected to the gate of PMOS transistor MP6, the drain of NMOS transistor MN6, the gate of NMOS transistor MN7, one end of capacitor C0, and the gates of PMOS transistors MP7 and NMOS transistor MN8; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN4 and the source of NMOS transistor MN7; the source of NMOS transistor MN4 is grounded to GND; the drain of PMOS transistor MP6 is connected to power supply VDD; the drain of NMOS transistor MN7 is grounded to GND; the other end of capacitor C0 and the source of NMOS transistor MN8 are grounded to GND; the source of PMOS transistor MP7 is connected to power supply VDD.

[0009] Preferably, the clock division and non-overlapping clock generation unit includes: The clock divider module consists of a cascaded first differential branch and a second differential branch forming a cross-coupled feedback loop, used to divide the clock signal CLK0 by four to output a single-ended clock signal with stable duty cycle and strong anti-interference capability. The non-overlapping clock generation module consists of a first logic gate and a second logic gate. The first logic gate consists of a NOR gate and an inverter delay chain, and outputs a set of high-level non-overlapping clock signals CLK1~CLK2. The second logic gate consists of a NAND gate and an inverter delay chain, and outputs a set of low-level non-overlapping clock signals CLK3~CLK4.

[0010] Preferably, the clock divider module includes: The first differential branch includes: PMOS transistors MP21~MP26, NMOS transistors MN21~MN23, and inverter INV0; the source of PMOS transistor MP21 is connected to power supply VDD, its gate is connected to the gate of NMOS transistor MN21 and serves as the feedback terminal of the first differential branch, and its drain is connected to the source of PMOS transistor MP22; the gate of PMOS transistor MP22 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN21 and the gate of PMOS transistor MP24; the sources of NMOS transistors MN21~MN23 are grounded to GND; the gate of NMOS transistor MN22 is connected to PMOS transistor MP23 and... The gate of PMOS transistor MP26 and the clock signal CLK0 are connected, and the drain is connected to the drain of PMOS transistor MP24. The source of PMOS transistor MP24 is connected to the drain of PMOS transistor MP23, and the gates of PMOS transistor MP25 and NMOS transistor MN23. The sources of PMOS transistors MP23 and MP25 are connected to the power supply VDD. The drain of PMOS transistor MP25 is connected to the source of PMOS transistor MP26 and the input terminal of inverter INV0. The drain of PMOS transistor MP26 is connected to the drain of NMOS transistor MN23. The output terminal of inverter INV0 serves as the output terminal of the first differential branch. The second differential branch includes: PMOS transistors MP11~MP16, NMOS transistors MN11~MN13, and inverters INV1~INV2; the source of PMOS transistor MP11 is connected to power supply VDD, its gate is connected to the output terminal of the first differential branch and the gate of NMOS transistor MN11, and its drain is connected to the source of PMOS transistor MP12; the gate of PMOS transistor MP12 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN11 and the gate of PMOS transistor MP14; the sources of NMOS transistors MN11~MN13 are grounded to GND; the gate of NMOS transistor MN12 is connected to the gate of PMOS transistor MP13, and its drain is connected to... The source of PMOS transistor MP14 is connected to the drain of PMOS transistor MP13, and the gates of PMOS transistor MP15 and NMOS transistor MN13. The sources of PMOS transistors MP13 and MP15 are connected to power supply VDD, and the drain of PMOS transistor MP15 is connected to the source of PMOS transistor MP16 and the input terminal of inverter INV1. The gate of PMOS transistor MP16 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN13. Inverters INV1 and INV2 are connected in series, and the output terminal of inverter INV2 is connected to the feedback terminal of the first differential branch.

[0011] Preferably, the non-overlapping clock generation module includes: The first logic gate includes: NOR gates NOR1~NOR2 and inverters INV3~INV8; the two inputs of NOR gate NOR1 are respectively connected to the output of inverter INV1 and the input of inverter INV8, and the output is connected to inverters INV3, INV5 and INV7 connected in series. The output of inverter INV7 outputs clock signal CLK1; the two inputs of NOR gate NOR2 are respectively connected to the outputs of inverters INV2 and INV5, and the output is connected to inverters INV4, INV6 and INV8 connected in series. The output of inverter INV8 outputs clock signal CLK2. The second logic gate includes: NAND gates NAND1~NAND2 and inverters INV9~INV14; the two inputs of NAND gate NAND1 are respectively connected to the output of inverter INV1 and the input of inverter INV14, and the output is connected to inverters INV9, INV11 and INV13 connected in series. The output of inverter INV13 outputs clock signal CLK3; the two inputs of NAND gate NAND2 are respectively connected to the outputs of inverters INV2 and INV11, and the output is connected to inverters INV10, INV12 and INV14 connected in series. The output of inverter INV14 outputs clock signal CLK4.

[0012] Preferably, the level conversion driving unit includes: PMOS transistors MP31~MP33, NMOS transistors MN31~MN33, and inverters INV31~INV35; the input terminal of the inverter INV31 and the gate of the PMOS transistor MP32 are connected to clock signals CLK1~CLK4, and the output terminal is connected to the gate of the PMOS transistor MP31; the source of the PMOS transistors MP31~MP33 is connected to the power supply VDD2P; the drain of the PMOS transistor MP31 is connected to the drain of the NMOS transistor MN31 and the gate of the NMOS transistor MN32; the gate of the NMOS transistor MN31 is connected to the drain of the NMOS transistor MN32 and the PMOS transistor MP32, and the gate of the PMOS transistor MP33 and the NMOS transistor MN33; the NMOS... The sources of transistors MN31-MN33 are connected to power supply VDD2N; the drain of NMOS transistor MN33 is connected to the drain of PMOS transistor MP33, as well as the input terminals of inverters INV32 and INV34; inverter INV32 is connected in series with inverter INV33, and the output terminal of inverter INV33 outputs clock signals CLK1A-CLK4A; inverter INV34 is connected in series with inverter INV35, and the output terminal of inverter INV35 outputs clock signals CLK1B-CLK4B; the positive power supply terminal of inverter INV31 is connected to power supply VDD, and the negative power supply terminal is grounded to GND; the positive power supply terminals of inverters INV32-INV35 are connected to power supply VDD2P, and the negative power supply terminals are connected to power supply VDD2N.

[0013] Preferably, the positive high-voltage charge pump module includes: PMOS transistors MP41~MP43, NMOS transistor MN41, and capacitors C41~C42; the gate of the NMOS transistor MN41 is connected to the clock signal CLK1A, the source and substrate are grounded to GND, and the drain is connected to the drain of the PMOS transistor MP41 and one end of the capacitor C41 to form node M; the gate of the PMOS transistor MP41 is connected to the clock signal CLK3B, and the source and substrate, as well as the drain of the PMOS transistor MP42, are connected to the power supply VDD; the gate of the PMOS transistor MP42 is connected to the clock signal CLK4A, and the source and substrate are connected to the other end of the capacitor C41 and the drain of the PMOS transistor MP43 to form node N; the gate of the PMOS transistor MP43 is connected to the clock signal CLK3A, and the source and substrate, as well as one end of the capacitor C42, are connected to the power supply VDD2P; the other end of the capacitor C42 is grounded to GND.

[0014] Preferably, the negative high-voltage charge pump module includes: a PMOS transistor MP44, NMOS transistors MN42~MN44, capacitor C40, and capacitor C43; the gate of the PMOS transistor MP44 is connected to the clock signal CLK4B, the source and substrate are connected to the power supply VDD2P, and the drain is connected to the drain of the NMOS transistor MN42 and one end of capacitor C40 to form node E; the gate of the NMOS transistor MN42 is connected to the clock signal CLK2A, and the source, substrate, and one end of capacitor C43 are grounded to GND; the other end of capacitor C40 is connected to the drain of NMOS transistor MN43 and the source of NMOS transistor MN44 to form node F; the gate of the NMOS transistor MN43 is connected to the clock signal CLK1B, and the source, substrate, and substrate of NMOS transistor MN44 are grounded to GND; the gate of the NMOS transistor MN44 is connected to the clock signal CLK2B, and the drain is connected to the other end of capacitor C43 and power supply VDD2N.

[0015] Preferably, the positive high-voltage charge pump module further includes: Phase 1: Clock signals CLK3B and CLK1A are high, and clock signal CLK4A is low. When CLK3A is high, PMOS transistors MP42 and MN41 are turned on, while PMOS transistors MP41 and MP43 are turned off. Power supply VDD charges capacitor C41. The voltage at node M is 0, and the voltage at node N is Vdd. Therefore, the voltage across capacitor C41 at this time... V MN =vdd; Second stage: Clock signals CLK3B and CLK1A go low, clock signal CLK4A goes high, and clock signal CLK3A goes low. PMOS transistors MP42 and MN41 are turned off, while PMOS transistors MP41 and MP43 are turned on. Power supply VDD charges node M through PMOS transistor MP41, and the voltage at node M becomes Vdd. Due to the voltage across capacitor C41... V MN =vdd, then the voltage at node N and the power supply VDD2P becomes 2vdd, thus achieving the voltage multiplication effect of the power supply voltage. V VDD2P =2vdd.

[0016] Preferably, the negative high-voltage charge pump module further includes: Phase 1: Clock signal CLK1B is high, while clock signals CLK4B, CLK2A, and CLK2B are low. At this time, PMOS transistor MP44 and NMOS transistor MN43 are turned on, while NMOS transistors MN42 and MN44 are turned off. Power supply VDD2P charges capacitor C40. The voltage at node F is 0, and the voltage at node E is... V VDD2P At this time, the voltage across capacitor C40 is... V FE = V VDD2P ; Second stage: Clock signal CLK1B goes low, clock signals CLK4B, CLK2A, and CLK2B go high. At this time, PMOS transistor MP44 and NMOS transistor MN43 are off, while NMOS transistors MN42 and MN44 are on. The voltage at node E becomes 0, due to the voltage across capacitor C40. V FE = V VDD2P Then the voltage at node F is - V VDD2P NMOS transistor MN44 is turned on, and the voltage at power supply VDD2N is also - V VDD2P To achieve negative high voltage output; when V VDD2P When VDD = 2Vdd, the final output voltage at the power supply VDD2N is -2Vdd, so as to achieve the reverse output of the positive high voltage.

[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention, based on the traditional Dickson charge pump structure model, designs a dual charge pump circuit structure that generates positive and negative high voltages based on a single power supply system. It can provide positive and negative high voltage outputs under the operating voltage of a single power supply system and can be used as a power source. Simultaneously, the circuit employs an improved non-overlapping clock control design, which effectively avoids the charge backflow problem caused by the simultaneous conduction of the transfer transistors in the charge pump, thus improving system efficiency. Attached Figure Description

[0018] Figure 1 This is a system framework diagram of a positive and negative high-voltage dual charge pump circuit based on a single power supply system provided in an embodiment of the present invention.

[0019] Figure 2 This is an oscillator circuit diagram provided in an embodiment of the present invention.

[0020] Figure 3 This is a circuit diagram of a clock division and non-overlapping clock generation unit provided in an embodiment of the present invention.

[0021] Figure 4 This is a circuit diagram of the level conversion driving unit provided in an embodiment of the present invention.

[0022] Figure 5 This is a circuit diagram of a positive high-voltage charge pump module provided in an embodiment of the present invention.

[0023] Figure 6 This is a circuit diagram of a negative high-voltage charge pump module provided in an embodiment of the present invention.

[0024] Figure 7 This is a schematic diagram of non-overlapping clock timing provided in an embodiment of the present invention. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0026] like Figure 1 As shown, this embodiment of the invention specifically provides a positive and negative high-voltage dual charge pump circuit based on a single power supply system, including: The oscillator, consisting of a loop of three inverters, is used to generate the clock signal CLK0. The frequency of the clock signal CLK0 can be effectively adjusted by adjusting the capacitor. The oscillator can be turned on or off by enabling EN. The clock division and non-overlapping clock generation unit is used to divide the clock signal CLK0 output by the oscillator by four and generate four non-overlapping clock signals CLK1~CLK4; wherein clock signals CLK1~CLK2 are a set of high-level non-overlapping clock signals; and non-overlapping clock signals CLK3~CLK4 are a set of low-level non-overlapping clock signals. The level conversion driver unit has four groups, which are used to convert clock signals CLK1~CLK4 into two clock signals CLK1A~CLK1B, two clock signals CLK2A~CLK2B, two clock signals CLK3A~CLK3B, and two clock signals CLK4A~CLK4B respectively. These four non-overlapping clock signals CLK1, CLK2, CLK3, and CLK4, after being converted by the level conversion driver unit, achieve a wider range of high and low signal amplitudes and enhance the driving capability. They are used as control signals for the transmission switching transistors in the subsequent charge pump unit, which can effectively reduce the loss of the transmission transistor threshold voltage. At the same time, the non-overlapping clocks can avoid the charge backflow problem caused by the simultaneous conduction of transmission transistors, thereby improving the transmission efficiency. The charge pump unit includes a positive high-voltage charge pump module and a negative high-voltage charge pump module employing a two-stage Dickson structure. Based on the Dickson structure principle, the clock signal converted by the level conversion drive unit controls the transmission transistor to charge and discharge the capacitor, thereby achieving voltage multiplication and reversal of the single power supply voltage, generating positive and negative high-voltage signals of 2Vdd and -2Vdd respectively for use as positive and negative power supplies. The positive high-voltage charge pump module uses PMOS transistor MP41 and NMOS transistor MN41 to alternately switch the node M connected to their drains between ground GND and power supply VDD. Through capacitor C41, the node N connected to the source and drain of PMOS transistors MP42 and MP43 is boosted. The boosted voltage is then output through PMOS transistor MP43 to generate power supply VDD2P. The negative high-voltage charge pump module uses PMOS transistor MP44 and NMOS transistor MN42 to alternately switch the node E connected to their drain between ground GND and power supply VDD2P. Through capacitor C40, the node F connected to the source and drain of NMOS transistors MN43 and MN44 is pulled low to a negative voltage. The negative voltage is then output through NMOS transistor MN44 to generate power supply VDD2N.

[0027] like Figure 2As shown, the oscillator includes: PMOS transistors MP0~MP8, NMOS transistors MN0~MN8, and capacitor C0; the source of PMOS transistor MP0 is connected to power supply VDD, and its gate and drain are connected to the drain of NMOS transistor MN0; the gate of NMOS transistor MN0 is connected to enable signal EN, and its source is connected to the gate and drain of NMOS transistor MN1, the gate of NMOS transistor MN2, and the gate of NMOS transistor MN3; the source of NMOS transistor MN1 is grounded to GND; the source of NMOS transistor MN2 is grounded, and its drain is connected to the gate and drain of PMOS transistor MP1 and the gate of PMOS transistor MP2; the source of PMOS transistor MP1 is connected to power supply VDD; the source of PMOS transistor MP2 is connected to power supply VDD, and its drain is connected to the source of PMOS transistor MP3; the gate of PMOS transistor MP3 is connected to the gate of NMOS transistor MN5, and the drains of PMOS transistors MP7 and NMOS transistor MN8, and outputs a clock signal CLK0, with its drain connected to the drain of NMOS transistor MN5 and the drain of PMOS transistor MN8. The gates of MP4~MP5, and the gates of NMOS transistors MN6 and MN4; the source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3, and the source of NMOS transistor MN3 is grounded to GND; the source of PMOS transistor MP4 is connected to power supply VDD, and the drain is connected to the source of PMOS transistors MP5~MP6; the drain of PMOS transistor MP5 is connected to the gate of PMOS transistor MP6, the drain of NMOS transistor MN6, the gate of NMOS transistor MN7, one end of capacitor C0, and the gates of PMOS transistors MP7 and NMOS transistor MN8; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN4 and the source of NMOS transistor MN7; the source of NMOS transistor MN4 is grounded to GND; the drain of PMOS transistor MP6 is connected to power supply VDD; the drain of NMOS transistor MN7 is grounded to GND; the other end of capacitor C0 and the source of NMOS transistor MN8 are grounded to GND; the source of PMOS transistor MP7 is connected to power supply VDD.

[0028] The circuit of the oscillator is as follows Figure 2As shown: MP0, MP1, MN0, MN1, and MN2 transistors form the startup bias circuit; three stages of inverters form the oscillation loop, where MP2, MP3, MN5, and MN3 form the first stage inverter, MP4, MP5, MN6, MN4, MP6, and MN7 form the second stage inverter, and MP7 and MN8 form the third stage inverter. The three stages of inverters form a closed-loop ring oscillation circuit, utilizing the inherent propagation delay characteristic of inverters to generate self-excited oscillation: the signal experiences a certain delay after passing through each stage of inverters; the three stages of inverters sequentially reverse the direction and delay each stage, forming a total phase shift of 0° / 360°, satisfying the sinusoidal oscillation phase condition. The circuit can spontaneously generate a periodically flipping oscillation waveform without an external input signal. The adjusting capacitor C0 is connected in parallel at a critical node in the oscillation loop. The charging and discharging time of the capacitor determines the switching speed of the inverter: the larger the capacitance of C0, the longer the charging and discharging time, the greater the signal transmission delay, and the lower the output clock frequency; decreasing C0 reduces the delay and increases the clock frequency, achieving continuous frequency adjustment. The enable signal EN controls the start and stop of the oscillator: when EN is high, MP0, MP1, MN0, MN1, and MN2 in the start bias circuit are all turned on, providing bias voltage to MP2 and MN3. The circuit is open, and the three-stage inverter loop normally forms a closed loop, continuously switching and oscillating, with CLK0 outputting a stable clock signal; when EN is low, the start bias circuit is turned off, MP2 and MN3 stop working, the loop path is cut off, the inverter's working state is clamped, the loop cannot form continuous phase switching, the oscillator stops oscillating, and there is no clock output.

[0029] like Figure 3 As shown, the clock division and non-overlapping clock generation unit includes: The clock divider module consists of a cascaded first differential branch and a second differential branch forming a cross-coupled feedback loop, used to divide the clock signal CLK0 by four to output a single-ended clock signal with a stable duty cycle and strong anti-interference capability. The non-overlapping clock generation module consists of a first logic gate and a second logic gate: the first logic gate is composed of a NOR gate and an inverter delay chain, and outputs CLK1 and CLK2 as a set of high-level non-overlapping clock signals; the second logic gate is composed of a NAND gate and an inverter delay chain, and outputs CLK3 and CLK4 as a set of low-level non-overlapping clock signals.

[0030] Continue reading Figure 3 As shown, the clock divider module includes: The first differential branch includes: PMOS transistors MP21~MP26, NMOS transistors MN21~MN23, and inverter INV0; the source of PMOS transistor MP21 is connected to power supply VDD, its gate is connected to the gate of NMOS transistor MN21 and serves as the feedback terminal of the first differential branch, and its drain is connected to the source of PMOS transistor MP22; the gate of PMOS transistor MP22 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN21 and the gate of PMOS transistor MP24; the sources of NMOS transistors MN21~MN23 are grounded to GND; the gate of NMOS transistor MN22 is connected to PMOS transistor MP23 and... The gate of PMOS transistor MP26 and the clock signal CLK0 are connected, and the drain is connected to the drain of PMOS transistor MP24. The source of PMOS transistor MP24 is connected to the drain of PMOS transistor MP23, and the gates of PMOS transistor MP25 and NMOS transistor MN23. The sources of PMOS transistors MP23 and MP25 are connected to the power supply VDD. The drain of PMOS transistor MP25 is connected to the source of PMOS transistor MP26 and the input terminal of inverter INV0. The drain of PMOS transistor MP26 is connected to the drain of NMOS transistor MN23. The output terminal of inverter INV0 serves as the output terminal of the first differential branch. The second differential branch includes: PMOS transistors MP11~MP16, NMOS transistors MN11~MN13, and inverters INV1~INV2; the source of PMOS transistor MP11 is connected to power supply VDD, its gate is connected to the output terminal of the first differential branch and the gate of NMOS transistor MN11, and its drain is connected to the source of PMOS transistor MP12; the gate of PMOS transistor MP12 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN11 and the gate of PMOS transistor MP14; the sources of NMOS transistors MN11~MN13 are grounded to GND; the gate of NMOS transistor MN12 is connected to the gate of PMOS transistor MP13, and its drain is connected to... The source of PMOS transistor MP14 is connected to the drain of PMOS transistor MP13, and the gates of PMOS transistor MP15 and NMOS transistor MN13. The sources of PMOS transistors MP13 and MP15 are connected to power supply VDD, and the drain of PMOS transistor MP15 is connected to the source of PMOS transistor MP16 and the input terminal of inverter INV1. The gate of PMOS transistor MP16 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN13. Inverters INV1 and INV2 are connected in series, and the output terminal of inverter INV2 is connected to the feedback terminal of the first differential branch.

[0031] Continue reading Figure 3 As shown, the non-overlapping clock generation module includes: The first logic gate includes: NOR gates NOR1~NOR2 and inverters INV3~INV8; the two inputs of NOR gate NOR1 are respectively connected to the output of inverter INV1 and the input of inverter INV8, and the output is connected to inverters INV3, INV5 and INV7 connected in series. The output of inverter INV7 outputs clock signal CLK1; the two inputs of NOR gate NOR2 are respectively connected to the outputs of inverters INV2 and INV5, and the output is connected to inverters INV4, INV6 and INV8 connected in series. The output of inverter INV8 outputs clock signal CLK2. The second logic gate includes: NAND gates NAND1~NAND2 and inverters INV9~INV14; the two inputs of NAND gate NAND1 are respectively connected to the output of inverter INV1 and the input of inverter INV14, and the output is connected to inverters INV9, INV11 and INV13 connected in series. The output of inverter INV13 outputs clock signal CLK3; the two inputs of NAND gate NAND2 are respectively connected to the outputs of inverters INV2 and INV11, and the output is connected to inverters INV10, INV12 and INV14 connected in series. The output of inverter INV14 outputs clock signal CLK4.

[0032] The circuit for clock division and non-overlapping clock generation unit is as follows: Figure 3 As shown: This is a cascaded clock divider module and a non-overlapping clock generation module. First, the input clock CLK0 enters a 4-divider unit consisting of two stages of symmetrical differential branches. This unit uses a three-stage cascaded current-mode logic (CML) differential pair to perform frequency division and signal shaping. Utilizing the propagation delay and phase reversal characteristics of the differential pair, the high-frequency input clock is divided by 4 and then buffered and shaped by the inverter INV1 to output a single-ended clock signal with a stable duty cycle and strong anti-interference capability.

[0033] Subsequently, the frequency-divided clock signal is converted into a complementary clock control signal by inverter INV2, and then enters the non-overlapping generation module. This module is divided into a first logic gate and a second logic gate, which, through the cooperation of NOR / NAND gate logic circuits and a multi-stage inverter delay chain, performs phase control on the clock signal.

[0034] The first logic gate includes: NOR gates NOR1~NOR2 and inverters INV3~INV8. Each input clock signal is introduced with a fixed propagation delay through a multi-stage inverter delay chain, so that the rising / falling edges of the complementary clocks are staggered. After being combined by logic gates, it is ensured that the two complementary clocks CLK1 and CLK2 at the final output will not be high at the same time. That is, CLK1 and CLK2 are a set of high-level non-overlapping clock signals.

[0035] The second logic gate includes NAND gates NAND1~NAND2 and inverters INV9~INV14. Each input clock signal is introduced with a fixed propagation delay through a multi-stage inverter delay chain, ensuring that the rising / falling edges of the complementary clocks are staggered. After being combined by logic gates, it is ensured that the two complementary clock signals CLK3 and CLK4 at the final output will not be low simultaneously. That is, CLK3 and CLK4 are a set of low-level non-overlapping clock signals.

[0036] Four clock signals CLK1~CLK4 with fixed non-overlapping times are generated to provide safe and reliable timing control for subsequent switched capacitor circuits or multiphase drive circuits, avoiding problems such as charge leakage and power supply short circuits.

[0037] like Figure 4 As shown, the level conversion driving unit includes: PMOS transistors MP31~MP33, NMOS transistors MN31~MN33, and inverters INV31~INV35; the input terminal of the inverter INV31 and the gate of the PMOS transistor MP32 are connected to clock signals CLK1~CLK4, and the output terminal is connected to the gate of the PMOS transistor MP31; the source of the PMOS transistors MP31~MP33 is connected to the power supply VDD2P; the drain of the PMOS transistor MP31 is connected to the drain of the NMOS transistor MN31 and the gate of the NMOS transistor MN32; the gate of the NMOS transistor MN31 is connected to the drain of the NMOS transistor MN32 and the PMOS transistor MP32, and the gate of the PMOS transistor MP33 and the NMOS transistor MN33; the NMOS... The sources of transistors MN31-MN33 are connected to power supply VDD2N; the drain of NMOS transistor MN33 is connected to the drain of PMOS transistor MP33, as well as the input terminals of inverters INV32 and INV34; inverter INV32 is connected in series with inverter INV33, and the output terminal of inverter INV33 outputs clock signals CLK1A-CLK4A; inverter INV34 is connected in series with inverter INV35, and the output terminal of inverter INV35 outputs clock signals CLK1B-CLK4B; the positive power supply terminal of inverter INV31 is connected to power supply VDD, and the negative power supply terminal is grounded to GND; the positive power supply terminals of inverters INV32-INV35 are connected to power supply VDD2P, and the negative power supply terminals are connected to power supply VDD2N.

[0038] The circuit of the level conversion driver unit is as follows: Figure 4 As shown, the circuit is a cross-power domain clock level conversion and driving unit. Its core part is a cross-coupled latch structure composed of MP31, MP32, MP33, MN31, MN32, and MN33. First, the input clocks CLK1~CLK4 are buffered and shaped by inverter INV31, providing complementary control signals for subsequent cross-coupled circuits. Second, the cross-coupled latch structure quickly converts the input clock signals from the VDD / GND power domain to the VDD2P / VDD2N power domain through positive feedback, achieving high-speed and interference-resistant level conversion. Finally, the converted signals are passed through two stages of inverter chains: INV32 and INV33, and INV34 and INV35, to enhance the drive and output a pair of clock signals CLK1A~CLK4A and CLK1B~CLK4B with the same phase and stronger driving capability, providing reliable timing drive for subsequent switching circuits.

[0039] The power supply domain of clock signals CLK1~CLK4 is converted from VDD / GND to VDD2P / VDD2N to achieve a wider range of high and low signal amplitudes and enhance drive capability. These signals are used as control signals for the subsequent PUMP (charge pump) module transmission transistors, effectively reducing voltage transmission loss caused by the transmission transistor threshold voltage and improving transmission efficiency. The two clock signals output by the level conversion driver unit—CLK1A and CLK1B, CLK2A and CLK2B, CLK3A and CLK3B, and CLK4A and CLK4B—are identical and are subsequently used to control different transmission transistors.

[0040] like Figure 5 As shown, the positive high-voltage charge pump module includes: PMOS transistors MP41~MP43, NMOS transistor MN41, and capacitors C41~C42; the gate of NMOS transistor MN41 is connected to clock signal CLK1A, the source and substrate are grounded to GND, and the drain is connected to the drain of PMOS transistor MP41 and one end of capacitor C41 to form node M; the gate of PMOS transistor MP41 is connected to clock signal CLK3B, the source and substrate, and the drain of PMOS transistor MP42 are connected to power supply VDD; the gate of PMOS transistor MP42 is connected to clock signal CLK4A, the source and substrate are connected to the other end of capacitor C41 and the drain of PMOS transistor MP43 to form node N; the gate of PMOS transistor MP43 is connected to clock signal CLK3A, the source and substrate, and one end of capacitor C42 are connected to power supply VDD2P; the other end of capacitor C42 is grounded to GND.

[0041] The structure of the positive high voltage charge pump module is as follows: Figure 5The diagram shows a two-stage Dickson transistor structure, with all boost transistors using PMOS transistors. In the first stage: CLK3B and CLK1A are high, CLK4A is low, CLK3A is high again, MP42 and MN41 are on, MP41 and MP43 are off, and the power supply VDD charges capacitor C41. The voltage at point M is 0, and the voltage at point N is Vdd, which is the voltage across capacitor C41. V MN =vdd. Second stage: CLK3B and CLK1A go low, CLK4A goes high, CLK3A goes low, MP42 and MN41 are off, MP41 and MP43 are on, the power supply VDD charges point M through MP41, and the voltage at point M becomes vdd. Because the voltage across capacitor C41... V MN =vdd, then the voltage at point N and point P becomes 2vdd, achieving the voltage multiplication effect of the power supply voltage, that is... V VDD2P =2Vdd. Typically, to obtain a stable high-voltage output and a large driving capability, a large voltage regulator capacitor C42 is connected to the VDD2P terminal. Therefore, multiple clock cycles are required for repeated charging and discharging to ultimately obtain a stable voltage output.

[0042] In the circuit, CLK3A and CLK4A, and CLK3B and CLK4A are low-level non-overlapping clocks. Therefore, MP41 and MP42, and MP42 and MP43 will not be turned on at the same time, which can effectively avoid the charge backflow problem and improve the transmission efficiency.

[0043] like Figure 6 As shown, the negative high-voltage charge pump module includes: a PMOS transistor MP44, NMOS transistors MN42~MN44, capacitor C40, and capacitor C43; the gate of the PMOS transistor MP44 is connected to the clock signal CLK4B, the source and substrate are connected to the power supply VDD2P, and the drain is connected to the drain of the NMOS transistor MN42 and one end of capacitor C40 to form node E; the gate of the NMOS transistor MN42 is connected to the clock signal CLK2A, and the source, substrate, and one end of capacitor C43 are grounded to GND; the other end of capacitor C40 is connected to the drain of NMOS transistor MN43 and the source of NMOS transistor MN44 to form node F; the gate of the NMOS transistor MN43 is connected to the clock signal CLK1B, and the source, substrate, and substrate of NMOS transistor MN44 are grounded to GND; the gate of the NMOS transistor MN44 is connected to the clock signal CLK2B, and the drain is connected to the other end of capacitor C43 and the power supply VDD2N.

[0044] The structure of the negative high-voltage charge pump module is as follows: Figure 6As shown: This is a 2-stage Dickson structure, with all boost transistors using NMOS transistors. First stage: CLK1B is high, CLK4B, CLK2A, and CLK2B are low. At this time, MP44 and MN43 are on, MN42 and MN44 are off, and VDD2P charges C40. The voltage at point F is 0, and the voltage at point E is... V VDD2P That is, the voltage across capacitor C40. V FE = V VDD2P Second stage: CLK1B goes low, CLK4B, CLK2A, and CLK2B go high. At this time, MP44 and MN43 are off, while MN42 and MN44 are on. The voltage at point E becomes 0, because the voltage across capacitor C40... V FE = V VDD2P Then the voltage at point F is - V VDD2P With MN44 conducting, the voltage at point VDD2N is also - V VDD2P This achieves a negative high-voltage output. Typically, to obtain a stable voltage output and a large driving capability, a large voltage regulator capacitor C43 is connected to the VDD2N terminal. Therefore, multiple clock cycles are required for repeated charging and discharging to obtain a stable negative high-voltage output. V VDD2P When VDD = 2Vdd, the final output voltage at the VDD2N terminal is -2Vdd, achieving a reverse output of the positive high voltage.

[0045] In the circuit, CLK1B and CLK2B, and CLK1B and CLK2A are high-level non-overlapping clocks. Therefore, MN43 and MN44, and MN43 and MN42 will not be turned on at the same time, which can effectively avoid the charge backflow problem and improve the transmission efficiency.

[0046] Non-overlapping clock timing diagram as shown below Figure 7 As shown: CLK1 and CLK2 are a set of non-overlapping clock signals, with high levels that are non-overlapping and a high-level duration of t1. CLK3 and CLK4 are a set of non-overlapping clock signals, with low levels that are non-overlapping and a low-level duration of t1. Non-overlapping clocks effectively avoid the current backflow problem caused by the simultaneous activation of the transmission transistors during the charge pump's voltage boosting process, thus improving operating efficiency.

[0047] When the PUMP circuit module is working, different clock combinations are used to control the transmission transistors in different states. Non-overlapping clock overlap can effectively avoid the charge backflow problem caused by the simultaneous conduction of transmission transistors, thus improving working efficiency.

[0048] In summary, this invention, based on the traditional Dickson charge pump structure model, designs a dual charge pump circuit structure that generates positive and negative high voltages based on a single power supply system. It can provide positive and negative high voltage outputs under the operating voltage of a single power supply system and can be used as a power source. Simultaneously, the circuit employs an improved non-overlapping clock control design, which effectively avoids the charge backflow problem caused by the simultaneous conduction of the transfer transistors in the charge pump, thus improving system efficiency. This invention can be used as a positive and negative high voltage power supply to power other circuits in the system; it can also be applied in bus driver circuits as positive and negative power supplies for high voltage drive outputs, such as ARINC429 bus and RS485 bus driver circuits.

[0049] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A positive and negative high-voltage dual charge pump circuit based on a single power supply system, characterized in that, include: The oscillator, consisting of a loop of three inverters, is used to generate the clock signal CLK0. The frequency of the clock signal CLK0 can be effectively adjusted by adjusting the capacitor. The oscillator is turned on or off by the enable signal EN. The clock division and non-overlapping clock generation unit is used to divide the clock signal CLK0 output by the oscillator by four and generate four non-overlapping clock signals CLK1~CLK4; wherein clock signals CLK1~CLK2 are a set of high-level non-overlapping clock signals; and non-overlapping clock signals CLK3~CLK4 are a set of low-level non-overlapping clock signals. The level conversion driver unit has four groups, which are used to convert clock signals CLK1~CLK4 into two clock signals CLK1A~CLK1B, two clock signals CLK2A~CLK2B, two clock signals CLK3A~CLK3B, and two clock signals CLK4A~CLK4B respectively; and the clock signals converted by the level conversion driver unit have a wider range of high and low signal amplitudes to enhance the driving capability. The charge pump unit includes a positive high-voltage charge pump module and a negative high-voltage charge pump module with a two-stage Dickson structure. Based on the Dickson structure principle, the clock signal converted by the level conversion drive unit controls the transmission tube to charge and discharge the capacitor, so as to realize the voltage multiplication and reverse action of the single power supply voltage, and generate positive and negative high-voltage signals respectively for use as positive and negative power supplies. The positive high voltage charge pump module uses PMOS transistor MP41 and NMOS transistor MN41 to alternately switch the node M connected to the drain of the PMOS transistor MP42 and NMOS transistor MN41 between ground GND and power supply VDD. The node N connected to the source and drain of PMOS transistor MP42 and PMOS transistor MP43 is boosted through the coupling of capacitor C41. The boosted voltage is output through PMOS transistor MP43 to generate power supply VDD2P. The negative high-voltage charge pump module uses PMOS transistor MP44 and NMOS transistor MN42 to alternately switch the node E connected to their drain between ground GND and power supply VDD2P. Through capacitor C40, the node F connected to the source and drain of NMOS transistors MN43 and MN44 is pulled low to a negative voltage. The negative voltage is then output through NMOS transistor MN44 to generate power supply VDD2N.

2. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 1, characterized in that, The oscillator includes: PMOS transistors MP0~MP8, NMOS transistors MN0~MN8, and capacitor C0; the source of PMOS transistor MP0 is connected to power supply VDD, and its gate and drain are connected to the drain of NMOS transistor MN0; the gate of NMOS transistor MN0 is connected to enable signal EN, and its source is connected to the gate and drain of NMOS transistor MN1, the gate of NMOS transistor MN2, and the gate of NMOS transistor MN3; the source of NMOS transistor MN1 is grounded to GND; the source of NMOS transistor MN2 is grounded, and its drain is connected to the gate and drain of PMOS transistor MP1 and the gate of PMOS transistor MP2; the source of PMOS transistor MP1 is connected to power supply VDD; the source of PMOS transistor MP2 is connected to power supply VDD, and its drain is connected to the source of PMOS transistor MP3; the gate of PMOS transistor MP3 is connected to the gate of NMOS transistor MN5, and the drains of PMOS transistors MP7 and MN8, and outputs a clock signal CLK0; its drain is connected to the drain of NMOS transistor MN5 and PMOS transistor MP7. The gates of PMOS transistors MN4-MP5, and the gates of NMOS transistors MN6 and MN4; the source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3, and the source of NMOS transistor MN3 is grounded to GND; the source of PMOS transistor MP4 is connected to power supply VDD, and the drain is connected to the source of PMOS transistors MP5-MP6; the drain of PMOS transistor MP5 is connected to the gate of PMOS transistor MP6, the drain of NMOS transistor MN6, the gate of NMOS transistor MN7, one end of capacitor C0, and the gates of PMOS transistors MP7 and MN8; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN4 and the source of NMOS transistor MN7; the source of NMOS transistor MN4 is grounded to GND; the drain of PMOS transistor MP6 is connected to power supply VDD; the drain of NMOS transistor MN7 is grounded to GND; the other end of capacitor C0 and the source of NMOS transistor MN8 are grounded to GND; the source of PMOS transistor MP7 is connected to power supply VDD.

3. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 1, characterized in that, The clock division and non-overlapping clock generation unit includes: The clock divider module consists of a cascaded first differential branch and a second differential branch forming a cross-coupled feedback loop, used to divide the clock signal CLK0 by four to output a single-ended clock signal with stable duty cycle and strong anti-interference capability. The non-overlapping clock generation module consists of a first logic gate and a second logic gate. The first logic gate consists of a NOR gate and an inverter delay chain, and outputs a set of high-level non-overlapping clock signals CLK1~CLK2. The second logic gate consists of a NAND gate and an inverter delay chain, and outputs a set of low-level non-overlapping clock signals CLK3~CLK4.

4. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 3, characterized in that, The clock divider module includes: The first differential branch includes: PMOS transistors MP21~MP26, NMOS transistors MN21~MN23, and inverter INV0; the source of PMOS transistor MP21 is connected to power supply VDD, its gate is connected to the gate of NMOS transistor MN21 and serves as the feedback terminal of the first differential branch, and its drain is connected to the source of PMOS transistor MP22; the gate of PMOS transistor MP22 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN21 and the gate of PMOS transistor MP24; the sources of NMOS transistors MN21~MN23 are grounded to GND; the gate of NMOS transistor MN22 is connected to PMOS transistor MP23 and... The gate of PMOS transistor MP26 and the clock signal CLK0 are connected, and the drain is connected to the drain of PMOS transistor MP24. The source of PMOS transistor MP24 is connected to the drain of PMOS transistor MP23, and the gates of PMOS transistor MP25 and NMOS transistor MN23. The sources of PMOS transistors MP23 and MP25 are connected to the power supply VDD. The drain of PMOS transistor MP25 is connected to the source of PMOS transistor MP26 and the input terminal of inverter INV0. The drain of PMOS transistor MP26 is connected to the drain of NMOS transistor MN23. The output terminal of inverter INV0 serves as the output terminal of the first differential branch. The second differential branch includes: PMOS transistors MP11~MP16, NMOS transistors MN11~MN13, and inverters INV1~INV2; the source of PMOS transistor MP11 is connected to power supply VDD, its gate is connected to the output terminal of the first differential branch and the gate of NMOS transistor MN11, and its drain is connected to the source of PMOS transistor MP12; the gate of PMOS transistor MP12 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN11 and the gate of PMOS transistor MP14; the sources of NMOS transistors MN11~MN13 are grounded to GND; the gate of NMOS transistor MN12 is connected to the gate of PMOS transistor MP13, and its drain is connected to... The source of PMOS transistor MP14 is connected to the drain of PMOS transistor MP13, and the gates of PMOS transistor MP15 and NMOS transistor MN13. The sources of PMOS transistors MP13 and MP15 are connected to power supply VDD, and the drain of PMOS transistor MP15 is connected to the source of PMOS transistor MP16 and the input terminal of inverter INV1. The gate of PMOS transistor MP16 is connected to clock signal CLK0, and its drain is connected to the drain of NMOS transistor MN13. Inverters INV1 and INV2 are connected in series, and the output terminal of inverter INV2 is connected to the feedback terminal of the first differential branch.

5. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 4, characterized in that, The non-overlapping clock generation module includes: The first logic gate includes: NOR gates NOR1~NOR2 and inverters INV3~INV8; the two inputs of NOR gate NOR1 are respectively connected to the output of inverter INV1 and the input of inverter INV8, and the output is connected to inverters INV3, INV5 and INV7 connected in series. The output of inverter INV7 outputs clock signal CLK1; the two inputs of NOR gate NOR2 are respectively connected to the outputs of inverters INV2 and INV5, and the output is connected to inverters INV4, INV6 and INV8 connected in series. The output of inverter INV8 outputs clock signal CLK2. The second logic gate includes: NAND gates NAND1~NAND2 and inverters INV9~INV14; the two inputs of NAND gate NAND1 are respectively connected to the output of inverter INV1 and the input of inverter INV14, and the output is connected to inverters INV9, INV11 and INV13 connected in series. The output of inverter INV13 outputs clock signal CLK3; the two inputs of NAND gate NAND2 are respectively connected to the outputs of inverters INV2 and INV11, and the output is connected to inverters INV10, INV12 and INV14 connected in series. The output of inverter INV14 outputs clock signal CLK4.

6. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 1, characterized in that, The level conversion driving unit includes: PMOS transistors MP31~MP33, NMOS transistors MN31~MN33, and inverters INV31~INV35; the input terminal of the inverter INV31 and the gate of the PMOS transistor MP32 are connected to clock signals CLK1~CLK4, and the output terminal is connected to the gate of the PMOS transistor MP31. The sources of the PMOS transistors MP31~MP33 are connected to the power supply VDD2P, and the drain of the PMOS transistor MP31 is connected to the drain of the NMOS transistor MN31 and the gate of the NMOS transistor MN32; the gate of the NMOS transistor MN31 is connected to the drain of the NMOS transistor MN32 and the PMOS transistor MP32, as well as the gate of the PMOS transistor MP33 and the NMOS transistor MN33; the NMOS transistor MP31~MP33~MP34~MP35~MP35~MP36~MP37~MP38~MP39~MP31~MP31~MP32~MP33~MP31~MP32~MP33~MP31~MP35~MP31~MP32~MP3 ... The sources of N31~MN33 are connected to power supply VDD2N; the drain of NMOS transistor MN33 is connected to the drain of PMOS transistor MP33, as well as the input terminals of inverters INV32 and INV34; inverter INV32 is connected in series with inverter INV33, and the output terminal of inverter INV33 outputs clock signals CLK1A~CLK4A; inverter INV34 is connected in series with inverter INV35, and the output terminal of inverter INV35 outputs clock signals CLK1B~CLK4B; the positive power supply terminal of inverter INV31 is connected to power supply VDD, and the negative power supply terminal is grounded to GND; the positive power supply terminals of inverters INV32~INV35 are connected to power supply VDD2P, and the negative power supply terminals are connected to power supply VDD2N.

7. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 1, characterized in that, The positive high-voltage charge pump module includes: PMOS transistors MP41~MP43, NMOS transistor MN41, and capacitors C41~C42; the gate of NMOS transistor MN41 is connected to clock signal CLK1A, the source and substrate are grounded to GND, and the drain is connected to the drain of PMOS transistor MP41 and one end of capacitor C41 to form node M; the gate of PMOS transistor MP41 is connected to clock signal CLK3B, the source and substrate, and the drain of PMOS transistor MP42 are connected to power supply VDD; the gate of PMOS transistor MP42 is connected to clock signal CLK4A, the source and substrate are connected to the other end of capacitor C41 and the drain of PMOS transistor MP43 to form node N; the gate of PMOS transistor MP43 is connected to clock signal CLK3A, the source and substrate, and one end of capacitor C42 are connected to power supply VDD2P; the other end of capacitor C42 is grounded to GND.

8. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 1, characterized in that, The negative high-voltage charge pump module includes: a PMOS transistor MP44, NMOS transistors MN42~MN44, capacitor C40, and capacitor C43. The gate of the PMOS transistor MP44 is connected to clock signal CLK4B, its source and substrate are connected to power supply VDD2P, and its drain is connected to the drain of NMOS transistor MN42 and one end of capacitor C40, forming node E. The gate of the NMOS transistor MN42 is connected to clock signal CLK2A, and its source, substrate, and one end of capacitor C43 are grounded to GND. The other end of capacitor C40 is connected to the drain of NMOS transistor MN43 and the source of NMOS transistor MN44, forming node F. The gate of the NMOS transistor MN43 is connected to clock signal CLK1B, and its source, substrate, and the substrate of NMOS transistor MN44 are grounded to GND. The gate of the NMOS transistor MN44 is connected to clock signal CLK2B, and its drain is connected to the other end of capacitor C43 and power supply VDD2N.

9. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 7, characterized in that, The positive high-voltage charge pump module also includes: Phase 1: Clock signals CLK3B and CLK1A are high, and clock signal CLK4A is low. When CLK3A is high, PMOS transistors MP42 and MN41 are turned on, while PMOS transistors MP41 and MP43 are turned off. Power supply VDD charges capacitor C41. The voltage at node M is 0, and the voltage at node N is Vdd. Therefore, the voltage across capacitor C41 at this time... V MN =vdd; Second stage: Clock signals CLK3B and CLK1A go low, clock signal CLK4A goes high, and clock signal CLK3A goes low. PMOS transistors MP42 and MN41 are turned off, while PMOS transistors MP41 and MP43 are turned on. Power supply VDD charges node M through PMOS transistor MP41, and the voltage at node M becomes Vdd. Due to the voltage across capacitor C41... V MN =vdd, then the voltage at node N and the power supply VDD2P becomes 2vdd, thus achieving the voltage multiplication effect of the power supply voltage. V VDD2P =2vdd.

10. The positive and negative high-voltage dual charge pump circuit based on a single power supply system as described in claim 8, characterized in that, The negative high-voltage charge pump module also includes: Phase 1: Clock signal CLK1B is high, while clock signals CLK4B, CLK2A, and CLK2B are low. At this time, PMOS transistor MP44 and NMOS transistor MN43 are turned on, while NMOS transistors MN42 and MN44 are turned off. Power supply VDD2P charges capacitor C40. The voltage at node F is 0, and the voltage at node E is... V VDD2P At this time, the voltage across capacitor C40 is... V FE = V VDD2P ; Second stage: Clock signal CLK1B goes low, clock signals CLK4B, CLK2A, and CLK2B go high. At this time, PMOS transistor MP44 and NMOS transistor MN43 are off, while NMOS transistors MN42 and MN44 are on. The voltage at node E becomes 0, due to the voltage across capacitor C40. V FE = V VDD2P Then the voltage at node F is - V VDD2P NMOS transistor MN44 is turned on, and the voltage at power supply VDD2N is also - V VDD2P To achieve negative high voltage output; when V VDD2P When VDD = 2Vdd, the final output voltage at the power supply VDD2N is -2Vdd, so as to achieve the reverse output of the positive high voltage.

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