Voltage controlled delay chain circuit with clock detection assisted start-up and method of starting the same

Abstract

This invention discloses a voltage-controlled delay chain circuit with clock detection-assisted startup and its startup method, belonging to the field of integrated circuit technology. To solve the problem of startup lock-up in existing closed-loop control VCDL circuits under PVT conditions due to excessively low supply voltage when there is no input clock, this invention adds an input clock detection module to the existing main closed-loop circuit composed of the VCDL module, phase detection module, and power supply module. This module detects the presence or absence of an input clock and outputs an auxiliary control signal to the power supply module; when there is no input clock, it outputs an active auxiliary control signal, forcing the supply voltage to build up to a level sufficient for the VCDL module to operate normally; when the input clock arrives, the auxiliary control signal is switched to an inactive state, removing the auxiliary intervention, and the supply voltage is then independently regulated by the main closed-loop circuit. This invention ensures startup reliability without affecting the steady-state accuracy of the loop, and has a simple circuit structure and wide applicability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a voltage-controlled delay chain circuit with clock detection-assisted startup and its startup method. Background Technology

[0002] Multiphase clock signals have wide applications in high-speed data communication, clock data recovery, and synchronous digital systems. Voltage-controlled delay line (VCDL) circuits are a common technique for generating multiphase clocks. Their main function is to generate a multiphase output clock with precise phase differences based on an input reference clock, providing a timing reference for various functional modules within the system and ensuring the accuracy and stability of data sampling, signal processing, and other operations. In a typical closed-loop controlled VCDL circuit, the input clock signal passes through the delay chain to output a multiphase clock signal. The phase detection module compares the phases of the output multiphase clocks and generates a control signal characterizing the phase relationship. This control signal forms a negative feedback loop through the power supply module, dynamically adjusting the supply voltage to the delay chain, thereby locking the delay amount of the delay chain to the desired value and obtaining a precise multiphase clock output.

[0003] However, the VCDL circuit with the above closed-loop architecture suffers from startup failure in practical applications, especially under full operating conditions of process deviation, power supply voltage fluctuation and ambient temperature (PVT).

[0004] Figure 1This is a schematic diagram of the basic architecture of a VCDL circuit in the prior art. As shown in the figure, the existing VCDL circuit mainly consists of a VCDL module, a four-phase phase detection module, and a power supply module. Differential input clocks clkinp and clkinn are input to the input terminal of the VCDL module. After delaying the input clocks, the VCDL module outputs four-phase clock signals cko0, cko90, cko180, and cko270 with a 90-degree phase difference. These four-phase clock signals are simultaneously input to the input terminal of the four-phase phase detection module. The four-phase phase detection module detects the phase relationship between the four-phase output clocks and the input clocks, and outputs a first control signal vdel_p and a second control signal vdel_n representing the phase deviation. The first control signal vdel_p and the second control signal vdel_n are input to the control terminal of the power supply module. The power supply module dynamically adjusts the output supply voltage VDD according to the phase deviation signal. The supply voltage VDD is applied to the power supply terminal of the VCDL module. By changing the supply voltage of the delay unit in the VCDL module, the delay amount is adjusted, ultimately forming a negative feedback closed-loop system to achieve phase locking between the output clock and the input clock. However, when the system is initially powered on or before the input reference clock is connected, the four-phase phase detection module lacks a valid input signal, and its first control signal vdel_p and second control signal vdel_n are in an uncertain state. Affected by PVT fluctuations, the power supply module may adjust the supply voltage VDD to a level far below the voltage level required for the normal operation of the VCDL module. If the input reference clock is connected at this time, due to the insufficient supply voltage of the VCDL module, it cannot respond to the input clock normally and generate a valid four-phase output clock. As a result, the four-phase phase detection module will never be able to output the correct phase control signal, and the entire closed-loop negative feedback system will be locked in a low-voltage state, ultimately causing the VCDL circuit to fail and affecting the normal operation of the entire integrated circuit system.

[0005] To address the aforementioned VCDL startup failure issue, various solutions have been proposed in existing technologies. One approach involves collecting output states under multiple delay settings and constructing statistical histograms, then using a state machine to determine the initial control signal, thus achieving rapid VCDL startup. However, such solutions require the introduction of complex digital logic circuits and statistical operation modules, significantly increasing circuit area and power consumption, as well as design complexity and manufacturing costs. Furthermore, their startup process relies on complex algorithmic calculations, and under extreme PVT conditions, startup reliability remains insufficient, making it difficult to meet the high reliability and low cost requirements of high-performance, low-power integrated circuit systems for VCDL circuits.

[0006] Therefore, there is an urgent need in this field for a technical solution that can effectively ensure the smooth transition of VCDL circuits from a clockless state to a clocked normal operating state under various PVT conditions. Summary of the Invention

[0007] To alleviate or partially alleviate the above-mentioned technical problems, the solution of the present invention is as follows: On one hand, the present invention provides a voltage-controlled delay chain circuit with clock detection-assisted startup, comprising: The voltage-controlled delay chain module is used to delay the input clock signal according to the supply voltage to generate the output clock signal; A phase detection module, whose input is connected to the output of the voltage-controlled delay chain module, is used to generate a phase control signal based on the phase of the output clock signal; A power supply module, whose control terminal is connected to the output terminal of the phase detection module and whose output terminal is connected to the power supply terminal of the voltage control delay chain module, is used to provide the power supply voltage to the voltage control delay chain module; An input clock detection module receives the input clock signal at its input terminal and its output terminal is connected to the auxiliary control terminal of the power supply module. It is used to detect the presence or absence of the input clock signal and generate an auxiliary control signal. The input clock detection module is configured as follows: When the input clock signal is not detected, the auxiliary control signal is output in an active state, so that the supply voltage is established by the auxiliary control signal to a voltage level sufficient to enable the voltage control delay chain module to operate. When the input clock signal is detected, an auxiliary control signal in a high-impedance state is output to remove the regulating effect of the auxiliary control signal on the power supply voltage, so that the power supply voltage is independently regulated by the phase control signal.

[0008] In one embodiment, the input clock detection module includes: A frequency divider is used to receive the input clock signal and output a down-frequency clock signal. A digital logic unit, whose input is connected to the output of the frequency divider, is used to determine the presence or absence of the input clock signal based on the down-frequency clock signal and output a digital control signal. A level conversion unit, whose input terminal is connected to the output terminal of the digital logic unit, is used to convert the digital control signal into an analog control signal; A switching device, the control terminal of which is connected to the output terminal of the level conversion unit, and the output terminal of which serves as the output terminal of the input clock detection module to output the auxiliary control signal.

[0009] In one embodiment, the switching device is an N-type metal-oxide-semiconductor field-effect transistor, with its gate serving as the control terminal, its source grounded, and its drain serving as the output terminal of the input clock detection module.

[0010] In one embodiment, the digital logic unit is configured as follows: When no level transition of the down-frequency clock signal is detected within the preset monitoring period, it is determined that the input clock signal does not exist, and the digital control signal outputting a high level is converted into an analog domain high-level signal by the level conversion unit to drive the switching device to conduct, so that the auxiliary control signal is pulled down to a low level, and the low level is the effective state of the auxiliary control signal; When a valid level transition of the down-frequency clock signal is detected within a preset monitoring period, it is determined that the input clock signal exists, and the low-level digital control signal is output. After being converted into a low-level analog signal by the level conversion unit, the switching device is turned off, and the auxiliary control signal presents a high-impedance state.

[0011] In one embodiment, the power supply module employs a low-dropout linear regulator architecture, including: An operational amplifier, whose first input terminal and second input terminal respectively receive the first phase control signal and the second phase control signal in the phase control signal, is used to output a first intermediate control signal; An adder, whose first input terminal is connected to the output terminal of the operational amplifier, and whose second input terminal is connected to the output terminal of the input clock detection module to receive the auxiliary control signal, is used to superimpose the first intermediate control signal and the auxiliary control signal to output a total control signal; The power transistor has its gate as the control terminal of the power supply module, its source connected to the system power supply, and its drain as the output terminal of the power supply module to provide the power supply voltage.

[0012] In one embodiment, the power transistor is a P-type metal-oxide-semiconductor field-effect transistor.

[0013] In one embodiment, when the auxiliary control signal is in the active state, the auxiliary control signal is at a low level, the level of the total control signal is pulled low, the conduction degree of the power transistor is increased, and the supply voltage is established to a voltage level sufficient to enable the voltage control delay chain module to operate.

[0014] In one embodiment, the output clock signal output by the voltage-controlled delay chain module is a four-phase clock signal with a 90-degree phase difference.

[0015] In one embodiment, the input clock detection module may also employ an analog clock detection architecture to detect the presence or absence of an input clock signal and output corresponding auxiliary control signals.

[0016] On the other hand, the present invention discloses a method for starting a voltage-controlled delay chain circuit, comprising: The input clock detection module detects the presence or absence of the input clock signal in real time; When no input clock signal is detected, an auxiliary control signal in an active state is output to the power supply module, so that the power supply voltage output by the power supply module is established by the auxiliary control signal to a voltage level sufficient to enable the voltage control delay chain module to operate. When an input clock signal is detected, the auxiliary control signal is switched to a high-impedance state to remove the regulating effect of the auxiliary control signal on the power supply voltage, so that the power supply voltage is independently regulated by the phase control signal output by the phase detection module.

[0017] The technical solution of this invention has one or more of the following beneficial technical effects: (1) The present invention adds an input clock detection module, which actively injects an auxiliary control signal when there is no input clock, so that the power supply module outputs a higher voltage, effectively avoiding the startup lock-up problem caused by the initial power supply voltage being too low under PVT conditions, and improving startup reliability.

[0018] (2) After the input clock arrives, the auxiliary control signal automatically switches to a high impedance state and completely exits the loop intervention. The power supply voltage regulation is independently completed by the main closed loop. The auxiliary path does not affect the steady-state accuracy and phase noise performance of the loop, thus achieving a balance between startup reliability and steady-state performance.

[0019] (3) The present invention has strong versatility. The clock detection module can be implemented in digital or analog mode. The power supply module is not limited to LDO architecture and is applicable to VCDL and delay-locked loop circuits with any number of phases. It has a wide range of application scenarios.

[0020] Furthermore, other beneficial effects of the present invention will be mentioned in the specific embodiments. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the basic architecture of VCDL circuits in the prior art; Figure 2 This is a schematic diagram of a VCDL circuit structure according to one embodiment of the present invention; Figure 3 This is a schematic diagram of a specific circuit structure of one embodiment of the present invention; Figure 4 This is a schematic diagram of the specific implementation structure of the input clock detection module according to an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order.

[0024] This invention addresses the startup lock-up problem of existing closed-loop voltage controlled delay line (VCDL) circuits under full operating conditions of process, voltage, and temperature (PVT). By adding an input clock detection module to the original closed-loop architecture, it enables active pre-adjustment of the loop supply voltage during periods without an input clock signal, thereby ensuring that the VCDL circuit can start normally and complete phase locking after the input clock signal is received.

[0025] Figure 2This is a schematic diagram of a VCDL circuit structure according to one embodiment of the present invention. As shown in the figure, the present invention adds an input clock detection module to the existing VCDL circuit. The input terminal of the input clock detection module is connected to the differential input clock signals clkinp and clkinn, and is used to detect the presence or absence of the input clock signal in real time; the output terminal of the input clock detection module is connected to the auxiliary control terminal of the power supply module, and is used to output the auxiliary control signal vfb to the power supply module. In this embodiment, the connection relationship between the original VCDL module, the four-phase phase detection module and the power supply module remains unchanged. Specifically, differential input clock signals clkinp and clkinn are simultaneously input to the clock input terminal of the VCDL module and the input terminal of the input clock detection module; the VCDL module outputs four-phase clock signals cko0, cko90, cko180 and cko270 to the four-phase phase detection module; the four-phase phase detection module outputs the first control signal vdel_p and the second control signal vdel_n to the main control terminal of the power supply module; the input clock detection module outputs the auxiliary control signal vfb to the auxiliary control terminal of the power supply module; the power supply module integrates the first control signal vdel_p and the second control signal vdel_n received by its main control terminal and the auxiliary control signal vfb received by its auxiliary control terminal, adjusts the power supply voltage VDD provided by its output terminal, and provides the power supply voltage VDD to the power supply terminals of each delay unit in the VCDL module.

[0026] Figure 3 This is a schematic diagram of a specific circuit structure of one embodiment of the present invention. In this embodiment, the power supply module is implemented using a low dropout regulator (LDO) architecture. This LDO power supply module serves as the core of power supply regulation for the entire circuit. Its power supply terminal is connected to the system power supply VCC, and its output terminal outputs a supply voltage VDD to the power supply terminal of the VCDL delay chain module. The LDO power supply module integrates an operational amplifier (OPA), an adder, and a PMOS power transistor. Its specific internal connections are as follows: the non-inverting and inverting input terminals of the operational amplifier receive the first control signal vdel_p and the second control signal vdel_n output by the four-phase phase detection module, respectively; the output terminal of the operational amplifier outputs a first intermediate control signal vctrl1 to the first input terminal of the adder; the second input terminal of the adder receives the auxiliary control signal vfb output by the input clock detection module; after superimposing the above two input signals, the adder outputs a total control signal vctrl to the gate of the PMOS power transistor; the source of the PMOS power transistor is connected to the system power supply VCC, and its drain serves as the output terminal of the LDO power supply module, outputting the supply voltage VDD. The input clock detection module outputs an auxiliary control signal, vfb, which is connected to the control link of the LDO power supply module via the aforementioned adder, thus forming an auxiliary pre-adjustment path independent of the main closed-loop circuit. It should be noted that... Figure 3 The use of an adder to superimpose the auxiliary control signal VFB and the loop control signal shown is merely an exemplary implementation. In practical applications, any circuit structure capable of introducing the auxiliary control signal VFB into the power supply module control terminal to adjust the output voltage can be applied to this invention. This embodiment uses an operational amplifier to process the phase control signal and the clock detection signal, enabling precise adjustment of the power supply voltage. This ensures that the power supply voltage remains stable at the preset working voltage value when there is no input clock signal, and that the auxiliary pre-adjustment path does not affect the normal adjustment accuracy of the closed-loop system when there is an input clock signal.

[0027] Figure 4 This is a schematic diagram illustrating the specific implementation structure of the input clock detection module according to an embodiment of the present invention. It should be noted that... Figure 4 This is merely an illustrative example of a feasible circuit implementation for the input clock detection function and is not intended to limit the scope of protection of this invention. In practical applications, any circuit structure capable of detecting the presence or absence of an input clock signal and outputting a corresponding control level based on the detection result to assist in loop establishment can be applied to this invention. As shown in the figure, the input clock detection module in this embodiment adopts a digital clock detection architecture, specifically including a frequency divider, a digital logic unit, a level conversion unit, and a switching device (e.g., an N-type metal-oxide-semiconductor field-effect transistor, NMOS) connected in sequence.

[0028] Differential input clock signals clkinp and clkinn are input to the input terminals of a frequency divider. The frequency divider down-converts the input differential clock signals to a frequency range suitable for the normal operation of subsequent digital logic units, thereby avoiding misjudgments or malfunctions of the digital logic units due to excessively high clock frequencies. By using a frequency divider to pre-convert high-frequency input clock signals into low-frequency clock signals, reliable operation of subsequent digital logic units under standard digital logic processes can be effectively guaranteed.

[0029] The output of the frequency divider is connected to the clock input of the digital logic unit (DLU). The down-clocked clock signal is then fed into the DLU as its clock reference. The DLU contains a state monitoring circuit to monitor and logically determine the presence of a valid clock signal transition at the input. In one implementation, the DLU can detect the presence of a clock signal by checking for level transitions within a certain time window. For example, if no rising or falling edge transition is detected within a preset monitoring period, the input is considered to lack a valid clock signal; conversely, if a level transition is detected as expected, a valid clock signal is considered present. This preset monitoring period can be configured according to system startup time requirements and power management strategies.

[0030] When the digital logic unit determines that there is no valid clock signal at the input, it outputs a high-level digital control signal, denoted as logic "H". This high-level digital control signal is the standard logic level in the digital logic domain. Since the subsequent switching devices operate in the analog power domain, requiring a higher drive voltage and sufficient drive capability, this high-level digital control signal is further fed into a level conversion unit. The level conversion unit converts the high-level logic signal in the digital logic domain into a high-level analog control signal VG in the analog domain with sufficient drive capability. This level conversion unit achieves voltage domain conversion (Digital to Analog, D2A) between the digital and analog domains, and provides the current drive capability required to drive the gate of the subsequent switching devices. The converted high-level signal VG is applied to the gate of the NMOS transistor, which acts as a switching device. Since the gate-source voltage Vgs of the NMOS transistor is equal to the difference between VG and ground potential, under the action of the high-level VG, the gate-source voltage of the NMOS transistor is greater than its threshold voltage Vth, thus putting the NMOS transistor in the on state. In the on state, a low-impedance path is formed between the drain and source of the NMOS transistor. Since the source of the NMOS transistor is grounded and its drain is pulled down to near ground potential, the auxiliary control signal vfb output from the drain is pulled down to a low level.

[0031] The low-level auxiliary control signal Vfb is provided to the auxiliary control terminal of the power supply module. Inside the power supply module, this low-level auxiliary control signal Vfb acts on the voltage regulation control node of the power supply module, for example, on the gate bias circuit of the PMOS power transistor, so that the PMOS power transistor in the power supply module obtains sufficient gate-source bias voltage and is fully turned on. Under this condition, the power supply module can provide a relatively high supply voltage VDD to the VCDL delay chain. The value of this supply voltage VDD can ensure that each delay unit in the VCDL delay chain can respond normally to the input clock signal under any PVT condition. Under this high supply voltage bias, each delay unit of the delay chain is pre-established at a normal DC operating point, in a working state that can respond to the input signal at any time. When the input clock signal arrives, the delay chain can immediately respond normally to the input clock signal and generate multi-phase output clock signals in sequence, so that the main closed-loop negative feedback loop composed of the VCDL module, phase detection module and power supply module can start smoothly and gradually converge to a stable phase-locked state under the action of the negative feedback regulation mechanism.

[0032] Conversely, when the digital logic unit determines in real-time that a valid clock signal exists at the input, it outputs a low-level digital control signal, denoted as logic "L". This low-level digital control signal is converted into a corresponding low-level analog signal VG in the analog domain by a level conversion unit. This low-level VG is applied to the gate of the NMOS transistor, causing the gate-source voltage of the NMOS transistor to be less than its threshold voltage Vth, and the NMOS transistor is in the off state. In the off state, there is a high impedance between the drain and source of the NMOS transistor; therefore, the auxiliary control signal vfb output from its drain is in a high-impedance state.

[0033] Since the auxiliary control signal Vfb is in a high-impedance state, it has almost no effect on the voltage or current of the auxiliary control terminal of the power supply module. The state of the power supply module control terminal is entirely determined by the first control signal Vdel_p and the second control signal Vdel_n output by the phase detection module in the main closed loop. In other words, the auxiliary pre-adjustment path is automatically cut off at this time, and the intervention of the input clock detection module on the closed loop is completely removed. The magnitude of the supply voltage VDD is then dynamically adjusted independently by the main closed-loop negative feedback loop composed of the four-phase phase detection module and the power supply module, based on the actual phase error of the clock signal output by the VCDL module, until the final locked state is reached.

[0034] As can be seen from the above working process, the input clock detection module of this embodiment can actively output a low-level auxiliary control signal vfb when there is no input clock signal, forcing the power supply module to output a higher initial supply voltage VDD, providing the necessary start-up bias conditions for the VCDL delay chain; and after the input clock signal arrives, it can automatically switch the auxiliary control signal vfb to a high impedance state, completely withdrawing from the intervention of the closed loop, thereby effectively solving the start-up lock-up problem of the existing closed-loop VCDL circuit under PVT conditions due to the initial supply voltage being too low, without affecting the normal adjustment accuracy of the main loop.

[0035] It should be noted that the specific implementation structure of the input clock detection module in this invention is not limited to... Figure 4 The digital architecture is shown. Any circuit structure capable of detecting the presence or absence of an input clock signal and outputting a low-level active signal when there is no input clock signal and a high-impedance signal when there is an input clock signal, such as an analog clock detection circuit, can be applied to this invention to achieve the same function. Furthermore, the internal circuit structure of the power supply module is not limited to... Figure 3 The LDO architecture shown includes an operational amplifier, adder, and PMOS power transistor. Any power supply circuit capable of comprehensively adjusting the output voltage based on the main control signal and auxiliary control signal should be included within the scope of protection of this invention. Furthermore, the technical solution provided by this invention is not only applicable to VCDL circuits generating four-phase clocks, but can also be extended to VCDL circuits generating clocks with any number of phases, as well as delay-locked loop (DLL) circuits employing a similar closed-loop power supply architecture. The core principle lies in using an input clock detection module to pre-adjust the power supply voltage during periods without an input clock signal, thereby preventing the closed-loop circuit from being locked into an abnormal operating state due to an initially low power supply voltage. To better illustrate this invention, numerous specific details are provided in the above-described embodiments. Those skilled in the art should understand that this invention can be implemented even without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail to highlight the main points of this invention.

[0036] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A voltage controlled delay chain circuit with clock detection assisted start-up, characterized by, include: The voltage-controlled delay chain module is used to delay the input clock signal according to the supply voltage to generate the output clock signal; A phase detection module, whose input is connected to the output of the voltage-controlled delay chain module, is used to generate a phase control signal based on the phase of the output clock signal; A power supply module, whose control terminal is connected to the output terminal of the phase detection module and whose output terminal is connected to the power supply terminal of the voltage control delay chain module, is used to provide the power supply voltage to the voltage control delay chain module; An input clock detection module receives the input clock signal at its input terminal and its output terminal is connected to the auxiliary control terminal of the power supply module. It is used to detect the presence or absence of the input clock signal and generate an auxiliary control signal. The input clock detection module is configured as follows: When the input clock signal is not detected, the auxiliary control signal is output in an active state, so that the supply voltage is established by the auxiliary control signal to a voltage level sufficient to enable the voltage control delay chain module to operate. When the input clock signal is detected, an auxiliary control signal in a high-impedance state is output to remove the regulating effect of the auxiliary control signal on the power supply voltage, so that the power supply voltage is independently regulated by the phase control signal.

2. The voltage controlled delay chain circuit with clocked detection assisted start-up of claim 1, wherein, The input clock detection module includes: A frequency divider is used to receive the input clock signal and output a down-frequency clock signal. A digital logic unit, whose input is connected to the output of the frequency divider, is used to determine the presence or absence of the input clock signal based on the down-frequency clock signal and output a digital control signal. A level conversion unit, whose input terminal is connected to the output terminal of the digital logic unit, is used to convert the digital control signal into an analog control signal; A switching device, the control terminal of which is connected to the output terminal of the level conversion unit, and the output terminal of which serves as the output terminal of the input clock detection module to output the auxiliary control signal.

3. The voltage-controlled delay chain circuit with clock detection-assisted startup as described in claim 2, characterized in that: The switching device is an N-type metal-oxide-semiconductor field-effect transistor, with its gate serving as the control terminal, its source grounded, and its drain serving as the output terminal of the input clock detection module.

4. The clocked detection assisted start-up voltage controlled delay chain circuit of claim 2, wherein, The digital logic unit is configured as follows: When no level transition of the down-frequency clock signal is detected within the preset monitoring period, it is determined that the input clock signal does not exist, and the digital control signal outputting a high level is converted into an analog domain high-level signal by the level conversion unit to drive the switching device to conduct, so that the auxiliary control signal is pulled down to a low level, and the low level is the effective state of the auxiliary control signal; When a valid level transition of the down-frequency clock signal is detected within a preset monitoring period, it is determined that the input clock signal exists, and the low-level digital control signal is output. After being converted into a low-level analog signal by the level conversion unit, the switching device is turned off, and the auxiliary control signal presents a high-impedance state.

5. The clocked detection assisted start-up voltage controlled delay chain circuit of claim 1, wherein, The power supply module adopts a low-dropout linear regulator architecture, including: An operational amplifier, whose first input terminal and second input terminal respectively receive the first phase control signal and the second phase control signal in the phase control signal, is used to output a first intermediate control signal; An adder, whose first input terminal is connected to the output terminal of the operational amplifier, and whose second input terminal is connected to the output terminal of the input clock detection module to receive the auxiliary control signal, is used to superimpose the first intermediate control signal and the auxiliary control signal to output a total control signal; The power transistor has its gate as the control terminal of the power supply module, its source connected to the system power supply, and its drain as the output terminal of the power supply module to provide the power supply voltage.

6. The voltage-controlled delay chain circuit with clock detection-assisted startup as described in claim 5, characterized in that: The power transistor is a P-type metal-oxide-semiconductor field-effect transistor.

7. The voltage-controlled delay chain circuit with clock detection-assisted startup as described in claim 5, characterized in that: When the auxiliary control signal is in the active state, the auxiliary control signal is at a low level, the level of the total control signal is pulled low, the conduction degree of the power transistor is increased, and the supply voltage is established to a voltage level sufficient to enable the voltage control delay chain module to operate.

8. The voltage-controlled delay chain circuit with clock detection-assisted startup according to claim 1, characterized in that: The output clock signal from the voltage-controlled delay chain module is a four-phase clock signal with a 90-degree phase difference.

9. The voltage-controlled delay chain circuit with clock detection-assisted startup according to claim 1, characterized in that: The input clock detection module can also adopt an analog clock detection architecture to detect the presence or absence of the input clock signal and output corresponding auxiliary control signals.

10. A method of starting a voltage controlled delay chain circuit, characterized by, include: The voltage-controlled delay chain module delays the input clock signal according to the supply voltage to generate an output clock signal; The input terminal of the phase detection module is connected to the output terminal of the voltage control delay chain module, and a phase control signal is generated according to the phase of the output clock signal; The control terminal of the power supply module is connected to the output terminal of the phase detection module, and its output terminal is connected to the power supply terminal of the voltage control delay chain module to provide the power supply voltage to the voltage control delay chain module. The input clock detection module receives the input clock signal at its input terminal and its output terminal is connected to the auxiliary control terminal of the power supply module to detect the presence or absence of the input clock signal in real time. When no input clock signal is detected, an auxiliary control signal in an active state is output to the power supply module, so that the power supply voltage output by the power supply module is established by the auxiliary control signal to a voltage level sufficient to enable the voltage control delay chain module to operate. When an input clock signal is detected, the auxiliary control signal is switched to a high-impedance state to remove the regulating effect of the auxiliary control signal on the power supply voltage, so that the power supply voltage is independently regulated by the phase control signal output by the phase detection module.

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