A circuit for converting a string wave clock signal into a square wave signal

Abstract

The application provides a kind of anti-noise interference string wave clock signal conversion square wave signal circuit, it is related to noise elimination, circuit design technical field, including: reference voltage generating circuit, for generating N group reference voltage while inputting string wave conversion square wave circuit;String wave conversion square wave circuit, according to the voltage situation of the rising edge or falling edge of received string wave clock signal, the N group reference voltage is used as flip point reference voltage to carry out level flip and generate square wave signal;The application solves when the rising process of string wave clock signal rising edge crosses a flip point, if the glitch interference jitter of string wave edge is generated at this time, as long as the amplitude of jitter does not reach the voltage of final flip point, or the voltage amplitude of jitter cannot be maintained to the last flip point to generate logic flip, the output cannot generate final logic flip, greatly improves the ability of string wave input clock to resist flip point glitch pulse interference, improves the running stability of digital logic system using the circuit.

Description

Technical Field

[0001] This invention relates to the fields of noise cancellation and circuit design, covering chip-level circuit design and PCB-level circuit design, and particularly to a noise-resistant sine wave clock signal to square wave signal conversion circuit. Background Technology

[0002] like Figure 1 As shown, in existing technology, when a sinusoidal clock signal is input to port X1, an amplifier circuit AMP0 is typically used to convert the sinusoidal signal into a square wave signal. The characteristics of AMP0 are typically as follows: when the peak-to-peak value of the input sinusoidal clock signal is VPP, if the sinusoidal voltage exceeds its switching threshold VPP / 2, it will quickly switch to a logic high level; if the sinusoidal voltage is below its switching threshold VPP / 2, it will quickly switch to a logic low level. The converted square wave signal will then serve as the clock signal for the digital system.

[0003] The drawback of this clock conversion method is that if there is noise interference near the flip point, the output square wave clock edge will flip multiple times unexpectedly due to the interference. Such unexpected edge flips will cause serious timing problems in the digital system, or even cause the digital system to malfunction.

[0004] Therefore, there is an urgent need for a noise-resistant sine wave clock signal to square wave signal conversion circuit to solve the above problems. Summary of the Invention

[0005] To address the aforementioned technical problems in related technologies, this invention proposes a noise-resistant sine wave clock signal to square wave signal conversion circuit, comprising a reference voltage generation circuit and a sine wave to square wave conversion circuit. The reference voltage generating circuit is used to generate N sets of reference voltages and simultaneously input them into the sine wave to square wave circuit. The sine wave to square wave circuit is used to generate a square wave signal by level flipping the N sets of reference voltages as flip point reference voltages based on the voltage condition of the rising or falling edge of the received sine wave clock signal.

[0006] Specifically, the reference voltage generating circuit generates three sets of reference voltages, including a first reference voltage, a second reference voltage, and a third reference voltage.

[0007] Specifically, when the sine wave clock signal voltage rises from 0 to the rising edge of the peak-to-peak value VPP of the sine wave clock signal, the initial flip point reference voltage is set to the first reference voltage. When the rising edge crosses the first reference voltage, it will trigger the flip point reference voltage to move up to the second reference voltage. When the rising edge crosses the second reference voltage, it will trigger the flip point reference voltage to move up to the third reference voltage again, until the rising edge crosses the third reference voltage, and the output flips to a logic high level.

[0008] Specifically, when the sine wave clock signal voltage drops from the peak-to-peak value VPP of the sine wave clock signal to the falling edge stage of 0, when the falling edge crosses the third reference voltage, it will trigger the flip point reference voltage to shift down to the second reference voltage. When the falling edge crosses the second reference voltage, it will trigger the flip point reference voltage to shift down to the first reference voltage again, until the falling edge crosses the first reference voltage, and the output flips to a logic low level.

[0009] Specifically, the sine wave to square wave circuit includes a first comparator COMP1, a second comparator COMP2, a third comparator COMP3, a first digital signal buffer BUF1, a second digital signal buffer BUF2, a third digital signal buffer BUF3, a fourth digital signal buffer BUF4, a first signal transmission gate, a second signal transmission gate, a three-input AND gate AND3, a three-input NOR gate NOR3, a third inverter INV3, a fourth inverter INV4, and a signal latch; The first comparator COMP1 has its VN terminal connected to a first reference voltage, its VP terminal connected to the sine wave clock signal, and its VO terminal connected to the input terminal of the first digital signal buffer BUF1; the second comparator COMP2 has its VN terminal connected to a second reference voltage, its VP terminal connected to the sine wave clock signal, and its VO terminal connected to the input terminal of the second digital signal buffer BUF2; the third comparator COMP3 has its VN terminal connected to a third reference voltage, its VP terminal connected to the sine wave clock signal, and its VO terminal connected to the input terminal of the third digital signal buffer BUF3. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are respectively connected to the inputs of the three-input AND gate AND3 and the three-input NOR gate NOR3. The output of the three-input NOR3 is connected to the control terminal of the first signal transmission gate, and is also connected to the inverting control terminal of the first signal transmission gate through the third inverter INV3. The output of the three-input AND gate AND3 is connected to the control terminal of the second signal transmission gate, and is also connected to the inverting control terminal of the second signal transmission gate through the fourth inverter INV4; The output terminals of the first and second signal transmission gates are connected through the signal latch and the fourth digital signal buffer BUF4 to output square wave signals.

[0010] Specifically, the signal latch is composed of a first inverter INV1 and a second inverter INV2; the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 to form the input terminal of the signal latch; the input terminal of the first inverter INV1 is connected to the output terminal of the second inverter INV2 to form the output terminal of the signal latch.

[0011] Specifically, the input terminal of the signal latch is connected to the output terminals of the first signal transmission gate and the second signal transmission gate, and its output terminal is connected to the input terminal of the fourth digital signal buffer BUF4; the output terminal of the fourth digital signal buffer BUF4 outputs a square wave signal.

[0012] Specifically, during initialization, the reference voltage for the flip point is the first reference voltage; When the voltage of the sine wave clock signal rises from 0 to the rising edge of the peak-to-peak value VPP of the sine wave clock signal: When the sine wave clock signal voltage is lower than the first reference voltage, the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 0, the outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 0, the output of the three-input NOR gate NOR3 is logic 1, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 0, the output of the fourth inverter INV4 is logic 1, the second transmission gate is closed, the first transmission gate is open, and the logic 0 output of the first digital signal buffer BUF1 is transmitted to the signal latch. The fourth digital signal buffer BUF4 finally outputs logic 0. When the rising edge of the sine wave clock signal crosses the first reference voltage, the output of the first comparator COMP1 is logic 1, the outputs of the second comparator COMP2 and the third comparator COMP3 are logic 0, the output of the first digital signal buffer BUF1 is logic 1, the outputs of the second digital signal buffer BUF2 and the third digital signal buffer BUF3 are logic 0, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 0, and the fourth digital signal buffer BUF4 maintains the output logic 0. At this time, the flip point reference voltage will be triggered to move up to the second reference voltage. When the rising edge of the sine wave clock signal crosses the second reference voltage, the outputs of the first comparator COMP1 and the second comparator COMP2 are logic 1, the output of the third comparator COMP3 is logic 0, the outputs of the first digital signal buffer BUF1 and the second digital signal buffer BUF2 are logic 1, the output of the third digital signal buffer BUF3 is logic 0, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 0, and the fourth digital signal buffer BUF4 maintains the output logic 0. At this time, the flip point reference voltage will be triggered to move up to the third reference voltage. When the rising edge of the sine wave clock signal crosses the third reference voltage, the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 1s. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 1s. The output of the three-input NOR gate NOR3 is logic 0. The output of the three-input AND gate AND3 is logic 1. The output of the third inverter INV3 is logic 1. The output of the fourth inverter INV4 is logic 0. The first transmission gate is closed, and the second transmission gate is opened, transmitting the logic 1 output of the third digital signal buffer BUF3 to the signal latch. The fourth digital signal buffer BUF4 quickly flips from logic 0 to output logic 1.

[0013] Specifically, during the falling edge phase when the sine wave clock signal voltage drops from the peak-to-peak value VPP of the sine wave clock signal to 0: When the falling edge crosses the third reference voltage, the output of the third comparator COMP3 is logic 0, the outputs of the first comparator COMP1 and the second comparator COMP2 are logic 1, the output of the third digital signal buffer BUF3 is logic 0, the outputs of the first digital signal buffer BUF1 and the second digital signal buffer BUF2 are logic 1, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 1, and the fourth digital signal buffer BUF4 maintains the output logic 1. At this time, the flip point reference voltage will be triggered to shift down to the second reference voltage. When the falling edge crosses the second reference voltage, the outputs of the second comparator COMP2 and the third comparator COMP3 are logic 0, the output of the first comparator COMP1 is logic 1, the outputs of the second digital signal buffer BUF2 and the third digital signal buffer BUF3 are logic 0, the output of the first digital signal buffer BUF1 is logic 1, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 1, and the fourth digital signal buffer BUF4 maintains the output logic 1. At this time, the flip point reference voltage will be triggered to shift down to the first reference voltage. When the falling edge crosses the first reference voltage, the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 0. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 0. The output of the three-input NOR gate NOR3 is logic 1. The output of the three-input AND gate AND3 is logic 0. The output of the third inverter INV3 is logic 0. The output of the fourth inverter INV4 is logic 1. The second transmission gate is closed, and the first transmission gate is opened, transmitting the logic 0 output of the first digital signal buffer BUF1 to the signal latch. The fourth digital signal buffer BUF4 quickly flips from logic 1 to output logic 0.

[0014] Specifically, the first signal transmission gate and the second signal transmission gate are CMOS transmission gates.

[0015] Specifically, the first reference voltage is VPP / 4; the second reference voltage is VPP / 2; and the third reference voltage is 3VPP / 4.

[0016] Specifically, the reference generation circuit is composed of a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4 connected in series to divide the voltage. One end of the first resistor R1 is connected to the second resistor R2, and the other end is connected to ground. One end of the second resistor R2 is connected to the third resistor R3, and the other end is connected to the first resistor R1. One end of the third resistor R3 is connected to the fourth resistor R4, and the other end is connected to the second resistor R2. One end of the fourth resistor R4 is connected to the input reference voltage, and the other end is connected to the third resistor R3. The connection point of the second resistor R2 and the first resistor R1 serves as the first voltage divider node, outputting the first reference voltage. The connection point of the third resistor R3 and the second resistor R2 serves as the second voltage divider node, outputting the second reference voltage. The connection point of the fourth resistor R4 and the third resistor R3 serves as the third voltage divider node, outputting the third reference voltage.

[0017] The present invention provides a noise-resistant sine wave clock signal to square wave signal conversion circuit that improves the anti-interference capability of the clock input path by using a combination of multiple flip points for judgment. During the rising edge phase of the sine wave clock signal from 0 to VPP, the initial toggle point is set to VPP / 4. When the rising edge crosses VPP / 4, it triggers the toggle point to move up to the next toggle reference voltage VPP / 2, without immediately causing the output to toggle to a logic high level. When the rising edge crosses VPP / 2, it triggers the toggle point to move up to the next toggle reference voltage 3VPP / 4 again, until the rising edge crosses 3VPP / 4, at which point the output finally quickly toggle to a logic high level. During the falling edge phase of the sine wave from VPP to 0, the initial switching point remains at 3VPP / 4. When the falling edge crosses 3VPP / 4 again, it will trigger the switching point to move down to the next switching reference voltage VPP / 2, without immediately causing the output to switch to a logic low level. When the falling edge crosses VPP / 2, it will trigger the switching point to move down to the next switching reference voltage VPP / 4 again, until the falling edge crosses VPP / 4, and the output will finally quickly switch to a logic low level. When the rising edge of the sine wave clock signal crosses a flip point during its rise, if glitches or jitters occur at the edge of the sine wave at this time, as long as the amplitude of the jitter does not reach the final flip point voltage, or the amplitude of the jitter voltage cannot be maintained until the last flip point to produce a logic flip, the output cannot produce a final logic flip. This greatly improves the ability of the sine wave input clock to resist flip point glitches and pulses, and improves the operational stability of the digital logic system using this circuit. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a prior art sine wave to square wave conversion circuit provided by an embodiment of the present invention; Figure 2 A schematic diagram of a noise-resistant sine wave clock signal to square wave signal conversion circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a noise-resistant sine wave clock signal to square wave signal conversion circuit provided in an embodiment of the present invention. Detailed Implementation

[0020] The invention will be explained in detail through the following embodiments. The purpose of this invention is to protect all technical improvements within its scope. In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0022] Example 1

[0023] refer to Figure 2-3 This embodiment provides a noise-resistant sine wave clock signal to square wave signal conversion circuit, including a reference voltage generation circuit and a sine wave to square wave conversion circuit; The reference voltage generating circuit is used to generate N sets of reference voltages and simultaneously input them into the sine wave to square wave circuit. Where N is a positive integer greater than or equal to 3, the reference voltage is used as the reference voltage for the flip point in the wave-to-square wave circuit; Preferably, in this embodiment, the value of N is 3, but more than 3 can be selected as needed; The reference voltage generating circuit generates three sets of reference voltages, including a first reference voltage, a second reference voltage, and a third reference voltage. The three sets of reference voltages are simultaneously input into the sine wave to square wave circuit as reference voltages for the flip point. The peak-to-peak value of the sine wave clock signal is VPP, which is input to the sine wave to square wave circuit. The first reference voltage is VPP / 4; the second reference voltage is VPP / 2; and the third reference voltage is 3VPP / 4. The reference generation circuit is composed of a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4 connected in series to divide the voltage; the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are the same. One end of the first resistor R1 is connected to the second resistor R2, and the other end is connected to ground; one end of the second resistor R2 is connected to the third resistor R3, and the other end is connected to the first resistor R1; one end of the third resistor R3 is connected to the fourth resistor R4, and the other end is connected to the second resistor R2; one end of the fourth resistor R4 is connected to the input reference voltage, and the other end is connected to the third resistor R3. The connection point between the second resistor R2 and the first resistor R1 serves as the first voltage divider node, outputting the first reference voltage; The connection point of the third resistor R3 and the second resistor R2 serves as the second voltage divider node, outputting the second reference voltage. The connection point of the fourth resistor R4 and the third resistor R3 serves as the third voltage divider node, outputting the third reference voltage. When the input reference voltage is VPP, the voltage divider outputs of the three voltage divider nodes are VPP / 4, VPP / 2, and 3VPP / 4, respectively. The specific voltage value of VPP can be defined according to the amplitude of the sine wave (peak-to-peak value of the sine wave clock signal).

[0024] The sine wave to square wave circuit is used to generate a square wave signal by level flipping the N sets of reference voltages as flip point reference voltages based on the voltage condition of the rising or falling edge of the received sine wave clock signal.

[0025] The sine wave to square wave circuit includes a first comparator COMP1, a second comparator COMP2, a third comparator COMP3, a first digital signal buffer BUF1, a second digital signal buffer BUF2, a third digital signal buffer BUF3, a fourth digital signal buffer BUF4, a first signal transmission gate, a second signal transmission gate, a three-input AND gate AND3, a three-input NOR gate NOR3, a third inverter INV3, a fourth inverter INV4, and a signal latch. The positive input of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 is VP, the negative input is VN, and the output is VO. When the voltage signal at the positive input VP is greater than the voltage signal at the negative input VN, the output VO outputs a logic 1 signal. When the voltage signal at the positive input VP is less than the voltage signal at the negative input VN, the output VO outputs a logic 0 signal.

[0026] The VN terminal of the first comparator COMP1 is connected to the first reference voltage, the VP terminal is connected to the sine wave clock signal, and the VO terminal is connected to the input terminal of the first digital signal buffer BUF1. The VN terminal of the second comparator COMP2 is connected to the second reference voltage, the VP terminal is connected to the sine wave clock signal, and the VO terminal is connected to the input terminal of the second digital signal buffer BUF2. The VN terminal of the third comparator COMP3 is connected to the third reference voltage, the VP terminal is connected to the sine wave clock signal, and the VO terminal is connected to the input terminal of the third digital signal buffer BUF3. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are respectively connected to the inputs of the three-input AND gate AND3 and the three-input NOR gate NOR3. A three-input AND gate (AND3) includes three input terminals and one output terminal; the three input terminals include a first input terminal, a second input terminal, and a third input terminal. Specifically, the output of the first digital signal buffer BUF1 is connected to the first input of the three-input AND gate AND3; the output of the second digital signal buffer BUF2 is connected to the second input of the three-input AND gate AND3; and the output of the third digital signal buffer BUF3 is connected to the third input of the three-input AND gate AND3. The three-input NOR3 gate includes three inputs and one output; the three inputs are the first input, the second input, and the third input. Specifically, the output of the first digital signal buffer BUF1 is connected to the first input of the three-input NOR gate NOR3; the output of the second digital signal buffer BUF2 is connected to the second input of the three-input NOR gate NOR3; and the output of the third digital signal buffer BUF3 is connected to the third input of the three-input NOR gate NOR3. The first signal transmission gate and the second signal transmission gate are CMOS transmission gates; The CMOS transmission gate includes an input terminal, an output terminal, a control terminal, and an inverting control terminal; A CMOS transmission gate is a controllable switching circuit that can transmit both digital and analog signals. A CMOS transmission gate consists of a PMOS transistor and an NMOS transistor connected in parallel.

[0027] The source of the NMOS transistor MN is connected to the source of the PMOS transistor MP and serves as the input terminal of the CMOS transmission gate; the drain of the NMOS transistor MN is connected to the drain of the PMOS transistor MP and serves as the output terminal of the CMOS transmission gate. The first signal transmission gate is composed of a first NMOS transistor NM1 and a first PMOS transistor PM1 connected in parallel; The source of the first NMOS transistor NM1 is connected to the source of the first PMOS transistor PM1 and then connected to the input terminal of the first signal transmission gate and the output terminal of the first digital signal buffer BUF1. Since the switching control of the CMOS transmission gate requires the PMOS and NMOS logic to be inverted, the output of the three-input NOR gate NOR3 is connected to the gate of the first NMOS transistor NM1, and is also connected to the gate of the first PMOS transistor PM1 through the third inverter INV3; the control signals of the gate of the first NMOS transistor NM1 and the gate of the first PMOS transistor PM1 are opposite; the gate of the first NMOS transistor NM1 serves as the control terminal of the first signal transmission gate, and the gate of the first PMOS transistor PM1 serves as the inverting control terminal of the first signal transmission gate; The second signal transmission gate is composed of a second NMOS transistor NM2 and a second PMOS transistor PM2 connected in parallel; The source of the second NMOS transistor NM2 is connected to the source of the second PMOS transistor PM2, and then serves as the input terminal of the second signal transmission gate, which is connected to the output terminal of the third digital signal buffer BUF3. Similarly, since the PMOS and NMOS logic in the switching control of the CMOS transmission gate needs to be inverted, the output of the three-input AND gate AND3 is connected to the gate of the second NMOS transistor NM2, and also connected to the gate of the second PMOS transistor PM12 through the fourth inverter INV4; the control signals of the gate of the second NMOS transistor NM2 and the gate of the second PMOS transistor PM2 are opposite; the gate of the second NMOS transistor NM2 serves as the control terminal of the second signal transmission gate, and the gate of the second PMOS transistor PM2 serves as the inverting control terminal of the second signal transmission gate; The output terminals of the first and second signal transmission gates are connected to the signal latch and then pass through the fourth digital signal buffer BUF4 to output a square wave signal. The signal latch is composed of a first inverter INV1 and a second inverter INV2; the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 to form the input terminal of the signal latch; the input terminal of the first inverter INV1 is connected to the output terminal of the second inverter INV2 to form the output terminal of the signal latch. The input terminal of the signal latch is connected to the output terminal of the first signal transmission gate and the output terminal of the second signal transmission gate, and the output terminal is connected to the input terminal of the fourth digital signal buffer BUF4; the output terminal of the fourth digital signal buffer BUF4 outputs a square wave signal. During initialization, the reference voltage for the flip point is the first reference voltage (VPP / 4). When the sine wave clock signal voltage rises from 0 to the rising edge of the peak-to-peak value VPP of the sine wave clock signal, and when the sine wave clock signal voltage is lower than the current flip point reference voltage (first reference voltage (VPP / 4)), the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 0, the outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 0, the output of the three-input NOR gate NOR3 is logic 1, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 0, the output of the fourth inverter INV4 is logic 1, the second transmission gate is closed, the first transmission gate is opened, and the logic 0 output of the first digital signal buffer BUF1 is transmitted to the signal latch, and the fourth digital signal buffer BUF4 finally outputs logic 0; When the rising edge of the sine wave clock signal crosses the current flip point reference voltage (first reference voltage (VPP / 4)), the output of the first comparator COMP1 is logic 1, the outputs of the second comparator COMP2 and the third comparator COMP3 are logic 0, the output of the first digital signal buffer BUF1 is logic 1, the outputs of the second digital signal buffer BUF2 and the third digital signal buffer BUF3 are logic 0, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 0, and the fourth digital signal buffer BUF4 maintains the output logic 0. At this time, the flip point reference voltage will be triggered to move up to the second reference voltage (VPP / 2). When the rising edge of the sine wave clock signal crosses the current flip point reference voltage (first reference voltage (VPP / 4)), the outputs of the first comparator COMP1 and the second comparator COMP2 are logic 1, the output of the third comparator COMP3 is logic 0, the outputs of the first digital signal buffer BUF1 and the second digital signal buffer BUF2 are logic 1, the output of the third digital signal buffer BUF3 is logic 0, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 0, and the fourth digital signal buffer BUF4 maintains the output logic 0. At this time, the flip point reference voltage will be triggered to move up to the third reference voltage (3VPP / 4). When the rising edge of the sine wave clock signal crosses the current flip point reference voltage (third reference voltage (3VPP / 4)), the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 1s. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 1s. The output of the three-input NOR gate NOR3 is logic 0. The output of the three-input AND gate AND3 is logic 1. The output of the third inverter INV3 is logic 1. The output of the fourth inverter INV4 is logic 0. The first transmission gate is closed, the second transmission gate is opened, and the logic 1 output of the third digital signal buffer BUF3 is transmitted to the signal latch. The fourth digital signal buffer BUF4 quickly flips from logic 0 to output logic 1. After the sine wave clock signal rises to its peak, it begins to enter the falling edge phase, that is, the falling edge phase when the sine wave clock signal voltage drops from its peak value VPP to 0: When the falling edge crosses the current flip point reference voltage (third reference voltage (3VPP / 4)), the output of the third comparator COMP3 is logic 0, the outputs of the first comparator COMP1 and the second comparator COMP2 are logic 1, the output of the third digital signal buffer BUF3 is logic 0, the outputs of the first digital signal buffer BUF1 and the second digital signal buffer BUF2 are logic 1, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 1, and the fourth digital signal buffer BUF4 maintains the output logic 1. At this time, the flip point reference voltage will be triggered to shift down to the second reference voltage (VPP / 2). When the falling edge crosses the current flip point reference voltage (second reference voltage (VPP / 2)), the outputs of the second comparator COMP2 and the third comparator COMP3 are logic 0, the output of the first comparator COMP1 is logic 1, the outputs of the second digital signal buffer BUF2 and the third digital signal buffer BUF3 are logic 0, the output of the first digital signal buffer BUF1 is logic 1, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 1, and the fourth digital signal buffer BUF4 maintains the output logic 1. At this time, the flip point reference voltage will be triggered to shift down to the first reference voltage (VPP / 4). When the falling edge crosses the current flip point reference voltage (first reference voltage (VPP / 4)), the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 0. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 0. The output of the three-input NOR gate NOR3 is logic 1. The output of the three-input AND gate AND3 is logic 0. The output of the third inverter INV3 is logic 0. The output of the fourth inverter INV4 is logic 1. The second transmission gate is closed, and the first transmission gate is opened, transmitting the logic 0 output of the first digital signal buffer BUF1 to the signal latch. The fourth digital signal buffer BUF4 quickly flips from logic 1 to output logic 0.

[0028] This completes one full cycle of sine wave to square wave conversion.

[0029] This embodiment provides a noise-resistant sine wave clock signal to square wave signal conversion circuit that uses a combination of multiple flip points to improve the anti-interference capability of the clock input path. Unlike the single flip point in the traditional solution, there are three flip points in this embodiment; During the rising edge phase of the sine wave clock signal from 0 to VPP, the initial toggle point is set to VPP / 4. When the rising edge crosses VPP / 4, it triggers the toggle point to move up to the next toggle reference voltage VPP / 2, without immediately causing the output to toggle to a logic high level. When the rising edge crosses VPP / 2, it triggers the toggle point to move up to the next toggle reference voltage 3VPP / 4 again, until the rising edge crosses 3VPP / 4, at which point the output toggle to a logic high level.

[0030] During the falling edge phase of the sine wave as it drops from VPP to 0, the initial switching point remains at 3VPP / 4. When the falling edge crosses 3VPP / 4 again, it triggers the switching point to move down to the next switching reference voltage VPP / 2, without immediately causing the output to switch to a logic low level. When the falling edge crosses VPP / 2, it triggers the switching point to move down to the next switching reference voltage VPP / 4 again, until the falling edge crosses VPP / 4, at which point the output switches to a logic high level.

[0031] When the rising edge of the sine wave clock signal crosses a flip point during its rise, if glitches or jitters occur at the edge of the sine wave at this time, as long as the amplitude of the jitter does not reach the final flip point voltage, or the amplitude of the jitter voltage cannot be maintained until the last flip point to produce a logic flip, the output cannot produce a final logic flip. This greatly improves the ability of the sine wave input clock to resist flip point glitches and pulses, and improves the operational stability of the digital logic system using this circuit.

[0032] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 A process, multiple processes, and / or boxes Figure 1 Devices that specify the functions in one or more boxes.

[0033] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including an instruction device, which is implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0034] These computer program instructions can also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0035] The parts of this invention not described in detail are prior art. It will be apparent to those skilled in the art that this invention is not limited to the details of the above exemplary embodiments, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and are intended to encompass all changes falling within the meaning and scope of equivalents within this invention.

Claims

1. A noise-resistant sine wave clock signal to square wave signal conversion circuit, characterized in that, Includes a reference voltage generation circuit and a sine wave to square wave conversion circuit; The reference voltage generating circuit is used to generate three sets of reference voltages that are simultaneously input into the sine wave to square wave circuit; the three sets of reference voltages include a first reference voltage, a second reference voltage, and a third reference voltage. The sine wave to square wave circuit is used to generate a square wave signal by level flipping the three sets of reference voltages as flip point reference voltages based on the voltage condition of the rising or falling edge of the received sine wave clock signal. The sine wave to square wave circuit includes a first comparator COMP1, a second comparator COMP2, a third comparator COMP3, a first digital signal buffer BUF1, a second digital signal buffer BUF2, a third digital signal buffer BUF3, a fourth digital signal buffer BUF4, a first signal transmission gate, a second signal transmission gate, a three-input AND gate AND3, a three-input NOR gate NOR3, a third inverter INV3, a fourth inverter INV4, and a signal latch. The first comparator COMP1 has its VN terminal connected to a first reference voltage, its VP terminal connected to the sine wave clock signal, and its VO terminal connected to the input terminal of the first digital signal buffer BUF1; the second comparator COMP2 has its VN terminal connected to a second reference voltage, its VP terminal connected to the sine wave clock signal, and its VO terminal connected to the input terminal of the second digital signal buffer BUF2; the third comparator COMP3 has its VN terminal connected to a third reference voltage, its VP terminal connected to the sine wave clock signal, and its VO terminal connected to the input terminal of the third digital signal buffer BUF3. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are connected to the input of the three-input AND gate AND3; The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are also connected to the input of the three-input NOR gate NOR3. The output of the three-input NOR3 is connected to the control terminal of the first signal transmission gate, and is also connected to the inverting control terminal of the first signal transmission gate through the third inverter INV3. The output of the three-input AND gate AND3 is connected to the control terminal of the second signal transmission gate, and is also connected to the inverting control terminal of the second signal transmission gate through the fourth inverter INV4; The output terminals of the first and second signal transmission gates are connected through the signal latch and the fourth digital signal buffer BUF4 to output square wave signals.

2. The circuit according to claim 1, characterized in that, When the sine wave clock signal voltage rises from 0 to the rising edge of the peak-to-peak value VPP of the sine wave clock signal, the initial flip point reference voltage is set to the first reference voltage. When the rising edge crosses the first reference voltage, it will trigger the flip point reference voltage to move up to the second reference voltage. When the rising edge crosses the second reference voltage, it will trigger the flip point reference voltage to move up to the third reference voltage again, until the rising edge crosses the third reference voltage, and the output flips to a logic high level.

3. The circuit according to claim 2, characterized in that, When the sine wave clock signal voltage drops from the peak-to-peak value VPP of the sine wave clock signal to the falling edge stage of 0, when the falling edge crosses the third reference voltage, it will trigger the flip point reference voltage to shift down to the second reference voltage. When the falling edge crosses the second reference voltage, it will trigger the flip point reference voltage to shift down to the first reference voltage again, until the falling edge crosses the first reference voltage, and the output flips to a logic low level.

4. The circuit according to claim 1, characterized in that, The signal latch is composed of a first inverter INV1 and a second inverter INV2; the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 to form the input terminal of the signal latch; the input terminal of the first inverter INV1 is connected to the output terminal of the second inverter INV2 to form the output terminal of the signal latch.

5. The circuit according to claim 4, characterized in that, The input terminal of the signal latch is connected to the output terminal of the first signal transmission gate and the output terminal of the second signal transmission gate, and the output terminal is connected to the input terminal of the fourth digital signal buffer BUF4; the output terminal of the fourth digital signal buffer BUF4 outputs a square wave signal.

6. The circuit according to claim 5, characterized in that, During initialization, the reference voltage for the flip point is the first reference voltage; When the voltage of the sine wave clock signal rises from 0 to the rising edge of the peak-to-peak value VPP of the sine wave clock signal: When the sine wave clock signal voltage is lower than the first reference voltage, the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 0, the outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 0, the output of the three-input NOR gate NOR3 is logic 1, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 0, the output of the fourth inverter INV4 is logic 1, the second transmission gate is closed, the first transmission gate is open, and the logic 0 output of the first digital signal buffer BUF1 is transmitted to the signal latch. The fourth digital signal buffer BUF4 finally outputs logic 0. When the rising edge of the sine wave clock signal crosses the first reference voltage, the output of the first comparator COMP1 is logic 1, the outputs of the second comparator COMP2 and the third comparator COMP3 are logic 0, the output of the first digital signal buffer BUF1 is logic 1, the outputs of the second digital signal buffer BUF2 and the third digital signal buffer BUF3 are logic 0, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 0, and the fourth digital signal buffer BUF4 maintains the output logic 0. At this time, the flip point reference voltage will be triggered to move up to the second reference voltage. When the rising edge of the sine wave clock signal crosses the second reference voltage, the outputs of the first comparator COMP1 and the second comparator COMP2 are logic 1, the output of the third comparator COMP3 is logic 0, the outputs of the first digital signal buffer BUF1 and the second digital signal buffer BUF2 are logic 1, the output of the third digital signal buffer BUF3 is logic 0, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 0, and the fourth digital signal buffer BUF4 maintains the output logic 0. At this time, the flip point reference voltage will be triggered to move up to the third reference voltage. When the rising edge of the sine wave clock signal crosses the third reference voltage, the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 1s. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 1s. The output of the three-input NOR gate NOR3 is logic 0. The output of the three-input AND gate AND3 is logic 1. The output of the third inverter INV3 is logic 1. The output of the fourth inverter INV4 is logic 0. The first transmission gate is closed, and the second transmission gate is opened, transmitting the logic 1 output of the third digital signal buffer BUF3 to the signal latch. The fourth digital signal buffer BUF4 quickly flips from logic 0 to output logic 1.

7. The circuit according to claim 6, characterized in that, During the falling edge phase when the sine wave clock signal voltage drops from the peak-to-peak value VPP of the sine wave clock signal to 0: When the falling edge crosses the third reference voltage, the output of the third comparator COMP3 is logic 0, the outputs of the first comparator COMP1 and the second comparator COMP2 are logic 1, the output of the third digital signal buffer BUF3 is logic 0, the outputs of the first digital signal buffer BUF1 and the second digital signal buffer BUF2 are logic 1, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 1, and the fourth digital signal buffer BUF4 maintains the output logic 1. At this time, the flip point reference voltage will be triggered to shift down to the second reference voltage. When the falling edge crosses the second reference voltage, the outputs of the second comparator COMP2 and the third comparator COMP3 are logic 0, the output of the first comparator COMP1 is logic 1, the outputs of the second digital signal buffer BUF2 and the third digital signal buffer BUF3 are logic 0, the output of the first digital signal buffer BUF1 is logic 1, the output of the three-input NOR gate NOR3 is logic 0, the output of the three-input AND gate AND3 is logic 0, the output of the third inverter INV3 is logic 1, the output of the fourth inverter INV4 is logic 1, the first transmission gate is closed, the second transmission gate is closed, the signal latch maintains the previously latched logic 1, and the fourth digital signal buffer BUF4 maintains the output logic 1. At this time, the flip point reference voltage will be triggered to shift down to the first reference voltage. When the falling edge crosses the first reference voltage, the outputs of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 are all logic 0. The outputs of the first digital signal buffer BUF1, the second digital signal buffer BUF2, and the third digital signal buffer BUF3 are all logic 0. The output of the three-input NOR gate NOR3 is logic 1. The output of the three-input AND gate AND3 is logic 0. The output of the third inverter INV3 is logic 0. The output of the fourth inverter INV4 is logic 1. The second transmission gate is closed, and the first transmission gate is opened, transmitting the logic 0 output of the first digital signal buffer BUF1 to the signal latch. The fourth digital signal buffer BUF4 quickly flips from logic 1 to output logic 0.

8. The circuit according to claim 1, characterized in that, The first reference voltage is VPP / 4; the second reference voltage is VPP / 2; the third reference voltage is 3VPP / 4; and VPP is the peak-to-peak value of the sine wave clock signal.

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