A digital input circuit and method

Abstract

The application discloses a kind of digital quantity input circuit and method, including input conditioning circuit and logic control circuit, input conditioning circuit includes the digital quantity input interface with signal input end and common end and voltage division circuit;Voltage division circuit carries out voltage division sampling to input signal between signal input end and common end, respectively in first, second sampling point generates first, second sampling signal;Logic control circuit carries out exclusive-or logic operation to two sampling signals, and outputs the logic level of characterizing input state;The voltage division circuit is configured as: when there is no signal input, the logic state of two sampling signals is opposite;When there is signal input, the logic state of two sampling signals is same.The application reduces the hardware cost and volume of multi-channel application, and can be compatible with different polarity input signals under the same hardware interface, greatly improves the versatility and long-term working stability of digital logic control system.

Description

Technical Field

[0001] This invention belongs to the technical field of digital logic circuits, specifically relating to a digital input circuit and method. Background Technology

[0002] In various digital logic control systems (such as programmable logic controllers PLCs), digital input is one of the essential basic functions of a PLC, mainly used to collect status signals from various sensors and switches in the industrial field.

[0003] In existing technologies, optocouplers or capacitive isolation integrated circuits based on OOK (On-Off Keying) modulation are typically used to design digital input circuits. However, as industrial automation applications become increasingly sophisticated and complex, these traditional solutions are gradually revealing the following significant drawbacks: (1) When the number of digital input channels required by the industrial control system is large, the use of independent optocouplers or isolation chips will lead to increased costs and the chip itself has a large package size, which is not conducive to the design of high-density multi-channel I / O boards.

[0004] (2) The photoelectric conversion performance of optocouplers is highly susceptible to drift due to ambient temperature. In harsh, wide-temperature industrial applications, this temperature sensitivity greatly increases the difficulty of designing and compensating for hardware circuits.

[0005] (3) The performance consistency of domestic optocouplers is difficult to guarantee, and the internal LED light-emitting diodes are prone to light decay after long-term operation, resulting in a decrease in signal transmission ratio, which seriously affects the long-term reliability and service life of the system.

[0006] (4) Capacitor isolation technology using OOK modulation is relatively weak in terms of noise immunity. Especially when facing input waveforms with slow-changing edge characteristics commonly found in industrial settings, the threshold decision of existing isolation schemes is easily interfered with, resulting in signal jitter and logic mis-triggering problems on the output side.

[0007] Therefore, there is an urgent need in this field for a new digital input circuit architecture that can break free from dependence on optocouplers or isolation chips, is low in cost, has stable performance, and is compatible with different field wiring methods. Summary of the Invention

[0008] To address the shortcomings of existing digital input circuits that rely on optocouplers or capacitor isolation chips, such as high cost, large size, poor wide-temperature performance, and reliability issues caused by LED light decay, this invention provides a digital input circuit and method that aims to achieve low-cost, high-reliability digital input compatible with both NPN and PNP connections through a simplified RC diode architecture and logic operations.

[0009] The present invention adopts the following technical solution: According to a first aspect of this application, a digital input circuit is provided, comprising: An input conditioning circuit includes a digital input interface and a voltage divider circuit. The digital input interface includes a signal input terminal and a common terminal. The voltage divider circuit is connected to the digital input interface and configured to perform voltage division sampling on the input signal between the signal input terminal and the common terminal to generate a first sampled signal at a first sampling point and a second sampled signal at a second sampling point. A logic control circuit, connected to the first sampling point and the second sampling point, is configured to perform an XOR logic operation on the first sampling signal and the second sampling signal, and output a logic level representing the input state based on the operation result; The voltage divider circuit is configured to: when there is no signal input at the digital input interface, reverse the logic state of the first sampled signal and the second sampled signal; and when there is a signal input at the digital input interface, make the logic state of the first sampled signal and the second sampled signal the same.

[0010] The above solution is based on a dual-channel voltage divider sampling design with a common terminal linkage. The circuit of this invention can automatically accommodate sensor signals of different polarities from external inputs. Regardless of whether the signal input terminal presents a positive or negative voltage relative to the common terminal, the voltage divider circuit can determine the state by whether the logic states of the first and second sampling signals are "the same" or "opposite". This allows the input interface to seamlessly adapt to different types of external wiring logic, greatly reducing the complexity of field deployment and wiring.

[0011] Preferably, the voltage divider circuit includes a first voltage divider branch and a second voltage divider branch; The first voltage divider branch includes a first resistor and a third resistor connected in series, and the first sampling point is located between the first resistor and the third resistor; The second voltage divider branch includes a second resistor and a fourth resistor connected in series, and the second sampling point is located between the second resistor and the fourth resistor.

[0012] The above scheme uses the series resistor network in the first and second voltage divider branches for direct sampling, so that the first sampling point and the second sampling point have a stable voltage ratio relationship under different input voltages. This enhances the circuit's anti-interference ability against field voltage fluctuations and avoids logic misjudgment caused by noise affecting single-point sampling.

[0013] Preferably, the input conditioning circuit further includes a clamping circuit connected to the first sampling point and the second sampling point, configured to limit the voltage amplitude of the first sampling signal and the second sampling signal within the input voltage threshold range of the logic control circuit.

[0014] More preferably, the circuit is configured with a first potential terminal and a second potential terminal, and the clamping circuit includes a first clamping unit corresponding to the first sampling point and a second clamping unit corresponding to the second sampling point; both the first clamping unit and the second clamping unit include a pull-up diode and a pull-down diode; wherein, the cathode of the pull-up diode is connected to the first potential terminal and the anode is connected to the corresponding sampling point; the cathode of the pull-down diode is connected to the corresponding sampling point and the anode is connected to the second potential terminal.

[0015] The above scheme limits the voltage amplitude of the sampled signal to the voltage range formed by the first and second potential terminals by setting clamping units composed of pull-up and pull-down diodes at the first and second sampling points respectively. When an abnormally high or low voltage is input externally, the diodes conduct to limit the node voltage, thereby preventing overvoltage or undervoltage from damaging the subsequent logic control circuit.

[0016] Preferably, the input conditioning circuit further includes a bidirectional TVS diode connected to the digital input interface. When a lightning surge or transient overvoltage caused by inductive load switching occurs at the signal input terminal, the TVS diode can instantly conduct and absorb the transient overcurrent, clamping the input voltage within a safe range, effectively improving the transient overvoltage protection performance of the circuit.

[0017] Preferably, the input conditioning circuit further includes a first filtering unit and a second filtering unit; the first filtering unit is connected between the first sampling point and the reference potential terminal, and the second filtering unit is connected between the second sampling point and the reference potential terminal. By setting the first / second filtering unit connected between the first / second sampling point and the reference potential terminal, the internal capacitance characteristics can filter out high-frequency electromagnetic noise mixed in the input signal; at the same time, by configuring the RC parameters of the filtering unit, the response time of the circuit to changes in the state of the input signal can be adjusted, reducing the output jitter caused by the gradual change of the input signal.

[0018] Preferably, the input conditioning circuit further includes an input matching resistor connected between the signal input terminal and the reference potential terminal. This resistor is used to set the static input impedance of the digital input interface. This resistor provides a discharge path for weak leakage current or induced charge, reducing the risk of false logic triggering when the interface is floating or without signal input.

[0019] Preferably, the circuit also includes an isolated power supply, which is electrically isolated from the external signal power supply connected to the digital input interface; the voltage divider circuit generates the logic state through a reference provided by the isolated power supply. Using an isolated power supply that is electrically isolated from the external signal power supply separates the internal reference ground of the circuit from the external industrial site's electrical ground, cutting off the common-mode noise conduction loop and improving the circuit's immunity to crosstalk in complex electromagnetic environments.

[0020] Preferably, the logic control circuit is any one of a logic gate chip, a microcontroller, or a field-programmable gate array.

[0021] According to a second aspect of this application, a digital input method is proposed, employing the aforementioned digital input circuit, comprising: The input signal between the signal input terminal and the common terminal is sampled by voltage divider circuit in input conditioning circuit, and a first sampling signal is generated at the first sampling point and a second sampling signal is generated at the second sampling point. Perform an XOR operation on the first sampled signal and the second sampled signal; The input state is determined by the result of the XOR logic operation; when the result is a logic high level, it is determined that there is a signal input; when the result is a logic low level, it is determined that there is no signal input.

[0022] The above scheme directly maps the state of physical signals to logic levels representing the input state based on the XOR logic operation. This architecture eliminates the reliance on opto-isolation components or OOK modulation isolation chips in traditional schemes, which not only significantly reduces the material cost under high-density channels, but also solves the problems of temperature drift of optocouplers and long-term light decay of LEDs in wide temperature environments, greatly improving the long-term stability of the circuit in harsh industrial environments.

[0023] Compared with the prior art, the beneficial results of the present invention are as follows: (1) By using a hardware-software co-design of basic resistor-capacitor networks and logic operations, the traditional technical path of relying on optocouplers or dedicated isolation chips for digital input is broken. This architecture not only significantly reduces the overall material cost under high-density I / O channels, but also fundamentally eliminates the risk of temperature drift and aging failure of optoelectronic devices in a wide temperature environment, giving the product extremely high stability throughout its entire life cycle.

[0024] (2) By utilizing dual-channel voltage sampling and XOR logic mapping linked to the common terminal, full compatibility of NPN and PNP sensor signals is achieved through a single physical interface without adding additional hardware switches or switching circuits. This feature greatly simplifies the wiring logic in industrial settings and lowers the threshold for users' construction and maintenance.

[0025] (3) This solution cleverly integrates a multi-level protection mechanism, including bidirectional voltage clamping, transient overvoltage absorption, high-frequency anti-interference filtering, and low-level electrical isolation, into a minimally simplistic main signal input circuit. This enables the circuit to ensure the safety and accurate sampling of the logic control core even when facing harsh industrial electromagnetic environments such as lightning surges, electrostatic discharge, and complex common-mode interference. Attached Figure Description

[0026] The accompanying drawings provide further illustration of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Other features, objects, and advantages of this application will become more apparent from reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of a digital input circuit structure using an optocoupler in the prior art; Figure 2 This is a schematic diagram of a digital input circuit structure using a capacitor isolation chip in the prior art. Figure 3 This is a block diagram of the overall architecture of a digital input circuit according to a specific embodiment of the present invention; Figure 4 This is a circuit diagram of a digital input circuit according to a specific embodiment of the present invention.

[0027] The numbers in the diagram have the following meanings: 01 - Input conditioning circuit; 02 - Logic control circuit; 03 - Isolation power supply; XIN - Signal input terminal; S / S - Common terminal; T1 - Bidirectional TVS diode; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Input matching resistor; C1 - First capacitor; C2 - Second capacitor; XP - First sampling point; XN - Second sampling point; First pull-up diode D1; Second pull-up diode D2; First pull-down diode D3; Second pull-down diode D4. Detailed Implementation

[0028] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0029] In the description of this invention, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed", "equipped", "sleeved / connected", "connected", etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0031] To facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0032] See Figure 1 and Figure 2 These are schematic diagrams of digital input circuit structures using optocouplers and capacitor isolation chips, respectively, in existing technologies. Figure 1 The diagram shows a digital input circuit using optocouplers in the prior art. When this circuit is applied to applications with many input channels, a large number of optocouplers are required, inevitably increasing the PLC's circuit board area. Furthermore, since optocouplers generally have low conduction speeds, high-speed optocouplers are needed for higher-speed applications, but high-speed optocouplers are more expensive. Therefore, digital input circuits using optocouplers suffer from high cost and increased PLC size. Figure 2 The diagram shows a digital input circuit designed using a capacitor-isolated chip in the prior art. Although this circuit meets the requirements in terms of conduction speed and package size, the unit procurement cost of the capacitor-isolated chip itself is high, and its application in multi-channel systems will also lead to a sharp increase in the overall cost of the PLC. To overcome the above-mentioned inherent defects, this invention proposes a novel digital input architecture that does not rely on opto-isolated components.

[0033] See Figure 3 This is a block diagram of the overall architecture of a digital input circuit provided in an embodiment of the present invention. The digital input circuit mainly includes: an input conditioning circuit 01, a logic control circuit 02, and an isolation power supply 03.

[0034] In a specific embodiment, the input conditioning circuit 01 is configured to receive external physical signals and perform transient protection, impedance matching, voltage division, and signal filtering. It converts the external high-voltage digital signal into two specific sampling levels through an internal RC network.

[0035] In a specific embodiment, the logic control circuit 02 is connected to the output of the input conditioning circuit 01. It is configured to receive two sampled levels and perform real-time calculations on the sampled signals using a built-in XOR logic algorithm, thereby outputting the input logic. Optionally, the logic control circuit 02 can be a simple XOR logic circuit or an XOR logic implemented using an MCU or FPGA.

[0036] In a specific embodiment, the isolation power supply 03 is configured to generate an internal power supply potential and an internal reference potential terminal GND, and to achieve electrical isolation between the internal reference potential terminal and the external signal ground.

[0037] See Figure 4 The input conditioning circuit 01 specifically includes a digital input interface, a bidirectional TVS (Transient Voltage Suppressor) transistor T1, an input matching resistor R5, a voltage divider circuit, a clamping circuit, and a filter circuit. The digital input interface includes a signal input terminal XIN and a common terminal S / S. The common terminal S / S is a shared terminal block; when connected to the positive terminal of an external power supply, the circuit adapts to an NPN connection; when connected to the negative terminal of an external power supply, the circuit adapts to a PNP connection. The bidirectional TVS transistor T1 is connected to the signal input terminal XIN to absorb transient overvoltages. The input matching resistor R5 is connected between the signal input terminal XIN and the internal reference potential terminal GND to adjust the static input impedance of the interface and discharge induced charges.

[0038] In a specific embodiment, the voltage divider circuit includes a first voltage divider branch and a second voltage divider branch. The first voltage divider branch consists of a first resistor R1 and a third resistor R3 connected in series, with their common connection point leading to a first sampling point XP; the second voltage divider branch consists of a second resistor R2 and a fourth resistor R4 connected in series, with their common connection point leading to a second sampling point XN. The clamping circuit includes a first clamping unit composed of a first pull-up diode D1 and a first pull-down diode D3, and a second clamping unit composed of a second pull-up diode D2 and a second pull-down diode D4. The cathodes of the first pull-up diode D1 and the second pull-up diode D2 are connected to a first potential terminal, and the anodes are connected to the corresponding sampling points. In this embodiment, the first potential terminal refers to the 3.3V power supply terminal; the cathodes of the first pull-down diode D3 and the second pull-down diode D4 are connected to the corresponding sampling points, and the anodes are connected to a second potential terminal. In this embodiment, the second potential terminal refers to the ground wire. The filtering circuit includes a first capacitor C1 and a second capacitor C2; wherein, the first capacitor C1 is connected between the first sampling point XP and the internal reference potential terminal GND, and the second capacitor C2 is connected between the second sampling point XN and the internal reference potential terminal GND.

[0039] In a specific embodiment, the bidirectional TVS diode T1 is of model SMF33CA, and the first pull-up diode D1, the second pull-up diode D2, the first pull-down diode D3, and the second pull-down diode D4 are all of model BAV99.

[0040] The following describes in detail the complete dynamic working process of the digital input signal in the embodiments of the present invention: When the circuit is in a static hold state with no signal input, the bias effect generated by the 3.3V power supply and GND in the internal resistor voltage divider network forces the first sampling point XP and the second sampling point XN to opposite logic levels. Specifically, the first sampling point XP is biased to a logic low level "0", while the second sampling point XN is biased to a logic high level "1". At this time, the logic control circuit 02 performs an XNOR operation on these two sets of signals, and the input logic is judged to be "0".

[0041] In NPN access mode, the common terminal S / S is connected to the positive terminal of an external 24V power supply. When the signal input terminal XIN is pulled down to ground potential (0V) by an external sensor, the current distribution in the voltage divider branch changes, causing the potentials of the first sampling point XP and the second sampling point XN to be pulled down synchronously. During this process, the potential drop of the first sampling point XP triggers the first pull-down diode D3 of the first clamping unit to conduct in time, limiting the voltage of XP to near the reference potential terminal GND, while the second sampling point XN safely returns to zero with the voltage divider. At the same time, the first capacitor C1 and the second capacitor C2 filter out high-frequency glitches and smooth the voltage curve. Finally, both the first sampling point XP and the second sampling point XN present a logic low level "0", and the logic control circuit 02 performs an XOR operation of "0" and "0", and the input logic is judged as "1".

[0042] In PNP access mode, the common terminal S / S is connected to the external ground potential. When the signal input terminal XIN is pulled high to the 24V power supply potential by the external sensor, the voltage divider circuit proportionally reduces the high voltage signal, causing the potentials of the first sampling point XP and the second sampling point XN to rise synchronously. During this process, the high voltage division of the second sampling point XN triggers the second pull-up diode D2 of the second clamping unit to quickly conduct, clamping the voltage of XN near the internal power supply voltage to protect the logic gate from damage. Meanwhile, the first sampling point XP remains safely within the high-level threshold due to the voltage division. The first capacitor C1 and the second capacitor C2 also play a debouncing role. Finally, both the first sampling point XP and the second sampling point XN present a logic high level "1". The logic control circuit 02 performs an XOR operation of "1" and "1", and the input logic is judged to be at the "1" level.

[0043] The following is a specific embodiment where the resistance values ​​of the first resistor R1 and the second resistor R2 are both 24KΩ, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are both 3.3KΩ, and the resistance value of the input matching resistor R5 is 4.7KΩ. Combined with a 3.3V internal power supply, the dynamic voltage changes and logic states of the first sampling point XP and the second sampling point XN in this embodiment are deduced: In the absence of signal input: When there is no signal input between the signal input terminal XIN and the common terminal S / S, only the internal 3.3V power supply operates. At this time, the voltage at the first sampling point XP can be calculated using circuit equivalents. ; Since 0.42V is below the high-level threshold of the logic gate, XP displays a low level "0".

[0044] The voltage at the second sampling point XN can be obtained through circuit equivalent calculation: ; Since 2.95V reaches the high-level threshold of the logic gate, XN presents a high level "1".

[0045] At this time, logic control circuit 02 performs an XOR logic operation on XP ("0") and XN ("1"), and the output result is "0" level, which the system determines is no signal input.

[0046] When inputting a standard 24V signal in NPN access mode: That is, the common terminal S / S is connected to the field side 24V+, and the signal input terminal XIN is connected to the field side 24V- (0V). The first resistor R1 and the third resistor R3 divide the voltage to 24V. Due to the presence of the isolation power supply, the 0V potential point (GND) of the internal VD3.3V is equivalent to the positive terminal of the field side 24V+ power supply. At this time, the signal input terminal XIN is -24V relative to the reference ground of the internal VD3.3V. The theoretical voltage division of the first sampling point XP is: ; However, due to the clamping effect of the first pull-down diode D3 in the first clamping unit, the final voltage at point XP is limited to near the forward voltage drop of the diode. This is equivalent to a low level "0".

[0047] The voltage at the second sampling point XN can be calculated by dividing the voltage using the second resistor R2 and the fourth resistor R4: ; Therefore, point XN is at a low level "0".

[0048] At this time, logic control circuit 02 performs an XOR logic operation on XP ("0") and XN ("0"), and the output result flips to the "1" level, which the system determines is a signal input.

[0049] When inputting a standard 24V signal in PNP access mode: That is, the common terminal S / S is connected to the field side GND (0V), and the signal input terminal XIN is connected to the field side 24V+. At this time, the voltage across the first resistor R1 and the third resistor R3 is 24V.

[0050] The voltage at the first sampling point XP can be calculated by voltage division using the first resistor R1 and the third resistor R3: ; Therefore, point XP is at a high level "1".

[0051] The voltage at the second sampling point XN can be calculated by the voltage division between the second resistor R2 and the fourth resistor R4: ; However, due to the clamping effect of the second pull-up diode D2 in the second clamping unit, the portion exceeding the internal power supply voltage is discharged, and the final voltage at point XN is limited to 3.3V plus the forward voltage drop of the diode, i.e. , which is a high level "1".

[0052] At this time, logic control circuit 02 performs an XOR logic operation on XP ("1") and XN ("1"), and the output result is flipped to "1" level, which the system determines is a signal input.

[0053] The above solution, through the coupling of the dual-point sampling signal generated by the voltage divider circuit and the XOR logic operation, eliminates the need for expensive optocoupler isolators or dedicated isolation chips. This not only significantly reduces material costs but also resolves the reliability risks caused by optocoupler drift due to temperature and LED aging. Thanks to the voltage divider design with common terminal potential linkage, the circuit can automatically adapt to changes in the polarity of the S / S terminals on the field side. Whether an NPN or PNP sensor is connected, accurate identification can be achieved through the level combination of the first / second sampling points, realizing adaptive wiring.

[0054] It should be noted that if the circuit of this application embodiment needs to achieve different circuit input impedances and input thresholds, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the input matching resistor R5 can be simply adjusted.

[0055] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A digital input circuit, characterized in that, include: An input conditioning circuit includes a digital input interface and a voltage divider circuit. The digital input interface includes a signal input terminal and a common terminal. The voltage divider circuit is connected to the digital input interface and is configured to perform voltage division sampling on the input signal between the signal input terminal and the common terminal to generate a first sampling signal at a first sampling point and a second sampling signal at a second sampling point. as well as A logic control circuit, connected to the first sampling point and the second sampling point, is configured to perform an XOR logic operation on the first sampling signal and the second sampling signal, and output a logic level representing the input state based on the operation result; The input conditioning circuit further includes a clamping circuit connected to the first sampling point and the second sampling point, configured to limit the voltage amplitude of the first sampling signal and the second sampling signal within the input voltage threshold range of the logic control circuit; The voltage divider circuit is configured to: when there is no signal input at the digital input interface, reverse the logic state of the first sampled signal and the second sampled signal; and when there is a signal input at the digital input interface, make the logic state of the first sampled signal and the second sampled signal the same.

2. The digital input circuit according to claim 1, characterized in that, The voltage divider circuit includes a first voltage divider branch and a second voltage divider branch; The first voltage divider branch includes a first resistor and a third resistor connected in series, and the first sampling point is located between the first resistor and the third resistor; The second voltage divider branch includes a second resistor and a fourth resistor connected in series, and the second sampling point is located between the second resistor and the fourth resistor.

3. The digital input circuit according to claim 1, characterized in that, The circuit is configured with a first potential terminal and a second potential terminal. The clamping circuit includes a first clamping unit corresponding to the first sampling point and a second clamping unit corresponding to the second sampling point. Both the first clamping unit and the second clamping unit include a pull-up diode and a pull-down diode. The cathode of the pull-up diode is connected to the first potential terminal, and the anode is connected to the corresponding sampling point. The cathode of the pull-down diode is connected to the corresponding sampling point, and the anode is connected to the second potential terminal.

4. The digital input circuit according to claim 1, characterized in that, The input conditioning circuit also includes a bidirectional TVS diode connected to the digital input interface.

5. The digital input circuit according to claim 1, characterized in that, The input conditioning circuit further includes a first filtering unit and a second filtering unit; the first filtering unit is connected between the first sampling point and the reference potential terminal, and the second filtering unit is connected between the second sampling point and the reference potential terminal.

6. The digital input circuit according to claim 1, characterized in that, The input conditioning circuit further includes an input matching resistor, which is connected between the signal input terminal and the reference potential terminal.

7. The digital input circuit according to claim 1, characterized in that, It also includes an isolation power supply, which is electrically isolated from the external signal power supply connected to the digital input interface; the voltage divider circuit generates the logic state through a reference provided by the isolation power supply.

8. The digital input circuit according to claim 1, characterized in that, The logic control circuit can be any one of a logic gate chip, a microcontroller, or a field-programmable gate array.

9. A digital input method, characterized in that, The digital input circuit according to any one of claims 1 to 8 comprises: The input signal between the signal input terminal and the common terminal is sampled by voltage divider circuit in input conditioning circuit, and a first sampling signal is generated at the first sampling point and a second sampling signal is generated at the second sampling point. Perform an XOR operation on the first sampled signal and the second sampled signal; The input state is determined by the result of the XOR logic operation; when the result is a logic high level, it is determined that there is a signal input; when the result is a logic low level, it is determined that there is no signal input.

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