A high-speed low-power comparator circuit for a continuous-time analog-to-digital converter
By using a three-stage cascaded structure and complementary differential inverter input technology, the problems of limited input range, insufficient gain, and high power consumption of traditional comparators are solved, realizing a comparator circuit with wide input range, high gain, and low power consumption, which is suitable for high-performance continuous-time analog-to-digital converters.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU MINGZHANG SEMICON TECH CO LTD
- Filing Date
- 2026-03-24
- Publication Date
- 2026-06-26
AI Technical Summary
Traditional continuous-time analog-to-digital converters (ADCs) suffer from limitations in input signal range, insufficient gain, high power consumption, and bandwidth, making it difficult to meet the high performance and low power consumption requirements of modern portable devices.
The comparator circuit employs a three-stage cascaded structure. The first stage is a rail-to-rail input pre-amplifier stage, the second stage is a gain boost stage, and the third stage is a differential-to-single-ended output stage. By combining complementary differential structure, fully differential inverter input, and self-biased current mirror technology, it achieves a wide input range, high gain, and low power consumption.
It achieves full-range input capability from negative to positive power rail, high gain and high-speed response, significantly reduced power consumption, and is suitable for high-performance continuous-time analog-to-digital converters.
Smart Images
Figure CN122293085A_ABST