Column address detection circuit of an image sensor and method of operation thereof

Abstract

This invention discloses a column address detection circuit and its operation method for an image sensor, aiming to solve the problems in existing technologies where column address decoding errors easily lead to pixel data misreading and image quality degradation. Furthermore, existing detection schemes suffer from large area requirements, inability to perform parallel detection across the entire column, inability to accurately distinguish decoding error types, and poor robustness. The detection circuit of this invention includes first and second detection circuits corresponding one-to-one with each column decoding circuit. Both circuits are arranged within the column pitch of the corresponding column, in the same area as the decoding circuits in the same column. The first detection circuit is used to detect address mistranslation / multiple translation anomalies caused by misaligned or multiple word lines, while the second detection circuit is used to detect address omission anomalies caused by word lines that have never been opened. This invention features an optimized pre-charge-level stabilization-edge-triggered sampling timing sequence and a built-in error injection module, enabling real-time parallel detection across the entire column, accurate differentiation of decoding error types, high area utilization, strong detection robustness, and effective protection of image quality. It is suitable for high-resolution, high-frame-rate image sensor applications.

Description

Technical Field

[0001] This invention relates to the field of image sensors, and more particularly to a column address detection circuit for an image sensor and its operation method. Background Technology

[0002] With the rapid development of CMOS image sensor technology, it has been widely used in consumer electronics, smart security, automotive imaging, industrial inspection and other fields. The market has placed increasingly stringent demands on the high resolution, high frame rate, high integration and high reliability of sensors. As the pixel array size continues to expand and the number of columns in image sensors increases significantly, the column address decoding circuit, as the core module for pixel data reading, directly determines the imaging quality and the reliability of device functions through its decoding accuracy and operational stability.

[0003] The core function of the column address decoding circuit is to generate the corresponding column word line strobe signal based on the input column address signal, thereby enabling the selection of the target column pixel unit and the reading of photoelectric signals. If the column address decoding malfunctions, such as misdecoding, overdecoding, or omission, it will directly lead to problems such as image data misalignment, pixel crosstalk, and data loss, and in severe cases, it will cause the sensor imaging function to fail.

[0004] Existing column address anomaly detection solutions often place the detection circuitry on the periphery of the chip, which cannot adapt to the column pitch size limitations of pixel arrays. This not only occupies additional chip layout area but also makes it difficult to achieve parallel real-time detection of each column. At the same time, most existing detection solutions can only identify whether a decoding anomaly has occurred, and cannot accurately distinguish between different error types such as address mistranslation / excessive opening and word line not being opened, which brings great inconvenience to chip debugging, fault location, and mass production testing. In addition, some solutions lack consideration for bus parasitic parameters in their timing design, and the sampling window is set in an unreasonable way, which easily leads to false detection and false negative detection. They have poor robustness and are difficult to adapt to high-resolution and high-frame-rate application scenarios. Summary of the Invention

[0005] To address the technical problems existing in the prior art, this invention proposes a column address detection circuit for an image sensor. Specifically, the image sensor includes a decoding circuit, a first detection circuit, and a second detection circuit. The first detection circuit is used to detect whether the word lines generated by the decoding circuit are misaligned or multiple. The second detection circuit is used to detect whether the word lines generated by the decoding circuit have been opened.

[0006] Furthermore, the first detection circuit comprises multiple NMOS transistors whose gates are electrically connected to the address signal line or the address signal line inverted, at least one NMOS transistor whose gate is connected to the word line, an NMOS transistor connected to the reset signal line, two inverters, two transmission transistors respectively connected to the word line signal line and the word line signal line inverted signal, an NMOS transistor whose drain is connected to the first output bus, and a PMOS transistor connected to the precharge line.

[0007] Furthermore, the second detection circuit comprises at least one NMOS transistor whose gate is connected to the word line, an NMOS transistor connected to the reset signal line, two inverters, two transmission transistors connected to the word line signal line and the inverted signal of the word line signal line respectively, an NMOS transistor whose drain is connected to the second output bus, and a PMOS transistor whose gate is connected to the precharge line; wherein the transmission transistor is also connected to the reset signal line and the inverted signal of the reset signal line.

[0008] Furthermore, the first detection circuit and / or the second detection circuit are arranged in the column spacing area of ​​the corresponding column, so that the detection circuit and its corresponding decoding circuit are located in the same column spacing area.

[0009] Furthermore, the detection circuit also includes an error injection module, which includes a register that connects to the address signal line and the inverted signal of the address signal line. The register is connected to the gate of the NMOS transistor of the first detection circuit that connects to the address signal line.

[0010] Furthermore, the present invention also provides an operation method for the above-mentioned column address detection circuit, the circuit comprising a first detection circuit and a second detection circuit; the first detection circuit comprises a plurality of NMOS transistors whose gates are electrically connected to address signal lines or inverted signals of address signal lines, and at least one NMOS transistor whose gate is connected to a word line, an NMOS transistor connected to a reset signal line, two inverters, two transmission transistors respectively connected to the word line signal line and the inverted signal of the word line signal line, and an NMOS transistor whose drain is connected to a first output bus, and a PMOS transistor connected to a precharge line; the second detection circuit comprises at least one NMOS transistor whose gate is connected to a word line, an NMOS transistor connected to a reset signal line, two inverters, two transmission transistors respectively connected to the word line signal line and the inverted signal of the word line signal line, and an NMOS transistor whose drain is connected to a second output bus, and a PMOS transistor whose gate is connected to a precharge line; wherein the transmission transistor is also connected to the reset signal line and the inverted signal of the reset signal line; The operation method includes: after the reset signal first drops from high level to low level within time t1, when the gate voltage of the NMOS transistor whose drain is connected to the first output bus in the first detection circuit is high, the column address is considered to have an error; when the gate voltage of the NMOS transistor whose drain is connected to the second output bus in the second detection circuit is low, the word line is considered to have been decoded.

[0011] Furthermore, after the precharge signal recovers from high level to low level, the levels of the first output bus and the second output bus are stabilized after a preset time t3. On the rising edge of the detection window signal changing from low level to high level, the first output bus and the second output bus are sampled, and the type of column address decoding error is determined based on the sampling results.

[0012] Furthermore, if the sampling results of the first output bus and the second output bus are low level and high level, respectively, then the column address decoding error type is an address error, and the address error is a mistranslated address or a multi-translated address. If the sampling results of the first output bus and the second output bus are high level and low level respectively, then the column address decoding error type is "word line never enabled".

[0013] Furthermore, when the outputs of the first output bus and the second output bus are high level and high level respectively, the image sensor column address decoding is normal.

[0014] Furthermore, the image sensor also includes an error injection module, which includes a register. The effectiveness of the detection circuit is verified by injecting an error signal into the register and sampling the first output bus.

[0015] This invention integrates two sets of column address detection circuits into the column pitch of the corresponding column, and lays them in the same area as the column decoding circuit. This eliminates the need for additional layout space on the outside of the chip, significantly reducing the area overhead of the detection circuit. It is suitable for the miniaturization and high integration design requirements of high-resolution image sensors, and at the same time realizes parallel real-time detection of the entire pixel array without detection blind spots.

[0016] This invention, through its differentiated first and second detection circuits, can accurately identify two types of core decoding anomalies: column address mistranslation / multiple opening and word line not being opened. By using two output signals, it can clearly distinguish between three working states: normal decoding, mistranslation / multiple decoding, and missing decoding. This solves the problem that existing technologies can only identify anomalies but cannot locate the error type, and greatly improves the efficiency of chip debugging and fault location.

[0017] This invention optimizes the timing design of pre-charging – stabilization waiting – edge-triggered sampling, reserves a bus level stabilization window, effectively avoids sampling misjudgment problems caused by bus parasitic parameters, has strong detection robustness, and the detection process is synchronized with column decoding, without occupying additional working cycles or affecting the normal imaging frame rate of the sensor. Simultaneously, a built-in error injection module can quickly simulate decoding anomalies, simplifying the mass production testing process and reducing testing costs. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a pixel array circuit in the prior art; Figure 2 This is a schematic diagram showing the location of the column address detection circuit; Figure 3 This is a schematic diagram of the first column address detection circuit; Figure 4 This is a schematic diagram of the second detection circuit for the column address; Figure 5 This is a schematic diagram of an incorrectly inserted circuit; Figure 6 This is the timing diagram for the column address detection circuit. Detailed Implementation To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] Figure 1This diagram illustrates the pixel array and column signal readout link of a CMOS image sensor in the prior art. The pixel array consists of multiple pixel units arranged in a row-column matrix. The output of each column of pixel units is connected to a corresponding column comparator. The analog pixel voltage output by the pixel unit is quantized by the column comparator and then written into the SRAM memory cell corresponding to that column address. In the subsequent pixel data readout stage, if the column address decoding circuit malfunctions, it will cause misalignment and crosstalk in the pixel data readout from the SRAM, resulting in image distortion and severely affecting image quality. Therefore, it is essential to effectively detect the accuracy of the column address decoding.

[0021] To address the technical problems existing in the prior art, this embodiment provides a column address detection circuit for an image sensor, applied to a column address decoding system of a CMOS image sensor. The CMOS image sensor includes a pixel array, a row decoding circuit, a column decoding circuit, a timing control circuit, a column signal processing circuit, and the column address detection circuit described in this embodiment. The pixel array consists of several pixel units arranged in rows and columns. The row decoding circuit generates row select word lines to select the corresponding row pixel unit in the pixel array. The column decoding circuit generates column select word lines (WL) based on the input column address signal to select the corresponding column pixel unit, transmitting the photoelectric signal collected by the pixel unit to the column signal processing circuit for subsequent signal amplification, analog-to-digital conversion, and other processing.

[0022] In the operation of an image sensor, the accuracy of column address decoding directly determines the correctness of pixel data reading. If anomalies such as mistranslation, overtranslation, or omission of column addresses occur, it can lead to image data misalignment, loss, or crosstalk, severely affecting image quality. In existing technologies, column address detection circuits are mostly located in the peripheral area of ​​the chip, which cannot adapt to the column pitch size limitations of the pixel array. This not only occupies additional chip area but also makes it difficult to achieve parallel real-time detection of each column. Furthermore, it cannot accurately distinguish the specific type of decoding error, causing significant inconvenience for chip debugging and fault location. The column address detection circuit in this embodiment aims to solve the above technical problems, achieving real-time detection of column address decoding anomalies and accurate identification of error types, while meeting the design requirements of high chip integration.

[0023] Please see Figure 2 In this embodiment, the column address detection circuit includes a first detection circuit (column address detection circuit 1) and a second detection circuit (column address detection circuit 2) that are configured one-to-one with the column decoding circuit. Both the first and second detection circuits are arranged within the column pitch area of ​​the corresponding column, ensuring that the first and second detection circuits are within the same pitch as their corresponding column decoding circuits.

[0024] Specifically, each column of the pixel array corresponds to an independent column decoding circuit unit, and each column decoding circuit unit corresponds to a set of first detection circuits and second detection circuits. The output terminals of the first detection circuits corresponding to all columns are connected to the first output bus Flag. <1> The output terminals of the second detection circuits corresponding to all columns are connected to the second output bus Flag. <0> By integrating the detection circuitry into the column pitch, the chip's area utilization is significantly improved, eliminating the need for additional peripheral layout space. Simultaneously, it enables independent, parallel detection of each column's decoding circuitry, enhancing the real-time performance and accuracy of the detection.

[0025] In this embodiment, the core components of both the first and second detection circuits adopt a minimum size design that adapts to the pitch width. The power, ground, and control signals of the two detection circuits are all connected in the same column, which further compresses the layout space and ensures that the detection circuit can be completely embedded in the column pitch without exceeding the layout boundary of the column decoding circuit.

[0026] Please see Figure 3 The first detection circuit is used to detect whether the word lines WL generated by the column decoding circuit are misaligned or multiple, i.e., the error type of column address mis-decoding or multiple-decoding. The first detection circuit includes n address detection NMOS transistors, a first reset NMOS transistor, a word line gating NMOS transistor, a first inverter, a second inverter, a first transmission gate, a second transmission gate, a first output control NMOS transistor, and a first pre-charge PMOS transistor, where n is the bit width of the column address signal, and is related to the column address signal line Addr. <n:0>The number of bits is consistent and can be flexibly adjusted according to the number of columns of the image sensor. For example, when the number of columns in the pixel array is 2048, the value of n is 11.

[0027] The specific circuit connections are as follows: The gates of n address detection NMOS transistors are respectively connected to the column address signal line Addr. <0> ~Addr <n-1>Or the inverted signal Addr_b of the corresponding address signal line <0> ~Addr_b <n-1>A one-to-one electrical connection is established, with the drains of the n address detection NMOS transistors shared by the chip's core power supply voltage VDD, and the sources of the n address detection NMOS transistors shared by the drain of the word line selection NMOS transistor. The gate connection rule for the address detection NMOS transistors is as follows: for an address bit that is high in the preset column address, the gate of the corresponding address detection NMOS transistor is connected to the inverted signal Addr_b of that address bit. <x>For a low-level address bit in the preset column address, the gate of the corresponding address detection NMOS transistor is connected to the in-phase signal Addr of that address bit. <x>With this configuration, when the input column address perfectly matches the preset column address, all address detection NMOS transistors are turned off; when the input column address does not match the preset column address, at least one address detection NMOS transistor is turned on, thereby realizing the detection of the address matching status.

[0028] The gate of the word line select NMOS transistor is electrically connected to the word line WL signal generated by the column decoding circuit of the corresponding column, and the source of the word line select NMOS transistor is connected to the first node A; the gate of the first reset NMOS transistor is electrically connected to the reset signal rst, the drain of the first reset NMOS transistor is connected to the first node A, and the source of the first reset NMOS transistor is connected to the chip ground voltage GND.

[0029] The input terminal of the first inverter is connected to the first node A, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first transmission gate. The first transmission gate is a CMOS transmission gate, whose positive control terminal is electrically connected to the word line WL signal, and its negative control terminal is electrically connected to the inverted signal WLB of the word line WL. The output terminal of the first transmission gate is connected to the input terminal of the second transmission gate. The second transmission gate is also a CMOS transmission gate, whose positive control terminal is electrically connected to the reset signal rst, and its negative control terminal is electrically connected to the inverted signal rstb of the reset signal rst. The output terminal of the second transmission gate is connected to the gate of the first output control NMOS transistor.

[0030] The drain of the first output control NMOS transistor is connected to the first output bus Flag. <1> The source of the first output control NMOS transistor is connected to ground (GND); the gate of the first precharge PMOS transistor is electrically connected to the precharge signal prch; the source of the first precharge PMOS transistor is connected to the core power supply voltage (VDD); and the drain of the first precharge PMOS transistor is connected to the first output bus (Flag). <1> .

[0031] Please see Figure 4 The second detection circuit is used to detect whether the word line WL generated by the column decoding circuit has an abnormal condition of never being turned on, i.e., the error type of missing column address decoding. The second detection circuit includes a second reset NMOS transistor, a word line latching NMOS transistor, a weak pull-up PMOS transistor, a third inverter, a fourth inverter, a third transmission gate, a fourth transmission gate, a second output control NMOS transistor, and a second precharge PMOS transistor.

[0032] The specific circuit connections are as follows: The gate of the weak pull-up PMOS transistor is connected to ground (GND), the source is connected to the core power supply (VDD), and the drain is connected to the second node (B), used to pull the second node (B) high after reset. The gate of the word line latch NMOS transistor is electrically connected to the word line (WL) signal generated by the column decoding circuit of the corresponding column. The drain of the word line latch NMOS transistor is connected to the second node (B), and the source of the word line latch NMOS transistor is connected to ground (GND). The gate of the second reset NMOS transistor is electrically connected to the reset signal (rst). The drain of the second reset NMOS transistor is connected to the second node (B), and the source of the second reset NMOS transistor is connected to ground (GND).

[0033] The input terminal of the third inverter is connected to the second node B, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the input terminal of the third transmission gate. The third transmission gate is a CMOS transmission gate, with its positive control terminal electrically connected to the word line WL signal and its inverting control terminal electrically connected to the inverted signal WLB of the word line WL. The output terminal of the third transmission gate is connected to the input terminal of the fourth transmission gate. The fourth transmission gate is also a CMOS transmission gate, with its positive control terminal electrically connected to the reset signal rst and its inverting control terminal electrically connected to the inverted signal rstb of the reset signal rst. The output terminal of the fourth transmission gate is connected to the gate of the second output control NMOS transistor.

[0034] The drain of the second output control NMOS transistor is connected to the second output bus Flag. <0> The source of the second output control NMOS transistor is connected to ground (GND); the gate of the second precharge PMOS transistor is electrically connected to the precharge signal prch; the source of the second precharge PMOS transistor is connected to the core power supply voltage (VDD); and the drain of the second precharge PMOS transistor is connected to the second output bus (Flag). <0> .

[0035] Unlike the first detection circuit, the second detection circuit does not require an address detection NMOS transistor array. Its core function is to use word line latching NMOS transistors to record whether the word line WL of the corresponding column has been effectively enabled, thereby detecting column address decoding errors. Furthermore, in this embodiment, the inverters, transmission gates, output control NMOS transistors, and pre-charge PMOS transistors in both the first and second detection circuits use the same device size design, thus adapting to the column pitch width limitation and ensuring that both detection circuits can be integrated with the column decoding circuit within the same column pitch without requiring additional layout space.

[0036] To verify the functional effectiveness of the column address detection circuit in this embodiment during the chip testing phase, the column address detection circuit in this embodiment is also equipped with an error injection module. Please continue reading. Figure 5 The error injection module includes an error injection register, a multiplexer, and an error address signal generation unit. The output of the error injection register is electrically connected to the control terminal of the multiplexer, and the first input of the multiplexer is connected to the normal column address signal line Addr. <0> ~Addr <n-1>and its inverted signal Addr_b <0> ~Addr_b <n-1>The second input of the multiplexer is connected to the output of the error address signal generation unit, and the output of the multiplexer is connected to the gates of the n address detection NMOS transistors in the first detection circuit.

[0037] The error injection module works as follows: When the chip is in normal operating mode, the error injection register outputs an invalid signal. The multiplexer transmits the normal column address signal and its inverted signal to the gate of the address detection NMOS transistor in the first detection circuit, and the detection circuit performs normal column address decoding and detection functions. When the chip is in test mode and functional verification is required, a valid configuration value is written to the error injection register, the error injection register outputs a valid signal, the multiplexer switches to the second input terminal, and transmits the error address signal output by the error address signal generation unit to the gate of the address detection NMOS transistor in the first detection circuit. At this time, even if the input column address matches the preset column address of the corresponding column, the erroneous address signal will cause at least one address detection NMOS transistor to be in the conducting state. When the WL signal of the corresponding column is turned on, the first node A will be pulled high, ultimately causing the first output bus Flag to be activated. <1> The Flag is pulled low during the sampling phase and obtained by the digital circuit sampling. <1> The level is low to simulate an abnormal situation of column address misinterpretation and realize the error injection function.

[0038] This error injection module enables rapid verification of the functionality of the detection circuit during the chip mass production testing phase, eliminating the need for additional complex test stimuli design, thus significantly improving testing efficiency and reducing testing costs.

[0039] The following is combined Figure 6 The timing diagram shown illustrates in detail the operation method of the column address detection circuit in this embodiment. This operation method, based on the aforementioned column address detection circuit, includes the following steps: Step S1: Reset and Initialization Phase In this embodiment, the internal clock dclk of the module is the main clock of the column address detection circuit. The reset signal rst is aligned with the first rising edge after dclk is valid, and the falling edge of the rst signal is aligned with a subsequent falling edge of dclk, ensuring the timing synchronization between the reset operation and the system clock.

[0040] When the reset signal rst is high, both the first reset NMOS transistor in the first detection circuit and the second reset NMOS transistor in the second detection circuit are in the ON state. The first node A is pulled to ground (GND), and the second node B is pulled to VDD, completing the node initialization reset. Simultaneously, the second and fourth transmission gates are in the ON state when rst is high, transmitting the initialized low level to the gate of the output control NMOS transistor. This keeps both the first and second output control NMOS transistors in the OFF state, preventing erroneous pull-down of the output bus during the reset phase and ensuring the stability of the initialization state.

[0041] Step S2, Address Decoding and Exception Latching Stage At time t1, after the reset signal rst is pulled low from high, the column address signal Addr... <n:0>The signal is activated and increments bit by bit according to a preset scanning order. The column decoding circuit decodes the input column address signal to generate the corresponding column word line (WL) signal. In this stage, the first detection circuit detects column address mis-decoding and over-decoding anomalies, while the second detection circuit detects column address omission anomalies. The specific process is as follows: For the first detection circuit: when the input column address does not match the preset column address of the corresponding column, i.e., when a misinterpretation or multiple interpretation occurs due to column address misalignment, multiple interpretation, or multiple interpretation anomalies, at least one address detection NMOS transistor is in the on state. When the WL signal corresponding to that column becomes high after decoding, the word line select NMOS transistor is turned on, and the core power supply voltage VDD pulls the first node A from low to high level through the turned-on address detection NMOS transistor and word line select NMOS transistor. This high level is buffered and shaped by the first inverter and the second inverter, and is transmitted through the turned-on first transmission gate during the WL signal's validity period, and latched to the gate of the first output control NMOS transistor through the turned-on second transmission gate during the rst signal's low level period, so that the first output control NMOS transistor remains in the on state. Conversely, when the input column address completely matches the preset column address of the corresponding column, all address detection NMOS transistors are turned off, and even if the WL signal is valid, the first node A will remain low, and the first output control NMOS transistor will remain in the off state.

[0042] For the second detection circuit: after the reset signal rst is pulled low, the second node B is set to a high level by rst; when the WL signal of the corresponding column is decoded and becomes high, that is, when the word line of that column has been normally turned on, the word line latch NMOS transistor is turned on, pulling the second node B from high to low; this low level is buffered and shaped by the third and fourth inverters, and transmitted through the conducting third transmission gate during the active period of the WL signal, and latched to the gate of the second output control NMOS transistor through the conducting fourth transmission gate during the low period of the rst signal, so that the second output control NMOS transistor remains in the off state. Conversely, when the WL signal of the corresponding column is never decoded, that is, when a column address decoding failure occurs, the word line latch NMOS transistor remains in the off state, the second node B maintains the high level after reset, and the second output control NMOS transistor remains in the on state.

[0043] It should be noted that the setting of time t1 must meet the timing margin requirements. The duration of t1 must be greater than the hold time of the reset signal rst, and less than the setup time of the column address signal. This ensures that the column address signal becomes effective only after the reset operation is fully completed, thus avoiding initialization anomalies.

[0044] Step S3, Pre-charging stage During time period t2, after all column address decoding operations are completed, the precharge signal prch changes from high to low, and both the first and second precharge PMOS transistors are turned on. The core power supply voltage VDD is then applied to the first output bus Flag through the turned-on precharge PMOS transistors. <1> With the second output bus Flag <0> Precharge by pulling the levels of both output buses high to VDD.

[0045] During the pre-charge phase, if an error occurs in the column address decoding, the corresponding column's output control NMOS transistor will be on, pulling the output bus level low. If there is a column address misdecoding or over-decoding error, the first output control NMOS transistor will be on, and the first output bus flag will be lowered. <1> Unable to be precharged to a high level; if a column address decoding failure exists, the second output control NMOS transistor is turned on, and the second output bus Flag... <0> It cannot be precharged to a high level.

[0046] Step S4: Sampling and Error Type Identification Stage At time t3, after the precharge signal prch is pulled back from low to high, the detection window is entered. At this time, the digital circuit checks the first output bus Flag. <1> With the second output bus Flag <0> The sampling level is used. The setting of time t3 must meet the timing requirements, and the duration of t3 must ensure that if there is a column address decoding error, the output bus has sufficient time to be fully pulled low to ground by the output control NMOS transistor, thus ensuring the stability and accuracy of the sampling results.

[0047] Based on the sampled values ​​of Flag<1:0>, the working status and error type of the column address decoding can be directly identified. The specific judgment rules are as follows: When the sampling result is 11, i.e., Flag <1> High level, Flag <0> A high level indicates that the column address decoding is normal. At this time, the first node A of all columns is low, the first output control NMOS transistor is turned off, and the Flag... <1> Normally precharged to high level; simultaneously, the second node B of all columns is low level, the second output control NMOS transistor is turned off, Flag <0> The fact that the address was precharged to a high level normally indicates that the address decoding of all columns is matched and that the word lines WL of all columns have been normally enabled without any decoding abnormalities.

[0048] When the sampling result is 01, i.e., Flag <1> Low level, Flag <0> A high level indicates a misdecoding or overdecoding anomaly in the column address decoding, i.e., the word lines WL are misaligned or have multiple lines. At this time, at least one column's first node A is high, the first output control NMOS transistor is turned on, and the Flag is set. <1> Pull low; and the second node B of all columns is low, Flag <0> The normal upward movement indicates a column address mismatch, but the word lines (WL) of all columns have been enabled, and there are no missing translation anomalies.

[0049] When the sampling result is 10, i.e., Flag <1> High level, Flag <0> A low level indicates a missing decoding error in the column address decoding, meaning the word line WL has never been enabled. In this case, the first node A of all columns is low. (Flag) <1> A normal high signal indicates that the address decoding of all columns is matched; however, at least one column's second node B is high, causing the second output to control the NMOS transistor to conduct, thus setting the Flag. <0> A low value indicates that there is a situation where the column word line WL has never been decoded and enabled.

[0050] Through the one-to-one correspondence between the sampling results and error types described above, the detection circuit in this embodiment can not only detect column address decoding anomalies, but also accurately distinguish between two different error types: mis-decoding / over-decoding and omission decoding. This provides a precise basis for chip fault location and debugging, and significantly improves chip debugging efficiency.

[0051] The column address detection circuit provided in this embodiment has the following significant advantages compared to the prior art: High integration and high area utilization: The detection circuit is integrated into the corresponding column pitch and laid out in the same area as the column decoding circuit. It does not require additional space on the chip's perimeter, which greatly reduces the area overhead of the detection circuit and meets the miniaturization design requirements of high-resolution image sensors.

[0052] High detection accuracy and ability to distinguish error types: Different anomaly types are detected by two independent detection circuits. The three states of normal decoding, mis-decoding / over-decoding, and omission can be accurately identified by two output signals, which solves the pain point of existing technologies that can only detect anomalies but cannot locate the error type.

[0053] High real-time performance and parallel detection: Each column is configured with an independent detection unit, and all columns perform detection operations in parallel. Anomaly latching is completed synchronously during address decoding, eliminating the need for additional detection cycles and not affecting the normal operating frame rate of the image sensor.

[0054] Highly testable and low testing cost: The built-in error injection module can quickly simulate decoding anomalies through register configuration, and the functional verification of the detection circuit can be completed during the testing phase without the need for complex test stimuli, thus reducing the mass production testing cost.

[0055] Strong timing compatibility and high robustness: The working timing is completely synchronized with the column decoding timing of the image sensor, and each stage is aligned with the internal clock. It has sufficient timing margin, strong anti-interference ability, and can be adapted to image sensor application scenarios with different resolutions and frame rates.

[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention. < / x> < / x>

Claims

1. A column address detection circuit for an image sensor, characterized in that, The image sensor includes a decoding circuit, a first detection circuit, and a second detection circuit; The first detection circuit is used to detect whether the word lines generated by the decoding circuit are misaligned or multiple. The second detection circuit is used to detect whether the word lines generated by the decoding circuit have been turned on.

2. The circuit as described in claim 1, characterized in that, The first detection circuit comprises multiple NMOS transistors whose gates are electrically connected to address signal lines or inverted address signal lines, at least one NMOS transistor whose gate is connected to a word line, an NMOS transistor connected to a reset signal line, two inverters, two transmission transistors connected to the word line signal line and the inverted signal of the word line signal line respectively, an NMOS transistor whose drain is connected to the first output bus, and a PMOS transistor connected to the precharge line.

3. The circuit as described in claim 1, characterized in that, The second detection circuit comprises at least one NMOS transistor whose gate is connected to the word line, an NMOS transistor connected to the reset signal line, two inverters, two transmission transistors connected to the word line signal line and the inverted signal of the word line signal line respectively, an NMOS transistor whose drain is connected to the second output bus, and a PMOS transistor whose gate is connected to the precharge line; wherein the transmission transistor is also connected to the reset signal line and the inverted signal of the reset signal line.

4. The circuit as described in claim 1, characterized in that, The first detection circuit and / or the second detection circuit are arranged in the column spacing area of ​​the corresponding column, so that the detection circuit and the corresponding decoding circuit are set in the same column spacing area.

5. The circuit as described in claim 2, characterized in that, The detection circuit further includes an error injection module, which includes a register that connects to the address signal line and the inverted signal of the address signal line. The register is connected to the gate of the NMOS transistor of the first detection circuit that connects to the address signal line.

6. A circuit operation method as claimed in any one of claims 1-5, characterized in that, The circuit includes a first detection circuit and a second detection circuit; The first detection circuit comprises multiple NMOS transistors whose gates are electrically connected to address signal lines or inverted address signal lines, at least one NMOS transistor whose gate is connected to a word line, an NMOS transistor connected to a reset signal line, two inverters, two transmission transistors connected to the word line signal line and the inverted signal of the word line signal line respectively, an NMOS transistor whose drain is connected to the first output bus, and a PMOS transistor connected to the precharge line. The second detection circuit comprises at least one NMOS transistor whose gate is connected to the word line, an NMOS transistor connected to the reset signal line, two inverters, two transmission transistors connected to the word line signal line and the inverted signal of the word line signal line respectively, an NMOS transistor whose drain is connected to the second output bus, and a PMOS transistor whose gate is connected to the precharge line; wherein the transmission transistor is also connected to the reset signal line and the inverted signal of the reset signal line. The method includes: After the reset signal first drops from high to low for time t1, if the gate voltage of the NMOS transistor whose drain is connected to the first output bus in the first detection circuit is high, the column address is considered to have an error; if the gate voltage of the NMOS transistor whose drain is connected to the second output bus in the second detection circuit is low, the word line is considered to have been decoded.

7. The method as described in claim 6, characterized in that, After the precharge signal returns from high to low, the levels of the first and second output buses are stabilized after a preset time t3. On the rising edge of the detection window signal transitioning from low to high, the first and second output buses are sampled, and the type of column address decoding error is determined based on the sampling results.

8. The method as described in claim 7, characterized in that, If the sampling results of the first output bus and the second output bus are low level and high level respectively, then the column address decoding error type is address error, and the address error is mistranslated address or over-translated address; If the sampling results of the first output bus and the second output bus are high level and low level respectively, then the column address decoding error type is "word line never enabled".

9. The method as described in claim 6, characterized in that, When the outputs of the first output bus and the second output bus are high level and high level respectively, the image sensor column address decoding is normal.

10. The method as described in claim 6, characterized in that, The image sensor also includes an error injection module, which includes a register. The effectiveness of the detection circuit is verified by injecting an error signal into the register and sampling the first output bus.

Images