Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes providing a substrate, sequentially forming a first floating gate layer and a mask layer over the substrate, and etching the substrate to form a trench and define an active region in the substrate. The method includes forming a first isolation structure in the trench and extending into the substrate, forming spacers on the sidewalls of the mask layer to form a first opening over the first isolation structure, and forming a second isolation structure to fill the first opening. The method further includes removing the mask layer and spacers to form a second opening, forming a second floating gate layer to fill the second opening, removing the second isolation structure to expose the top surface of the first isolation structure, compliantly forming an inter-gate dielectric layer over the substrate, and forming a control gate layer on the inter-gate dielectric layer.

Description

Technical Field

[0001] This invention relates to semiconductor process technology, and in particular to a method for forming a floating gate in a flash memory. Background Technology

[0002] To increase component density and improve overall performance within flash memory devices, current manufacturing technologies continue to focus on miniaturizing component sizes. However, as the smallest component continues to shrink, numerous challenges arise. For example, with the miniaturization of floating gates, the formation process needs to be simplified to improve process margins and the coupling ratio between the floating gate and the control gate. Therefore, the industry still needs to refine flash memory device manufacturing methods to overcome the challenges posed by component size reduction. Summary of the Invention

[0003] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate; sequentially forming a first floating gate layer and a mask layer over the substrate; etching the substrate to form a trench and define an active region in the substrate; forming a first isolation structure in the trench and extending into the substrate; forming spacers on the sidewalls of the mask layer to form a first opening over the first isolation structure; forming a second isolation structure to fill the first opening; removing the mask layer and the spacers to form a second opening; forming a second floating gate layer to fill the second opening; removing the second isolation structure to expose the top surface of the first isolation structure; compliantly forming an inter-gate dielectric layer over the substrate; and forming a control gate layer on the inter-gate dielectric layer. Attached Figure Description

[0004] The embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings.

[0005] Figures 1 to 15 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor structure according to an embodiment of the present invention.

[0006] Symbol explanation:

[0007] 10. Semiconductor structure;

[0008] 100 substrates;

[0009] 102 Active Zone;

[0010] 103 top width;

[0011] 105 penetrated the oxide layer;

[0012] 110 First floating gate layer;

[0013] 111 Bottom width;

[0014] 115 buffer layer;

[0015] 120 mask layers;

[0016] 121 top width;

[0017] 125 groove;

[0018] 130 First isolation material layer;

[0019] 135 First isolation structure;

[0020] 136 upper part;

[0021] 137 top width;

[0022] 140 layers of spacer material;

[0023] 145 spacers;

[0024] 150 First opening;

[0025] 155 groove;

[0026] 160 Second isolation material layer;

[0027] 165 Second isolation structure;

[0028] 166 top width;

[0029] 170 Second opening;

[0030] 175 Second floating gate material layer;

[0031] 180 Second floating gate layer;

[0032] 181 bottom width;

[0033] 182 top width;

[0034] 183 acute angle;

[0035] 184 lower surface;

[0036] 185 inter-gate dielectric layer;

[0037] 186 bottom surface;

[0038] 190 Control gate layer;

[0039] D distance;

[0040] T thickness. Detailed Implementation

[0041] See Figure 1 , Figure 1A cross-sectional schematic diagram of semiconductor structure 10 is shown. A substrate 100 is provided. In some embodiments, substrate 100 may be an elemental semiconductor substrate, a compound semiconductor substrate, or an alloy semiconductor substrate. In other embodiments, substrate 100 may be a semiconductor-on-insulator (SOI) substrate. The aforementioned SOI substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer.

[0042] See also Figure 1 A tunneling oxide layer 105, a first floating gate layer 110, a buffer layer 115, and a mask layer 120 are sequentially formed on a substrate 100. The buffer layer 115 can protect the first floating gate layer 110 during the etching of the mask layer 120. In some embodiments, the tunneling oxide layer 105 can be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination thereof. In some embodiments, the first floating gate layer 110 can be formed by a chemical vapor deposition process or a similar deposition process. In some embodiments, the buffer layer 115 and the mask layer 120 can be formed by a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof. In some embodiments, the tunneling oxide layer 105 is formed of an oxide, such as silicon oxide. In some embodiments, the material of the first floating gate layer 110 may include doped polysilicon, metal, polycide, or a combination thereof. In some embodiments, the buffer layer 115 is formed of an oxide, such as silicon oxide. In some embodiments, the mask layer 120 is formed of a nitride, such as silicon nitride.

[0043] See next Figure 2 , Figure 2A cross-sectional schematic diagram of a trench 125 formed in a semiconductor structure 10 is shown. An etching process is performed on a substrate 100 to form the trench 125. The trench 125 penetrates the mask layer 120, the buffer layer 115, the first floating gate layer 110, and the tunnel oxide layer 105, and extends into the substrate 100. After the trench 125 is formed, it defines an active region 102 in the substrate 100. In some embodiments, the top width 121 of the mask layer 120 is smaller than the bottom width 111 of the first floating gate layer 110. In some embodiments, the bottom width 111 of the first floating gate layer 110 is less than or equal to the top width 103 of the active region 102. In some embodiments, the etching process may include anisotropic etching processes (or directional etching processes), such as reactive ion etching (RIE), plasma etching, inductively coupled plasma (ICP) etching, or dry etching processes combining the above.

[0044] See Figure 3 , Figure 3 A cross-sectional schematic diagram is shown of the semiconductor structure 10 forming a first isolation material layer 130. After trench 125 is formed, the first isolation material layer 130 is formed to overfill trench 125. In some embodiments, the first isolation material layer 130 may be formed by chemical vapor deposition, atomic layer deposition, or a combination thereof. In some embodiments, the first isolation material layer 130 is formed of an oxide, such as silicon oxide.

[0045] See next Figure 4 , Figure 4 A cross-sectional schematic diagram of the semiconductor structure 10 forming a first isolation structure 135 is illustrated. After forming the first isolation material layer 130, a planarization process such as Chemical Mechanical Polishing (CMP) can be performed on the first isolation material layer 130 to expose the top surface of the mask layer 120, followed by an etch-back process to form the first isolation structure 135. The first isolation structure 135 extends into the substrate 100. In some embodiments, performing the etch-back process includes making the top surface of the first isolation structure 135 lower than the top surface of the first floating gate layer 110 and higher than the bottom surface of the first floating gate layer 110, which helps to control the formation of the floating gate of the memory device. In some embodiments, the etch-back process may include anisotropic etching processes (or directional etching processes), such as reactive ion etching, plasma etching, inductively coupled plasma etching, or dry etching of combinations thereof.

[0046] See Figure 5 , Figure 5 A cross-sectional schematic diagram of a spacer material layer 140 formed in a semiconductor structure 10 is illustrated. The spacer material layer 140 is compliantly formed over a substrate 100. In embodiments of the invention, the spacer material layer 140 (i.e., subsequently formed spacers 145) is used to define the width of the floating gate of a memory device. In other words, embodiments of the invention avoid repetitive patterning of the structure surrounding the floating gate by forming the spacer material layer 140 and subsequent spacers 145, simplifying the floating gate formation process while maintaining the required dimensions of the floating gate. In some embodiments, the spacer material layer 140 may be formed by chemical vapor deposition, atomic layer deposition, or a combination thereof. In some embodiments, the spacer material layer 140 is formed of a nitride, such as silicon nitride.

[0047] See Figure 6 , Figure 6 A cross-sectional schematic diagram of the semiconductor structure 10 forming a spacer 145 is shown. An etching process is performed on the spacer material layer 140 to expose the top surface of the first isolation structure 135 and the mask layer 120, thus forming the spacer 145. More specifically, the spacer 145 is formed on the sidewall of the mask layer 120. After forming the spacer 145, a first opening 150 is formed above the first isolation structure 135. In some embodiments, to avoid residue of the spacer material layer 140, the step of etching the spacer material layer 140 further includes forming a groove 155 in the upper portion 136 of the first isolation structure 135. In some embodiments, the spacer 145 is in direct contact with the first floating gate layer 110. In some embodiments, the etching process may include anisotropic etching processes (or directional etching processes), such as reactive ion etching, plasma etching, inductively coupled plasma etching, or dry etching combining the above.

[0048] See then Figure 7 , Figure 7 A cross-sectional schematic diagram of the semiconductor structure 10 forming a second isolation material layer 160 is shown. After forming a first opening 150, a second isolation material layer 160 is formed to overfill the first opening 150. In some embodiments, the second isolation material layer 160 completely fills the recess 155. In some embodiments, the second isolation material layer 160 may be formed by a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof. In some embodiments, the second isolation material layer 160 is formed of an oxide, such as silicon oxide.

[0049] See Figure 8 , Figure 8A cross-sectional schematic diagram of the semiconductor structure 10 forming a second isolation structure 165 is shown. After forming the second isolation material layer 160, a planarization process such as chemical mechanical polishing can be performed on the second isolation material layer 160 to form the second isolation structure 165. More specifically, the second isolation structure 165 fills the first opening 150. In some embodiments, after forming the second isolation structure 165, the second isolation structure 165 completely fills the recess 155. In some embodiments, the top width 166 of the second isolation structure 165 is smaller than the top width 137 of the first isolation structure 135. In some embodiments, the spacer 145 has different etching selectivity than the first isolation structure 135 and the second isolation structure 165, and the mask layer 120 has the same etching selectivity as the spacer 145.

[0050] See next Figure 9 , Figure 9 A cross-sectional schematic diagram of the semiconductor structure 10 forming a second opening 170 is shown. After forming the second isolation structure 165, the mask layer 120 and the spacer 145 are removed to form the second opening 170. More specifically, the second opening 170 is formed to expose the sidewalls of the second isolation structure 165, the top surface of the buffer layer 115, and a portion of the top surface of the first isolation structure 135. The second opening 170 is used to form the second floating gate layer 180, which will be described in detail below. In some embodiments, the step of removing the mask layer 120 and the spacer 145 may include a dry etching process, a wet etching process, or a combination thereof.

[0051] See Figure 10 , Figure 10 A cross-sectional schematic diagram of the semiconductor structure 10 after the removal of the buffer layer 115 is shown. After removing the mask layer 120 and the spacer 145, the buffer layer 115 is further removed to expose the top surface of the first floating gate layer 110. In other words, the second opening 170 exposes the top surface of the first floating gate layer 110 and a portion of the top surface of the first isolation structure 135. The removal of the buffer layer 115 to subsequently form the second floating gate material layer 175 will be described in detail below.

[0052] See then Figure 11 , Figure 11 A cross-sectional schematic diagram is shown of the semiconductor structure 10 forming a second floating gate material layer 175. The second floating gate material layer 175 is formed to overfill the second opening 170. In some embodiments, the second floating gate material layer 175 may be formed by a chemical vapor deposition process or a similar deposition process. In some embodiments, the material of the second floating gate material layer 175 may comprise doped polysilicon, metal, polysilicon silicide, or a combination thereof. In some embodiments, the material of the second floating gate material layer 175 may be the same as the material of the first floating gate layer 110.

[0053] See Figure 12 , Figure 12 A cross-sectional schematic diagram of the semiconductor structure 10 forming a second floating gate layer 180 is shown. After forming the second floating gate material layer 175, a planarization process such as chemical mechanical polishing can be performed on the second floating gate material layer 175 to form the second floating gate layer 180. In other words, the second floating gate layer 180 fills the second opening 170. In some embodiments, the bottom width 181 of the second floating gate layer 180 is greater than the bottom width 111 of the first floating gate layer 110. In some embodiments, the top width 182 of the second floating gate layer 180 is less than the bottom width 181 of the second floating gate layer 180. In some embodiments, the top width 182 of the second floating gate layer 180 is equal to the sum of the top width 121 of the mask layer 120 and twice the thickness T of the spacer 145. In some embodiments, the thickness T of the spacer 145 is equal to the distance D by which the sidewall of the second floating gate layer 180 extends beyond the sidewall of the first floating gate layer 110. The first floating gate layer 110 and the second floating gate layer 180 may be collectively referred to as a floating gate. In some embodiments, the bottom of the second floating gate layer 180 has an acute angle 183. In some embodiments, the acute angle 183 is greater than 80 degrees and less than 90 degrees.

[0054] See Figure 13 , Figure 13 A cross-sectional view of semiconductor structure 10 with the second isolation structure 165 removed is shown. The second isolation structure 165 is removed to expose the top surface of the first isolation structure 135 and the sidewalls of the second floating gate layer 180. More specifically, in some embodiments, the top surface of the first isolation structure 135 is exposed after the recess 155 is filled. In some embodiments, the step of removing the second isolation structure 165 may include anisotropic etching processes (or directional etching processes), such as reactive ion etching, plasma etching, inductively coupled plasma etching, or dry etching of combinations thereof.

[0055] See next Figure 14 , Figure 14 A cross-sectional schematic diagram of the formation of an inter-gate dielectric layer 185 in the semiconductor structure 10 is shown. The inter-gate dielectric layer 185 is compliantly formed above the substrate 100. In some embodiments, the bottom surface 186 of the inter-gate dielectric layer 185 is flush with the lower surface 184 of the second floating gate layer 180. In some embodiments, the inter-gate dielectric layer 185 may be a single-layer structure or a multi-layer structure, and the material of the inter-gate dielectric layer 185 may include silicon oxide, silicon nitride, or a combination thereof. For example, the inter-gate dielectric layer 185 may be a silicon oxide / silicon nitride / silicon oxide structure (ONO structure). In some embodiments, the inter-gate dielectric layer 185 may be formed by chemical vapor deposition, atomic layer deposition, or a combination thereof.

[0056] See Figure 15 , Figure 15 A cross-sectional schematic diagram of a semiconductor structure 10 forming a control gate layer 190 is shown. The control gate layer 190 is formed on an inter-gate dielectric layer 185. In some embodiments, the control gate layer 190 may be a single-layer or multi-layer structure, and the material of the control gate layer 190 may include polysilicon, metal, metal silicide, similar conductive materials, or combinations thereof. In some embodiments, the control gate layer 190 may be formed by chemical vapor deposition, atomic layer deposition, or combinations thereof.

[0057] After the control gate layer 190 is formed, other further processes can be performed to continue forming various components of the flash memory device, which will not be described in detail here.

[0058] In summary, the embodiments of the present invention provide a method for forming a semiconductor structure, which simplifies the original multi-step patterning process, facilitates the formation of miniaturized semiconductor structures, and improves the coupling ratio between the floating gate and the control gate of a memory device, thereby enhancing the performance of the memory device. In other words, the floating gate formed in the embodiments of the present invention can have straight tapered sidewalls, which facilitates the subsequent formation of the inter-gate dielectric layer and the control gate.

[0059] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a substrate; A first floating gate layer and a mask layer are sequentially formed above the substrate; The substrate is etched to form a trench and define an active region in the substrate; A first isolation structure is formed in the trench and extends into the substrate; A spacer is formed on the sidewall of the mask layer to form a first opening above the first isolation structure; A second isolation structure is formed to fill the first opening; Remove the mask layer and the spacer to form a second opening; A second floating gate layer is formed to fill the second opening; Remove the second isolation structure to expose the top surface of the first isolation structure; An inter-gate dielectric layer is compliantly formed above the substrate; as well as A control gate layer is formed on the inter-gate dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of forming the spacers on the sidewalls of the mask layer further includes: A spacer material layer is compliantly formed over the substrate; and The spacer material layer is etched to expose the top surface of the first isolation structure and the mask layer, and the spacer is formed.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of forming the first isolation structure in the trench further includes: A first insulating material layer is formed to overfill the trench; Planarize the first insulating material layer to expose the top surface of the mask layer; and The first insulating material layer is etched back to form the first insulating structure. The top surface of the first isolation structure is lower than the top surface of the first floating gate layer and higher than the bottom surface of the first floating gate layer.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, Before sequentially forming the first floating gate layer and the mask layer above the substrate, the method further includes: forming a tunnel oxide layer on the substrate, wherein the first floating gate layer is formed on the tunnel oxide layer.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The bottom width of the second floating gate layer is greater than the bottom width of the first floating gate layer.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The top width of the second floating gate layer is smaller than the bottom width of the second floating gate layer.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The top width of the second floating gate layer is equal to the sum of the top width of the mask layer and twice the thickness of the spacer.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The bottom surface of the inter-gate dielectric layer is flush with the bottom surface of the second floating gate layer.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The spacer is in direct contact with the first floating gate layer.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The second opening exposes the top surface of the first floating gate layer and a portion of the top surface of the first isolation structure.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The top width of the second isolation structure is smaller than the top width of the first isolation structure.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness of the spacer is equal to the distance by which the sidewall of the second floating gate layer extends beyond the sidewall of the first floating gate layer.

13. The method for forming a semiconductor structure according to claim 1, characterized in that, The spacer has different etching selectivity compared to the first isolation structure and the second isolation structure. The mask layer and the spacer have the same etching selectivity.

14. The method for forming a semiconductor structure according to claim 1, characterized in that, The bottom of the second floating gate layer has an acute angle.

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