LDMOS device and method of manufacturing the same
By using a drift region photomask for insulating dielectric layer photolithography and SAB material etching in LDMOS device manufacturing, the problem of balancing low on-resistance and high withstand voltage HCI reliability was solved, achieving cost control and process optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CSMC TECH FAB2 CO LTD
- Filing Date
- 2024-12-26
- Publication Date
- 2026-06-26
AI Technical Summary
Existing LDMOS devices struggle to achieve both low on-resistance and high voltage withstand capability for HCI reliability, and increasing the number of photolithography layers leads to increased process complexity and cost.
By using a drift region photomask to perform photolithography on the insulating dielectric layer, a thicker dielectric layer is formed. Combined with the etching of SAB material, this avoids increasing the number of photolithography layers and improves HCI reliability.
Without increasing the number of photolithography layers, the HCI reliability of LDMOS devices is improved and the on-resistance is reduced, thus optimizing the competitiveness of the BCD platform.
Smart Images
Figure CN122294538A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to an LDMOS device and a method for manufacturing an LDMOS device. Background Technology
[0002] As a core device in BCD (Bipolar-CMOS-DMOS) technology, LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) typically requires low on-resistance and high voltage withstand capability, and we also hope that LDMOS can have good HCI (Hot Carrier Influence) reliability. Summary of the Invention
[0003] Therefore, it is necessary to provide an LDMOS device and its manufacturing method that can balance low on-resistance and good HCI reliability.
[0004] A method for manufacturing an LDMOS device includes: performing a first photolithography using a drift region photomask to form a photoresist pattern as a drift region implantation barrier layer on a first main surface of a wafer; implanting ions of a first conductivity type into the wafer on which the drift region implantation barrier layer is formed to form a drift region; removing the drift region implantation barrier layer and forming an insulating dielectric layer on the first main surface; and performing a second photolithography using the drift region photomask to form a photoresist pattern as an etch barrier layer on the insulating dielectric layer; wherein the photoresists used in the first and second photolithography have opposite photosensitivity. The patterns of the drift region injection barrier layer and the etch barrier layer are complementary on a plane; the insulating dielectric layer is etched, and then the etch barrier layer is removed; a gate dielectric layer, a gate, a source region, and a drain region are formed, the gate extending onto the insulating dielectric layer, the thickness of the insulating dielectric layer being greater than the thickness of the gate dielectric layer; an SAB material is formed on the first main surface; the SAB material is patterned by photolithography and etching to form a metal silicide barrier layer, the insulating dielectric layer directly above the drain region is over-etched away, and the source and drain regions are located on either side of the remaining insulating dielectric layer.
[0005] The aforementioned method for manufacturing LDMOS devices enhances the dielectric layer thickness at the point of strongest impact ionization by adding an insulating dielectric layer, thereby achieving better HCI reliability. Furthermore, the photolithography of the insulating dielectric layer utilizes a drift region photomask, which does not increase the number of photomasks, thus controlling manufacturing costs.
[0006] In one embodiment, the step of performing the first photolithography using the drift region photomask is to perform photolithography using positive photoresist, and the step of performing the second photolithography using the drift region photomask is to perform photolithography using negative photoresist.
[0007] In one embodiment, after the step of patterning the SAB material by photolithography and etching to form a metal silicide barrier layer, the method further includes: forming a field plate structure on the insulating dielectric layer.
[0008] In one embodiment, the step of forming a field plate structure on the insulating dielectric layer includes: forming an interlayer dielectric layer on the first main surface; photolithographically etching the interlayer dielectric layer to form a field plate hole, the bottom of the field plate hole extending to the metal silicide barrier layer; and filling the field plate hole with a conductive material.
[0009] In one embodiment, the step of photolithography and etching the interlayer dielectric further includes forming a source contact hole, and the step of filling the field plate hole with conductive material further includes filling the source contact hole with conductive material; after the step of filling the field plate hole with conductive material, the method further includes forming a first metal interconnect on the interlayer dielectric layer, the first metal interconnect being electrically connected to the conductive material in the field plate hole and the source contact hole.
[0010] In one embodiment, prior to the first photolithography step using a drift region photomask, the process includes: forming a buried region in the wafer by ion implantation; forming an isolation trap region with an annular structure on the buried region, the isolation trap region and the buried region having the same conductivity type; forming an insulating isolation structure to define an active region; wherein the drift region, source region and drain region are formed within the region surrounded by the annular structure.
[0011] In one embodiment, prior to the step of performing the first photolithography using the drift region photomask, the method further includes the step of forming a first well region and a second well region, wherein the first well region is formed in the isolation well region and the second well region is formed on the outside of the annular structure; the first well region has the same conductivity type as the isolation well region and the doping concentration is greater than that of the isolation well region; the second well region has the same conductivity type as the substrate of the wafer.
[0012] In one embodiment, after the step of removing the etch barrier layer and before the step of forming SAB material on the first main surface, the method further includes forming a body region within the region surrounded by the annular structure. The body region is formed on the side of the drift region away from the isolation well region, and the conductivity type of the body region is opposite to that of the source region. The source region is formed within the body region. After the step of removing the etch barrier layer and before the step of forming SAB material on the first main surface, the method further includes forming an isolation lead-out region in the first well region and forming a substrate lead-out region in the second well region. The conductivity type of the isolation lead-out region is the same as that of the first well region, and the doping concentration is greater than that of the first well region. The conductivity type of the substrate lead-out region is the same as that of the second well region, and the doping concentration is greater than that of the second well region.
[0013] In one embodiment, the SAB material is silicon oxide.
[0014] In one embodiment, the step of forming a metal silicide barrier layer by patterning the SAB material through photolithography and etching, and removing the insulating dielectric layer directly above the drain region by over-etching, adopts an etching endpoint detection method, and stops etching when the etching reaches the silicon layer below the insulating dielectric layer.
[0015] An LDMOS device is manufactured according to the manufacturing method of an LDMOS device according to any of the foregoing embodiments. Attached Figure Description
[0016] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.
[0017] Figure 1 This is a schematic diagram of an exemplary NLDMOS structure.
[0018] Figure 2 This is a schematic diagram of another exemplary NLDMOS structure.
[0019] Figure 3 This is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of this application.
[0020] Figures 4a to 4f Is adopted Figure 3 This is a schematic diagram of the structure of an LDMOS device during the manufacturing process in one embodiment of the method shown.
[0021] Figure 5 This is a flowchart of the sub-steps before step S310 in the manufacturing method of an LDMOS device in one embodiment of this application.
[0022] Figure 6 This is a flowchart of a sub-step of step S390 in one embodiment of this application. Detailed Implementation
[0023] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0026] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0028] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.
[0029] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.
[0030] One of the most widespread applications of LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) in BCD (Bipolar-CMOS-DMOS) processes with exemplary critical dimensions of 0.11 micrometers to 0.18 micrometers is as a switching transistor. Taking high-side (HS) NLDMOS as an example, for the sake of low on-resistance (Low Rdson), one NLDMOS structure is as follows... Figure 1 As shown.
[0031] Figure 1 The structure shown is often affected by the gate oxide thickness and the carrier concentration on the Nshift surface of the drift region, resulting in the strongest collisional ionization sites being concentrated at the gate oxide interface at the Poly (polycrystalline silicon) boundary (i.e., Figure 1 The HCI in LDMOS transistors is a weak point, which can lead to various reliability issues (such as VTS / HCI / HTRB). To improve reliability, one exemplary approach is to form an STI structure in the drift region. However, this STI structure prevents current from flowing through the surface of the drift region, resulting in excessively high channel resistance, making it unsuitable for use as an LDMOS switch.
[0032] Figure 2 Another exemplary NLDMOS structure is formed in which an oxide layer OX with a thickness greater than the gate oxide layer is formed at the position of the drift region Nshift near the polysilicon gate (i.e., the JFET region and the front end of the drift region near the JFET region). Figure 2 (The location indicated by the middle arrow). Specifically, after forming the drift region Nshift, an oxide layer can be formed on the front side of the wafer, and then the OX can be formed by photolithography and etching using a TUN layer photomask. This OX can significantly improve the impact ionization degree at the front end of the drift region, reduce the electric field of the drift region near the sidewalls (spacers) of the polysilicon gate, and thus greatly improve the HCI of the device, achieving a balance between the low on-resistance and high reliability of NLDMOS. However, Figure 2 The scheme shown is relative to Figure 1 This requires adding a TUN layer photomask and incurring corresponding process costs. Furthermore, from a process window perspective, the addition of the TUN layer photomask also introduces additional overlay errors. Figure 1 The photolithography of the drift region N-shift is aligned with the active region SDG, and the photolithography of the polysilicon gate (Poly) is also aligned with the active region SDG. Therefore, only the alignment deviation between the drift region N-shift and the polysilicon gate (Poly) photolithography layers needs to be considered. Figure 2 However, the proposed solution introduces additional photomask alignment errors between the drift region Nshift and the TUN layer, as well as between the TUN layer and the polysilicon gate (Poly), making the process more difficult to control and requiring stricter process window management.
[0033] This application proposes a unique method for manufacturing LDMOS devices, which can effectively reduce the HCI reliability risk of LDMOS without increasing the number of photolithography layers. Furthermore, by sufficiently expanding the reliability window while keeping Rdson constant, Rdson can be further reduced by sacrificing some reliability process window, thereby improving the overall competitiveness of the BCD platform.
[0034] Figure 3 This is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of this application, including the following steps:
[0035] S310 uses a drift region photomask for photolithography to form a photoresist pattern that serves as a barrier layer for drift region injection.
[0036] Photoresist is coated onto the first major surface of the wafer (i.e., the front side of the wafer), and then exposed using a drift area photomask. After development, it forms... Figure 4a The photoresist pattern shown is 192. Figures 4a to 4f The structure shown is symmetrical from left to right, so some structures are only labeled on one side.
[0037] Reference Figure 5 In one embodiment of this application, the following steps are included before step S310:
[0038] S302 is formed in the wafer by ion implantation to create a buried region.
[0039] In one embodiment of this application, a buried region 112 can be formed in a substrate 110 by photolithography and ion implantation. In one embodiment of this application, ions of a first conductivity type are implanted, the buried region 112 has a first conductivity type, and the substrate 110 has a second conductivity type. The device shown in FIG4 is an NLDMOS, and correspondingly, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.
[0040] S304 forms an isolation trap area with a ring structure in the burial area.
[0041] In one embodiment of this application, a second conductivity type layer 111 (located on the buried region 112) is epitaxially formed on the substrate 110, and then an isolation well region 124 with a ring structure is formed on the buried region 112 by photolithography and ion implantation. The isolation well region 124 and the buried region 112 have the same conductivity type.
[0042] S306 forms an insulating and isolation structure to define the active region.
[0043] The active region is located where the insulating isolation structure 162 is not provided. In one embodiment of this application, the insulating isolation structure 162 is a shallow trench isolation structure (STI).
[0044] S308 forms the first and second well regions.
[0045] A first well region 122 and a second well region 128 are formed by photolithography and ion implantation, respectively. The first well region 122 is formed within an isolation well region 124, and the second well region 128 is formed outside the annular isolation well region 124. The first well region 122 has the same conductivity type as the isolation well region 124, but its doping concentration is higher than that of the isolation well region 124. The second well region 128 has the same conductivity type as the substrate 110.
[0046] After step S308 is completed, proceed to step S310. After step S310 is completed, proceed to step S320.
[0047] S320, implanting ions of the first conductivity type into the wafer in which the drift region implantation barrier layer has been formed, to form the drift region.
[0048] In one embodiment of this application, a photoresist pattern 192 is used as an injection barrier layer to implant ions of a first conductivity type to form a drift region 132.
[0049] S330, after removing the drift region injection barrier layer, forms an insulating dielectric layer on the front side of the wafer.
[0050] After the resist is removed, an insulating dielectric layer 164 is formed on the front side of the wafer. In one embodiment of this application, the insulating dielectric layer 164 is made of silicon oxide, such as silicon dioxide. In one embodiment of this application, the insulating dielectric layer 164 is formed by chemical vapor deposition (CVD).
[0051] S340 uses a drift region photomask for photolithography to form a photoresist pattern that serves as an etch barrier layer.
[0052] Photolithography is performed using the same drift region photomask as in step S310, and the photoresists used in step S310 and step S340 have opposite photosensitivity, i.e., one is a positive photoresist and the other is a negative photoresist. In this way, the photoresist pattern 192 formed in step S310 and the photoresist pattern 194 formed in step S340 are complementary on the plane.
[0053] S350, etch the insulating dielectric layer, and then remove the etching barrier layer.
[0054] Using photoresist pattern 194 as an etch barrier layer, the insulating dielectric layer 164 is etched to obtain... Figure 4c The structure shown is then removed.
[0055] S360 forms the gate dielectric layer, gate, source region, and drain region.
[0056] The thickness of the gate dielectric layer 145 is less than the thickness of the insulating dielectric layer 164. In one embodiment of this application, the gate dielectric layer 145 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 145 may comprise a generally higher dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
[0057] In one embodiment of this application, the gate 146 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 146.
[0058] A gate 146 is formed over the region between the source region 142 and the drain region 144. In one embodiment of this application, the source region 142 and the drain region 144 have a first conductivity type. The drift region 132, the source region, and the drain region 144 are located within the region surrounded by the isolation trap region 124 of the annular structure.
[0059] In one embodiment of this application, step S360 further includes forming a body region 126 within the region surrounded by the isolation well region 124 of the annular structure. Further, the body region 126 may be formed before the gate 146 is formed. The body region 126 is located on the side of the drift region 132 away from the isolation well region 124. The body region 126 has a second conductivity type, and the source region 142 is formed within the body region 126.
[0060] In one embodiment of this application, step S360 further includes forming a body lead-out region 141 in the body region 126. The body lead-out region 141 has a second conductivity type, and the doping concentration of the body lead-out region 141 is greater than the doping concentration of the body region 126.
[0061] In one embodiment of this application, step S360, after forming the gate 146 and before forming the source region 142 and the drain region 144, further includes the steps of forming the LDD region and forming the sidewall 147.
[0062] In one embodiment of this application, step S360 further includes forming an isolation lead-out region 138 in the first well region 122 and forming a substrate lead-out region 136 in the second well region 128. The isolation lead-out region 138 has the same conductivity type as the first well region 122, and its doping concentration is greater than that of the first well region 122. The substrate lead-out region 136 has the same conductivity type as the second well region 128, and its doping concentration is greater than that of the second well region 128.
[0063] S370 forms SAB material on the front side of the wafer.
[0064] Self-aligned metallicide (salicide) is a relatively simple and convenient contact metallization process. During the fabrication of semiconductor devices, some areas require the salicide process, while others require a non-salicide process. For devices requiring a non-salicide process, the properties of salicide are utilized by covering the areas requiring non-salicide with a material that does not react with metal (i.e., SAB material). This material used to cover non-salicide devices is called a self-aligned silicide barrier (SAB). In one embodiment of this application, the SAB material 151 is silicon oxide, such as silicon dioxide.
[0065] S380 forms a metal silicide barrier layer by patterning SAB material through photolithography and etching.
[0066] See Figure 4d and Figure 4e The SAB material 151 is patterned by photolithography and etching to form a metal silicide barrier layer 152. Since the insulating dielectric layer 164 obtained in step S350 still obscures the drain region 144, during step S380 when etching the SAB material 151, the portion of the insulating dielectric layer 164 not obscured by the photoresist 196 (e.g., directly above the drain region 144) is removed by over-etching. The source region 142 and drain region 144 are located on either side of the remaining insulating dielectric layer 164. After step S380, the upper surfaces of the source region 142, drain region 144, gate 146, and other structures are salinated.
[0067] The aforementioned LDMOS device manufacturing method enhances the dielectric layer thickness at the point of strongest impact ionization by adding an insulating dielectric layer 164, thereby achieving better HCI reliability. Furthermore, the photolithography of the insulating dielectric layer 164 utilizes a drift region photomask, which does not increase the number of photomasks, thus controlling manufacturing costs. Compared to... Figure 2The scheme shown does not introduce a new lithography layer (i.e., the TUN layer), so there is no overlay error between the TUN layer and the drift region lithography / polysilicon gate lithography.
[0068] In one embodiment of this application, the etching in step S380 adopts an end-point detection method, and the etching stops when the silicon layer below the insulating dielectric layer 164 is detected.
[0069] In one embodiment of this application, after step S380, step S390 is further included: forming a field plate structure on the insulating dielectric layer 164. See also Figure 6 In one embodiment of this application, step S390 specifically includes:
[0070] S392 forms an interlayer dielectric layer on the front side of the wafer.
[0071] Interlayer dielectric (ILD) Figure 4f (Not shown) The layer can be silicon oxide, such as a doped or undoped silicon oxide material layer formed using thermal chemical vapor deposition (TCVD) or high-density plasma chemical vapor deposition (HDPCVD) processes. Specifically, it can be undoped silicon glass (USG), phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). Furthermore, the interlayer dielectric can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS), etc.
[0072] S394, photolithography and etching of the interlayer dielectric to form field plate holes.
[0073] The field plate via 154 penetrates the interlayer dielectric layer, and the bottom of the field plate via 154 extends to the metal silicide barrier layer 152. In one embodiment of this application, step S394 further includes forming a source contact via 156.
[0074] S396, fill the holes in the field plate with conductive material.
[0075] The conductive material can be a metal and / or an alloy. In one embodiment of this application, a tungsten plug is formed in the field plate hole 154 as a hole field plate. In one embodiment of this application, step S396 further includes filling the source contact hole 156 with conductive material.
[0076] In one embodiment of this application, step S396 is followed by a step of forming a first metal interconnect 172 on the interlayer dielectric layer. See also Figure 4fThe first metal interconnect 172 is electrically connected to the conductive material in the field plate hole 154 and the source contact hole 156. In one embodiment of this application, the isolation lead-out area 138 is connected through the contact hole above it ( Figure 4f (Not marked in the text) is electrically connected to the first metal connection 172.
[0077] exist Figure 4f In the illustrated embodiment, the buried region 112, the first well region 122, the isolation well region 124, the drift region 132, the isolation lead-out region 138, the source region 142, and the drain region 144 are all N-type. The isolation well region 124 is a deep N-well, the buried region 112 is an N-type buried layer, and the isolation lead-out region 138, the source region 142, and the drain region 144 are N+ regions. The substrate 110, the second conductivity type layer 111, the body region 126, the second well region 128, the substrate lead-out region 136, and the body lead-out region 141 are all P-type. The substrate lead-out region 136 is a P+ region.
[0078] Based on all the above embodiments, the LDMOS device manufacturing method of this application uses a drift region photolithography + negative resist secondary photolithography method to create an insulating dielectric layer 164 as a field plate that is not affected by overlay deviation. Simultaneously, the existing SAB etching is used to perform a secondary etching on this field plate, ensuring that the complete metallization of the drain terminal is not affected, achieving high reliability and low channel resistance without adding a mask layer. Furthermore, the CVD formation of this field plate has virtually no impact on other devices on the process platform. The field plate formed by the combination of the drift region photolithography and SAB photolithography processes will not affect other devices on the BCD process platform that also use drift region photolithography. For example, DENMOS (Drain Extension NMOS) can achieve higher reliability with the addition of an HTO (Rapid Thermal Oxidation) field plate. For option devices made using NG, the presence of SAB only results in a slightly thicker SAB dielectric, which generally has no impact. Therefore, it is suitable for further upgrades and optimizations of already solidified platforms.
[0079] This application also provides an LDMOS device manufactured according to the manufacturing method of any of the foregoing embodiments.
[0080] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0081] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0082] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0083] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for manufacturing an LDMOS device, comprising: The first photolithography is performed using a drift region photomask to form a photoresist pattern on the first main surface of the wafer, which serves as a drift region injection barrier layer. Implanting ions of a first conductivity type into a wafer in which the drift region implantation barrier layer is formed, thereby forming a drift region; After removing the injection barrier layer in the drift region, an insulating dielectric layer is formed on the first main surface; A second photolithography is performed using the drift region photomask to form a photoresist pattern as an etch barrier layer on the insulating dielectric layer; the photoresists used in the first and second photolithography have opposite photosensitivity, and the patterns of the drift region injection barrier layer and the etch barrier layer are complementary in the plane. The insulating dielectric layer is etched, and then the etching barrier layer is removed; A gate dielectric layer, a gate, a source region, and a drain region are formed, wherein the gate extends onto the insulating dielectric layer, and the thickness of the insulating dielectric layer is greater than the thickness of the gate dielectric layer; SAB material is formed on the first main surface; The SAB material is patterned by photolithography and etching to form a metal silicide barrier layer. The insulating dielectric layer directly above the drain region is over-etched away, and the source and drain regions are located on both sides of the remaining insulating dielectric layer.
2. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The step of performing the first photolithography using the drift region photomask is to perform photolithography using positive photoresist, and the step of performing the second photolithography using the drift region photomask is to perform photolithography using negative photoresist.
3. The method for manufacturing an LDMOS device according to claim 1, characterized in that, After the step of patterning the SAB material by photolithography and etching to form a metal silicide barrier layer, the method further includes: forming a field plate structure on the insulating dielectric layer.
4. The method for manufacturing an LDMOS device according to claim 3, characterized in that, The step of forming the field plate structure on the insulating dielectric layer includes: An interlayer dielectric layer is formed on the first main surface; The interlayer dielectric layer is photolithographically etched to form field plate holes, the bottom of which extends to the metal silicide barrier layer. The field plate holes are filled with conductive material.
5. The method for manufacturing an LDMOS device according to claim 4, characterized in that, The step of photolithography and etching the interlayer dielectric further includes forming a source contact hole, and the step of filling the field plate hole with conductive material further includes filling the source contact hole with conductive material; After the step of filling the field plate hole with conductive material, the method further includes: forming a first metal interconnect on the interlayer dielectric layer, wherein the first metal interconnect is electrically connected to the conductive material in the field plate hole and the source contact hole.
6. The method for manufacturing an LDMOS device according to claim 1, characterized in that, Before the step of performing the first photolithography using the drift region photomask, the following steps are included: A buried region is formed in the wafer by ion implantation; An isolation trap region with a ring structure is formed on the buried area, and the isolation trap region and the buried area have the same conductivity type; An insulating and isolating structure is formed to define the active region; The drift region, source region, and drain region are formed within the area surrounded by the annular structure.
7. The method for manufacturing an LDMOS device according to claim 6, characterized in that, Before the step of performing the first photolithography using the drift region photomask, the method further includes the step of forming a first well region and a second well region. The first well region is formed in the isolation well region, and the second well region is formed on the outside of the annular structure. The first well region has the same conductivity type as the isolation well region, and its doping concentration is greater than that of the isolation well region. The second well region has the same conductivity type as the substrate of the wafer.
8. The method for manufacturing an LDMOS device according to claim 7, characterized in that, After the step of removing the etch barrier layer and before the step of forming SAB material on the first main surface, the method further includes the step of forming a body region within the area surrounded by the annular structure. The body region is formed on the side of the drift region away from the isolation trap region, and the conductivity type of the body region is opposite to that of the source region. The source region is formed within the body region. After the step of removing the etch barrier layer and before the step of forming SAB material on the first main surface, the method further includes the steps of forming an isolation lead-out region in the first well region and forming a substrate lead-out region in the second well region; the conductivity type of the isolation lead-out region is the same as that of the first well region, and the doping concentration is greater than that of the first well region; the conductivity type of the substrate lead-out region is the same as that of the second well region, and the doping concentration is greater than that of the second well region.
9. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The SAB material is silicon oxide; and / or The step of forming a metal silicide barrier layer by patterning the SAB material through photolithography and etching, and removing the insulating dielectric layer directly above the drain region by over-etching, adopts an etching endpoint detection method, and stops etching when the etching reaches the silicon layer below the insulating dielectric layer.
10. An LDMOS device, characterized in that, The LDMOS device is manufactured according to any one of claims 1-9.