Display device and electronic device

Abstract

This application relates to display devices and electronic devices. The display device includes a base layer, a first wiring line, a second wiring line, and an inorganic insulating layer. The base layer has a first region having a display area, a second region spaced apart from the first region in a first direction, and a curved region between the first and second regions. The first wiring line overlaps with the second region and extends in the first direction. The second wiring line overlaps with the curved region and is electrically connected to the first wiring line. The inorganic insulating layer is disposed on the first wiring line and includes an opening overlapping a contact portion connecting the first and second wiring lines. The opening is defined by a first side surface extending in the first direction, a second side surface extending in a second direction intersecting the first direction, and a third side surface connecting the first and second side surfaces and having a curved shape.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0195119, filed on December 24, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to display devices and electronic devices, and more specifically, to display devices and electronic devices with improved reliability. Background Technology

[0004] Display devices such as televisions, monitors, smartphones, and tablet computers use display panels to provide images to users. Various types of display panels have been developed, including, for example, liquid crystal display panels, organic light-emitting diode (OLED) display panels, electrowetting display panels, and electrophoretic display panels.

[0005] The touch insulating layer can include inorganic and organic insulating layers. In this case, the inorganic insulating layer can also be located in the pad area where the solder pads are situated. When the inorganic insulating layer is oxidized, hydrogen radicals and ammonia gas may be released. When the hydrogen radicals and ammonia gas reach the underlying conductive layer, the underlying conductive layer may also be oxidized. Summary of the Invention

[0006] This disclosure provides a display device and an electronic device that can prevent or reduce cracking in the inorganic layer adjacent to a bending region, thereby improving the reliability of the display device.

[0007] According to an embodiment, the display device includes: a base layer including a first region containing a display area, a second region spaced apart from the first region in a first direction, and a curved region disposed between the first region and the second region; a first wiring line overlapping the second region and extending in the first direction; a second wiring line overlapping the curved region and electrically connected to the first wiring line; and an inorganic insulating layer disposed on the first wiring line, and defining an opening in the inorganic insulating layer that overlaps with a contact portion, in which the first wiring line and the second wiring line are connected to each other. The inorganic insulating layer includes: a first side surface extending in the first direction; a second side surface extending in a second direction intersecting the first direction; and a third side surface connecting the first side surface and the second side surface, and having a curved shape in a plan view. The opening is defined by the first side surface to the third side surface.

[0008] According to an embodiment, the display device includes: a base layer including a first region, a second region spaced apart from the first region in a first direction, and a curved region disposed between the first region and the second region; a first wiring line overlapping the second region and extending in the first direction; a second wiring line overlapping the curved region and electrically connected to the first wiring line; and an inorganic insulating layer disposed on the first wiring line, and defining an opening in the inorganic insulating layer overlapping the curved region. The inorganic insulating layer includes: a first side surface extending in the first direction; and a second side surface extending in a second direction intersecting the first direction. In a plan view, the second side surface is spaced apart from the curved region in the first direction.

[0009] According to an embodiment, the electronic device includes: a housing; an electronic module disposed inside the housing; and a display device disposed on and overlapping the electronic module. The display device includes: a base layer including a first region, a second region spaced apart from the first region in a first direction, and a curved region disposed between the first and second regions; a first wiring line overlapping the second region and extending in the first direction; a second wiring line overlapping the curved region and electrically connected to the first wiring line; and an inorganic insulating layer disposed on the first wiring line, defining an opening in the inorganic insulating layer that overlaps with a contact portion in which the first and second wiring lines are connected to each other. The inorganic insulating layer includes: a first side surface extending in the first direction; a second side surface extending in a second direction intersecting the first direction; and a third side surface connecting the first and second side surfaces, and having a curved shape in a plan view. The opening is defined from the first side surface to the third side surface. Attached Figure Description

[0010] The above and other objects and features of this disclosure will become more apparent from a detailed description of the embodiments of this disclosure with reference to the accompanying drawings.

[0011] Figure 1A This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0012] Figures 1B to 1D An electronic device according to an embodiment of the present disclosure is shown.

[0013] Figure 2 This is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0014] Figure 3 This is a perspective view of an electronic device according to an embodiment of the present disclosure, showing... Figure 2 The folded state of the electronic device.

[0015] Figure 4 This is a perspective view of an electronic device according to an embodiment of the present disclosure, showing... Figure 2 The folded state of the electronic device.

[0016] Figure 5 This is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0017] Figure 6A and Figure 6B This is a cross-sectional view of the display module according to the implementation method.

[0018] Figure 7 This is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0019] Figure 8 This is a plan view of a display panel according to an embodiment of the present disclosure.

[0020] Figure 9A This is an enlarged view of a portion of the display panel according to an embodiment of the present disclosure.

[0021] Figure 9B This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0022] Figure 10 yes Figure 9A An enlarged view of region CC' shown in the image.

[0023] Figure 11 This is an enlarged view of a portion of the display panel according to an embodiment of the present disclosure.

[0024] Figure 12 This is an enlarged view of a portion of the display panel according to an embodiment of the present disclosure. Detailed Implementation

[0025] In the following description, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0026] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0027] It should be understood that, unless the context clearly indicates otherwise, the description of a feature or aspect within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments.

[0028] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well.

[0029] Spatial relative terms such as “below,” “under,” “down,” “below,” “above,” and “above” may be used herein for ease of description to describe the relationship between one element or feature and another element(s) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are intended to also encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can encompass both above and below orientations.

[0030] It will be understood that when a component is referred to as being "on" another component, "connected to," "linked to," or "adjacent to" another component, it may be directly on, directly connected to, directly linked to, or directly adjacent to the other component, or there may be intervening components. It will also be understood that when a component is referred to as being "between" two components, it may be the only component between the two components, or there may be one or more intervening components. It will also be understood that when a component is referred to as "covering" another component, it may be the only component covering the other component, or it may be one or more intervening components covering the other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0031] In this document, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it should be understood that the elements or values ​​are the same, the elements or values ​​are equal to each other within measurement error, or, if measurably unequal, are sufficiently close in value to be functionally equal to each other, as will be understood by one of ordinary skill in the art. For example, given the measurement in question and the error associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the term “about” as used herein includes the value and means within an acceptable deviation of a particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations as understood by one of ordinary skill in the art, such as within ±30%, ±20%, ±10%, or ±5% of the value. Furthermore, it should be understood that although a parameter may be described herein as having “about” a certain value, according to an implementation, the parameter may be an exact value, or approximately a value within measurement error as will be understood by one of ordinary skill in the art. Other uses of these terms and similar terms used to describe relationships between components should be interpreted in a similar manner.

[0032] The term "and / or" includes one or more combinations defined for each relevant element.

[0033] It will be understood that the terms "comprising," "including," "having," etc., specify the presence of features, numbers, steps, operations, elements or components, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements or components, or combinations thereof.

[0034] Flexible display devices are often subjected to mechanical stress, for example, in areas subjected to repeated bending. In such devices, wiring must extend across the bending areas to maintain electrical connections between different functional areas. However, stress concentration at the connection points between these wiring lines (including where the wiring lines are covered by a brittle inorganic insulating layer) can lead to cracking and degradation over time.

[0035] This disclosure addresses the problem by providing a display device in which, when viewed in a plan view, an inorganic insulating layer disposed throughout the wiring connection area in or near a curved region includes a curved side surface. The curved geometry of the openings in the insulating layer can help distribute mechanical stress more evenly during bending, which can reduce the likelihood of crack formation and improve reliability.

[0036] By implementing this structure, the display device according to the present disclosure can maintain electrical continuity across the flexible region while improving the long-term durability of the wiring and surrounding insulation materials.

[0037] Figure 1A This is a block diagram of an electronic device according to an embodiment of the present disclosure. Figures 1B to 1D An electronic device according to an embodiment of the present disclosure is shown.

[0038] The electronic device ED according to embodiments of this disclosure includes a display device DD (see...) Figure 5 The electronic device ED according to embodiments of this disclosure can be as follows: Figures 2 to 4 The foldable phone shown is an example, but not limited to this.

[0039] like Figure 1A As shown, the electronic device ED outputs various information through the display module 140 in the operating system. When the processor 110 runs an application stored in the memory 120, the display module 140 provides application information to the user through the display panel 141.

[0040] Processor 110 receives external input via input module 130 or sensor module 161 and runs the application corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 141, processor 110 receives user input via input sensor 161-2 and activates camera module 171. Processor 110 transmits image data corresponding to the captured image obtained by camera module 171 to display module 140. Display module 140 can display the image corresponding to the captured image via display panel 141.

[0041] As another example, when authentication of personal information is performed in display module 140, fingerprint sensor 161-1 obtains the input fingerprint information as input data. Processor 110 compares the input data obtained by fingerprint sensor 161-1 with the verification data stored in memory 120, and runs the application based on the comparison result. Display module 140 can display information running according to the application's logic via display panel 141.

[0042] As another example, when a user selects the music stream icon displayed in display module 140, processor 110 obtains user input via input sensor 161-2 and activates the music stream application stored in memory 120. When a music playback command is input to the music stream application, processor 110 activates sound output module 163 and provides the user with sound information corresponding to the music playback command.

[0043] The operation of the electronic device ED has been briefly described above. The configuration of the electronic device ED will be described in detail below. Some of the components of the electronic device ED, which will be further described below, can be implemented integrally with a single component, and this single component can be divided into two or more components.

[0044] refer to Figure 1A The electronic device ED can communicate with the external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to embodiments, the electronic device ED may include a processor 110, a memory 120, an input module 130, a display module 140, a power module 150, an embedded module (or internal module) 160, and an external module 170. According to embodiments, the electronic device ED may not include at least one of the above components, or it may include one or more other components. According to embodiments, some of the above components (e.g., sensor module 161, antenna module 162, or audio output module 163) may be integrated into any other component (e.g., display module 140).

[0045] The processor 110 can run software to control at least one component (e.g., hardware or software component) of the electronic device ED connected to the processor 110, and can perform various data processing or operations. According to embodiments, as at least part of the data processing or operation, the processor 110 can store commands or data received from any other component (e.g., input module 130, sensor module 161, or communication module 173) in volatile memory 121, can process the commands or data stored in volatile memory 121, and can store the processed data in non-volatile memory 122.

[0046] Processor 110 may include a main processor 111 and an auxiliary processor 112. Main processor 111 may include one or more of a central processing unit (CPU) 111-1 and an application processor (AP). Main processor 111 may also include one or more of a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 111 may also include a neural processing unit (NPU) 111-3. Neural processing unit 111-3 may be a processor specifically designed for processing artificial intelligence models, and the artificial intelligence models may be created through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may be deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), deep Q-networks, or combinations of two or more of the networks described above, but are not limited to the examples described above. In addition to the hardware architecture, the artificial intelligence model may additionally or optionally include a software architecture. At least two of the above processing units and processors can be implemented as a single component (e.g., a single chip), or each of the above processing units and processors can be implemented using independent components (e.g., multiple chips).

[0047] The auxiliary processor 112 may include a controller 112-1. The controller 112-1 may include interface conversion circuitry and timing control circuitry. The controller 112-1 receives image signals from the main processor 111 and outputs image data obtained by converting the data format of the image signals to suit the specifications of the interface with the display module 140. The controller 112-1 may output various control signals required to drive the display module 140.

[0048] The auxiliary processor 112 may also include a data conversion circuit 112-2, a gamma correction circuit 112-3, a rendering circuit 112-4, etc. The data conversion circuit 112-2 can receive image data from the controller 112-1. The data conversion circuit 112-2 can compensate the image data to display an image at a desired brightness according to the characteristics of the electronic device ED or user settings, or it can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit 112-3 can convert the image data or a gamma reference voltage so that the image displayed on the electronic device ED has desired gamma characteristics. The rendering circuit 112-4 can receive image data from the controller 112-1 and can render the image data based on the pixel arrangement of the display panel 141 applied to the electronic device ED. At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into any other component (e.g., the main processor 111 or the controller 112-1). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into the data driver 143, which will be described further below.

[0049] The memory 120 may store various data used by at least one component of the electronic device ED (e.g., processor 110 or sensor module 161), as well as input or output data for commands associated therewith. The memory 120 may include at least one of volatile memory 121 and non-volatile memory 122.

[0050] The input module 130 can receive commands or data from outside the electronic device ED (e.g., from a user or external electronic device 102) that will be used by components of the electronic device ED (e.g., processor 110, sensor module 161, or sound output module 163).

[0051] Input module 130 may include a first input module 131 for inputting commands or data from a user and a second input module 132 for inputting commands or data from an external electronic device 102. The first input module 131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 132 may support a specified protocol enabling wired or wireless connection to the external electronic device 102. According to embodiments, the second input module 132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 132 may include a connector (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)) capable of physically connecting to the external electronic device 102.

[0052] Display module 140 provides information to the user visually. Display module 140 may include display panel 141, scan driver 142, and data driver 143. Display module 140 may also include a window, housing, and bracket to protect display panel 141.

[0053] The display panel 141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of display panel 141 is not particularly limited. The display panel 141 may be of a rigid type or a flexible type that can be rolled up or folded. The display module 140 may also include a support member, bracket, or heat dissipation member that supports the display panel 141.

[0054] The scan driver 142 can be mounted as a driver chip on the display panel 141. Alternatively, the scan driver 142 can be integrated into the display panel 141. For example, the scan driver 142 may include an amorphous silicon TFT gate driver circuit (ASG), a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) built into the display panel 141. The scan driver 142 receives a control signal from the controller 112-1 and outputs a scan signal to the display panel 141 in response to the control signal.

[0055] The display panel 141 may also include a transmitter driver. The transmitter driver outputs a light emission control signal to the display panel 141 in response to a control signal received from the controller 112-1. The transmitter driver may be configured separately from the scan driver 142, or it may be integrated into the scan driver 142.

[0056] The data driver 143 receives a control signal from the controller 112-1, converts the image data into an analog voltage (e.g., a data voltage) in response to the control signal, and outputs the data voltage to the display panel 141.

[0057] The data driver 143 can be integrated into other components (e.g., controller 112-1). The functions of the interface conversion circuit and timing control circuit of the controller 112-1 described above can be integrated into the data driver 143.

[0058] The display module 140 may also include a voltage generator, etc. The voltage generator can output various types of voltages for driving the display panel 141.

[0059] Power module 150 supplies power to components of electronic device ED. Power module 150 may include a battery that is charged to a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable rechargeable battery, or a fuel cell. Power module 150 may include a power management integrated circuit (PMIC). The PMIC provides power for each of the modules described above and further described below. Power module 150 may include a wireless power transmission / reception component electrically connected to the battery. The wireless power transmission / reception component may include multiple antenna radiators in the form of coils.

[0060] The electronic device ED may also include an embedded module 160 and an external module 170. The embedded module 160 may include a sensor module 161, an antenna module 162, and a sound output module 163. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0061] Sensor module 161 can sense input from the user's body or from the pen in the first input module 131, and can generate an electrical signal or data value corresponding to the input. Sensor module 161 may include at least one of fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3.

[0062] The fingerprint sensor 161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 161-1 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0063] Input sensor 161-2 can generate data values ​​corresponding to the coordinate information of the user's body input or pen input. Input sensor 161-2 generates data values ​​from the capacitance changes caused by the input. Input sensor 161-2 can sense input from a passive pen or exchange data with an active pen.

[0064] Input sensor 161-2 can measure biometric signals such as blood pressure, humidity, or body fat. For example, when a user touches a part of his / her body to the sensor layer or sensing panel and does not move it for a given period of time, input sensor 161-2 can detect biometric signals based on changes in the electric field caused by the body part and can output the information desired by the user to display module 140.

[0065] The digitizer 161-3 can generate data values ​​corresponding to the coordinate information input by the pen. The digitizer 161-3 generates data values ​​from the electromagnetic changes caused by the input. The digitizer 161-3 can sense input from a passive pen or exchange data with an active pen.

[0066] At least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be implemented using a sensor layer formed on the display panel 141 by a continuous process. The fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be disposed above / on the display panel 141, and at least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 (e.g., digitizer 161-3) can be disposed below / under the display panel 141.

[0067] At least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be integrally formed with a sensing panel using the same process. When these components are integrally formed with a sensing panel, the sensing panel can be positioned between the display panel 141 and a window positioned above / on the display panel 141. According to an embodiment, the sensing panel can be positioned on the window. However, the position of the sensing panel is not particularly limited.

[0068] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be embedded in the display panel 141. That is, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements and transistors) included in the display panel 141.

[0069] Furthermore, sensor module 161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device ED. Sensor module 161 may also include, for example, gesture sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0070] Antenna module 162 may include one or more antennas to transmit or receive signals or power from an external source. According to an embodiment, communication module 173 may transmit or receive signals from external electronic device 102 via an antenna suitable for a communication method. The antenna pattern of antenna module 162 may be integrated with a component of display module 140 (e.g., display panel 141) or input sensor 161-2.

[0071] The sound output module 163, which serves as a means of outputting sound signals to the external electronic device ED, may include, for example, a speaker for general purposes (such as multimedia playback or recording playback) and a receiver specifically for receiving calls. Depending on the implementation, the receiver and speaker may be integrated or implemented separately. The sound output pattern of the sound output module 163 may be integrated with the display module 140.

[0072] Camera module 171 can capture still images or moving images (e.g., video). According to embodiments, camera module 171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0073] The light module 172 can provide light. The light module 172 may include a light-emitting diode or a xenon lamp. The light module 172 can operate together with the camera module 171, or it can operate independently.

[0074] Communication module 173 can establish a wired or wireless communication channel between electronic device ED and external electronic device 102, and can support communication through the established communication channel. Communication module 173 may include one or all of the following: a wireless communication module (such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) and a wired communication module (such as a local area network (LAN) communication module or a power line communication module). Communication module 173 can communicate with external electronic device 102 via short-range communication networks such as Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA) or long-range communication networks such as cellular networks, the Internet, or computer networks (e.g., LANs or WANs). The various types of communication modules 173 described above can be implemented using a single chip or separate chips.

[0075] The input module 130, sensor module 161, camera module 171, etc., can be used in conjunction with the processor 110 to control the operation of the display module 140.

[0076] The processor 110 outputs commands or data to the display module 140, the sound output module 163, the camera module 171, or the optical module 172 based on the input data received from the input module 130. For example, in one embodiment, the processor 110 can generate image data corresponding to the input data applied by a mouse or active pen, and can output the image data to the display module 140. In another embodiment, the processor 110 can generate command data corresponding to the input data, and can output the command data to the camera module 171 or the optical module 172. When no input data is received from the input module 130 during a given time period, the processor 110 can switch the operating mode of the electronic device ED to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device ED.

[0077] Processor 110 outputs commands or data to display module 140, sound output module 163, camera module 171, or optical module 172 based on sensing data received from sensor module 161. For example, processor 110 can compare authentication data applied by fingerprint sensor 161-1 with authentication data stored in memory 120, and then run an application based on the comparison result. Processor 110 can run commands based on sensing data sensed by input sensor 161-2 or digitizer 161-3, or it can output image data corresponding to the sensing data to display module 140. When sensor module 161 includes a temperature sensor, processor 110 can receive temperature data related to the measured temperature from sensor module 161, and can also perform brightness correction on image data based on the temperature data.

[0078] Processor 110 can receive measurement data from camera module 171 regarding the presence or absence of a user, the user's position, and the user's line of sight. Processor 110 can also perform brightness correction on image data based on the measurement data. For example, processor 110, which determines the presence or absence of a user based on input from camera module 171, can display image data whose brightness has been corrected by data conversion circuit 112-2 or gamma correction circuit 112-3.

[0079] Some of the above components can be connected to each other via communication schemes between peripheral devices (e.g., buses, general purpose input / output (GPIO), serial peripheral interfaces (SPI), mobile industrial processor interfaces (MIPI), or hyperpath interconnect (UPI) links) and can exchange signals (e.g., commands or data). Processor 110 can communicate with display module 140 through a given interface. For example, one of the communication methods described above can be used, and this disclosure is not limited thereto.

[0080] According to the various embodiments disclosed in this disclosure, the electronic device ED can include various types of devices. The electronic device ED can include at least one of, for example, portable communication devices (e.g., smartphones), tablet devices, portable multimedia devices, wearable devices, and home appliances. The electronic device ED according to embodiments of this disclosure is not limited to the electronic device ED described above. For example, Figure 1B The augmented reality (AR) glasses shown Figure 1C The various types of vehicle information providing devices shown are Figure 1D The smartwatch shown can be implemented as an electronic device (ED).

[0081] Figure 2 This is a perspective view of an electronic device according to an embodiment of the present disclosure. Figure 3 This is a perspective view of an electronic device according to an embodiment of the present disclosure, showing... Figure 2 The folded state of the electronic device. Figure 4 This is a perspective view of an electronic device according to an embodiment of the present disclosure, showing... Figure 2 The folded state of the electronic device.

[0082] refer to Figure 2 The electronic device ED according to embodiments of the present disclosure may have a rectangular shape having two short sides extending in a first direction DR1 and two long sides extending in a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited thereto, and the electronic device ED may have various shapes such as, for example, circles or other polygons.

[0083] In the following text, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, in this specification, the phrase "when viewed in a plane" can be defined as the state of the object being viewed from the third direction DR3. For example, the phrase "when viewed in a plane" can mean when viewed in a plan view.

[0084] The thickness direction of the electronic device ED can correspond to a third direction DR3, which is the normal direction relative to the plane defined by the first direction DR1 and the second direction DR2. In this specification, the front (or top) surface and rear (or bottom) surface of the component constituting the electronic device ED can be defined relative to the third direction DR3. In this specification, "thickness" can refer to a value measured in the third direction DR3, and "width" can refer to a value measured in the first direction DR1 or the second direction DR2, which is a horizontal direction.

[0085] An electronic device ED according to an embodiment may include a flat display surface DS. An image IM generated by the electronic device ED can be provided to a user through the display surface DS. The display surface DS may include a plane defined by a first direction DR1 and a second direction DR2. However, this disclosure is not limited thereto, and the display surface DS may also include a curved surface that is curved from at least one side of the plane defined by the first direction DR1 and the second direction DR2.

[0086] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. In an embodiment, an image may be displayed in the display area DA, and no image may be displayed in the non-display area NDA. The non-display area NDA may surround the display area DA. However, this disclosure is not limited thereto, and the shape of the display area DA and the non-display area NDA may be modified. In an embodiment, the non-display area NDA may be omitted.

[0087] refer to Figures 2 to 4 The electronic device ED according to the embodiments of this disclosure can be a foldable electronic device.

[0088] The electronic device ED may include a folded region FA and multiple non-folded regions NFA1 and NFA2. For example, the non-folded regions NFA1 and NFA2 may include a first non-folded region NFA1 and a second non-folded region NFA2. The folded region FA may be disposed between the first non-folded region NFA1 and the second non-folded region NFA2. The folded region FA, the first non-folded region NFA1, and the second non-folded region NFA2 may be arranged in a first direction DR1. By way of example, one folded region FA and two non-folded regions NFA1 and NFA2 are shown, but the number of folded regions FA and non-folded regions NFA1 and NFA2 is not limited to this. For example, the electronic device ED may include more than two non-folded regions and multiple folded regions arranged between the non-folded regions.

[0089] like Figure 3 As shown, the folding region FA can be folded relative to a folding axis FX extending in the second direction DR2. The folding region FA has a specific curvature and a specific radius of curvature R1. The first non-folding region NFA1 and the second non-folding region NFA2 can face each other, and the electronic device ED can be folded inward so that the display surface DS is not exposed when folded.

[0090] like Figure 4 As shown, the folding region FA can be folded outward relative to the folding axis FX parallel to the second direction DR2, so that the display surface DS is exposed when folded.

[0091] In embodiments of this disclosure, the electronic device ED can be configured to repeat the inward folding operation or the outward folding operation from the start of the unfolding operation, but this disclosure is not limited thereto. In embodiments of this disclosure, the electronic device ED can be configured to select any one of the unfolding operation, the inward folding operation, and the outward folding operation.

[0092] Figure 5 This is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0093] refer to Figure 5 The electronic device ED may include a display device DD, an electronic module EM, a power module PSM, and a housing HM. In some embodiments, the electronic device ED may also include a mechanical structure for controlling the folding operation of the display device DD. The electronic device ED may also include a photoelectric module for outputting or receiving optical signals. The photoelectric module may include a camera module and / or a proximity sensor.

[0094] The display device DD generates images and detects external input. The display device DD includes a window module WM and a display module DM. The window module WM provides the front surface of the electronic device ED.

[0095] The display module (DM) may include at least one display panel (DP). For example... Figure 5 As shown, the display panel DP is depicted as a representative component of the stacked structure of the display module DM. Although only the display panel DP is shown, according to embodiments, the display module DM may also include additional structural and functional layers disposed on or above the display panel DP. A detailed description of a stacking configuration including such additional layers is provided below.

[0096] The display panel DP is not particularly limited thereto, and for example, the display panel DP can be a light-emitting display panel such as an organic light-emitting display panel or a quantum dot light-emitting display panel. The display panel DP can be a display panel that includes ultra-small light-emitting elements such as micro LEDs or nano LEDs.

[0097] The display panel DP includes the display area DA, which is connected to the electronic device ED (see [link]). Figure 2 ) and non-display area NDA (see Figure 2 The corresponding display area DP-DA and non-display area DP-NDA. In this specification, "area / part corresponds to another area / part" may mean "this area / part overlaps with another area / part", but its meaning is not limited to this.

[0098] like Figure 5As shown, the data driver DDV can be located in the non-display area DP-NDA of the display panel DP. A printed circuit board (PCB) can be connected to the non-display area DP-NDA of the display panel DP. The PCB can be connected to the display panel DP, and a flexible circuit board is inserted between the PCB and the display panel DP.

[0099] Data driver (DDV) can include driving elements (e.g., drivers) that drive the pixels of the display panel (DP). Although Figure 5 The diagram shows a structure in which the data driver DDV is mounted on the display panel DP, but this disclosure is not limited thereto. For example, the data driver DDV may be mounted on a printed circuit board PCB.

[0100] An electronic module (EM) may include, for example, a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, and an external interface module. The module can be mounted on a printed circuit board (PCB) or electrically connected to the PCB via a flexible circuit board. The electronic module (EM) can be electrically connected to a power supply module (PSM).

[0101] An electronic module EM can be disposed in each of the first housing HM1 and the second housing HM2, and a power module PSM can be disposed in each of the first housing HM1 and the second housing HM2. The electronic module EM disposed in the first housing HM1 and the electronic module EM disposed in the second housing HM2 can be electrically connected to each other via a flexible circuit board.

[0102] The Power Supply Module (PSM) supplies power for the overall operation of electronic devices (EDs). The PSM may include a general-purpose battery device.

[0103] The housing HM is coupled to the display device DD (e.g., coupled to the window module WM) to accommodate other modules. Although the housing HM is shown to include a first housing HM1 and a second housing HM2 that are separate from each other, this disclosure is not limited thereto. The electronic device ED may also include a hinge structure connecting the first housing HM1 and the second housing HM2.

[0104] Figure 6A and Figure 6B This is a cross-sectional view of the display module according to the implementation method.

[0105] refer to Figure 6AAccording to embodiments of the present disclosure, the display module DM may include an electronic panel EP. The electronic panel EP may include a display panel DP and an input sensor ISP disposed on the display panel DP. The display panel DP may include a base layer BS, a circuit layer DP-CL disposed on the base layer BS, a light-emitting element layer DP-OLED disposed on the circuit layer DP-CL, and a thin-film encapsulation layer TFE disposed on the light-emitting element layer DP-OLED.

[0106] The display panel DP according to embodiments of this disclosure can be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots or quantum rods. Furthermore, the light-emitting layer of the display panel DP may include micro-LED elements and / or nano-LED elements. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0107] In a display panel (DP), the base layer (BS) can be a component that provides the base surface on which the light-emitting element layer (DP-OLED) is disposed. The base layer (BS) can be, for example, a glass substrate, a metal substrate, a polymer substrate, or the like. However, the implementation is not limited to this, and the base layer (BS) can be, for example, an inorganic layer, a functional layer, or a composite material layer.

[0108] The base layer BS can have a multilayer structure. For example, the base layer BS can have a three-layer structure including a polymer resin layer, an adhesive layer, and a polymer resin layer. For example, the polymer resin layer can include a polyimide-based resin. Furthermore, the polymer resin layer can include at least one of acrylate-based resins, methacrylate-based resins, polyisoprene-based resins, ethylene-based resins, epoxy-based resins, urethane-based resins, cellulose-based resins, siloxane-based resins, polyamide-based resins, and dinoflagellated resins. As used herein, "a-based" resin means resin including the functional group "a".

[0109] The circuit layer DP-CL can include, for example, organic layers, inorganic layers, semiconductor patterns, conductive patterns, signal lines, etc. Organic layers, inorganic layers, semiconductor layers, and conductive layers can be formed on the base layer BS by methods such as coating or deposition. Subsequently, the organic layers, inorganic layers, semiconductor layers, and conductive layers can be selectively patterned using multiple photolithography processes to form semiconductor patterns, conductive patterns, and signal lines.

[0110] Semiconductor patterns, conductive patterns, and signal lines can form a pixel PX, which will be described below (see [link to documentation]). Figure 8The pixel drivers and signal lines (e.g., scan lines SL1 to SLm, data lines DL1 to DLn, light emission lines EL1 to ELm, first control line CSL1, second control line CSL2, and power line PL) (see [link to relevant documentation]). Figure 8 A pixel driver may include at least one transistor.

[0111] DP-OLED, a light-emitting element layer, includes pixel PX (see...). Figure 8 The light-emitting element is electrically connected to at least one transistor. Furthermore, the light-emitting element layer of a DP-OLED may also include at least one of an organic layer and an inorganic layer.

[0112] A thin-film encapsulation layer (TFE) can be disposed on the circuit layer DP-CL to cover the light-emitting element layer DP-OLED. The TFE protects the light-emitting element from foreign matter such as moisture / oxygen and dust particles. The TFE can comprise, for example, sequentially stacked inorganic, organic, and inorganic layers. There are no particular limitations on the stacking structure of the TFE.

[0113] The display module DM defines a display area DM-DA and a non-display area DM-NDA. The display area DM-DA and the non-display area DM-NDA of the display module DM are respectively associated with the electronic device ED (see...). Figure 2 The display area DA corresponds to the non-display area NDA.

[0114] The pixel drivers for the circuit layer DP-CL are located in the display area DM-DA. Furthermore, the signal lines of the circuit layer DP-CL (e.g., scan lines SL1 to SLm, data lines DL1 to DLn, light emission lines EL1 to ELm, first control line CSL1, second control line CSL2, and power line PL) (see [link to documentation]) Figure 8 Some settings in the display area DM-DA and the non-display area DM-NDA are in the display area.

[0115] The light-emitting element layer of the DP-OLED is disposed in the display area DM-DA. The thin-film encapsulation layer TFE is disposed in the display area DM-DA and the non-display area DM-NDA. However, in an embodiment, the thin-film encapsulation layer TFE is sufficient to cover at least a portion of the non-display area DM-NDA and the display area DM-DA, and it may not extend across the entire non-display area DM-NDA.

[0116] An input sensor ISP may include multiple electrodes for sensing external input, multiple traces connected to the multiple electrodes, and organic and / or inorganic layers that isolate / protect the multiple electrodes or traces. An input sensor ISP may be a capacitive sensor, but is not particularly limited to that.

[0117] When manufacturing the display module DM, the input sensor ISP can be directly mounted on the thin-film encapsulation layer TFE via a continuous process. That is, in this embodiment, no separate adhesive component is provided between the thin-film encapsulation layer TFE and the input sensor ISP. However, this disclosure is not limited to this, and the input sensor ISP can be manufactured as a panel separate from the display module DM and attached to the display module DM via an adhesive layer.

[0118] The display module DM may also include a functional layer disposed on the electronic panel EP. The functional layer may be, for example, an anti-reflective layer or a shock-absorbing layer. The functional layer may be manufactured separately from the electronic panel EP, may be disposed on the electronic panel EP, and may be attached to the electronic panel EP along with adhesive components.

[0119] Figure 6B The display module DM-1 includes a display module with a... Figure 6A The electronic panel EP shown has a different structure than the electronic panel EP-1. (See reference.) Figure 6B The electronic panel EP-1 according to the embodiment may include an anti-reflective layer RPL. When manufacturing the display module DM-1, the anti-reflective layer RPL can be formed directly on the input sensor ISP.

[0120] The anti-reflective layer RPL can reduce the input to the display device DD (see...) Figure 5 The reflectivity of external light. The anti-reflective layer RPL may include an optical film that reduces the reflectivity of external light. For example, the anti-reflective layer RPL may include multiple color filters and light-blocking patterns, or it may include a reflectance modulating layer containing pigments and / or dyes.

[0121] Figure 7 This is a cross-sectional view of a display module according to an embodiment of the present disclosure. For example, Figure 7 A cross-section of a pixel set in the display area DM-DA is shown by way of example.

[0122] refer to Figure 7 The display module DM may include a display panel DP and an input sensor ISP disposed on the display panel DP. The above description can be applied equivalently to the corresponding configurations described herein.

[0123] As referenced above Figure 6A As described, the display panel DP may include a base layer BS, a circuit layer DP-CL disposed on the base layer BS, a light-emitting element layer DP-OLED disposed on the circuit layer DP-CL, and a thin-film encapsulation layer TFE disposed on the light-emitting element layer DP-OLED.

[0124] The base layer BS has insulating properties and provides a base surface for components on which the display module DM is mounted. The base layer BS can be flexible and bendable. For example, the base layer BS can be bent at a specific curvature.

[0125] The circuit layer DP-CL may include insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BS, and pixels PX (see [link to documentation]). Figure 8 The transistor TR, upper electrode UE, and connection electrodes CN1 and CN2 are included. Insulating layers 10 to 60 may include a first insulating layer 10 to a sixth insulating layer 60 sequentially stacked on the base layer BS in the thickness direction. However, the implementation of insulating layers 10 to 60 included in the circuit layer DP-CL is not limited thereto and may vary depending on the configuration or manufacturing process of the circuit layer DP-CL.

[0126] A first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be configured as a barrier layer and / or a buffer layer to prevent foreign matter from being introduced into the display module DM. The first insulating layer 10 may improve the connection between the base layer BS and the conductive patterns of the semiconductor pattern SM and / or the circuit layer DP-CL. The first insulating layer 10 may include at least one of a silicon oxide layer and a silicon nitride layer. In an embodiment, the first insulating layer 10 may include alternately stacked silicon oxide layers and silicon nitride layers.

[0127] In one implementation, the base layer BS and the first insulating layer 10 may extend across the display panel DP, including extending into a second region AA2 where the wiring interconnects and insulating structures are located (see [link to implementation]). Figure 8 These layers can be connected to the curved region BA as further described below (see...). Figure 8 The wiring provides the basic mechanical support.

[0128] Pixel PX (see) Figure 8 ) can be set on the base layer BS. Pixel PX (see Figure 8 This can be set to correspond to the display area DA. Pixel PX (see...) Figure 8 It can include transistors (TR) and light-emitting elements (OL).

[0129] The transistor TR may include a semiconductor pattern SM and a gate electrode GE. The semiconductor pattern SM may be disposed on the first insulating layer 10. The semiconductor pattern SM may include a channel C, a source S, and a drain D. The semiconductor pattern SM may include silicon semiconductors, and may include, for example, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, or amorphous silicon semiconductors. However, this disclosure is not limited thereto, and the semiconductor pattern SM may include oxide semiconductors. The semiconductor pattern SM according to embodiments of this disclosure may be formed of various materials, as long as the material has semiconductor properties, and is not limited to any particular configuration.

[0130] Semiconductor patterns SM can include multiple regions with different electrical properties depending on whether they are doped or reduced. For example, a semiconductor pattern SM can include regions with high conductivity due to doping or reduction of metal oxides, and these highly conductive regions can be used as electrodes or signal wiring lines of a transistor TR. This can correspond to the source (S) and drain (D) of the transistor TR. A semiconductor pattern SM can also include undoped regions and therefore with relatively low conductivity, and this can correspond to the channel (C) (or active region) of the transistor TR.

[0131] A second insulating layer 20 may be disposed on the first insulating layer 10 to cover the semiconductor pattern SM. A gate electrode GE may be disposed on the second insulating layer 20. The second insulating layer 20 may be disposed between the semiconductor pattern SM and the gate electrode GE of the transistor TR. The gate electrode GE may overlap with the channel C of the semiconductor pattern SM in a plane. The gate electrode GE may be used as a mask in a process of doping the semiconductor pattern SM. The gate electrode GE may include, for example, heat-resistant molybdenum (Mo), molybdenum-containing alloys, titanium (Ti), titanium-containing alloys, etc., but this disclosure is not limited thereto.

[0132] Figure 7 The structure of the transistor TR shown is an example. In an embodiment, the source S or drain D of the transistor TR can be an electrode formed independently of the semiconductor pattern SM. In this case, the source S and drain D can contact the semiconductor pattern SM or can be connected to the semiconductor pattern SM through an insulating layer. Furthermore, the gate electrode GE can be disposed under the semiconductor pattern SM. The transistor TR according to embodiments of this disclosure can be formed in various structures, and this disclosure is not limited to any particular embodiment.

[0133] The second insulating layer 20 and the third to sixth insulating layers 30, which will be further described below, may include at least one of inorganic and organic layers. For example, the inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, zirconium oxide, and hafnium oxide. For example, the organic layer may include at least one of acrylate-based resins, methacrylate-based resins, polyisoprene-based resins, ethylene-based resins, epoxy-based resins, urethane-based resins, cellulose-based resins, siloxane-based resins, polyamide-based resins, and dinoflagellated resins.

[0134] A third insulating layer 30 is disposed on the second insulating layer 20 and may cover the gate electrode GE. An upper electrode UE may be disposed on the third insulating layer 30. The upper electrode UE may overlap with the gate electrode GE in a plane, and the overlapping gate electrode GE and upper electrode UE may form a capacitor.

[0135] A fourth insulating layer 40 is disposed on the third insulating layer 30 and may cover the upper electrode UE. Connecting electrodes CN1 and CN2 may include a first connecting electrode CN1 and a second connecting electrode CN2. The first connecting electrode CN1 may be disposed on the fourth insulating layer 40. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the first connecting electrode CN1. The second connecting electrode CN2 may be disposed on the fifth insulating layer 50. A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the second connecting electrode CN2. In an embodiment, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 may include an organic layer and may provide a substantially flat upper surface while covering the step difference between the components disposed below.

[0136] The first connecting electrode CN1 can be electrically connected to the semiconductor pattern SM through contact holes passing through the second insulating layer 20 to the fourth insulating layer 40. The second connecting electrode CN2 can be electrically connected to the first connecting electrode CN1 through contact holes passing through the fifth insulating layer 50.

[0137] Each of the first connecting electrode CN1 and the second connecting electrode CN2 may include a conductive material. Each of the first connecting electrode CN1 and the second connecting electrode CN2 may include, for example, gold, silver, copper, aluminum, platinum, molybdenum, titanium, and alloys thereof. At least any one of the first connecting electrode CN1 and the second connecting electrode CN2 may include a conductive layer with a multilayer structure. For example, at least any one of the first connecting electrode CN1 and the second connecting electrode CN2 may have a titanium / aluminum / titanium three-layer structure. However, the implementation is not limited to this.

[0138] According to the embodiment of the DP-CL circuit layer, at least one of the first connection electrode CN1 and the second connection electrode CN2 can be omitted. According to the embodiment of the DP-CL circuit layer, additional connection electrodes connecting the transistor TR and the light-emitting element OL can also be provided. The electrical connection method between the light-emitting element OL and the transistor TR can vary depending on the number of insulating layers disposed between the light-emitting element OL and the transistor TR, and this disclosure is not limited to any particular embodiment.

[0139] The DP-OLED light-emitting element layer may include a light-emitting element OL and a pixel-defining film PDL. The light-emitting element OL and the pixel-defining film PDL may be disposed on a sixth insulating layer 60. The light-emitting element OL may include a first electrode AE, a light-emitting layer EML, and a second electrode CE.

[0140] The first electrode AE ​​can be electrically connected to the second connecting electrode CN2 through a contact hole passing through the sixth insulating layer 60. The first electrode AE ​​can be electrically connected to the transistor TR through the first connecting electrode CN1 and the second connecting electrode CN2.

[0141] In a pixel-defining film (PDL), a pixel opening (PX-OP) can be defined to expose at least a portion of the first electrode (AE). The area of ​​the first electrode (AE) exposed by the pixel-defining film (PDL) can correspond to the light-emitting area. The pixel-defining film (PDL) can include, for example, an inorganic layer, an organic layer, or a composite material layer. According to an embodiment, the pixel-defining film (PDL) can also include a black pigment or a black dye.

[0142] A light-emitting layer EML can be disposed on the first electrode AE. The light-emitting layer EML can provide light of a specific color. The light-emitting layer EML can be disposed corresponding to a pixel opening PX-OP defined in a pixel defining film PDL. Multiple light-emitting elements OL and pixel openings PX-OP can be disposed, and the light-emitting layer EML of each light-emitting element OL can be disposed corresponding to a pixel opening PX-OP, and can be disposed in a pattern spaced apart from each other. However, this disclosure is not limited to this, and the light-emitting layer EML of each light-emitting element OL can be formed as a single common layer.

[0143] The second electrode CE can be disposed on the light-emitting layer EML and the pixel-defining film PDL. The second electrode CE can also be disposed commonly on the pixel PX (see [link to PX]). Figure 8 The common electrode in ).

[0144] The light-emitting element OL may further include at least one of a hole control region disposed between the first electrode AE ​​and the light-emitting layer EML, and an electron control region disposed between the light-emitting layer EML and the second electrode CE. The hole control region may include at least one of a hole generation layer, a hole transport layer, and an electron blocking layer, and the electron control region may include at least one of an electron generation layer, an electron transport layer, and a hole blocking layer.

[0145] In this embodiment, the same or similar organic material used for the pixel defining film PDL can also be used to form the first organic insulating layer OIL1, which is further described below (see [link]). Figure 9B This shared material base simplifies manufacturing and improves the uniformity of mechanical response across the folded region.

[0146] A thin-film encapsulation layer (TFE) can be disposed on the light-emitting element layer (DP-OLED). The TFE can be disposed on the light-emitting element (OL) and the pixel defining film (PDL), and can seal the light-emitting element (OL). The TFE can include at least any one of inorganic and organic layers. In an embodiment, the TFE can include a first inorganic layer EN1, a second inorganic layer EN3, and an organic layer EN2 disposed between the first inorganic layer EN1 and the second inorganic layer EN3. However, the configuration of the TFE is not limited to this, as long as the light-emitting element (OL) can be sealed.

[0147] A first inorganic layer EN1 can be disposed on the second electrode CE, and an organic layer EN2 and a second inorganic layer EN3 can be sequentially disposed on the first inorganic layer EN1 in the thickness direction of the display panel DP. The first inorganic layer EN1 and the second inorganic layer EN3 can protect the light-emitting element OL from, for example, moisture or oxygen that may be introduced into the display module DM. For example, each of the first inorganic layer EN1 and the second inorganic layer EN3 can include at least any one of silicon nitride, silicon oxide nitride, silicon oxide, titanium oxide, and aluminum oxide. However, the materials of the first inorganic layer EN1 and the second inorganic layer EN3 are not limited to the examples above. The organic layer EN2 can prevent foreign matter from being introduced into the light-emitting element OL and can cover the step difference of components disposed below the organic layer EN2. For example, the organic layer EN2 can include an acrylic organic material. However, the material of the organic layer EN2 is not limited to the examples above.

[0148] The input sensor ISP can be mounted on the display panel DP. The input sensor ISP may include a first sensing insulating layer IL1, a second sensing insulating layer IL2, a third sensing insulating layer IL3, a first sensing conductive layer CL1, and a second sensing conductive layer CL2. The above description can be equivalently applied to the corresponding configurations described herein.

[0149] The first sensing insulating layer IL1 may contact the uppermost layer of the thin-film encapsulation layer TFE. For example, the first sensing insulating layer IL1 may contact the second inorganic layer EN3 of the thin-film encapsulation layer TFE. The first sensing insulating layer IL1 of the input sensor ISP may be formed directly on the base surface provided by the thin-film encapsulation layer TFE. However, this disclosure is not limited thereto. For example, in an embodiment, the first sensing insulating layer IL1 may be omitted, and in this case, the first sensing conductive layer CL1 of the input sensor ISP may contact the thin-film encapsulation layer TFE.

[0150] A first sensing conductive layer CL1 may be disposed on a first sensing insulating layer IL1, and a second sensing conductive layer CL2 may be disposed on a second sensing insulating layer IL2. A third sensing insulating layer IL3 may be disposed on the second sensing insulating layer IL2 to cover the second sensing conductive layer CL2. Each of the first sensing insulating layer IL1 and the second sensing insulating layer IL2 may include a silicon nitride. The third sensing insulating layer IL3 may include a substantially flat upper surface. The third sensing insulating layer IL3 may include an organic material.

[0151] The first sensing conductive layer CL1 and the second sensing conductive layer CL2 can constitute a sensing electrode TE. For example, the first sensing conductive layer CL1 may include a connection pattern BP of the sensing electrode TE, and the second sensing conductive layer CL2 may include a sensing pattern SP of the sensing electrode TE. However, this disclosure is not limited thereto, and in embodiments, the first sensing conductive layer CL1 may include a sensing pattern SP, and the second sensing conductive layer CL2 may include a connection pattern BP.

[0152] The connection pattern BP can be disposed on a different layer from the sensing pattern SP, and can be connected through a contact hole passing through the second sensing insulating layer IL2. However, this disclosure is not limited thereto, and the connection pattern BP and the sensing pattern SP can be disposed on the same layer and integrally formed.

[0153] The sensing electrode TE can be a grid pattern and can be disposed corresponding to an area in which the pixel defining film PDL is disposed. However, this disclosure is not limited thereto. For example, in an embodiment, the sensing electrode TE can be disposed in a pattern of a single shape overlapping the light-emitting element OL, and in this case, the sensing electrode TE can include a transparent conductive material.

[0154] Figure 8 This is a plan view of a display panel according to an embodiment of the present disclosure.

[0155] refer to Figure 8The display panel DP may include a display area DP-DA and a non-display area DP-NDA surrounding the display area DP-DA. The display area DP-DA and the non-display area DP-NDA are distinguished based on the arrangement of pixels PX. The display area DP-DA and the non-display area DP-NDA are respectively associated with the electronic device ED (see [link to electronic device ED]). Figure 2 The display area DA corresponds to the non-display area NDA. The scan driver SDV, data driver DDV, and transmit driver EDV can be set in the non-display area DP-NDA.

[0156] The display panel DP includes a first region AA1, a second region AA2, and a curved region BA, which are separated from each other in a first direction DR1. In electronic devices such as... Figure 2 As shown in the diagram, the first region AA1 and the second region AA2 of the display panel DP mounted on the electronic device ED are positioned on different planes. A curved region BA is positioned between the first region AA1 and the second region AA2. The curved region BA can be bent about a bending axis extending in the second direction DR2.

[0157] like Figure 8 As shown, in the embodiment, data lines DL1 to DLn and power lines PL can extend across a first region AA1, a bending region BA, and a second region AA2. For example, during panel folding, the connection structure formed in the second region AA2 near the interface with the bending region BA may be subjected to mechanical stress. To address this issue, the structural layout of the wiring interconnects and insulation layers (such as the configuration of contact portions and the shape of openings in the inorganic insulation layer) can be adapted to reduce the effects of repeated bending. Reference will be made below. Figure 9A and Figure 9B Describe the relevant structure in more detail.

[0158] The first region AA1 is connected to the display surface DS (see...). Figure 2 The corresponding area. The first area AA1 may include a first non-folded area NFA10, a second non-folded area NFA20, and a folded area FA1. The first non-folded area NFA10, the second non-folded area NFA20, and the folded area FA1 are respectively associated with the area of ​​the first non-folded area NFA10, the second non-folded area NFA20, and the folded area FA1. Figures 2 to 4 The first non-folded region NFA1, the second non-folded region NFA2, and the folded region FA correspond to each other.

[0159] The lengths of the curved region BA and the second region AA2 in the first direction DR1 can be less than the length of the first region AA1 in the first direction DR1. The second region AA2 and the curved region BA can be portions of the non-display region DP-NDA.

[0160] The display panel (DP) may include multiple pixels (PX), multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple light-emitting lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a power line PL, and multiple pads (PD). Here, m and n are positive integers. Pixels (PX) may be connected to scan lines SL1 to SLm, data lines DL1 to DLn, and light-emitting lines EL1 to ELm.

[0161] The data driver DDV can be located in the second region AA2. The data driver DDV can be an integrated circuit chip. Scan lines SL1 to SLm can extend in the second direction DR2 to connect to the scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 and can be connected to the data driver DDV via the bending region BA. Emitting lines EL1 to ELm can extend in the second direction DR2 to connect to the transmit driver EDV.

[0162] A power line PL can extend along a first direction DR1 and can extend from a first region AA1 through a curved region BA to a second region AA2. The power line PL can provide a driving voltage to the pixel PX. The power line PL can be disposed in the non-display region DP-NDA. Although the power line PL is shown disposed between the display region DA and the transmit driver EDV, this disclosure is not limited thereto. For example, in an embodiment, the power line PL can be disposed between the display region DA and the scan driver SDV.

[0163] The connecting line CNL can extend along the second direction DR2 and can be arranged along the first direction DR1. The connecting line CNL can be connected to the power line PL and the pixel PX. The driving voltage can be applied to the pixel PX through the power line PL and the connecting line CNL that are connected to each other.

[0164] The first control line CSL1 can be connected to the scan driver SDV and can extend through the curved area BA toward the lower end of the second area AA2. The second control line CSL2 can be connected to the transmit driver EDV and can extend through the curved area BA toward the lower end of the second area AA2.

[0165] When viewed in a planar orientation, pad PD can be positioned adjacent to the lower end of the second region AA2. Data driver DDV, power line PL, first control line CSL1, and second control line CSL2 can be connected to pad PD. Data lines DL1 to DLn can be connected to their corresponding pad PDs via data driver DDV. For example, data lines DL1 to DLn can be connected to data driver DDV, and data driver DDV can be connected to the pad PDs corresponding to data lines DL1 to DLn respectively.

[0166] A printed circuit board (PCB) can be connected to pads (PD), and a timing controller and voltage generator can be mounted on the PCB. The timing controller can be manufactured as an integrated circuit chip and mounted on the PCB. The timing controller and voltage generator can be connected to pads (PD) via the PCB. The timing controller can control the operation of the scan driver (SDV), data driver (DDV), and transmit driver (EDV). The timing controller can generate scan control signals, data control signals, and emission control signals in response to control signals received from an external source. The scan control signal can be provided to the scan driver (SDV) via a first control line (CSL1). The emission control signal can be provided to the transmit driver (EDV) via a second control line (CSL2). The data control signal can be provided to the data driver (DDV).

[0167] The scan driver SDV can generate multiple scan signals in response to scan control signals. These scan signals can be applied to pixels PX via scan lines SL1 to SLm. The scan signals can be applied to pixels PX sequentially.

[0168] The data driver DDV can generate multiple data voltages corresponding to the image signal in response to the data control signal. These data voltages can be applied to the pixel PX via data lines DL1 to DLn.

[0169] The emitter driver EDV can generate multiple emission signals in response to the emission control signal. The emission signals can be applied to the pixel PX through the emission lines EL1 to ELm.

[0170] A pixel (PX) can receive data voltage in response to a scan signal. A pixel (PX) can display an image by emitting light of a brightness corresponding to the data voltage in response to a transmission signal. The transmission time of a pixel (PX) can be controlled by the transmission signal.

[0171] Figure 9A This is an enlarged view of a portion of the display panel according to an embodiment of the present disclosure. Figure 9B This is a cross-sectional view of a display device according to an embodiment of the present disclosure. For example, Figure 9A yes Figure 8 An enlarged view of region AA' shown, and Figure 9B It is along Figure 9A The image shows a cross-sectional view of the display device DD according to the embodiment, taken along line I-I'. For ease of explanation, further descriptions of the previously described components and technical aspects will be omitted below.

[0172] refer to Figure 9AThe first wiring line WL1 can be located in the second area AA2, and the second wiring line WL2 can be located in the bending area BA. The first wiring line WL1 and the second wiring line WL2 can be from... Figure 8 The signal lines shown (e.g., scan lines SL1 to SLm, data lines DL1 to DLn, light emission lines EL1 to ELm, first control line CSL1, second control line CSL2, and power line PL) extend from this point. Multiple first wiring lines WL1 and multiple second wiring lines WL2 can be provided separately. The first wiring lines WL1 and second wiring lines WL2 can extend in a first direction DR1 and can be arranged in a second direction DR2. The first wiring lines WL1 can be referred to as signal wiring lines, and the second wiring lines WL2 can be referred to as connection wiring lines.

[0173] refer to Figure 9A and Figure 9B The base layer BS and the first insulating layers 10 to 60 may extend to the bending region BA and the second region AA2. For ease of explanation, further description of the previously described base layer BS and the first insulating layers 10 to 60 will be omitted.

[0174] The first wiring line WL1 can be disposed on the fourth insulation layer 40 and can overlap with the second area AA2. The first wiring line WL1 can be with Figure 7 The first connecting electrode CN1 shown is disposed on the same layer. That is, the first wiring line WL1 can be formed by the same process as the first connecting electrode CN1. The fifth insulating layer 50 can cover the first wiring line WL1. However, this disclosure is not limited thereto. For example, the first wiring line WL1 can be formed with... Figure 7 The gate electrode GE shown is disposed on the same layer.

[0175] The second wiring line WL2 can extend from the second region AA2 in the first direction DR1. That is, the second wiring line WL2 can extend from the second region AA2 to the bending region BA. The second wiring line WL2 can overlap with the bending region BA. The second wiring line WL2 can be disposed on the first wiring line WL1. For example, the second wiring line WL2 can be disposed on the fifth insulating layer 50. The second wiring line WL2 can be disposed on the same layer as the second connecting electrode CN2. That is, the second wiring line WL2 can be formed by the same process as the second connecting electrode CN2. The second wiring line WL2 can be covered by the sixth insulating layer 60. However, this disclosure is not limited thereto. For example, in an embodiment, the second wiring line WL2 can be disposed on the same layer as the first wiring line WL1. Figure 7 The upper electrode UE shown is disposed on the same layer.

[0176] The first wiring line WL1 and the second wiring line WL2 can be electrically connected to each other. For example, the first wiring line WL1 and the second wiring line WL2 can be electrically connected to each other through a contact portion CNP. The contact portion CNP can be defined as the portion in which the second wiring line WL2 passes through the fifth insulating layer 50 and contacts the first wiring line WL1. The contact portion CNP can be provided in the second region AA2. Multiple contact portions CNP can be provided. Although in Figure 9A The diagram shows that the number of contact portions CNP in a first wiring line WL1 is 9, but this disclosure is not limited thereto. For example, the number of contact portions CNP in a first wiring line WL1 can be set to a single digit, or it can be set to ten or more.

[0177] In this implementation, the area including the contact portion CNP may be located adjacent to the bending region BA and may be subjected to mechanical strain when the display device DD is folded. Since the contact portion CNP electrically connects the stacked wiring lines WL1 and WL2, mechanical stress near this interface may adversely affect electrical continuity or, if not properly managed, lead to physical damage. Therefore, the material stacking and insulation structure in this area are configured in the spatial arrangement disclosed herein, which maintains reliability under repeated bending.

[0178] An organic insulating layer (OIL) can be disposed on the second wiring line WL2. For example, the organic insulating layer (OIL) can be disposed on the sixth insulating layer 60. The organic insulating layer (OIL) can completely overlap with the second wiring line WL2. Furthermore, in a planar plane, the organic insulating layer (OIL) can cover the second wiring line WL2 and can also cover one end of the first wiring line WL1. The end of the first wiring line WL1 that overlaps with the organic insulating layer (OIL) can be adjacent to the bending region BA.

[0179] The organic insulating layer OIL may include a first organic insulating layer OIL1 and a second organic insulating layer OIL2. The first organic insulating layer OIL1 may be disposed on the sixth insulating layer 60. The second organic insulating layer OIL2 may be disposed on the first organic insulating layer OIL1 and may completely overlap with the first organic insulating layer OIL1. According to an embodiment of the present disclosure, the length of the first organic insulating layer OIL1 in the first direction DR1 may be greater than the length of the second organic insulating layer OIL2 in the first direction DR1. That is, the second organic insulating layer OIL2 may expose one end of the first organic insulating layer OIL1.

[0180] The first organic insulating layer OIL1 may include... Figure 7 The pixel-defining film PDL shown is made of the same material. That is, the first organic insulating layer OIL1 can be made of the same material as... Figure 7The pixel-defining film (PDL) shown is formed using the same process. The second organic insulating layer (OIL2) may include materials disposed in the same manner as those used in the pixel-defining film (PDL). Figure 7 The spacers on the pixel-defining film (PDL) shown are made of the same material. That is, the second organic insulating layer (OIL2) can be formed simultaneously with the spacers. In an embodiment, the first organic insulating layer (OIL1) and the second organic insulating layer (OIL2) may comprise the same material. For example, the first organic insulating layer (OIL1) and the second organic insulating layer (OIL2) can be formed substantially simultaneously.

[0181] According to embodiments of this disclosure, an inorganic insulating layer IIL can be disposed on a first wiring line WL1. For example, the inorganic insulating layer IIL can be disposed on a sixth insulating layer 60. An opening OP overlapping with an organic insulating layer OIL can be defined in the inorganic insulating layer IIL. The opening OP can completely overlap with the bend region BA. For example, the opening OP can overlap the entire bend region BA. The opening OP can overlap with the contact portion CNP. The opening OP can extend in a second direction DR2. The inorganic insulating layer IIL can be spaced apart from the organic insulating layer OIL in a first direction DR1. However, this disclosure is not limited thereto, and in embodiments, one end of the organic insulating layer OIL can be covered by the inorganic insulating layer IIL.

[0182] In an implementation, the opening OP defined in the inorganic insulating layer IIL can be configured to reduce internal stress concentration by altering the stiffness distribution near the contact portion CNP. For example, the shape of the opening OP can include a curved boundary portion that can limit abrupt changes in the mechanical modulus of the entire insulating interface. This configuration can help reduce the likelihood of localized crack formation or delamination in the inorganic insulating layer IIL when adjacent areas undergo deformation during bending.

[0183] The inorganic insulating layer IIL may include a first sub-insulating layer IIL1 and a second sub-insulating layer IIL2. The second sub-insulating layer IIL2 may be disposed on the first sub-insulating layer IIL1. The first sub-insulating layer IIL1 may include, with... Figure 7 The first sensing insulating layer IL1 shown is made of the same material. That is, the first sub-insulating layer IL1 can be formed using the same process as the first sensing insulating layer IL1. The second sub-insulating layer IL2 may include materials similar to... Figure 7 The material of the second sensing insulating layer IL2 shown is the same. That is, the second sub-insulating layer IL2 can be formed by the same process as the second sensing insulating layer IL2.

[0184] In this embodiment, the first sub-insulating layer IIL1 and the second sub-insulating layer IIL2 may comprise the same material. For example, each of the first sub-insulating layer IIL1 and the second sub-insulating layer IIL2 may comprise silicon nitride. The first sub-insulating layer IIL1 may be formed using the same process as the second sub-insulating layer IIL2. That is, the first sub-insulating layer IIL1 and the second sub-insulating layer IIL2 may be patterned in one step using the same mask.

[0185] The auxiliary insulating layer AIL can be disposed on the inorganic insulating layer IIL. The auxiliary insulating layer AIL can completely overlap with the inorganic insulating layer IIL. The auxiliary insulating layer AIL can cover one end of the inorganic insulating layer IIL. The auxiliary insulating layer AIL can include organic materials. The auxiliary insulating layer AIL can include materials that are compatible with organic materials. Figure 7 The material of the third sensing insulating layer IL3 shown is the same. That is, the auxiliary insulating layer AIL can be formed by the same process as the third sensing insulating layer IL3. In the auxiliary insulating layer AIL, a sub-opening SOP that overlaps with the organic insulating layer OIL can be defined. The sub-opening SOP can completely overlap with the bending region BA. The sub-opening SOP can overlap with the contact portion CNP. The sub-opening SOP can extend in the second direction DR2. The sub-opening SOP can overlap with the opening OP in a plane. The size of the sub-opening SOP in the plane (e.g., in a plan view) can be smaller than the size of the opening OP in the plane (e.g., in a plan view).

[0186] According to embodiments of the present disclosure, the organic insulating layer OIL can cover the ends of the first wiring line WL1 and the second wiring line WL2, which can prevent damage to the first wiring line WL1 and the second wiring line WL2 caused by the inorganic insulating layer IIL. For example, due to oxidation of the inorganic insulating layer IIL, hydrogen free radicals and ammonia gas may be generated. In this case, when the distance between one end of the inorganic insulating layer IIL and the first wiring line WL1 and the second wiring line WL2 is short, hydrogen free radicals and ammonia gas may easily reach the first wiring line WL1 and the second wiring line WL2. According to embodiments of the present disclosure, the organic insulating layer OIL can cover the ends of the first wiring line WL1 and the second wiring line WL2, and therefore, damage to the first wiring line WL1 and the second wiring line WL2 caused by hydrogen free radicals and ammonia gas can be prevented or reduced.

[0187] According to the implementation, the organic insulating layer (OIL), combined with the stress dispersion effect of the opening geometry, can also contribute to the physical and chemical protection of the contact portion of the CNP. By covering the ends of the first wiring line WL1 and the second wiring line WL2, the organic insulating layer (OIL) can reduce the direct exposure of the metal wiring to reactive substances such as hydrogen radicals and ammonia generated during encapsulation or environmental intrusion. This can help prevent the contact resistance from corroding or deteriorating over time.

[0188] Figure 10 yes Figure 9A An enlarged view of region CC' shown in the image.

[0189] refer to Figure 10 The inorganic insulating layer IIL may include a first side surface S1, a second side surface S2, a third side surface S3, a fourth side surface S4, and a fifth side surface S5 defining the opening OP. The first side surface S1, second side surface S2, third side surface S3, fourth side surface S4, and fifth side surface S5 may define the inorganic insulating layer IIL. Figure 9B The side surface of the opening OP shown corresponds to this.

[0190] The first side surface S1 may extend in a first direction DR1. Each of the second side surface S2 and the fourth side surface S4 may extend in a second direction DR2. According to an embodiment of this disclosure, the third side surface S3 connecting the first side surface S1 and the second side surface S2, and the fifth side surface S5 connecting the first side surface S1 and the fourth side surface S4, may include curved surfaces. When viewed in a plane, the curved surfaces of the third side surface S3 and the fifth side surface S5 may have a certain shape.

[0191] The auxiliary insulating layer (AIL) may include a first auxiliary side surface SS1, a second auxiliary side surface SS2, a third auxiliary side surface SS3, a fourth auxiliary side surface SS4, and a fifth auxiliary side surface SS5. The first auxiliary side surface SS1, the second auxiliary side surface SS2, the third auxiliary side surface SS3, the fourth auxiliary side surface SS4, and the fifth auxiliary side surface SS5 may define the auxiliary insulating layer (AIL). Figure 9B The side surface of the sub-opening SOP shown corresponds to this.

[0192] The first auxiliary side surface SS1 may extend in the first direction DR1. Each of the second auxiliary side surface SS2 and the fourth auxiliary side surface SS4 may extend in the second direction DR2. According to an embodiment of the present disclosure, the third auxiliary side surface SS3 connecting the first auxiliary side surface SS1 and the second auxiliary side surface SS2, and the fifth auxiliary side surface SS5 connecting the first auxiliary side surface SS1 and the fourth auxiliary side surface SS4, may include curved surfaces. When viewed in a plane, the curved surfaces of the third auxiliary side surface SS3 and the fifth auxiliary side surface SS5 may have a certain shape. Each of the first auxiliary side surface SS1, the second auxiliary side surface SS2, the third auxiliary side surface SS3, the fourth auxiliary side surface SS4, and the fifth auxiliary side surface SS5 may be formed parallel to the first side surface S1, the second side surface S2, the third side surface S3, the fourth side surface S4, and the fifth side surface S5, respectively. However, this disclosure is not limited thereto, and in the embodiments, the first auxiliary side surface SS1, the second auxiliary side surface SS2, the third auxiliary side surface SS3, the fourth auxiliary side surface SS4 and the fifth auxiliary side surface SS5 may extend in the second direction DR2, and do not correspond to the first side surface S1, the second side surface S2, the third side surface S3, the fourth side surface S4 and the fifth side surface S5.

[0193] In this embodiment, the auxiliary side surfaces SS1 to SS5 of the auxiliary insulating layer AIL and the side surfaces S1 to S5 of the inorganic insulating layer IIL can be shaped and aligned such that the combined sub-openings SOP and OP form a continuous cut-out region in the stacked insulating structure. This continuous cut-out allows for local bending deformation and reduces mechanical resistance, which can help reduce stress concentration near the contact portion CNP.

[0194] refer to Figure 7 as well as Figures 9A to 10When the display panel DP according to an embodiment of the present disclosure is bent, the inorganic insulating layer IIL adjacent to the bending region BA may be subjected to compressive stress, and therefore, cracks may occur in the inorganic insulating layer IIL. For example, cracks may occur due to compressive stress at the corners of the inorganic insulating layer IIL. However, because the third side surface S3 and the fifth side surface S5 of the inorganic insulating layer IIL corresponding to the corners of the inorganic insulating layer IIL include curved surfaces, the stress applied to the inorganic insulating layer IIL can be dispersed when the display panel DP is bent, thus preventing cracks from occurring in the inorganic insulating layer IIL. For example, when the display panel DP is bent, compressive stress may be applied to the inorganic insulating layer IIL disposed adjacent to the bending region BA. If this stress accumulates near the corners of the opening OP, cracks may occur in the inorganic insulating layer IIL due to the brittleness of the inorganic material. However, in the embodiment, the third side surface S3 and the fifth side surface S5 of the opening OP may include curved shapes, which can reduce sudden geometric changes across a wide area and help disperse stress. This configuration can reduce the peak stress value at the corners during repeated bending and suppress crack formation in the inorganic insulation layer IIL.

[0195] The first side surface S1 can be spaced apart from the first wiring line WL1 and the second wiring line WL2 in the second direction DR2. Therefore, when the display panel DP according to the embodiment of this disclosure is bent, even when the inorganic insulating layer IIL is subjected to compressive stress, the inorganic insulating layer IIL is still spaced apart from the first wiring line WL1 and the second wiring line WL2 in the plane. Therefore, the stress applied from the inorganic insulating layer IIL to the first wiring line WL1 and the second wiring line WL2 can be reduced.

[0196] In this implementation, in addition to the curved geometry, the spatial offset of the first side surface S1 from the wiring lines WL1 and WL2 in the second direction DR2 further reduces the transmission of mechanical stress. Because the opening OP does not directly overlap with the ends of the wiring lines WL1 and WL2 in the plane, deformation of the inorganic insulation layer IIL under bending conditions is less likely to cause strain at the contact point. This helps improve the reliability of the electrical connection by reducing the likelihood of mechanical damage or delamination near the contact portion CNP.

[0197] Figure 11 This is an enlarged view of a portion of the display panel according to an embodiment of the present disclosure. For example, Figure 11 yes Figure 8 An enlarged view of region BB' shown in the image.

[0198] refer to Figure 11 A third cabling line, WL3, can also be installed in the first area AA1. The third cabling line WL3 can be from... Figure 8The portion extending from the signal lines shown (e.g., scan lines SL1 to SLm, data lines DL1 to DLn, light emission lines EL1 to ELm, first control line CSL1, second control line CSL2, and power line PL). Multiple third wiring lines WL3 can be provided. The third wiring lines WL3 can extend in the first direction DR1 and can be arranged in the second direction DR2. The third wiring lines WL3 can be referred to as signal lines. The third wiring lines WL3 can be located on the same layer as the first wiring lines WL1.

[0199] The third wiring line WL3 and the second wiring line WL2 can be electrically connected to each other. For example, the third wiring line WL3 and the second wiring line WL2 can be electrically connected to each other through the contact part CNPa. Although in Figure 11 The diagram shows that the number of contact portions CNPas in a third wiring line WL3 is 9, but this disclosure is not limited thereto. For example, according to an embodiment, the number of contact portions CNPas in a third wiring line WL3 may be set to a single digit, or it may be set to ten or more.

[0200] According to embodiments of this disclosure, the inorganic insulating layer IIL can be disposed on the third wiring line WL3. For example, the inorganic insulating layer IIL can be disposed on the sixth insulating layer 60 (see...). Figure 9B The opening OP, defined in the inorganic insulating layer IIL, may overlap with one end of the third wiring line WL3. The description of the third wiring line WL3 can be applied substantially equivalently to the description of the first wiring line WL1, and therefore, further description thereof is omitted.

[0201] In an implementation, the structural layout around the third wiring line WL3 and the contact portion CNPa can be configured in a manner similar to that of the first wiring line WL1 and the contact portion CNP. For example, the opening OP defined in the inorganic insulating layer IIL may include a side surface with a curved profile and may be spaced apart from the wiring lines WL1, WL2, and WL3 in the second direction DR2. This arrangement can help to align with the reference... Figure 10 The same method described disperses stress and reduces crack formation at the upper end of the second wiring line WL2.

[0202] Figure 12 This is an enlarged view of a portion of the display panel according to an embodiment of the present disclosure. For example, Figure 12 According to the implementation method Figure 8 An enlarged view of region AA' shown in the image.

[0203] refer to Figure 12An opening OPa can be defined in the inorganic insulating layer IIL, and a sub-opening SOPa can be defined in the auxiliary insulating layer AIL. Each of the opening OPa and the sub-opening SOPa can completely overlap with the bending region BA.

[0204] According to embodiments of the present disclosure, the second side surface S2 and the fourth side surface S4 of the inorganic insulating layer IIL can be spaced apart from the bending region BA in a plane along the first direction DR1. For example, the second side surface S2 of the inorganic insulating layer IIL adjacent to the bending region BA can be spaced apart from the bending region BA in a plane along the first direction DR1. Furthermore, the second auxiliary side surface SS2 and the fourth auxiliary side surface SS4 of the auxiliary insulating layer AIL can be spaced apart from the bending region BA in a plane along the first direction DR1. For example, the second auxiliary side surface SS2 of the auxiliary insulating layer AIL adjacent to the bending region BA can be spaced apart from the bending region BA in a plane along the first direction DR1. Therefore, when the display panel DP according to embodiments of the present disclosure (see...) Figure 8 When bent, it can reduce the compressive stress in the inorganic insulating layer IIL of the adjacent bending area BA.

[0205] As is common in the art of this disclosure, embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented using electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented using microprocessors or similar components, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. Each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing certain functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry).

[0206] When the display panel according to an embodiment of the present disclosure is bent, the inorganic insulating layer adjacent to the bending region may be subjected to compressive stress, and therefore, cracks may be generated in the inorganic insulating layer. Because the side surface of the inorganic insulating layer corresponding to the corner of the inorganic insulating layer includes a bending surface, cracks in the inorganic insulating layer can be prevented or the number of cracks can be reduced by dispersing the stress received by the inorganic insulating layer.

[0207] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, comprising: The base layer includes a first region containing a display area, a second region spaced apart from the first region in a first direction, and a curved region disposed between the first region and the second region; The first wiring line overlaps with the second area and extends in the first direction; The second wiring line overlaps with the curved area and is electrically connected to the first wiring line; as well as An inorganic insulating layer is disposed on the first wiring line, and an opening overlapping a contact portion is defined in the inorganic insulating layer, in which the first wiring line and the second wiring line are connected to each other. The inorganic insulating layer includes: A first side surface extends in the first direction; The second side surface extends in a second direction intersecting the first direction; and The third side surface connects the first side surface and the second side surface, and has a curved shape in the plan view. The opening is defined by the first side surface to the third side surface.

2. The display device according to claim 1, further comprising: An auxiliary insulating layer is disposed on the inorganic insulating layer and covers the inorganic insulating layer.

3. The display device according to claim 2, further comprising: Sub-opening, defined within the auxiliary insulating layer, The sub-opening overlaps with the contact portion.

4. The display device according to claim 3, wherein The auxiliary insulating layer includes: A first auxiliary side surface extends in the first direction; A second auxiliary side surface extends in the second direction; and A third auxiliary side surface connects the first auxiliary side surface and the second auxiliary side surface, and has the curved shape in the plan view. The sub-opening is defined by the first auxiliary side surface to the third auxiliary side surface.

5. The display device according to claim 4, wherein, The first auxiliary side surface is parallel to the first side surface. The second auxiliary side surface is parallel to the second side surface, and The third auxiliary side surface is parallel to the third side surface.

6. The display device according to claim 3, wherein, In the plan view, the sub-opening overlaps with the opening, and In the plan view, the size of the sub-opening is smaller than the size of the opening.

7. The display device according to claim 1, further comprising: An organic insulating layer is disposed on the second wiring line. Wherein, the organic insulating layer overlaps with the opening, and The organic insulating layer covers the ends of the first wiring line and the ends of the second wiring line.

8. The display device according to claim 1, wherein, The inorganic insulating layer further includes: The fourth side surface extends in a direction opposite to the second direction; and The fifth side surface connects the first side surface and the fourth side surface, and includes a curved surface.

9. The display device of claim 8, wherein, The second side surface and the fourth side surface are spaced apart from the curved region in the first direction.

10. The display device according to claim 1, wherein, In the plan view, the first side surface is spaced apart from the contact portion in the second direction.

11. The display device according to claim 1, wherein, The opening overlaps with the entire curved region.

12. The display device according to claim 1, further comprising: A third wiring line is installed in the first area and electrically connected to the second wiring line. The inorganic insulating layer is disposed on the third wiring line, and One end of the third wiring line overlaps with the opening.

13. A display device, comprising: The base layer includes a first region, a second region spaced apart from the first region in a first direction, and a curved region disposed between the first region and the second region; The first wiring line overlaps with the second area and extends in the first direction; The second wiring line overlaps with the curved area and is electrically connected to the first wiring line; as well as An inorganic insulating layer is disposed on the first wiring line, and an opening overlapping the bending region is defined in the inorganic insulating layer. The inorganic insulating layer includes: A first side surface, extending in the first direction; and The second side surface extends in a second direction that intersects the first direction. In the plan view, the second side surface is spaced apart from the curved region in the first direction.

14. The display device according to claim 13, wherein, The inorganic insulating layer further includes a third side surface, which connects the first side surface and the second side surface and has a curved shape in the plan view. The opening is defined by the first side surface to the third side surface.

15. The display device according to claim 13, wherein, The opening overlaps with the contact portion, in which the first wiring line and the second wiring line are electrically connected to each other.

16. The display device according to claim 15, wherein, In the plan view, the first side surface is spaced apart from the contact portion in the second direction.

17. The display device according to claim 15, further comprising: An auxiliary insulating layer is disposed on the inorganic insulating layer and covers the inorganic insulating layer; as well as Sub-opening, defined within the auxiliary insulating layer, The sub-opening overlaps with the contact portion.

18. The display device according to claim 17, wherein, In the plan view, the sub-opening overlaps with the opening, and In the plan view, the size of the sub-opening is smaller than the size of the opening.

19. Electronic devices, including: case; The electronic module is housed inside the casing; as well as A display device is disposed on and overlaps with the electronic module. The display device includes: The base layer includes a first region, a second region spaced apart from the first region in a first direction, and a curved region disposed between the first region and the second region; The first wiring line overlaps with the second area and extends in the first direction; A second wiring line overlaps with the curved area and is electrically connected to the first wiring line; and An inorganic insulating layer is disposed on the first wiring line, and an opening overlapping a contact portion is defined in the inorganic insulating layer, in which the first wiring line and the second wiring line are connected to each other. The inorganic insulating layer includes: A first side surface extends in the first direction; The second side surface extends in a second direction intersecting the first direction; and The third side surface connects the first side surface and the second side surface, and has a curved shape in the plan view. The opening is defined by the first side surface to the third side surface.

20. The electronic device of claim 19, further comprising: The driver is located in the second area; as well as A printed circuit board is disposed in the second area and electrically connected to the display device.

Images