Algalnp red light micro-led chip with high al component polarization induced barrier layer and preparation method

Abstract

The application discloses an AlGaInP red light Micro-LED chip with a high Al component polarization-induced barrier layer and a preparation method. x2 Ga 1‑x2 ) y2 InP continuously changes to a high Al component structure of Al 0.5 In 0.5 P, the valence band step is raised to 250-320 meV, and the carrier confinement capability is significantly enhanced; meanwhile, the barrier layer is doped with a low concentration of p type, and a three-dimensional hole gas is induced to be formed by means of the polarization effect of the Al component change, so that the hole concentration breaks through the doping limitation, and the light emission quenching problem caused by high doping is avoided; the core problems of insufficient carrier confinement, low hole injection efficiency and poor high-temperature stability of the existing red light Micro-LED chip are solved, and the device external quantum efficiency, high-temperature retention rate and long-term reliability are greatly improved; the preparation process is compatible with the existing production line, and is suitable for multiple fields.

Description

Technical Field

[0001] This invention relates to the field of Micro-LED chip technology, specifically to an AlGaInP red-light Micro-LED chip with a high Al composition polarization-induced barrier layer and its fabrication method, which is particularly suitable for AlGaInP-based red-light Micro-LED chips for scenarios such as high-resolution Micro-LED displays, AR / VR near-eye displays, and automotive high-definition displays. Background Technology

[0002] Micro-LED display technology, with its core advantages such as high brightness, high contrast, low power consumption, long lifespan, fast response, and wide temperature range, has become the core development direction of next-generation display technology. Among them, the AlGaInP-based quaternary compound semiconductor material system is the mainstream technical route for achieving efficient light emission in the visible light red band (620~660nm), and it is also the core red light device solution for full-color Micro-LED displays.

[0003] Currently, in the epitaxial design of mainstream commercial AlGaInP red Micro-LED chips, AlGaInP materials with an Al composition of <0.4% are commonly used as the barrier layer of the quantum well structure. This technology faces three major insurmountable technical bottlenecks in Micro-LED applications at the micro-pixel scale (<50μm): First, the carrier confinement capability of the barrier layer is severely insufficient. The valence band order ΔEv between low-Al composition AlGaInP materials and GaInP well layers is only 150~220meV, which is extremely weak in confining holes with already low mobility. At the microscale of Micro-LEDs, the lateral diffusion and surface overflow effects of carriers are significantly amplified, further exacerbating the carrier leakage problem and directly leading to a significant decrease in the external quantum efficiency of the device, resulting in a severe "size-effect efficiency collapse".

[0004] Second, there is an inherent contradiction between low hole injection efficiency in the active region and doping. P-type doping in the barrier layer is the core method to improve hole injection efficiency, but there is an inherent contradiction that cannot be resolved simultaneously: at low doping concentrations, the hole supply is insufficient to meet the demand for efficient radiative recombination in the active region; while increasing the doping concentration can increase the hole supply, it will trigger a severe self-compensation effect, leading to a significant deterioration in crystal quality and a sharp increase in the density of non-radiative recombination centers; more seriously, highly concentrated doped Mg acceptor atoms can easily diffuse into the quantum well active region, causing a severe luminescence quenching effect, directly damaging the luminescence intensity and efficiency of the device.

[0005] Third, the devices exhibit poor high-temperature stability. The carrier confinement capability of existing low-Al composition barrier layers decreases rapidly with increasing temperature, exacerbating carrier thermal leakage. Simultaneously, the ionization efficiency of p-type doped impurities fluctuates significantly with increasing temperature, resulting in poor hole concentration stability. Consequently, the devices experience rapid efficiency degradation and insufficient reliability under high power density and high-temperature operating conditions, making them unsuitable for wide-temperature-range applications such as automotive and outdoor displays.

[0006] In existing technologies, some solutions only suppress electron overflow by optimizing the compositional gradient design of the electron blocking layer, without solving the core problems of insufficient carrier confinement and hole doping in the quantum well barrier layer itself. Chinese patent CN119730492A designs a variable Al composition electron blocking layer for GaN-based LEDs, but its material system is fundamentally different from that of AlGaInP-based red LEDs, with completely different lattice matching and polarization characteristics, making it unsuitable for direct application. Chinese patent CN114639761B discloses a conventional AlGaInP red LED structure, which still uses a low Al composition barrier layer and conventional doping scheme, failing to overcome the aforementioned technical bottlenecks.

[0007] Therefore, developing a red LED chip structure and fabrication method that can simultaneously solve the three core problems of insufficient carrier confinement, low hole injection efficiency, and easy luminescence quenching caused by doping has become an urgent technical challenge in this field. Summary of the Invention

[0008] The purpose of this invention is to provide an AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer and its fabrication method, which solves the core technical problems of insufficient carrier confinement capability of the barrier layer, low hole injection efficiency in the active region, inherent contradictions in p-type doping, and poor high-temperature stability in the existing AlGaInP red micro-LED chip. Without sacrificing crystal quality, the invention significantly improves the luminous efficiency and operational reliability of the device.

[0009] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: An AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer includes, from bottom to top, a GaAs substrate, an n-type GaAs buffer layer, an n-type AlGaInP etch barrier layer, an n-type GaAs ohmic contact layer, an n-type AlGaInP confinement layer, a periodic quantum well structure, a p-type AlGaInP spacer layer, a p-type AlInP electron blocking layer, and a p-type GaP ohmic contact layer. The periodic quantum well structure comprises alternating layers of GaInP wells and p-type doped polarization-induced barrier layers. The polarization-induced barrier layer is a quaternary semiconductor structure with a continuously gradient Al composition, its composition consisting of (Al...x2 Ga 1-x2 ) y2 InP gradually changes to Al 0.5 In 0.5 P, where x2 takes the value of 0.7~0.9 and y2 takes the value of 0.5; the p-type doping concentration of the polarization-induced barrier layer is 1.0×10⁻⁶. 17 ~3.0×10 17 cm -3 The polarization effect induced by the gradual change in Al composition induces the formation of three-dimensional hole gas, resulting in a hole concentration of 1.0 × 10⁻⁶ within the barrier layer. 18 cm -3 and above.

[0010] In a preferred embodiment, the periodic quantum well structure has 1 to 5 pairs of quantum wells, the GaInP well layer has a thickness of 1.5 to 4.5 nm, the polarization-induced barrier layer has a thickness of 4 to 10 nm, and the valence band order of the polarization-induced barrier layer is 250 to 320 meV.

[0011] In a preferred embodiment, the n-type AlGaInP confinement layer is (Al x1 Ga 1-x1 ) y1 The InP structure has x1 values ​​ranging from 0.7 to 1, y1 values ​​ranging from 0.5, and a thickness of 150 to 500 nm; the p-type AlGaInP spacer layer is (Al x3 Ga 1-x3 ) y3 The AlInP structure has x3 values ​​of 0.8–0.9 and y3 values ​​of 0.5, with a thickness of 30–100 nm; the p-type AlInP electron blocking layer is Al x4 In 1-x4 The structure is a P-structure, where x4 is 0.5 and the thickness is 200~900nm.

[0012] In a preferred embodiment, a p-type ITO transparent conductive layer and a bonding metal layer are sequentially stacked on the top surface of the p-type GaP ohmic contact layer, and the bonding metal layer is bonded to the Si-based CMOS driving circuit; after the GaAs substrate is removed by wet process, an n-type ITO transparent conductive layer and an n-type metal electrode are disposed on the surface of the n-type GaAs ohmic contact layer, and the sidewalls of the chip mesa are covered with a SiO2 sidewall passivation layer.

[0013] In a preferred embodiment, the thickness of the p-type ITO transparent conductive layer is 150 nm, and its indium-tin molar ratio is 9:1; the bonding metal layer is a Cr / Pt / Au three-layer stacked structure with a total thickness of 800 nm; and the thickness of the SiO2 sidewall passivation layer is 10~100 nm.

[0014] This invention also provides a method for fabricating an AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer, comprising the following steps: S1, using a metal-organic chemical vapor deposition system, an n-type GaAs buffer layer, an n-type AlGaInP etch barrier layer, an n-type GaAs ohmic contact layer, and an n-type AlGaInP confinement layer are epitaxially grown sequentially from bottom to top on a GaAs substrate. S2, a periodic quantum well structure is epitaxially grown on the n-type AlGaInP confinement layer, wherein the barrier layer of the periodic quantum well structure is made of Al composition (Al x2 Ga 1-x2 ) y2 InP gradually changes to Al 0.5 In 0.5 P polarization-induced barrier layer, and p-type doping of the polarization-induced barrier layer; S3, continue to epitaxially grow a p-type AlGaInP spacer layer, a p-type AlInP electron blocking layer, and a p-type GaP ohmic contact layer on the periodic quantum well structure to complete the epitaxial wafer fabrication; S4, a p-type ITO transparent conductive layer is prepared on the p-type GaP ohmic contact layer of the epitaxial wafer and annealed. The epitaxial wafer is bonded to the Si-based CMOS driving circuit through a bonding metal layer, and the GaAs substrate is removed by wet process. S5. Fabricate a Micro-LED mesa structure, deposit a SiO2 sidewall passivation layer, complete the fabrication of the n-type interconnect structure and n-type metal electrode, and obtain a red LED chip.

[0015] In a preferred embodiment, the p-type dopant source of the polarization-induced barrier layer is magnesia-dimethylzinc or dimethyl MgO, with a doping concentration of 1.0 × 10⁻⁶. 17 ~3.0×10 17 cm -3 The growth temperature is 700~780℃, and the growth rate is 0.1~0.2nm / s.

[0016] In a preferred embodiment, the bonding process involves a bonding temperature of 400~700℃, a bonding pressure of 3000~9000kg, and a bonding time of 10~60 minutes.

[0017] In one preferred embodiment, the GaAs substrate is removed by wet etching using a mixed solution of 10% ammonia and 10% hydrogen peroxide in a volume ratio of 4:1 for 30-50 minutes; the Micro-LED mesa structure is then fabricated by ICP etching using a Cl2+BCl3 mixed gas.

[0018] In a preferred embodiment, a SiO2 sidewall passivation layer is deposited using a PECVD process, with N2O and SiH4 as the reaction gases and a deposition temperature of 250°C; an ITO transparent conductive layer and a metal electrode are prepared using an electron beam evaporation process, and the electrode patterning is completed by a lift-off process.

[0019] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows: 1. Significantly enhanced carrier confinement capability, solving the efficiency collapse problem: This invention designs the quantum well barrier layer as a high-Al composition continuously gradient structure. By gradually changing the Al composition from 0.3~0.4 to 0.5, the valence band level between the barrier layer and the well layer is significantly increased from the traditional 150~220meV to 250~320meV, an improvement of more than 50%. This greatly enhances the hole confinement capability, effectively suppresses the lateral diffusion and overflow of carriers at the micro-scale of Micro-LEDs, and fundamentally solves the efficiency collapse problem of micro-pixels.

[0020] 2. Overcoming inherent contradictions in doping, significantly improving hole injection efficiency: This invention uses only 1.0 × 10⁻⁶ holes in the polarization-induced barrier layer. 17 ~3.0×10 17 cm -3 The low-concentration p-type doping completely avoids the self-compensation effect, crystal degradation, and Mg diffusion luminescence quenching problems caused by high-concentration doping. Simultaneously, by utilizing the polarization effect generated by the continuous gradual change in Al composition, a three-dimensional hole gas (3DHG) is induced in the barrier layer, allowing the hole concentration within the barrier layer to break through the doping concentration limit and jump to 1.0 × 10⁻⁶. 18 cm -3 The hole concentration is increased by an order of magnitude, significantly improving the hole injection efficiency and radiative recombination efficiency in the active region.

[0021] 3. Significantly Improved High-Temperature Stability and Reliability: The high-Al composition gradient barrier layer of this invention effectively suppresses carrier thermal leakage at high temperatures by significantly increasing the valence band barrier height. Simultaneously, the three-dimensional hole gas formed by polarization induction is independent of impurity ionization, and the hole concentration fluctuates minimally with temperature, ensuring the stability of device performance under high-temperature conditions. Testing shows that the device of this invention retains over 92% efficiency at 85℃ and exhibits less than 5% optical decay after 1000 hours of long-term aging, far exceeding existing technologies and perfectly suited for wide-temperature-range, high-reliability applications such as automotive and outdoor displays.

[0022] 4. Strong process compatibility, suitable for large-scale mass production: The epitaxial structure and fabrication process of this invention are fully compatible with existing commercial MOCVD epitaxial equipment, Micro-LED chip processing lines and CMOS driving bonding processes. No new dedicated equipment is required, and there is no need to significantly adjust the process parameters of existing production lines. It has extremely strong process compatibility and mass production capability. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the epitaxial structure of an AlGaInP red Micro-LED chip with a high Al composition polarization-induced barrier layer according to the present invention. Figure 2 This is a flowchart of a method for fabricating an AlGaInP red Micro-LED chip with a high Al composition polarization-induced barrier layer according to the present invention. Figure 3 This is a schematic diagram of the structure of an AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer according to the present invention. Among them, 1. GaAs substrate; 2. n-type GaAs buffer layer; 3. n-type AlGaInP etch barrier layer; 4. n-type GaAs ohmic contact layer; 5. n-type AlGaInP confinement layer; 6. periodic quantum well structure; 7. p-type AlGaInP spacer layer; 8. p-type AlInP electron blocking layer; 9. p-type GaP ohmic contact layer; 10. epitaxial wafer; 11. p-type ITO transparent conductive layer; 12. bonding metal layer; 13. Si-based CMOS driving circuit; 14. SiO2 sidewall passivation layer; 15. n-type ITO transparent conductive layer; 16. n-type metal electrode. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0028] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0029] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0030] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] All epitaxial growth in the embodiments and comparative examples of this invention was performed using a commercial Thomas Swan 3×2-inch MOCVD system. The carrier gas was high-purity hydrogen, the group III sources were trimethylaluminum, trimethylgallium, and trimethylindium, the group V sources were arsine and phosphine, the n-type doping source was silane, and the p-type doping source was magnesium thiocene. The chip process was performed using standard equipment from commercial semiconductor processing lines, and performance testing was conducted using a probe station, spectrometer, integrating sphere, and high and low temperature test chamber.

[0032] Example 1 Please see Figure 1-3 This application provides an AlGaInP red-light Micro-LED chip with a high Al composition polarization-induced barrier layer and its fabrication method. It is a standard type, adapted to general Micro-LED displays, as detailed below: I. Epitaxial growth.

[0033] (a) Growth of n-type GaAs buffer layer 2: A 6-inch n-type GaAs substrate 1 with a thickness of 550 μm, crystal orientation (100), and bevel angle of 10° was selected; an n-type GaAs buffer layer 2 was epitaxially grown on the substrate, with silane as the doping source and a doping concentration of 2.0 × 10⁻⁶. 18 cm -3 The thickness is 200 nm, the growth temperature is 650 ℃, and the growth rate is 0.5 nm / s.

[0034] (b) Growth of n-type AlGaInP etch barrier layer 3: n-type (AlGaInP) is epitaxially grown on n-type GaAs buffer layer 2. 0.3 Ga 0.7 ) 0.5 The InP etch barrier layer is doped with silane as the doping source at a concentration of 2.0 × 10⁻⁶. 18 cm -3 The thickness is 200 nm, the growth temperature is 750 ℃, and the growth rate is 0.5 nm / s.

[0035] (c) Growth of n-type GaAs ohmic contact layer 4: An n-type GaAs ohmic contact layer 4 is epitaxially grown on the etch stop layer, with silane as the doping source and a doping concentration of 4.0 × 10⁻⁶. 18 cm -3 The thickness is 30 nm, the growth temperature is 650 ℃, and the growth rate is 0.2 nm / s.

[0036] (d) Growth of n-type AlGaInP confinement layer 5: n-type (AlGaInP) confinement layer 5 is epitaxially grown on n-type GaAs ohmic contact layer 4. 0.8 Ga 0.2 ) 0.5 The InP confinement layer has a doping source of silane and a doping concentration of 2.0 × 10⁻⁶. 18 cm -3The thickness is 300 nm, the growth temperature is 750 ℃, and the growth rate is 0.3 nm / s.

[0037] (e) Growth of periodic quantum well structures 6: Three pairs of periodic quantum well structures 6 are epitaxially grown on the n-type AlGaInP confinement layer 5, each pair consisting of alternating GaInP well layers and p-type doped polarization-induced barrier layers; wherein the GaInP well layer thickness is 3 nm, the growth temperature is 750 °C, and the growth rate is 0.15 nm / s; the polarization-induced barrier layer thickness is 7 nm, and the Al composition is (Al... 0.8 Ga 0.2 ) 0.5 InP continuously and linearly transitions to Al 0.5 In 0.5 P, the doping source is magnesia-diocene, and the doping concentration is 2.0 × 10⁻⁶. 17 cm -3 The growth temperature was 750℃, and the growth rate was 0.15 nm / s; Hall effect measurements showed that the hole concentration within the barrier layer was 1.5 × 10⁻⁶. 18 cm -3 The valence band level is 300 meV.

[0038] (f) Growth of p-type AlGaInP spacer layer 7: Epitaxial growth of p-type (AlGaInP) spacer layer on quantum well structure 0.85 Ga 0.15 ) 0.5 The InP spacer layer is doped with magnesium pyrocene as the doping source and has a doping concentration of 1.5 × 10⁻⁶. 18 cm -3 The thickness is 50 nm, the growth temperature is 750 ℃, and the growth rate is 0.3 nm / s.

[0039] (g) Growth of p-type AlInP electron blocking layer 8: Epitaxial growth of p-type Al on the spacer layer 0.5 In 0.5 The p-electron blocking layer is doped with magnesia-diocene as the doping source and has a doping concentration of 2.0 × 10⁻⁶. 18 cm -3 The thickness is 500 nm, the growth temperature is 750 ℃, and the growth rate is 0.3 nm / s.

[0040] (h) Growth of p-type GaP ohmic contact layer 9: A p-type GaP ohmic contact layer 9 is epitaxially grown on the electron blocking layer. The doping source is magnesia-magnesium diacene and carbon tetrabromide, and the doping concentration is 4.0 × 10⁻⁶. 18 cm -3 The epitaxial wafer 10 was prepared with a thickness of 200 nm, a growth temperature of 750 °C, and a growth rate of 0.3 nm / s.

[0041] II. Chip fabrication process.

[0042] (a) Preparation and annealing of p-type ITO transparent conductive layer 11: A 150 nm thick p-type ITO transparent conductive layer 11 was deposited on the p-type GaP ohmic contact layer 9 of the epitaxial wafer 10 by electron beam evaporation. The indium-tin molar ratio of the ITO target was 9:1, and the deposition rate was 1 nm / s. Subsequently, the layer was annealed using a rapid thermal annealing (RTA) machine at a temperature of 400 °C for 180 s under nitrogen atmosphere protection.

[0043] (b) Preparation of bonding metal layer 12 and CMOS bonding: On the p-type ITO transparent conductive layer 11, a 300nm Cr / 300nm Pt / 200nm Au bonding metal layer 12 is deposited sequentially by electron beam evaporation at a deposition rate of 1nm / s; at the same time, a bonding metal layer 12 with the same structure is deposited on the front side of the Si-based CMOS driving circuit 13; the front side of the epitaxial wafer 10 is bonded to the front side of the CMOS driving circuit, and a hot press bonding machine is used for bonding at a bonding temperature of 500℃, a bonding pressure of 4500kg, and a bonding time of 30 minutes to form a stable electrical and mechanical connection.

[0044] (c) Wet removal of GaAs substrate 1: A mixed solution of 10% ammonia and 10% hydrogen peroxide with a volume ratio of 4:1 was used to wet etch the bonded sample to completely remove GaAs substrate 1. The etching time was 40 minutes. The sample was then rinsed with deionized water and dried with nitrogen.

[0045] (d) Fabrication of Micro-LED mesa structure: A 1500 nm thick positive photoresist 5214 was spin-coated onto the sample surface, pre-baked and cured, and then exposed to ultraviolet light. The sample was developed with tetramethylammonium hydroxide (TMAH) aqueous solution for 120 s to form a mesa patterning mask. The epitaxial layer of the patterned area was removed by ICP etching process. The etching gas was a mixture of Cl2 and BCl3. The etching was stopped at the n-type GaAs ohmic contact layer 4. The sample was then cleaned with acetone and isopropanol in sequence to remove the remaining photoresist, forming a 20 μm × 20 μm Micro-LED mesa array with a pixel pitch of 30 μm.

[0046] (e) Sidewall passivation and device isolation: A 50 nm thick SiO2 sidewall passivation layer 14 was deposited on the sample surface using PECVD process. The reaction gases were N2O (flow rate 1200 sccm) and SiH4 (flow rate 300 sccm), the plasma power was 100 W, the deposition temperature was 250 °C, and the deposition rate was 1 nm / s. Subsequently, the inter-pixel region was etched using ion beam etching (IBE) process to etch through the ITO layer and the bonding metal layer 12 to achieve electrical isolation between devices. The etching power was 300 W, the etching rate was 2 nm / s, and the etching time was 600 s.

[0047] (f) n-type interconnect and electrode fabrication: A 300 nm thick SiO2 mask layer was deposited on the sample surface using PECVD, with deposition parameters consistent with step (e); after spin-coating photoresist and exposure and development, the SiO2 in the n-type electrode area was removed by ICP etching to expose the n-type GaAs ohmic contact layer 4. The etching gas was a CF4+Ar mixed gas, and the etching time was 400 s; after removing the photoresist, an n-type ITO transparent conductive layer 15 was deposited by electron beam evaporation to realize the n-type interconnect, and then a 300 nm Cr / 300 nm Pt / 200 nm Au was deposited as the n-type metal electrode 16. The electrode patterning was completed by a lift-off process to obtain the final red LED chip.

[0048] Performance test results: The red LED chip prepared in this embodiment has a peak emission wavelength of 630nm at room temperature, a turn-on voltage of 2.1V, and a voltage rating of 20A / cm. 2 The external quantum efficiency (EQE) at current density is 23.5%, and the optical output power is 12.8mW; the efficiency retention rate is 93.2% at 85℃; and the optical decay is only 4.2% after 1000 hours of constant current aging.

[0049] Example 2 This application provides an AlGaInP red-light Micro-LED chip with a high Al composition polarization-induced barrier layer and its fabrication method. It is a low-power chip suitable for AR / VR near-eye displays. The only difference between this embodiment and Embodiment 1 is: 1. Epitaxial structure parameters: The n-type AlGaInP confinement layer 5 is (Al 0.9 Ga 0.1 ) 0.5 InP, thickness 400nm; The quantum well pair number is 3, and the polarization-induced barrier layer Al composition consists of (Al... 0.8 Ga 0.2 ) 0.5 InP gradually transitions to Al 0.5 In 0.5 P, thickness 8 nm, doping concentration 1.5 × 10⁻⁶ 17 cm -3 Hole concentration 1.3×10 18 cm -3 ; p-type AlInP electron blocking layer 8 has a thickness of 600 nm, and p-type GaP ohmic contact layer 9 has a thickness of 250 nm.

[0050] 2. Chip process parameters: The SiO2 sidewall passivation layer 14 has a thickness of 60nm, a mesa size of 15μm×15μm, and a pixel pitch of 25μm.

[0051] Performance test results: The red LED chip prepared in this embodiment has a peak wavelength of 630nm at room temperature and a wavelength of 5A / cm². 2 With an EQE of 24.8% at low current density and a turn-on voltage of 2.0V, it maintains an efficiency of 94.1% at 85℃ and exhibits a light decay of 3.8% after 1000 hours of aging, perfectly meeting the low power consumption and high stability requirements of AR / VR.

[0052] Example 3 This application provides an AlGaInP red-light Micro-LED chip with a high Al composition polarization-induced barrier layer and its fabrication method. It is a high-brightness, high-power type suitable for automotive / outdoor displays. The only difference between this embodiment and Embodiment 1 is: 1. Epitaxial structure parameters: The n-type AlGaInP confinement layer 5 is Al 0.5 In 0.5 P, thickness 500nm; The quantum well pair count is 5, the GaInP well layer thickness is 4.5 nm, and the polarization-induced barrier layer Al composition consists of (Al... 0.9 Ga 0.1 ) 0.5 InP gradually transitions to Al 0.5 In 0.5 P, 10 nm thick, doped with dimethyl zinc at a doping concentration of 3.0 × 10⁻⁶. 17 cm -3 Hole concentration 1.8 × 10 18 cm -3 320meV; p-type AlGaInP spacer layer 7 has a thickness of 100 nm, p-type AlInP electron blocking layer 8 has a thickness of 900 nm, and p-type GaP ohmic contact layer 9 has a thickness of 300 nm.

[0053] 2. Chip process parameters: Bonding temperature 600℃, bonding pressure 9000kg, bonding time 30 minutes; The mesa has a size of 50μm×50μm, a pixel pitch of 75μm, and a SiO2 sidewall passivation layer with a thickness of 100nm.

[0054] Performance test results: The red LED chip prepared in this embodiment has a peak wavelength of 635nm at room temperature and a wavelength of 50A / cm. 2At high current density, the EQE is 21.2% and the optical output power is 35.6mW; the efficiency retention rate is 92.5% at 85℃, and the optical decay is 4.5% after 1000 hours of aging. The efficiency droop at high current is significantly lower than that of existing technologies, making it suitable for high brightness and wide temperature range requirements in automotive and outdoor applications.

[0055] Example 4 This application provides an AlGaInP red-light Micro-LED chip with a high Al composition polarization-induced barrier layer and its fabrication method. It is a micro-pixel type, suitable for ultra-high-definition Micro-LED displays. The only difference between this embodiment and Embodiment 1 is: 1. Epitaxial structure parameters: The quantum well pair count is 1, the GaInP well layer thickness is 1.5 nm, and the polarization-induced barrier layer Al composition consists of (Al... 0.7 Ga 0.3 ) 0.5 InP gradually transitions to Al 0.5 In 0.5 P, thickness 4 nm, doping concentration 1.0 × 10⁻⁶ 17 cm -3 Hole concentration 1.1×10 18 cm -3 ; The n-type AlGaInP confinement layer 5 is (Al 0.7 Ga 0.3 ) 0.5 InP, 150nm thick, p-type AlInP electron blocking layer 8, 200nm thick.

[0056] 2. Chip process parameters: Bonding temperature 400℃, bonding pressure 3000kg, bonding time 60 minutes; The mesa has a size of 5μm × 5μm, a pixel pitch of 10μm, and a SiO2 sidewall passivation layer with a thickness of 10nm.

[0057] Performance test results: The red LED chip prepared in this embodiment has a peak wavelength of 625nm at room temperature and a wavelength of 20A / cm². 2 At current density, the EQE is 19.8%, which is more than 85% more efficient than existing technology chips of the same size, solving the efficiency collapse problem of ultra-small pixels.

[0058] Example 5 This application provides an AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer and its fabrication method, which is a low-cost mass production type. The only difference between this embodiment and Embodiment 1 is that: 1. Epitaxial structure parameters: The substrate used is a 4-inch GaAs substrate 1 with a thickness of 500μm and a bevel angle of 8°; The polarization-induced barrier layer doping source is dimethyl zinc, with a doping concentration of 2.0 × 10⁻⁶. 17 cm -3 The number of quantum well pairs is 3, the well layer thickness is 3nm, and the barrier layer thickness is 7nm. The thickness of each epitaxial layer is taken from the middle value within the process window to meet the uniformity requirements of mass production lines.

[0059] 2. Chip process parameters: All process steps use standard formulas for mass production lines, are compatible with existing production lines, and require no additional adjustments.

[0060] Performance test results: The red LED chip prepared in this embodiment has an intra-wafer wavelength uniformity of ±2nm, an EQE uniformity of ±1.5%, a yield exceeding 95%, and a performance of @20A / cm. 2 With an EQE of 22.7%, it combines high performance with high mass production capability.

[0061] Comparative Example 1 This comparative example adopts the mainstream solution of existing technology, and the only difference from Example 1 is: The barrier layer of the quantum well structure uses Al with an Al composition of 0.3%. 0.3 Ga 0.2 In 0.5 The p-type structure is a conventional fixed-composition structure with no Al composition gradient and a p-type doping concentration of 1.0 × 10⁻⁶. 18 cm -3 The remaining epitaxial structure and chip process parameters are exactly the same as in Example 1.

[0062] Performance test results: The red LED chip prepared in this comparative example achieves a light output of 20 A / cm² at room temperature. 2 The EQE at current density is only 12.3%, the efficiency retention rate at 85℃ is only 76.5%, and the light decay is as high as 18.7% after 1000 hours of aging. All performance characteristics are far inferior to those of the embodiments of the present invention.

[0063] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer, characterized in that, It includes, from bottom to top, a GaAs substrate, an n-type GaAs buffer layer, an n-type AlGaInP etch barrier layer, an n-type GaAs ohmic contact layer, an n-type AlGaInP confinement layer, a periodic quantum well structure, a p-type AlGaInP spacer layer, a p-type AlInP electron blocking layer, and a p-type GaP ohmic contact layer. The periodic quantum well structure comprises alternating layers of GaInP wells and p-type doped polarization-induced barrier layers. The polarization-induced barrier layer is a quaternary semiconductor structure with a continuously gradient Al composition, its composition consisting of (Al... x2 Ga 1-x2 ) y2 InP gradually changes to Al 0.5 In 0.5 P, where x2 takes the value of 0.7~0.9 and y2 takes the value of 0.5; the p-type doping concentration of the polarization-induced barrier layer is 1.0×10⁻⁶. 17 ~3.0×10 17 cm -3 The polarization effect induced by the gradual change in Al composition induces the formation of three-dimensional hole gas, resulting in a hole concentration of 1.0 × 10⁻⁶ within the barrier layer. 18 cm -3 and above.

2. The AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer according to claim 1, characterized in that, The periodic quantum well structure has 1 to 5 quantum well pairs, the GaInP well layer has a thickness of 1.5 to 4.5 nm, the polarization-induced barrier layer has a thickness of 4 to 10 nm, and the valence band order of the polarization-induced barrier layer is 250 to 320 meV.

3. The AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer according to claim 1, characterized in that, The n-type AlGaInP confinement layer is (Al x1 Ga 1-x1 ) y1 The InP structure has x1 values ​​ranging from 0.7 to 1, y1 values ​​ranging from 0.5, and a thickness of 150 to 500 nm; the p-type AlGaInP spacer layer is (Al x3 Ga 1-x3 ) y3 The AlInP structure has x3 values ​​of 0.8–0.9 and y3 values ​​of 0.5, with a thickness of 30–100 nm; the p-type AlInP electron blocking layer is Al x4 In 1-x4 The structure is a P-structure, where x4 is 0.5 and the thickness is 200~900nm.

4. The AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer according to claim 1, characterized in that, The top surface of the p-type GaP ohmic contact layer is sequentially stacked with a p-type ITO transparent conductive layer and a bonding metal layer, and the bonding metal layer is bonded to the Si-based CMOS driving circuit. After the GaAs substrate is removed by wet process, the surface of the n-type GaAs ohmic contact layer is provided with an n-type ITO transparent conductive layer and an n-type metal electrode, and the sidewalls of the chip mesa are covered with a SiO2 sidewall passivation layer.

5. The AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer according to claim 4, characterized in that, The thickness of the p-type ITO transparent conductive layer is 150 nm, and its indium-tin molar ratio is 9:1; the bonding metal layer is a Cr / Pt / Au three-layer stacked structure with a total thickness of 800 nm; the thickness of the SiO2 sidewall passivation layer is 10~100 nm.

6. A method for fabricating an AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer, characterized in that, Includes the following steps: S1, using a metal-organic chemical vapor deposition system, an n-type GaAs buffer layer, an n-type AlGaInP etch barrier layer, an n-type GaAs ohmic contact layer, and an n-type AlGaInP confinement layer are epitaxially grown sequentially from bottom to top on a GaAs substrate. S2, a periodic quantum well structure is epitaxially grown on the n-type AlGaInP confinement layer, wherein the barrier layer of the periodic quantum well structure is made of Al composition (Al x2 Ga 1-x2 ) y2 InP gradually changes to Al 0.5 In 0.5 P polarization-induced barrier layer, and p-type doping of the polarization-induced barrier layer; S3, continue to epitaxially grow a p-type AlGaInP spacer layer, a p-type AlInP electron blocking layer, and a p-type GaP ohmic contact layer on the periodic quantum well structure to complete the epitaxial wafer fabrication; S4, a p-type ITO transparent conductive layer is prepared on the p-type GaP ohmic contact layer of the epitaxial wafer and annealed. The epitaxial wafer is bonded to the Si-based CMOS driving circuit through a bonding metal layer, and the GaAs substrate is removed by wet process. S5. Fabricate a Micro-LED mesa structure, deposit a SiO2 sidewall passivation layer, complete the fabrication of the n-type interconnect structure and n-type metal electrode, and obtain a red LED chip.

7. The method for fabricating an AlGaInP red Micro-LED chip with a high Al composition polarization-induced barrier layer according to claim 6, characterized in that, The p-type dopant source of the polarization-induced barrier layer is magnesia-dimethylzinc or dimethyl magnesia, with a doping concentration of 1.0 × 10⁻⁶. 17 ~3.0×10 17 cm -3 The growth temperature is 700~780℃, and the growth rate is 0.1~0.2nm / s.

8. The method for fabricating an AlGaInP red Micro-LED chip with a high Al composition polarization-induced barrier layer according to claim 6, characterized in that, The bonding process has a bonding temperature of 400~700℃, a bonding pressure of 3000~9000kg, and a bonding time of 10~60 minutes.

9. The method for fabricating an AlGaInP red micro-LED chip with a high Al composition polarization-induced barrier layer according to claim 6, characterized in that, The GaAs substrate was removed by wet etching using a mixed solution of 10% ammonia and 10% hydrogen peroxide at a volume ratio of 4:1 for 30-50 minutes. The Micro-LED mesa structure was fabricated by ICP etching using a Cl2+BCl3 mixed gas.

10. The method for fabricating an AlGaInP red Micro-LED chip with a high Al composition polarization-induced barrier layer according to claim 6, characterized in that, A SiO2 sidewall passivation layer was deposited using PECVD with N2O and SiH4 as the reaction gases at a deposition temperature of 250℃. An ITO transparent conductive layer and metal electrodes were prepared using electron beam evaporation, and the electrodes were patterned using a lift-off process.

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