A vertical high-voltage light-emitting diode chip and its fabrication method

Abstract

This invention provides a vertical high-voltage light-emitting diode (LED) chip and its fabrication method. The vertical high-voltage LED chip includes a conductive silicon substrate; a bonding metal layer disposed above the conductive silicon substrate; an epitaxial layer disposed above the bonding metal layer, the epitaxial layer comprising, from bottom to top, a P-type GaN layer, an active light-emitting layer, and an N-type GaN layer; a segmentation channel structure within the epitaxial layer, dividing the epitaxial layer into several independently driveable epitaxial layer units; the segmentation channel structure is composed of a first segmentation channel and a second segmentation channel, with their projection centers coinciding and penetrating the entire epitaxial layer; wherein the width of the first segmentation channel is greater than the width of the second segmentation channel, and the depth of the first segmentation channel is less than the depth of the second segmentation channel; a conductive metal layer is disposed between the epitaxial layer and the bonding metal layer, and a P-type pad layer, significantly improving the chip fabrication yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a vertical high-voltage light-emitting diode chip and its fabrication method. Background Technology

[0002] Light-emitting diode (LED) chips are widely used in lighting and display fields due to their energy efficiency and high performance. In recent years, vertical LED chips have been developed for use in automotive headlights, and subsequently, vertical high-voltage LED chips were proposed.

[0003] In existing technologies, the fabrication method for vertical high voltage LED chips still follows the same approach as that for flip-chip LED chips. However, vertical high voltage LED chips require bonding and stripping processes. If the traditional flip-chip fabrication method is followed, the epitaxial layer of some chips will detach after the stripping process, resulting in a low overall yield for the vertical high voltage LED chips. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a vertical high-voltage light-emitting diode chip and its fabrication method, thereby resolving the technical issues described in the background section.

[0005] On the one hand, the invention provides the following technical solution: a vertical high-voltage light-emitting diode chip, comprising: Conductive silicon substrate; A bonding metal layer is disposed above the conductive silicon substrate; An epitaxial layer is disposed above the bonding metal layer. The epitaxial layer includes, from bottom to top, a P-type GaN layer, an active light-emitting layer, and an N-type GaN layer. A segmentation channel structure is provided within the epitaxial layer, dividing it into several independently driveable epitaxial layer units. The segmentation channel structure is composed of a first segmentation channel and a second segmentation channel, with their projection centers coinciding and both penetrating the entire epitaxial layer. The width of the first segmentation channel is greater than the width of the second segmentation channel, and the depth of the first segmentation channel is less than the depth of the second segmentation channel. A conductive metal layer is disposed between the epitaxial layer and the bonding metal layer for electrically connecting each epitaxial layer unit; A P-type pad layer is disposed on the surface of the N-type GaN layer and is electrically connected to the conductive metal layer.

[0006] Compared with the prior art, the beneficial effects of the present invention are as follows: by setting a segmentation channel structure composed of a first segmentation channel and a second segmentation channel in the epitaxial layer, wherein the width of the first segmentation channel is greater than the width of the second segmentation channel and the depth of the first segmentation channel is less than the depth of the second segmentation channel, the first segmentation channel is prepared before the bonding process and the second segmentation channel is prepared after the laser lift-off process, which effectively solves the problem that the epitaxial layer of the vertical high voltage light-emitting diode chip is easy to fall off after the lift-off process in the prior art, and significantly improves the chip preparation yield.

[0007] Furthermore, the width of the first dividing channel is between 10 μm and 15 μm, and the depth is between 1 / 20 and 1 / 10 of the overall thickness of the epitaxial layer; The width of the second segment is between 5 μm and 10 μm, and the depth is between 9 / 10 and 19 / 20 of the overall thickness of the epitaxial layer.

[0008] Furthermore, it also includes: A first insulating layer is disposed on the surface of the epitaxial layer, and the first insulating layer has a P-type first insulating layer opening and an N-type first insulating layer opening; A metal reflective layer is disposed on the first insulating layer. The metal reflective layer is electrically connected to the P-type GaN layer through the opening in the P-type first insulating layer, and electrically connected to the N-type GaN layer conductive step through the opening in the N-type first insulating layer. A second insulating layer is disposed on the metal reflective layer, and the second insulating layer has P-type second insulating layer through holes and N-type second insulating layer through holes; A third insulating layer is disposed on the conductive metal layer, and the third insulating layer has an N-type third insulating layer through hole to expose the conductive metal layer.

[0009] Furthermore, the conductive metal layer includes a P-type metal layer, a bridging metal layer, and an N-type metal layer, wherein: The P-type metal layer is electrically connected to the metal reflective layer corresponding to the first epitaxial layer unit in the series direction; The bridging metal layer electrically connects the N-type metal layer of the upstream epitaxial layer unit to the metal reflective layer of the downstream epitaxial layer unit in two adjacent epitaxial layer units. The N-type metal layer is electrically connected to the N-type GaN layer conductive step corresponding to the last epitaxial layer unit in the series direction.

[0010] Furthermore, it also includes a P-type conductive via, which sequentially penetrates the N-type GaN layer, the active light-emitting layer, the P-type GaN layer, the first insulating layer, and the second insulating layer until the P-type metal layer is exposed.

[0011] Furthermore, the bonding metal layer is formed by hot-pressing a first bonding metal sublayer and a second bonding metal sublayer, wherein the first bonding metal sublayer is disposed between the epitaxial layer and the second bonding metal sublayer, and the second bonding metal sublayer is disposed between the conductive silicon substrate and the first bonding metal sublayer.

[0012] On the other hand, the present invention also proposes a method for fabricating a vertical high-voltage light-emitting diode chip, the method comprising the following steps: An epitaxial layer is formed by sequentially growing an N-type GaN layer, an active light-emitting layer, and a P-type GaN layer on the growth substrate. The epitaxial layer is etched for the first time to form the first dividing channel; A first insulating layer, a metal reflective layer, a second insulating layer, a conductive metal layer, and a third insulating layer are sequentially formed on the surface of the epitaxial layer. The epitaxial layer on which the third insulating layer is formed is transferred onto a conductive silicon substrate; Remove the growth substrate to expose the N-type GaN layer; The exposed N-type GaN layer is etched a second time, aligning with the position of the first dividing channel and etched downwards from one side of the N-type GaN layer to form a second dividing channel; wherein, the width of the first dividing channel is greater than the width of the second dividing channel, and the depth of the first dividing channel is less than the depth of the second dividing channel; the first dividing channel and the second dividing channel together constitute a dividing channel penetrating the epitaxial layer, dividing the epitaxial layer into multiple epitaxial layer units; A P-type conductive via is formed on the surface of the N-type GaN layer, and a P-type pad layer is formed to complete the fabrication of the vertical high-voltage light-emitting diode chip.

[0013] Furthermore, the step of transferring the epitaxial layer on which the third insulating layer is formed onto the conductive silicon substrate includes: A first bonding metal sublayer is formed above the conductive metal layer; A conductive silicon substrate is provided, and a second bonding metal sublayer is formed on the conductive silicon substrate; The first bonding metal sublayer and the second bonding metal sublayer are bonded together using a hot-press bonding process.

[0014] Furthermore, the step of forming the first bonded metal sublayer includes: sequentially depositing a Cr metal layer, an Al metal layer, a Ti metal layer, a first Ni metal layer, a first Sn metal layer, a second Ni metal layer, and a second Sn metal layer on the third insulating layer using an electron beam evaporation process; The step of forming the second bonded metal sublayer includes: sequentially depositing a Ti metal layer, a first Ni metal layer, a first Sn metal layer, a second Ni metal layer, and a second Sn metal layer on the conductive silicon substrate using an electron beam evaporation process; The thickness of the Cr metal layer is 30-50 Å, and the thickness of the Al metal layer is 1200-2000 Å. In the first and second bonded metal sublayers: the thickness of the Ti metal layer is 2000-4000 Å, the thickness of the first Ni metal layer is 3000-5000 Å, the thickness of the first Sn metal layer is 5000-10000 Å, the thickness of the second Ni metal layer is 1000-2000 Å, and the thickness of the second Sn metal layer is 2000-4000 Å.

[0015] Furthermore, the step of forming the metal reflective layer includes: sequentially depositing an ITO thin film, an Ag metal layer, and a Ti / Ni / Pt multilayer metal structure using an electron beam evaporation process, and forming it using a lift-off process; wherein the thickness of the ITO thin film is 30-50 Å, and the thickness of the Ag metal layer is 1200-2000 Å. The formation of the conductive metal layer specifically includes: sequentially depositing a multi-layered metal structure of Ti / Au / Ti / Pt / Ti / Pt / Ti using an electron beam evaporation process, and then shaping it using a lift-off process. Attached Figure Description

[0016] Figure 1 This is a top view of the vertical high-voltage light-emitting diode chip in the first embodiment of the present invention; Figure 2 for Figure 1 Sectional view at point AA; Figure 3 This is a schematic diagram of the structure of forming the epitaxial layer and conductive steps in step S01 of the second embodiment of the present invention; Figure 4 for Figure 3 Sectional view at point AA; Figure 5 This is a schematic diagram of the structure for forming the first dividing channel in step S02 of the second embodiment of the present invention; Figure 6 for Figure 5 Sectional view at point AA; Figure 7 This is a schematic diagram of the structure of forming the first insulating layer and opening in step S31 of the second embodiment of the present invention; Figure 8 for Figure 7 Sectional view at point AA; Figure 9This is a schematic diagram of the structure of the metal reflective layer formed in step S32 of the second embodiment of the present invention; Figure 10 for Figure 9 Sectional view at point AA; Figure 11 This is a schematic diagram of the structure of forming the second insulating layer and through hole in step S33 of the second embodiment of the present invention; Figure 12 for Figure 11 Sectional view at point AA; Figure 13 This is a schematic diagram of the structure for forming a conductive metal layer in step S34 of the second embodiment of the present invention; Figure 14 for Figure 13 Sectional view at point AA; Figure 15 This is a schematic diagram of the structure of forming the third insulating layer and through hole in step S35 of the second embodiment of the present invention; Figure 16 for Figure 15 Sectional view at point AA; Figure 17 This is a schematic diagram of the structure in the second embodiment of the present invention, showing the transfer of the epitaxial layer to the conductive silicon substrate in step S04. Figure 18 for Figure 17 Sectional view at point AA; Figure 19 This is a schematic diagram of the structure for laser lift-off of the growth substrate in step S05 of the second embodiment of the present invention; Figure 20 for Figure 19 Sectional view at point AA; Figure 21 This is a schematic diagram of the structure for forming the second dividing channel in step S06 of the second embodiment of the present invention; Figure 22 for Figure 21 Sectional view at point AA; Figure 23 This is a schematic diagram of the structure formed in step S07 of the second embodiment of the present invention, showing the formation of the P-type conductive via and the P-type pad layer. Figure 24 for Figure 23 Sectional view at point AA.

[0017] Key component symbols: 10. Growth substrate; 11. Epitaxial layer; 111. N-type GaN layer; 112. Active light-emitting layer; 113. P-type GaN layer; 114. Conductive step of N-type GaN layer; 115. First dividing channel; 12. First insulating layer; 121. P-type first insulating layer opening; 122. N-type first insulating layer opening; 13. Metal reflective layer; 14. Second insulating layer; 141. P-type second insulating layer via. ; 142, N-type second insulating layer via; 15, conductive metal layer; 151, P-type metal layer; 152, bridging metal layer; 153, N-type metal layer; 16, third insulating layer; 161, N-type third insulating layer via; 17, bonding metal layer; 171, first bonding metal sublayer; 172, second bonding metal sublayer; 18, conductive silicon substrate; 19, second partition channel; 20, P-type conductive via; 21, P-type pad layer.

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Example 1 Please see Figure 1 and Figure 2 The image shows a vertical high-voltage light-emitting diode chip in the first embodiment of the present invention, comprising: Conductive silicon substrate 18; A bonding metal layer 17 is disposed above the conductive silicon substrate 18; An epitaxial layer 11 is disposed above the bonding metal layer 17. The epitaxial layer 11 includes, from bottom to top, a P-type GaN layer 113, an active light-emitting layer 112, and an N-type GaN layer 111. The epitaxial layer 11 has a segmentation channel structure that divides the epitaxial layer 11 into several independently driveable epitaxial layer units. The segmentation channel structure is jointly formed by a first segmentation channel 115 and a second segmentation channel 19, and the projection centers of the two channels coincide and they run through the entire epitaxial layer 11. The width of the first segmentation channel 115 is greater than the width of the second segmentation channel 19, and the depth of the first segmentation channel 115 is less than the depth of the second segmentation channel 19. A conductive metal layer 15 is disposed between the epitaxial layer 11 and the bonding metal layer 17, and is used to electrically connect each epitaxial layer unit. The P-type pad layer 21 is disposed on the surface of the N-type GaN layer 111 and is electrically connected to the conductive metal layer 15.

[0023] Optionally, the width of the first dividing channel 115 is between 10 μm and 15 μm, and the depth is between 1 / 20 and 1 / 10 of the overall thickness of the epitaxial layer 11. The width of the second dividing channel 19 is between 5 μm and 10 μm, and the depth is between 9 / 10 and 19 / 20 of the overall thickness of the epitaxial layer 11.

[0024] In this embodiment, the width of the first dividing channel 115 is 10μm, 12.5μm, or 15μm, and the depth is 1 / 20, 1 / 15, or 1 / 10 of the overall thickness of the epitaxial layer 11; the width of the second dividing channel 19 is 5μm, 7μm, or 10μm, and the depth is 9 / 10, 37 / 40, or 19 / 20 of the overall thickness of the epitaxial layer 11.

[0025] Specifically, it also includes: A first insulating layer 12 is disposed on the surface of the epitaxial layer 11, and the first insulating layer 12 is provided with a P-type first insulating layer opening 121 and an N-type first insulating layer opening 122. A metal reflective layer 13 is disposed on the first insulating layer 12. The metal reflective layer 13 is electrically connected to the P-type GaN layer 113 through the P-type first insulating layer opening 121, and is electrically connected to the N-type GaN layer conductive step 114 of the N-type GaN layer 111 through the N-type first insulating layer opening 122. The second insulating layer 14 is disposed on the metal reflective layer 13, and the second insulating layer 14 has a P-type second insulating layer through hole 141 and an N-type second insulating layer through hole 142. A third insulating layer 16 is disposed on the conductive metal layer 15. The third insulating layer 16 has an N-type third insulating layer through hole 161 to expose the conductive metal layer 15.

[0026] More specifically, the metal reflective layer 13 is a multi-layer metal structure; The first insulating layer 12, the second insulating layer 14, and the third insulating layer 16 are all SiO2 thin films; The conductive metal layer 15 has a multi-layer metal structure.

[0027] In this embodiment, the metal reflective layer 13 is a multilayer metal structure, formed by sequentially depositing an ITO thin film (30-50 Å thick), Ag metal (1200-2000 Å thick), a Ti metal layer (1000-2000 Å thick), a Ni metal layer (1000-2000 Å thick), a Pt metal layer (1000-2000 Å thick), another Ti metal layer (1000-2000 Å thick), a Ni metal layer (1000-2000 Å thick), a Pt metal layer (2000-3000 Å thick), and another Ti metal layer (30-50 Å thick) using an electron beam evaporation process. Then, a lift-off process is used to remove the metal and photoresist layer on top of the photoresist, forming the metal reflective layer 13. The thickness of the conventional epitaxial layer 11 is 5-6 μm.

[0028] Specifically, the conductive metal layer 15 includes a P-type metal layer 151, a bridging metal layer 152, and an N-type metal layer 153, wherein: The P-type metal layer 151 is electrically connected to the metal reflective layer 13 corresponding to the first epitaxial layer unit in the series direction; The bridging metal layer 152 electrically connects the N-type metal layer 153 of the upstream epitaxial layer unit to the metal reflective layer 13 of the downstream epitaxial layer unit in two adjacent epitaxial layer units. The N-type metal layer 153 is electrically connected to the N-type GaN layer conductive step 114 corresponding to the last epitaxial layer unit in the series direction.

[0029] In this embodiment, the conductive metal layer 15 is a multilayer metal structure, which is formed by sequentially depositing Ti metal (thickness 30-50 Å), Au metal (thickness 5000-8000 Å), Ti metal (thickness 1000-2000 Å), Pt metal (thickness 1000-2000 Å), Ti metal (thickness 1000-2000 Å), Pt metal (thickness 1000-2000 Å), and Ti metal (thickness 1000-2000 Å) using an electron beam evaporation process; then the metal and photoresist on the photoresist are removed using a lift-off process to form the conductive metal layer 15.

[0030] Specifically, it also includes a P-type conductive via 20, which sequentially penetrates the N-type GaN layer 111, the active light-emitting layer 112, the P-type GaN layer 113, the first insulating layer 12 and the second insulating layer 14 until the P-type metal layer 151 is exposed.

[0031] Specifically, the bonding metal layer 17 is formed by hot-pressing a first bonding metal sublayer 171 and a second bonding metal sublayer 172. The first bonding metal sublayer 171 is disposed between the epitaxial layer 11 and the second bonding metal sublayer 172, and the second bonding metal sublayer 172 is disposed between the conductive silicon substrate 18 and the first bonding metal sublayer 171.

[0032] In this embodiment, the first bonding metal sublayer 171 is a multilayer metal structure, which, from bottom to top, includes a Cr layer, an Al layer, a Ti layer, a first Ni layer, a first Sn layer, a second Ni layer, and a second Sn layer. The second bonding metal sublayer 172 is a multilayer metal structure, which, from bottom to top, includes a Ti layer, a first Ni layer, a first Sn layer, a second Ni layer, and a second Sn layer.

[0033] Example 2 A method for fabricating a vertical high-voltage light-emitting diode chip according to a second embodiment of the present invention, the method comprising steps S01-S07: S01: A growth substrate 10 is provided, and an N-type GaN layer 111, an active light-emitting layer 112 and a P-type GaN layer 113 are sequentially grown on the growth substrate 10 to form an epitaxial layer 11; Please see Figure 3 and Figure 4 As shown, in this embodiment, a sapphire substrate is first provided. Then, an N-type GaN layer 111, an active light-emitting layer 112, and a P-type GaN layer 113 are sequentially fabricated on the sapphire substrate from bottom to top using an MOCVD process, forming an epitaxial layer 11. Subsequently, photoresist is coated on the surface of the P-type GaN layer 113. After exposure and development, part of the photoresist is removed, exposing the P-type GaN layer 113 in the area to be etched. Then, an inductively coupled plasma etching process is used to remove part of the P-type GaN layer 113 and the active light-emitting layer 112 below it until the N-type GaN layer 111 is exposed. Finally, the photoresist is removed, forming an N-type GaN layer conductive step 114.

[0034] S02: The epitaxial layer 11 is etched for the first time to form the first dividing channel 115; Please see Figure 5 and Figure 6As shown, in this embodiment, photoresist is coated on the surface of the N-type GaN layer conductive step 114 and the remaining P-type GaN layer 113. After exposure and development, part of the photoresist is removed. Then, part of the epitaxial layer 11 is removed using an inductively coupled plasma etching process. Finally, the photoresist is removed to form the first dividing channel 115. The width L1 of the first dividing channel 115 is greater than the width of the subsequently prepared second dividing channel 19, and L1 is between 10-15 μm. The depth H1 of the first dividing channel 115 is much smaller than the depth H2 of the subsequently prepared second dividing channel 19, and H1 is between 1 / 20 and 1 / 10 of the overall thickness of the epitaxial layer 11.

[0035] S03: A first insulating layer 12, a metal reflective layer 13, a second insulating layer 14, a conductive metal layer 15 and a third insulating layer 16 are sequentially formed on the surface of the epitaxial layer 11. Please see Figures 7 to 16 As shown, the specific steps of step S03 are as follows: S31: On the surfaces of the N-type GaN layer conductive step 114, the first dividing channel 115, and the remaining P-type GaN layer 113, a SiO2 thin film is deposited as a first insulating layer 12 using a PECVD process. Then, photoresist is coated on the surface of the first insulating layer 12, and after exposure and development, part of the photoresist is removed to expose the area to be opened. The exposed first insulating layer 12 is removed using BOE etching solution, and finally the photoresist is removed to form a P-type first insulating layer opening 121 on the P-type GaN layer 113 and an N-type first insulating layer opening 122 on the N-type GaN layer conductive step 114.

[0036] S32: A negative photoresist is coated on the first insulating layer 12 and the surface of the opening. After exposure and development, part of the photoresist is removed. Then, an ITO thin film (30-50 Å), an Ag metal layer (1200-2000 Å), a Ti layer (1000-2000 Å), a Ni layer (1000-2000 Å), a Pt layer (1000-2000 Å), a Ti layer (1000-2000 Å), a Ni layer (1000-2000 Å), a Pt layer (2000-3000 Å), and a Ti layer (30-50 Å) are deposited sequentially using an electron beam evaporation process. Then, the photoresist and the metal on it are removed using a lift-off process to form a metal reflective layer 13.

[0037] S33: A SiO2 thin film is deposited as a second insulating layer 14 using a PECVD process at the locations of the metal reflective layer 13 and those not covered by the metal reflective layer 13. Then, photoresist is coated on the surface of the second insulating layer 14, and after exposure and development, part of the photoresist is removed to expose the area to be opened. The exposed second insulating layer 14 is removed using an inductively coupled plasma etching process, and finally the photoresist is removed to form a P-type second insulating layer via 141 located on the metal reflective layer 13, and an N-type second insulating layer via 142 located within the N-type first insulating layer via 12.

[0038] S34: A negative photoresist is coated on the second insulating layer 14 and the vias of the second insulating layer 14. After exposure and development, part of the photoresist is removed. Then, a Ti layer (30-50 Å), an Au layer (5000-8000 Å), a Ti layer (1000-2000 Å), a Pt layer (1000-2000 Å), a Ti layer (1000-2000 Å), a Pt layer (1000-2000 Å), and a Ti layer (1000-2000 Å) are deposited sequentially using an electron beam evaporation process. Then, the photoresist and the metal on it are removed using a lift-off process to form a conductive metal layer 15. The conductive metal layer 15 includes a P-type metal layer 151, a bridging metal layer 152, and an N-type metal layer 153. Specifically, the P-type metal layer 151 is electrically connected to the metal reflective layer 13 corresponding to the first epitaxial layer unit in the series direction; the bridging metal layer 152 electrically connects the N-type metal layer 153 of the previous unit to the metal reflective layer 13 of the next unit in two adjacent epitaxial layer units; and the N-type metal layer 153 is electrically connected to the N-type GaN layer conductive step 114 corresponding to the last epitaxial layer unit in the series direction.

[0039] S35: A SiO2 thin film is deposited as a third insulating layer 16 using a PECVD process at the locations of the conductive metal layer 15 and those not covered by the conductive metal layer 15. Then, photoresist is coated on the surface of the third insulating layer 16, and after exposure and development, part of the photoresist is removed to expose the area to be opened. The exposed third insulating layer 16 is removed using an inductively coupled plasma etching process, and finally the photoresist is removed to form an N-type third insulating layer via 161.

[0040] S04: The epitaxial layer 11 on which the third insulating layer 16 is formed is transferred onto the conductive silicon substrate 18; Specifically, the step of transferring the epitaxial layer 11 on which the third insulating layer 16 is formed onto the conductive silicon substrate 18 includes: S41: A first bonding metal sublayer 171 is formed above the conductive metal layer 15; S42: Provide a conductive silicon substrate 18, and form a second bonding metal sublayer 172 on the conductive silicon substrate 18; S43: The first bonding metal sublayer 171 and the second bonding metal sublayer 172 are bonded by hot pressing bonding process.

[0041] More specifically, the step of forming the first bonding metal sublayer 171 includes: sequentially depositing a Cr layer (30-50 Å), an Al layer (1200-2000 Å), a Ti layer (2000-4000 Å), a first Ni layer (3000-5000 Å), a first Sn layer (5000-10000 Å), a second Ni layer (1000-2000 Å), and a second Sn layer (2000-4000 Å) on the third insulating layer 16 using an electron beam evaporation process. The step of forming the second bonding metal sublayer 172 includes: sequentially depositing a Ti layer (2000-4000 Å), a first Ni layer (3000-5000 Å), a first Sn layer (5000-10000 Å), a second Ni layer (1000-2000 Å), and a second Sn layer (2000-4000 Å) on the conductive silicon substrate 18 using an electron beam evaporation process.

[0042] Please see Figure 17 and Figure 18 As shown, in this embodiment, on the surface of the N-type third insulating layer via 161 and the third insulating layer 16, a Cr layer (30-50 Å), an Al layer (1200-2000 Å), a Ti layer (2000-4000 Å), a first Ni layer (3000-5000 Å), a first Sn layer (5000-10000 Å), a second Ni layer (1000-2000 Å), and a second Sn layer (2000-4000 Å) are sequentially deposited using an electron beam evaporation process to form a first bonding metal sublayer 171; Then, a conductive silicon substrate 18 is provided, on which a Ti layer (2000-4000 Å), a first Ni layer (3000-5000 Å), a first Sn layer (5000-10000 Å), a second Ni layer (1000-2000 Å), and a second Sn layer (2000-4000 Å) are sequentially deposited using an electron beam evaporation process to form a second bonding metal sublayer 172; then, the first bonding metal sublayer 171 and the second bonding metal sublayer 172 are bonded together by a hot-press bonding process.

[0043] S05: Remove the growth substrate 10 to expose the N-type GaN layer 111; Please see Figure 19 and Figure 20 As shown, in this embodiment, the growth substrate 10 is removed using a laser lift-off process to expose the N-type GaN layer 111.

[0044] S06: Perform a second etching on the exposed N-type GaN layer 111, etching downwards from one side of the N-type GaN layer 111, aligned with the position of the first dividing channel 115, to form a second dividing channel 19; wherein, the width of the first dividing channel 115 is greater than the width of the second dividing channel 19, and the depth of the first dividing channel 115 is less than the depth of the second dividing channel 19; the first dividing channel 115 and the second dividing channel 19 together constitute a dividing channel penetrating the epitaxial layer 11, dividing the epitaxial layer 11 into multiple epitaxial layer units; Please see Figure 21 and Figure 22 As shown, in this embodiment, photoresist is coated on the exposed N-type GaN layer 111. After exposure and development, part of the photoresist is removed, exposing the epitaxial layer 11 region above the first dividing channel 115. Then, this exposed part of the epitaxial layer 11 is removed using inductively coupled plasma etching (ICP-CED), and finally, the photoresist is removed to form the second dividing channel 19. The projection center of the second dividing channel 19 coincides with that of the first dividing channel 115, together forming a dividing channel that runs through the entire epitaxial layer 11, dividing the epitaxial layer 11 into several independently driveable epitaxial layer units. These epitaxial layer units are electrically connected in series through the aforementioned conductive metal layer 15 to form a high-voltage light-emitting diode chip. The width L2 of the second dividing channel 19 is smaller than the width of the first dividing channel 115, ranging from 5-10 μm; the depth H2 of the second dividing channel 19 is much larger than the depth of the first dividing channel 115, ranging from 9 / 10 to 19 / 20 of the overall thickness of the epitaxial layer 11.

[0045] S07: A P-type conductive via 20 is formed on the surface of the N-type GaN layer 111, and a P-type pad layer 21 is formed to complete the fabrication of the vertical high voltage light-emitting diode chip.

[0046] Please see Figure 1 , Figure 2 , Figure 23 and Figure 24As shown, in this embodiment, photoresist is coated on the surface of the N-type GaN layer 111 and the surface of the second dividing channel 19. After exposure and development, part of the photoresist is removed, exposing the area to be etched. Then, inductively coupled plasma etching is used to remove the exposed N-type GaN layer 111 and the first insulating layer 12 and the second insulating layer 14 below it until the P-type metal layer 151 is exposed. Finally, the photoresist is removed to form a P-type conductive via 20. Next, negative photoresist is coated on the surface of the P-type conductive via 20 and the N-type GaN layer 111. After exposure and development, part of the photoresist is removed. Then, an electron beam evaporation process is used to sequentially deposit a Ti layer (500-1000 Å), a Ni layer (500-1000 Å), and an Au layer (4000-6000 Å). Then, a lift-off process is used to remove the photoresist and the metal on it to form a P-type pad layer 21. Thus, the fabrication of the vertical high-voltage light-emitting diode chip is completed.

[0047] To verify the technical effectiveness of the vertical high-voltage light-emitting diode chip and its fabrication method provided by this invention, vertical high-voltage light-emitting diode chips were fabricated according to conventional processes (Comparative Example 1) and different parameter conditions of this invention (Experimental Groups 1-2), and the fabrication yield of each batch of chips was statistically analyzed. The overall thickness of the epitaxial layer was set to 5.5 μm. Specific parameters and yield results are shown in the table below.

[0048]

[0049] As shown in the table above, the vertical high-voltage light-emitting diode chips fabricated using the segmented channel structure provided by this invention (composed of a first segmented channel 115 and a second segmented channel 19, with the width of the first segmented channel 115 greater than the width of the second segmented channel 19 and the depth of the first segmented channel 115 less than the depth of the second segmented channel 19) exhibit significantly higher yields than those prepared using conventional processes. Specifically, the yield of experimental group 2 reached 98.45%, an improvement of approximately 9 percentage points compared to the 89.36% of comparative example 1. This indicates that by rationally setting the width and depth ratio of the first segmented channel 115 and the second segmented channel 19, the problem of epitaxial layer 11 detachment during the laser lift-off process can be effectively avoided, thereby significantly improving the chip fabrication yield.

[0050] In summary, the vertical high-voltage light-emitting diode chip and its fabrication method in the above embodiments of the present invention have the following beneficial effects: By setting a segmentation channel structure composed of a first segmentation channel 115 and a second segmentation channel 19 in the epitaxial layer 11, wherein the width of the first segmentation channel 115 is greater than the width of the second segmentation channel 19 and the depth of the first segmentation channel 115 is less than the depth of the second segmentation channel 19, the first segmentation channel 115 is prepared before the bonding process and the second segmentation channel 19 is prepared after the laser lift-off process, which effectively solves the problem that the epitaxial layer 11 of the vertical high voltage light-emitting diode chip is easy to fall off after the lift-off process in the prior art, and significantly improves the chip preparation yield.

[0051] Meanwhile, by electrically connecting each epitaxial layer unit in series through the conductive metal layer 15, a high-voltage light-emitting diode chip is realized to meet the needs of high-voltage application scenarios such as automotive headlights.

[0052] By setting a multilayer insulating structure of a first insulating layer 12, a metal reflective layer 13, a second insulating layer 14 and a third insulating layer 16 in the chip, and setting a series connection structure of a P-type metal layer 151, a bridging metal layer 152 and an N-type metal layer 153, reliable electrical series connection between each epitaxial layer unit is achieved. At the same time, the metal reflective layer 13 effectively improves the light extraction efficiency of the chip.

[0053] By limiting the width of the first dividing channel 115 to 10-15 μm and the depth to 1 / 20-1 / 10 of the thickness of the epitaxial layer 11, and the width of the second dividing channel 19 to 5-10 μm and the depth to 19 / 20-9 / 10 of the thickness of the epitaxial layer 11, the size parameters of the dividing channels are further optimized, so as to maximize the protection of the integrity of the epitaxial layer 11 in the peeling process while ensuring the dividing effect.

[0054] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0055] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A vertical high voltage light emitting diode chip, characterized by, include: Conductive silicon substrate; A bonding metal layer is disposed above the conductive silicon substrate; An epitaxial layer is disposed above the bonding metal layer. The epitaxial layer includes, from bottom to top, a P-type GaN layer, an active light-emitting layer, and an N-type GaN layer. A segmentation channel structure is provided within the epitaxial layer, dividing it into several independently driveable epitaxial layer units. The segmentation channel structure is composed of a first segmentation channel and a second segmentation channel, with their projection centers coinciding and both penetrating the entire epitaxial layer. The width of the first segmentation channel is greater than the width of the second segmentation channel, and the depth of the first segmentation channel is less than the depth of the second segmentation channel. A conductive metal layer is disposed between the epitaxial layer and the bonding metal layer for electrically connecting each epitaxial layer unit; A P-type pad layer is disposed on the surface of the N-type GaN layer and is electrically connected to the conductive metal layer; The width of the first segment is between 10 μm and 15 μm, and the depth is between 1 / 20 and 1 / 10 of the overall thickness of the epitaxial layer; The width of the second segment is between 5 μm and 10 μm, and the depth is between 9 / 10 and 19 / 20 of the overall thickness of the epitaxial layer.

2. The vertical high-voltage light-emitting diode chip according to claim 1, characterized in that, Also includes: A first insulating layer is disposed on the surface of the epitaxial layer, and the first insulating layer has a P-type first insulating layer opening and an N-type first insulating layer opening; A metal reflective layer is disposed on the first insulating layer. The metal reflective layer is electrically connected to the P-type GaN layer through the opening in the P-type first insulating layer, and is electrically connected to the N-type GaN layer conductive step through the opening in the N-type first insulating layer. A second insulating layer is disposed on the metal reflective layer, and the second insulating layer has P-type second insulating layer through holes and N-type second insulating layer through holes; A third insulating layer is disposed on the conductive metal layer, and the third insulating layer has an N-type third insulating layer through hole to expose the conductive metal layer.

3. The vertical high-voltage light-emitting diode chip according to claim 2, characterized in that, The conductive metal layer includes a P-type metal layer, a bridging metal layer, and an N-type metal layer, wherein: The P-type metal layer is electrically connected to the metal reflective layer corresponding to the first epitaxial layer unit in the series direction; The bridging metal layer electrically connects the N-type metal layer of the upstream epitaxial layer unit to the metal reflective layer of the downstream epitaxial layer unit in two adjacent epitaxial layer units. The N-type metal layer is electrically connected to the N-type GaN layer conductive step corresponding to the last epitaxial layer unit in the series direction.

4. The vertical high-voltage light-emitting diode chip according to claim 3, characterized in that, It also includes a P-type conductive via, which sequentially penetrates the N-type GaN layer, the active light-emitting layer, the P-type GaN layer, the first insulating layer, and the second insulating layer until the P-type metal layer is exposed.

5. The vertical high-voltage light-emitting diode chip according to claim 1, characterized in that, The bonding metal layer is formed by hot-pressing a first bonding metal sublayer and a second bonding metal sublayer. The first bonding metal sublayer is disposed between the epitaxial layer and the second bonding metal sublayer, and the second bonding metal sublayer is disposed between the conductive silicon substrate and the first bonding metal sublayer.

6. A method for fabricating a vertical high-voltage light-emitting diode chip as described in any one of claims 1-5, characterized in that, Includes the following steps: An epitaxial layer is formed by sequentially growing an N-type GaN layer, an active light-emitting layer, and a P-type GaN layer on the growth substrate. The epitaxial layer is etched for the first time to form the first dividing channel; A first insulating layer, a metal reflective layer, a second insulating layer, a conductive metal layer, and a third insulating layer are sequentially formed on the surface of the epitaxial layer. The epitaxial layer on which the third insulating layer is formed is transferred onto a conductive silicon substrate; Remove the growth substrate to expose the N-type GaN layer; The exposed N-type GaN layer is etched a second time, aligning with the position of the first dividing channel and etched downwards from one side of the N-type GaN layer to form a second dividing channel; wherein, the width of the first dividing channel is greater than the width of the second dividing channel, and the depth of the first dividing channel is less than the depth of the second dividing channel; the first dividing channel and the second dividing channel together constitute a dividing channel penetrating the epitaxial layer, dividing the epitaxial layer into multiple epitaxial layer units; A P-type conductive via is formed on the surface of the N-type GaN layer, and a P-type pad layer is formed to complete the fabrication of the vertical high-voltage light-emitting diode chip.

7. The method for fabricating a vertical high-voltage light-emitting diode chip according to claim 6, characterized in that, The step of transferring the epitaxial layer on which the third insulating layer is formed to the conductive silicon substrate includes: A first bonding metal sublayer is formed above the conductive metal layer; A conductive silicon substrate is provided, and a second bonding metal sublayer is formed on the conductive silicon substrate; The first bonding metal sublayer and the second bonding metal sublayer are bonded together using a hot-press bonding process.

8. The method for fabricating a vertical high-voltage light-emitting diode chip according to claim 7, characterized in that, The step of forming the first bonded metal sublayer includes: sequentially depositing a Cr metal layer, an Al metal layer, a Ti metal layer, a first Ni metal layer, a first Sn metal layer, a second Ni metal layer, and a second Sn metal layer on the third insulating layer using an electron beam evaporation process; The step of forming the second bonded metal sublayer includes: sequentially depositing a Ti metal layer, a first Ni metal layer, a first Sn metal layer, a second Ni metal layer, and a second Sn metal layer on the conductive silicon substrate using an electron beam evaporation process; The thickness of the Cr metal layer is 30-50 Å, and the thickness of the Al metal layer is 1200-2000 Å. In the first and second bonded metal sublayers: the thickness of the Ti metal layer is 2000-4000 Å, the thickness of the first Ni metal layer is 3000-5000 Å, the thickness of the first Sn metal layer is 5000-10000 Å, the thickness of the second Ni metal layer is 1000-2000 Å, and the thickness of the second Sn metal layer is 2000-4000 Å.

9. The method for fabricating a vertical high-voltage light-emitting diode chip according to claim 6, characterized in that, The steps for forming the metal reflective layer include: sequentially depositing an ITO thin film, an Ag metal layer, and a Ti / Ni / Pt multilayer metal structure using an electron beam evaporation process, and then forming it using a lift-off process; wherein the thickness of the ITO thin film is 30-50 Å, and the thickness of the Ag metal layer is 1200-2000 Å. The formation of the conductive metal layer specifically includes: sequentially depositing a multi-layered metal structure of Ti / Au / Ti / Pt / Ti / Pt / Ti using an electron beam evaporation process, and then shaping it using a lift-off process.

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