A flip-chip light-emitting diode and its fabrication method

Abstract

This invention provides a flip-chip light-emitting diode (LED) and its fabrication method. The flip-chip LED includes, from bottom to top, a substrate, an epitaxial layer, a current spreading layer, a first insulating layer, a second insulating layer, and a first semiconductor layer. The epitaxial layer includes, from bottom to top, an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer. An N-type semiconductor layer conductive step is provided on the top of the N-type semiconductor layer. P-type and N-type first insulating layer vias are provided on the first insulating layer. A buffer layer that does not participate in any electrical connection is provided between the first and second insulating layers. The buffer layer includes 2-3 buffer rings arranged sequentially around the P-type first insulating layer vias. The width L of the buffer rings is the same, and the distance L1 between two adjacent buffer rings increases linearly from the center of the buffer ring towards the edge of the outermost buffer ring.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a flip-chip light-emitting diode and its fabrication method. Background Technology

[0002] Flip-chip LEDs are widely used due to their advantages such as back-side light emission, good solderability, high thrust, and high reliability.

[0003] Backlight LED chips have very high requirements for electrostatic discharge (ESD) resistance, and improving the ESD resistance of LED chips has been a goal that industry professionals have been pursuing.

[0004] In existing technologies, for conventional LED chips, the P electrode is the current input terminal. The edge of the P electrode accumulates the highest charge density. When an ESD event occurs (a sudden impact of several kilovolts of high voltage), the extremely high charge density at the electrode edge will cause the electric field strength at that location to rise sharply. When this local electric field strength exceeds the critical breakdown field strength of P-GaN or multiple quantum wells (MQW), breakdown will occur first here. Once breakdown occurs, all current will rush to this low-resistance path, forming an extremely thin current filament. The local Joule heat generated by the current filament can instantly reach thousands of degrees Celsius, directly melting the semiconductor material and forming the black hole or dark spot we see. Summary of the Invention

[0005] Therefore, the purpose of this invention is to provide a flip-chip light-emitting diode and its fabrication method, which can effectively solve the shortcomings of the prior art.

[0006] A flip-chip light-emitting diode (LED) chip, comprising: The substrate, epitaxial layer, current spreading layer, first insulating layer, second insulating layer and first semiconductor layer are arranged sequentially from bottom to top. The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer arranged sequentially from bottom to top. An N-type semiconductor layer conductive step is provided on the top of the N-type semiconductor layer. A P-type first insulating layer via and an N-type first insulating layer via are provided on the first insulating layer. The P-type first insulating layer via is a current input via and the projection of the P-type first insulating layer via on the plane is circular. The current extension layer is electrically connected to the first semiconductor layer through the P-type first insulating layer via. A buffer layer that does not participate in any electrical connection is provided between the first insulating layer and the second insulating layer, surrounding the P-type first insulating layer through hole. The buffer layer includes 2-3 buffer rings arranged sequentially around the P-type first insulating layer through hole, with the center of the P-type first insulating layer through hole on the same axis. The buffer layer is used to induce opposite charges at the edge of the via of the P-type first insulating layer through capacitive coupling effect, so as to lengthen the equipotential line distribution and reduce the peak electric field intensity, thereby suppressing the breakdown and current wire effect caused by local electric field concentration in ESD events. The buffer rings have a consistent width L, and the distance L1 between two adjacent buffer rings increases linearly from the center of the buffer ring towards the edge of the outermost buffer ring.

[0007] Compared with the prior art, the beneficial effects of the present invention are as follows: By setting a buffer layer that does not participate in any electrical connection between the first insulating layer and the second insulating layer and the P-type first insulating layer through hole serving as a current input hole, the buffer layer forms an electrically floating structure at the edge of the P-type first insulating layer through hole serving as a current input hole. It does not participate in the electrical connection, but induces opposite charges on the buffer layer through capacitive coupling effect, elongating the equipotential line distribution, thereby reducing the peak electric field intensity at the edge of the P electrode. The buffer layer includes 2-3 buffer rings arranged sequentially around the P-type first insulating layer through hole and coaxial with the center of the P-type first insulating layer through hole. The 2-3 buffer rings with the center of the circle on the same axis make the depletion region at the edge of the P-type first insulating layer through hole laterally widen, the electric field distribution is more gradual, and the peak electric field is further reduced, avoiding premature breakdown caused by excessively high local electric field. The spacing L1 between two adjacent buffer rings increases linearly from the center of the buffer ring towards the edge of the outermost buffer ring, making the gradient of the electric field in the radial direction more uniform, avoiding secondary concentration of electric field between rings, and further improving the ESD resistance.

[0008] Furthermore, the width L of the buffer ring is between 2um and 4um, the distance L1 between two adjacent buffer rings is between 3um and 4um, and the distance L1 between two adjacent buffer rings increases linearly from the center to the edge by 0.5um to 1um.

[0009] Furthermore, the distance L2 between the projection of the outer ring of the P-type first insulating layer through hole on the horizontal plane and the projection of the inner ring of the adjacent buffer ring on the horizontal plane is less than L1.

[0010] Furthermore, the distance L2 between the projection of the outer ring of the P-type first insulating layer through hole on the horizontal plane and the projection of the inner ring of the adjacent buffer ring on the horizontal plane is between 2um and 3um.

[0011] Furthermore, a P-type second insulating layer through hole and an N-type second insulating layer through hole are provided on the second insulating layer, and the centers of the P-type second insulating layer through hole, the buffer ring and the P-type first insulating layer through hole are on the same axis.

[0012] Furthermore, the distance L3 between the projection of the outer ring of the P-type second insulating layer through hole on the horizontal plane and the projection of the inner ring of the adjacent buffer ring on the horizontal plane is less than L2.

[0013] Furthermore, the distance L3 between the projection of the outer ring of the P-type second insulating layer through hole on the horizontal plane and the projection of the inner ring of the adjacent buffer ring on the horizontal plane is between 1.5um and 2um.

[0014] Furthermore, the first semiconductor layer includes, from bottom to top, a reflective metal layer, a third insulating layer, a connecting metal layer, a fourth insulating layer, and a pad layer.

[0015] Furthermore, a P-type third insulating layer via and an N-type third insulating layer via are provided on the third insulating layer, the connecting metal layer includes a P-type connecting metal layer and an N-type connecting metal layer, the pad layer includes a P-type pad and an N-type pad, and the reflective metal layer is electrically connected to the current spreading layer through the P-type first insulating layer via.

[0016] On the other hand, the present invention also provides a method for fabricating a flip-chip light-emitting diode as described above, comprising: S1. A substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially prepared on the substrate as epitaxial layers. A current spreading layer is prepared on the epitaxial layers, and conductive steps of the N-type semiconductor layer are prepared on the current spreading layer and the epitaxial layers. S2. Deposit a SiO2 thin film as a first insulating layer in the current spreading layer and in the locations not covered by the current spreading layer. S3. A negative photoresist is coated on the surface of the first insulating layer, and then exposed and developed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially deposit Ag metal with a thickness of 1200Å-2000Å, Ti metal with a thickness of 500Å-1000Å, Pt metal with a thickness of 500Å-1000Å, and Ti metal with a thickness of 30Å-50Å. Then, a lift-off process is used to remove the metal and photoresist on the photoresist to form a buffer layer. S4. Prepare a second insulating layer in the buffer layer and in the areas not covered by the buffer layer; S5. A P-type second insulating layer through-hole and an N-type second insulating layer through-hole are prepared on the second insulating layer, and a P-type first insulating layer through-hole and an N-type first insulating layer through-hole are prepared on the second insulating layer, the P-type second insulating layer through-hole and the N-type second insulating layer through-hole; S6. A first semiconductor layer is prepared on the second insulating layer, the P-type second insulating layer via, and the P-type first insulating layer via; The buffer layer includes 2-3 buffer rings arranged sequentially around the through hole of the P-type first insulating layer, with the center of the through hole on the same axis. The width L of the buffer rings is the same, and the distance L1 between two adjacent buffer rings increases linearly from the center of the buffer ring towards the edge of the outermost buffer ring. Attached Figure Description

[0017] Figure 1 This is a cross-sectional schematic diagram of the flip-chip light-emitting diode in Embodiment 1 of the present invention; Figure 2 This is a flowchart of the fabrication method of the flip-chip light-emitting diode in Embodiment 2 of the present invention; Explanation of key component symbols:

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Example 1 Please see Figure 1 Embodiment 1 of the present invention provides a flip-chip light-emitting diode, comprising: The substrate 10, epitaxial layer, current spreading layer 12, first insulating layer 13, second insulating layer 15 and first semiconductor layer are arranged sequentially from bottom to top. The epitaxial layer includes an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 arranged sequentially from bottom to top. An N-type semiconductor layer conductive step 114 is provided on the top of the N-type semiconductor layer 111. A P-type first insulating layer through-hole 131 and an N-type first insulating layer through-hole 132 are provided on the first insulating layer 13. The P-type first insulating layer through-hole 131 is a current input hole and the projection of the P-type first insulating layer through-hole 131 on the plane is circular. The current extension layer 12 is electrically connected to the first semiconductor layer through the P-type first insulating layer through-hole 131. A buffer layer that does not participate in any electrical connection is provided between the first insulating layer 13 and the second insulating layer 15, surrounding the P-type first insulating layer through hole 131. The buffer layer includes 2-3 buffer rings 14 arranged sequentially around the P-type first insulating layer through hole 131, with the center of the P-type first insulating layer through hole 131 on the same axis. The width L of the buffer rings 14 is the same, and the distance L1 between two adjacent buffer rings 14 increases linearly from the center of the buffer ring 14 toward the edge of the outermost buffer ring 14.

[0023] Specifically, the buffer ring is made of a conductive material, preferably a metal.

[0024] Specifically, in this embodiment, three buffer rings 14 are provided that are on the same axis as the center of the P-type first insulating layer through hole 131.

[0025] It should be noted that if only one buffer ring 14 is set, a radial electric field gradient cannot be formed, and the effect of elongating the equipotential lines is limited; if more than three are set, the effect of further suppressing the peak electric field tends to saturate, and it will excessively increase the process complexity and occupy chip area.

[0026] Understandably, by providing a buffer layer that does not participate in any electrical connection between the first insulating layer 13 and the second insulating layer 15, surrounding the P-type first insulating layer through-hole 131 which serves as a current input hole, the buffer layer forms an electrically floating structure at the edge of the P-type first insulating layer through-hole 131, which serves as a current input hole. It does not participate in the electrical connection, but through capacitive coupling, it induces opposite charges on the buffer layer, elongating the equipotential line distribution, thereby reducing the peak electric field intensity at the edge of the P electrode. The buffer layer includes components sequentially surrounding the P-type first insulating layer through-hole 131. The three buffer rings 14, whose centers are on the same axis as the P-type first insulating layer through-hole 131, make the depletion region at the edge of the P-type first insulating layer through-hole 131 laterally wider, the electric field distribution more gradual, and the peak electric field further reduced, avoiding premature breakdown due to excessively high local electric field; the spacing L1 between two adjacent buffer rings 14 increases linearly from the center of the buffer ring 14 toward the edge of the outermost buffer ring 14, making the electric field gradient more uniform in the radial direction, avoiding secondary concentration of electric field between rings, and further improving ESD resistance.

[0027] Furthermore, the width L of the buffer ring 14 is between 2um and 4um, the distance L1 between two adjacent buffer rings 14 is between 3um and 4um, and the distance L1 between two adjacent buffer rings 14 increases linearly from the center to the edge by 0.5um to 1um.

[0028] Understandably, the width L of the buffer ring 14 is between 2um and 4um, ensuring that the buffer ring 14 has sufficient physical size to carry the induced charge, while avoiding occupying too much chip area; the spacing L1 between two adjacent buffer rings 14 is between 3um and 4um, and the spacing L1 between two adjacent buffer rings 14 increases linearly from the center to the edge by 0.5um to 1um, making the electric field transition between rings smoother, avoiding electric field spikes between rings, and further suppressing the formation of current filaments.

[0029] Specifically, in this embodiment, the width L of the buffer ring 14 is 4µm, the spacing L1 between adjacent buffer rings 14 is 3µm and 4µm respectively, and the spacing L1 between two adjacent buffer rings 14 increases linearly by 1µm from the center to the edge.

[0030] Furthermore, the distance L2 between the projection of the outer ring of the P-type first insulating layer through hole 131 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane is less than L1.

[0031] Understandably, by setting the distance L2 between the projection of the outer ring of the P-type first insulating layer through hole 131 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane to be less than L1, it is ensured that the first buffer ring 14 is in close contact with the edge of the P-type first insulating layer through hole 131, thereby maximizing its "buffering" effect on the edge electric field.

[0032] Furthermore, the distance L2 between the projection of the outer ring of the P-type first insulating layer through hole 131 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane is between 2um and 3um.

[0033] Understandably, this distance ensures that there is a sufficiently strong capacitive coupling between the buffer ring 14 and the P-type first insulating layer through-hole 131, while avoiding difficulties in process alignment or short circuit risks due to excessively small distances.

[0034] Specifically, in this embodiment, the distance L2 between the projection of the outer ring of the P-type first insulating layer through hole 131 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane is 2um.

[0035] Furthermore, a P-type second insulating layer through hole 151 and an N-type second insulating layer through hole 152 are provided on the second insulating layer 15, and the centers of the P-type second insulating layer through hole 151, the buffer ring 14 and the P-type first insulating layer through hole 131 are on the same axis.

[0036] It is understandable that the centers of the P-type second insulating layer through-hole 151, the buffer ring 14, and the P-type first insulating layer through-hole 131 are on the same axis, which can ensure the axial symmetry of the electric field distribution and avoid local electric field enhancement due to offset.

[0037] Furthermore, the distance L3 between the projection of the outer ring of the P-type second insulating layer through hole 151 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane is less than L2.

[0038] Understandably, the P-type second insulating layer via 151 is closer to the buffer ring 14, further enhancing the suppression effect of the buffer ring 14 on the upper layer electric field. Since the second insulating layer 15 is located between the reflective metal layer 16 and the buffer ring 14, the smaller L3 helps the edge electric field of the reflective metal layer 16 to be modulated by the buffer ring 14, thereby improving the overall ESD resistance.

[0039] Furthermore, the distance L3 between the projection of the outer ring of the P-type second insulating layer through hole 151 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane is between 1.5um and 2um.

[0040] Understandably, this distance maximizes capacitive coupling efficiency while ensuring electrical isolation, enabling the buffer ring 14 to effectively sense charges on the edge of the upper metal layer.

[0041] Specifically, in this embodiment, the distance L3 between the projection of the outer ring of the P-type second insulating layer through hole 151 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane is 1.5 μm.

[0042] Example 2 Please see Figure 2 Embodiment 2 of the present invention provides a method for fabricating a flip-chip light-emitting diode as described above, comprising: S1. Provide a substrate 10, and sequentially prepare an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 as an epitaxial layer on the substrate 10. Prepare a current spreading layer 12 on the epitaxial layer, and prepare an N-type semiconductor layer conductive step 114 on the current spreading layer 12 and the epitaxial layer. Specifically, in this embodiment, step S1 includes: First, a substrate 10 is provided. Then, on the substrate 10, the N-type semiconductor layer 111, the active light-emitting layer 112, and the P-type semiconductor layer 113 are sequentially prepared from bottom to top using MOCVD process as epitaxial layers. Then, indium tin oxide is deposited on the surface of the epitaxial layer as the current spreading layer 12 using magnetron sputtering process. Then, photoresist is coated on the surface of the current spreading layer 12. Then, exposure and development are used to remove part of the photoresist, exposing the current spreading layer 12 below the photoresist. Then, indium tin oxide etchant is used to remove the exposed current spreading layer. Then, inductively coupled plasma etching process is used to remove the P-type semiconductor layer 113 and the active light-emitting layer 112 below the P-type semiconductor layer 113 until the N-type semiconductor layer 111 is exposed. Then, the photoresist is removed to form the N-type semiconductor layer conductive step 114. S2. A SiO2 thin film is deposited on the current spreading layer 12 and at the locations not covered by the current spreading layer 12 as a first insulating layer 13; Specifically, in this embodiment, step S2 includes: A SiO2 thin film is deposited as a first insulating layer 13 on the current spreading layer 12 and on the locations not covered by the current spreading layer 12 using a PECVD process. S3. A negative photoresist is coated on the surface of the first insulating layer 13, and then exposed and developed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially deposit Ag metal with a thickness of 1200Å-2000Å, Ti metal with a thickness of 500Å-1000Å, Pt metal with a thickness of 500Å-1000Å, and Ti metal with a thickness of 30Å-50Å. Then, a lift-off process is used to remove the metal and photoresist on the photoresist to form a buffer layer. S4. A second insulating layer 15 is prepared in the buffer layer and in the locations not covered by the buffer layer; Specifically, in this embodiment, step S4 includes: The second insulating layer 15 is formed by depositing 3-10 layers of SiO2 and Ti3O5 in the buffer layer and the areas not covered by the buffer layer using an electron beam evaporation process. It should be noted that the second insulating layer 15 also functions as an inorganic reflective layer; S5. A P-type second insulating layer through-hole 151 and an N-type second insulating layer through-hole 152 are prepared on the second insulating layer 15. A P-type first insulating layer through-hole 131 and an N-type first insulating layer through-hole 132 are prepared on the second insulating layer 15, the P-type second insulating layer through-hole 151 and the N-type second insulating layer through-hole 152. Specifically, in this embodiment, step S5 includes: Photoresist is coated on the surface of the second insulating layer 15, and then exposed and developed to remove part of the photoresist, exposing the second insulating layer 15 underneath. Then, inductively coupled plasma etching is used to remove the exposed second insulating layer 15 down to the first insulating layer 13. Then, the photoresist is removed to form the P-type second insulating layer via 151 and the N-type second insulating layer via 152. Next, photoresist is coated on the second insulating layer 15, the P-type second insulating layer via 151 and the N-type second insulating layer via 152. Then, exposed and developed, part of the photoresist in the P-type second insulating layer via 151 and the N-type second insulating layer via 152 is removed, exposing the first insulating layer 13 underneath. Then, the exposed first insulating layer 13 is etched away with BOE solution. Then, the photoresist is removed to form the P-type first insulating layer via 131 and the N-type first insulating layer via 132. S6. A first semiconductor layer is formed on the second insulating layer 15, the P-type second insulating layer via 151 and the P-type first insulating layer via 131. Furthermore, the first semiconductor layer includes a reflective metal layer 16, a third insulating layer 17, a connecting metal layer, a fourth insulating layer 19, and a pad layer, which are disposed sequentially from bottom to top.

[0043] Furthermore, a P-type third insulating layer via 171 and an N-type third insulating layer via 172 are provided on the third insulating layer 17. The connecting metal layer includes a P-type connecting metal layer 181 and an N-type connecting metal layer 182. The pad layer includes a P-type pad 201 and an N-type pad 202. The reflective metal layer 16 is electrically connected to the current spreading layer 12 through the P-type first insulating layer via 131.

[0044] Specifically, in this embodiment, step S6 includes: Negative photoresist is coated on the second insulating layer 15, the P-type second insulating layer via 151, and the P-type first insulating layer via 131. Then, exposure and development are performed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially deposit Ag metal with a thickness of 1200Å-2000Å, Ti metal with a thickness of 500Å-1000Å, Pt metal with a thickness of 500Å-1000Å, and Ti metal with a thickness of 30Å-50Å. Then, a lift-off process is used to remove the metal and photoresist on the photoresist to form the reflective metal layer 16. An Al2O3 film is prepared using an ALD process in the reflective metal layer 16 and the areas not covered by the reflective metal layer 16. Then, a SiO2 film is prepared on the surface of the Al2O3 film using a PECVD process. The Al2O3 film and the SiO2 film together constitute the third insulating layer 17. Photoresist is then coated on the surface of the third insulating layer 17. After exposure and development, part of the photoresist is removed, exposing the third insulating layer 17 under the photoresist. Then, the exposed third insulating layer 17 is removed using an inductively coupled plasma etching process to form the P-type third insulating layer via 171 and the N-type third insulating layer via 172. Finally, the photoresist is removed. Negative photoresist is coated on the surfaces of the third insulating layer 17, the P-type third insulating layer via 171, and the N-type third insulating layer via 172. Then, exposure and development are used to remove part of the photoresist. Then, Cr metal, Al metal, Ti metal, Pt metal, Ti metal, Pt metal, Ti metal, Au metal, Pt metal, and Ti metal are deposited sequentially using an electron beam evaporation process to form the P-type connection metal layer 181 and the N-type connection metal layer 182. Then, a blue film stripping process is used to remove the metal located on the photoresist, and then the photoresist is removed. A SiO2 thin film is prepared as the fourth insulating layer 19 on the surface of the connecting metal layer and the areas not covered by the connecting metal layer using a PECVD process. A negative photoresist is coated on the surface of the fourth insulating layer 19. Then, exposure and development are performed to remove part of the photoresist, exposing the fourth insulating layer 19 underneath. The exposed fourth insulating layer is then removed by etching with BOE solution. Then, Al metal with a thickness of 10000Å-15000Å, Ti metal with a thickness of 1000Å-2000Å, Pt metal with a thickness of 1000Å-2000Å, Ni metal with a thickness of 8000Å-12000Å, and Au metal with a thickness of 300Å-600Å are deposited sequentially using an electron beam evaporation process. Then, the metal on the photoresist is removed using a blue film stripping process. Finally, the photoresist is removed to form the P-type pad 201 and the N-type pad 202.

[0045] Example 3 A flip-chip LED chip, which differs from the flip-chip LED chip in Example 1 in that: Specifically, in this embodiment, the width L of the buffer ring 14 is 2µm.

[0046] Example 4 A flip-chip LED chip, which differs from the flip-chip LED chip in Example 1 in that: Specifically, in this embodiment, the width L of the buffer ring 14 is 3.5 μm, the spacing L1 between adjacent buffer rings 14 is 3 μm and 3.5 μm respectively, and the spacing L1 between two adjacent buffer rings 14 increases linearly by 0.5 μm from the center to the edge.

[0047] Specifically, in this embodiment, the distance L2 between the projection of the outer ring of the P-type first insulating layer through hole 131 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane is 2.5 μm.

[0048] Specifically, in this embodiment, the distance L3 between the projection of the outer ring of the P-type second insulating layer through hole 151 on the horizontal plane and the projection of the inner ring of the adjacent buffer ring 14 on the horizontal plane is 2 μm.

[0049] Example 5 A flip-chip LED chip, which differs from the flip-chip LED chip in Example 1 in that: Specifically, in this embodiment, two buffer rings 14 are provided that are on the same axis as the center of the P-type first insulating layer through hole 131.

[0050] Specifically, in this embodiment, the width L of the buffer ring 14 is 4µm, and the spacing L1 between adjacent buffer rings 14 is 3µm.

[0051] Comparative Example 1 A flip-chip LED chip, which differs from the flip-chip LED chip in Example 1 in that: Specifically, in this embodiment, a buffer ring 14 is provided that is on the same axis as the center of the P-type first insulating layer through hole 131.

[0052] Specifically, in this embodiment, the width L of the buffer ring 14 is 4µm.

[0053] Comparative Example 2 A flip-chip LED chip, which differs from the flip-chip LED chip in Example 1 in that: Specifically, in this embodiment, no buffer layer is provided.

[0054] Based on the flip-chip LEDs of Examples 1, 3, 4, 5, Comparative Example 1, and Comparative Example 2 described above, the ESD resistance of the 245µm*500µm flip-chip LEDs of Examples 1, 3, 4, 5, Comparative Example 1, and Comparative Example 2 was tested, and the corresponding test results are shown in the table below:

[0055] It should be noted that, in order to ensure the reliability of the verification results, when comparing the flip-chip LEDs of the present invention in Embodiments 1, 3, 4, 5, Comparative Example 1 and Comparative Example 2 with the same test current applied to the flip-chip LEDs for ESD resistance testing, all other processes and parameters should remain consistent except for the parameters mentioned above.

[0056] According to the table above, it can be seen that Example 1 has the strongest antistatic ability, and the antistatic abilities of Examples 1, 3, 4 and 5 are all better than those of Comparative Example 1 and Comparative Example 2.

[0057] In summary, the flip-chip LED chip and its fabrication method in the above embodiments of the present invention, by setting a buffer layer that does not participate in any electrical connection between the first insulating layer and the second insulating layer and surrounds the P-type first insulating layer via which serves as a current input hole, forms an electrically floating structure at the edge of the P-type first insulating layer via which the current input hole is located. It does not participate in the electrical connection, but induces opposite charges on the buffer layer through capacitive coupling effect, elongating the equipotential line distribution, thereby reducing the peak electric field intensity at the edge of the P electrode. The buffer layer includes 2-3 buffer rings arranged sequentially around the P-type first insulating layer via which the center of the P-type first insulating layer via is on the same axis. The 2-3 buffer rings with the center on the same axis make the depletion region at the edge of the P-type first insulating layer via laterally widen, the electric field distribution is more gradual, and the peak electric field is further reduced, avoiding premature breakdown caused by excessively high local electric fields. The spacing L1 between two adjacent buffer rings increases linearly from the center of the buffer ring towards the edge of the outermost buffer ring, making the gradient of the electric field in the radial direction more uniform, avoiding secondary concentration of the electric field between the rings, and further improving the ESD resistance.

[0058] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0059] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A flip-chip light-emitting diode, characterized in that, include: The substrate, epitaxial layer, current spreading layer, first insulating layer, second insulating layer and first semiconductor layer are arranged sequentially from bottom to top. The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer arranged sequentially from bottom to top. An N-type semiconductor layer conductive step is provided on the top of the N-type semiconductor layer. A P-type first insulating layer via and an N-type first insulating layer via are provided on the first insulating layer. The P-type first insulating layer via is a current input via and the projection of the P-type first insulating layer via on the plane is circular. The current extension layer is electrically connected to the first semiconductor layer through the P-type first insulating layer via. A buffer layer that does not participate in any electrical connection is provided between the first insulating layer and the second insulating layer, surrounding the P-type first insulating layer through hole. The buffer layer includes 2-3 buffer rings arranged sequentially around the P-type first insulating layer through hole, with the center of the P-type first insulating layer through hole on the same axis. The buffer layer is used to induce opposite charges at the edge of the via of the P-type first insulating layer through capacitive coupling effect, so as to lengthen the equipotential line distribution and reduce the peak electric field intensity, thereby suppressing the breakdown and current wire effect caused by local electric field concentration in ESD events. The buffer rings have a consistent width L, and the distance L1 between two adjacent buffer rings increases linearly from the center of the buffer ring towards the edge of the outermost buffer ring.

2. The flip-chip LED according to claim 1, characterized in that, The width L of the buffer ring is between 2um and 4um, the distance L1 between two adjacent buffer rings is between 3um and 4um, and the distance L1 between two adjacent buffer rings increases linearly from the center to the edge by 0.5um to 1um.

3. The flip-chip LED according to claim 2, characterized in that, The distance L2 between the projection of the outer ring of the P-type first insulating layer through hole on the horizontal plane and the projection of the inner ring of the adjacent buffer ring on the horizontal plane is less than L1.

4. The flip-chip LED according to claim 3, characterized in that, The distance L2 between the projection of the outer ring of the P-type first insulating layer through hole on the horizontal plane and the projection of the inner ring of the adjacent buffer ring on the horizontal plane is between 2um and 3um.

5. The flip-chip LED according to claim 4, characterized in that, The second insulating layer is provided with a P-type second insulating layer through hole and an N-type second insulating layer through hole, and the centers of the P-type second insulating layer through hole, the buffer ring and the P-type first insulating layer through hole are on the same axis.

6. The flip-chip LED according to claim 5, characterized in that, The distance L3 between the projection of the outer ring of the P-type second insulating layer through hole on the horizontal plane and the projection of the inner ring of the adjacent buffer ring on the horizontal plane is less than L2.

7. The flip-chip LED according to claim 6, characterized in that, The distance L3 between the projection of the outer ring of the P-type second insulating layer through hole on the horizontal plane and the projection of the inner ring of the adjacent buffer ring on the horizontal plane is between 1.5um and 2um.

8. The flip-chip LED according to claim 1, characterized in that, The first semiconductor layer includes, from bottom to top, a reflective metal layer, a third insulating layer, a connecting metal layer, a fourth insulating layer, and a pad layer.

9. The flip-chip LED according to claim 8, characterized in that, The third insulating layer has P-type and N-type third insulating layer vias. The connecting metal layer includes a P-type connecting metal layer and an N-type connecting metal layer. The pad layer includes a P-type pad and an N-type pad. The reflective metal layer is electrically connected to the current spreading layer through the P-type first insulating layer via.

10. A method for fabricating a flip-chip light-emitting diode as described in any one of claims 1-9, characterized in that, include: S1. A substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially prepared on the substrate as epitaxial layers. A current spreading layer is prepared on the epitaxial layers, and conductive steps of the N-type semiconductor layer are prepared on the current spreading layer and the epitaxial layers. S2. Deposit a SiO2 thin film as a first insulating layer in the current spreading layer and in the locations not covered by the current spreading layer. S3. A negative photoresist is coated on the surface of the first insulating layer, and then exposed and developed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially deposit Ag metal with a thickness of 1200Å-2000Å, Ti metal with a thickness of 500Å-1000Å, Pt metal with a thickness of 500Å-1000Å, and Ti metal with a thickness of 30Å-50Å. Then, a lift-off process is used to remove the metal and photoresist on the photoresist to form a buffer layer. S4. Prepare a second insulating layer in the buffer layer and in the areas not covered by the buffer layer; S5. A P-type second insulating layer through-hole and an N-type second insulating layer through-hole are prepared on the second insulating layer, and a P-type first insulating layer through-hole and an N-type first insulating layer through-hole are prepared on the second insulating layer, the P-type second insulating layer through-hole and the N-type second insulating layer through-hole; S6. A first semiconductor layer is prepared on the second insulating layer, the P-type second insulating layer via, and the P-type first insulating layer via; The buffer layer includes 2-3 buffer rings arranged sequentially around the through hole of the P-type first insulating layer, with the center of the through hole on the same axis. The width L of the buffer rings is the same, and the distance L1 between two adjacent buffer rings increases linearly from the center of the buffer ring towards the edge of the outermost buffer ring.

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