Chip sorting method and apparatus
By acquiring wafer test data files, determining the target chip cell coordinate set within the outer ring region and assigning electrical parameter marker values, automatic sorting of chip cells in the outer ring region of the wafer is achieved, solving the problems of low sorting accuracy and efficiency, and improving yield and sorting efficiency.
CN122294869APending Publication Date: 2026-06-26HC SEMITEK ZHEJIANG CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HC SEMITEK ZHEJIANG CO LTD
- Filing Date
- 2026-03-20
- Publication Date
- 2026-06-26
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Figure CN122294869A_ABST
Abstract
This disclosure provides a chip sorting method and apparatus. The chip sorting method is used to sort chip cells in the outer region of a wafer, the wafer including multiple chip cells arranged in an array. The chip sorting method includes: acquiring a test data file of the wafer, the test data file including unique coordinates of each chip cell on the wafer and electrical parameters of the chip cell; obtaining a set of coordinates of target chip cells in the outer region of the wafer based on the test data file and the number of removal rings; assigning at least one electrical parameter value corresponding to all target chip cells in the coordinate set as a predefined mark value; and sorting the chip cells with the mark value from the wafer. The method provided by this disclosure can improve the sorting accuracy of chip cells in the outer region of a wafer.
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