A chip testing and sorting apparatus and a sorting method

Abstract

The present application relates to the technical field of chip testing, in particular to a chip testing and sorting device and method, which comprises: transferring a chip to be tested to a visual detection station; determining the testing and sorting requirement state of the chip according to a brightness imbalance characteristic value; when the chip is in a first testing and sorting requirement state, if there is no candidate bright spot area, the chip is sorted to an electrical detection position; if there is a candidate bright spot area, a first sorting strategy is determined according to a polarization attenuation ratio; whether the chip in the first testing and sorting requirement state is in a suspected contamination state is determined according to the determination result of the polarization attenuation ratio; when the chip is in a second testing and sorting requirement state or in the suspected contamination state, a second sorting strategy is determined according to a bridging focal plane characteristic value; for the chip sorted to the electrical detection position, an electrical performance test is performed, and the testing and sorting process of the chip is completed. Thus, the chip testing and sorting accuracy is improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, specifically to a chip testing and sorting device and method. Background Technology

[0002] Existing translational chip testing and sorting equipment typically begins by having a vision inspection module capture an image of the chip's bottom surface to identify appearance defects such as missing solder balls and bridging. The chip is then transferred to an electrical testing module, where probes contact the solder balls to perform open / short circuit tests and functional tests, with the electrical results serving as the final judgment.

[0003] There is a risk of misjudgment during actual equipment operation: The lubricating oil in the equipment's guide rails evaporates slightly due to long-term temperature rise, condensing into a transparent oil film on the chip surface. This oil film adsorbs metal particles from the environment, forming a composite contaminant of "oil film + conductive particles." During visual inspection, metal particles produce strong specular reflection under coaxial light, which is highly similar to solder ball bridging defects in grayscale value and shape. Existing single coaxial light algorithms cannot distinguish between the two, misjudging contaminated chips as bridging defective products. During electrical inspection, the probe pressure forces conductive particles into the gaps between solder balls, causing the oil film to rupture and resulting in intermittent high-impedance conduction between the solder balls. This fluctuation does not trigger the preset contaminant alarm threshold, and the electrical system directly outputs a "short circuit" judgment based on the detected partial conduction. The erroneous conclusions of visual and electrical inspections corroborate each other, causing intact chips with only surface contamination to be mistakenly judged as scrapped. Summary of the Invention

[0004] To address this issue, the present invention provides a chip testing and sorting device and method to overcome the problem in the prior art that the composite contaminants composed of transparent oil film and conductive particles do not consider the specular reflection bright spots generated during chip testing and sorting, which leads to misjudgment of solder ball bridging and thus results in poor chip testing and sorting accuracy.

[0005] To achieve the above objectives, in one aspect, the present invention provides a chip testing and sorting method, comprising: The chip to be tested is transferred to the vision inspection station, a first grayscale image of the bottom surface of the chip is captured, the grayscale histogram of the first grayscale image is obtained, and the brightness imbalance characterization value of the chip is obtained. The test sorting requirement state of the chip is determined based on the brightness imbalance characterization value, wherein the test sorting requirement state includes a first type of test sorting requirement state and a second type of test sorting requirement state. When the chip is in a state requiring a type of test and sorting, first identify whether there is a candidate bright spot area in the first grayscale image of the chip; if there is no candidate bright spot area, sort the chip to the electrical testing compartment; if there is a candidate bright spot area, determine the polarization attenuation ratio based on the grayscale value of the candidate bright spot area in the first grayscale image and the grayscale value of the corresponding area in the second grayscale image, and determine the first sorting strategy based on the polarization attenuation ratio. Based on the polarization attenuation ratio determination result, determine whether the chip in the first-class test and sorting requirement state is in a suspected contamination state; When the chip is in a state requiring secondary testing and sorting or in a state of suspected contamination, the bridging focal plane characterization value is determined based on the clarity of the bright spot area to be verified in the first focal plane image and the second focal plane image, and the second sorting strategy is determined based on the bridging focal plane characterization value. For chips sorted to the electrical testing compartment, electrical performance tests are performed to complete the chip testing and sorting process.

[0006] Preferably, the chip's test and sorting requirements include a first type of test and sorting requirements and a second type of test and sorting requirements, wherein... If the brightness imbalance characterization value of the chip is less than the preset brightness imbalance characterization value, the chip is determined to be in a type of test and sorting requirement state. If the brightness imbalance characterization value is greater than or equal to the preset brightness imbalance characterization value, the chip is determined to be in the second-class test and sorting requirement state.

[0007] Preferably, the process for obtaining the brightness imbalance characterization value includes: The chip is illuminated using coaxial light, and a first grayscale image of the bottom surface of the chip is captured. The grayscale histogram of the first grayscale image is statistically analyzed, and the pixels in the first grayscale image are divided into a first pixel set and a second pixel set, wherein the grayscale value of the first pixel set is less than a first preset grayscale value, and the grayscale value of the second pixel set is greater than or equal to the first preset grayscale value. The average gray value of the first pixel set is calculated as the first statistical gray value, and the average gray value of the second pixel set is calculated as the second statistical gray value. The ratio of the first statistical gray level to the second statistical gray level is used as the brightness imbalance characterization value.

[0008] Preferably, when the chip is in a state requiring a certain type of test and sorting... Identify whether candidate bright spot regions exist in the first grayscale image of the chip; If no candidate bright spot area is found, the chip is sorted to the electrical testing compartment. If candidate bright spot regions exist, the first sorting strategy for the chip is determined based on the polarization attenuation ratio of the chip, wherein: If the polarization attenuation ratio is less than the first preset polarization attenuation ratio, the chip will be sorted into the defective product storage area. If the polarization attenuation ratio is greater than or equal to the first preset polarization attenuation ratio and less than the second preset polarization attenuation ratio, the chip is marked as suspected contamination. If the polarization attenuation ratio is greater than or equal to the second preset polarization attenuation ratio, the chip will be sorted to the cleaning and rework compartment. The first preset polarization attenuation ratio is less than the second preset polarization attenuation ratio.

[0009] Preferably, the process of obtaining the polarization attenuation ratio includes: The chip is illuminated using coaxial light, and a first grayscale image of the bottom surface of the chip is captured. The chip is illuminated with orthogonally polarized light, and a second grayscale image of the bottom surface of the chip is captured. Identify candidate bright spot regions in the first grayscale image, wherein the candidate bright spot regions are connected regions in the first grayscale image whose grayscale value is greater than a second preset grayscale value and whose area is greater than a preset area; Calculate the average gray value of the candidate bright spot region in the first grayscale image, and record it as the gray value under coaxial light; Based on the centroid position of each candidate bright spot region, regions with the same coordinates are located in the second grayscale image, and the average grayscale value of the region in the second grayscale image is calculated and recorded as the grayscale under polarized light. The ratio of the gray level under polarized light to the gray level under coaxial light is denoted as the polarization attenuation ratio.

[0010] Preferably, when the chip is in a Class II test sorting requirement state, or when the chip is marked as suspected contamination in the first test sorting requirement, the process of determining the second sorting strategy for the chip based on the bridging focal plane characterization value of the chip includes: If the bridging focal plane characterization value is less than the first preset bridging focal plane characterization value, the chip will be sorted to the cleaning and rework compartment. If the bridging focal plane characterization value is greater than or equal to the first preset bridging focal plane characterization value and less than the second preset bridging focal plane characterization value, then the chip is sorted to the electrical testing compartment. If the bridging focal plane characterization value is greater than or equal to the second preset bridging focal plane characterization value, the chip will be sorted into the defective product warehouse. The first preset bridging focal plane characterization value is less than the second preset bridging focal plane characterization value.

[0011] Preferably, the process of obtaining the bridging focal plane characterization value of the chip includes: Based on the centroid position of the candidate bright spot region, magnify the image and switch to a high-magnification lens to magnify the candidate bright spot region to obtain a locally magnified image; Keep the relative position of the camera and the chip unchanged, and only change the focus height; Adjust the focus height to the plane of the solder ball gap and take a picture of the first focal plane; Adjust the focus height to the surface of the chip substrate and capture the second focal plane image; In the first focal plane image and the second focal plane image, the bright spot region to be verified is located respectively; Calculate the sharpness of the bright spot region to be verified in the first focal plane image, and denote it as the first sharpness; Calculate the sharpness of the bright spot region to be verified in the second focal plane image, and denote it as the second sharpness; The ratio of the first sharpness to the second sharpness is denoted as the bridging focal plane characterization value of the chip. Preferably, the solder ball gap plane is determined by focusing on several complete and defect-free solder balls on the chip until the solder ball imaging clarity reaches its peak. The focus position on the chip substrate surface is determined by focusing on the exposed area of ​​the substrate without solder balls or contaminants until the substrate image sharpness reaches its peak.

[0012] Preferably, the process of locating the bright spot region to be verified in the first focal plane image and the second focal plane image respectively includes: Based on the centroid coordinates of the candidate bright spot regions identified in the first test sorting requirements, the points in the first focal plane image that have the same centroid coordinates are used as the search center. With the search center as the center, within a circular area of ​​a preset radius, connected regions whose pixel gray values ​​are greater than or equal to the second preset gray value and whose area is greater than or equal to the preset area are denoted as candidate regions; Each candidate region is compared with the gray value of a corresponding pixel in the candidate bright spot region to obtain a gray value similarity of several candidate regions; the candidate region corresponding to the maximum gray value similarity is recorded as the bright spot region to be verified in the first focal plane. The outline of the bright spot region to be verified in the first focal plane is mapped to the same coordinate position in the second focal plane image; since the relative position of the camera and the chip is fixed during the two shots, the corresponding pixel region of the same coordinate region is taken and recorded as the bright spot region to be verified in the second focal plane.

[0013] On the other hand, the present invention provides a chip testing and sorting device suitable for the above-described method, comprising: A vision acquisition module is used to sequentially capture a first grayscale image, a second grayscale image, a first focal plane image focused on the solder ball gap plane, and a second focal plane image focused on the chip substrate surface. It includes an industrial camera unit, a switchable light source unit, and an autofocus unit. The switchable light source unit includes a coaxial light source and an orthogonally polarized light source. The autofocus unit is used to adjust the focus height to the solder ball gap plane or the chip substrate surface. An image processing module, connected to the vision acquisition module, is used to calculate the brightness imbalance characterization value based on the grayscale histogram; to calculate the polarization attenuation ratio based on the average grayscale in the first grayscale image and the second grayscale image; and to obtain the bridging focal plane characterization value based on the sharpness in the first focal plane image and the second focal plane image. A control module, connected to the image processing module, is used to determine the test sorting requirement state of the chip based on the chip's brightness imbalance characterization value; to determine the first sorting strategy of the chip based on the chip's polarization attenuation ratio; and to determine the second sorting strategy of the chip based on the chip's bridging focal plane characterization value. The sorting execution module is connected to the control module and is used to transfer the chip to the corresponding compartment according to the first sorting strategy or the second sorting strategy. The compartment includes a defective product compartment, a cleaning and rework compartment, and an electrical testing compartment. An electrical testing module, which is connected to the sorting execution module and the control module respectively, is used to perform open circuit / short circuit tests, DC parameter tests and functional tests on the chips in the electrical testing compartment, and transfer qualified chips to the good product compartment and unqualified chips to the defective product compartment according to the test results.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention achieves automated, non-interventional grading of chip inspection difficulty through brightness imbalance characterization values, balancing the production efficiency and inspection accuracy of high-speed continuous operation of sorting machines; it completes rapid initial screening and sorting of low-risk chips through polarization attenuation ratio; and it achieves accurate judgment of real solder ball bridging defects and surface composite contaminants from a physical spatial dimension through bridging focal plane characterization values, significantly reducing the defect misjudgment rate and preventing qualified chips with intact bodies from being misjudged and scrapped; at the same time, it can accurately identify and sort chips with attached contaminants, eliminating long-term reliability risks such as solder joint corrosion and electrostatic resistance degradation that may be caused by contaminants from the source, improving the quality stability of chip products, and thus improving the accuracy of chip testing and sorting.

[0015] 2. This invention determines whether a chip meets Class I or Class II testing and sorting requirements by comparing its brightness imbalance characterization value with a preset threshold. The complexity of the chip can be automatically determined with a single rapid global scan. The brightness imbalance characterization value directly reflects the optical contrast between the solder balls and the gaps, and this contrast is closely related to the chip's solder ball density, spacing, and surface contamination level. Through this threshold determination, the device can adaptively guide simple chips towards rapid basic testing and complex chips towards fine-grained testing, thereby maximizing overall testing efficiency while ensuring testing accuracy.

[0016] 3. In a certain test and sorting requirement, this invention first determines whether a candidate bright spot area exists. If not, it skips polarization detection and directly sends the sample to electrical detection. If it does exist, it performs three-level sorting based on the polarization attenuation ratio. The polarization attenuation ratio utilizes the physical characteristics of metal mirror reflection, which shows significant attenuation under orthogonally polarized light and relatively small attenuation under diffuse reflection, to effectively separate true bridging from contaminant reflection. Chips suspected of being contaminated in the middle level trigger subsequent fine detection, forming a progressive anti-false judgment mechanism of fast screening and fine inspection. The setting of the cleaning and rework compartment allows contaminated intact chips to be salvaged instead of being directly scrapped, thereby improving the stability of the sorting process.

[0017] 4. This invention captures first and second grayscale images of the chip's bottom surface under coaxial light and orthogonally polarized light, respectively. It identifies candidate bright spot regions and calculates the average grayscale ratio of the same region in the two images as the polarization attenuation ratio. By utilizing the strong suppression characteristic of orthogonally polarized light on the reflection of metal mirrors, the essential difference in optical response between genuine solder ball bridging and contaminant reflection is quantified into a calculable judgment criterion, enabling rapid identification and classification of composite contaminants in the visual inspection stage.

[0018] 5. This invention, based on the physical height difference between the solder ball gap plane and the chip substrate surface, uses the sharpness ratio of the same bright spot in different focal plane images as a bridging focal plane characterization value. The chips are then sorted to a cleaning / rework compartment, an electrical testing compartment, or a defective product compartment based on the comparison result of this characterization value with first and second preset thresholds. This makes the final judgment based on the actual physical height of the bright spot rather than its optical appearance, eliminating interference from optical factors such as light source color and reflectivity. It can accurately distinguish between actual bridging defects at the same height as the solder balls and contaminants deposited on the substrate surface. Furthermore, the cleaning / rework compartment helps salvage contaminated, intact chips, thereby improving the reliability of the judgment. Attached Figure Description

[0019] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0020] Figure 1 This is a flowchart of the chip testing and sorting method according to an embodiment of the present invention; Figure 2This is a flowchart illustrating the process of determining the test and sorting requirements of a chip based on its brightness imbalance characterization value, according to an embodiment of the present invention. Figure 3 This is a flowchart illustrating how a first sorting strategy for a chip is determined based on the polarization attenuation ratio of the chip, according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the module connection of the chip testing and sorting equipment according to an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] Please see Figure 1 , Figure 2 , Figure 3 as well as Figure 4 The following are flowcharts of the chip testing and sorting method according to an embodiment of the present invention; flowcharts of determining the chip testing and sorting requirement state based on the brightness imbalance characterization value of the chip according to an embodiment of the present invention; flowcharts of determining the first sorting strategy of the chip based on the polarization attenuation ratio of the chip according to an embodiment of the present invention; and a schematic diagram of the module connection of the chip testing and sorting equipment according to an embodiment of the present invention.

[0023] On one hand, the chip testing and sorting method of this invention includes: Step S1: The chip to be tested is transferred to the vision inspection station by the vacuum suction nozzle robotic arm of the translational chip testing and sorting machine, ensuring that the bottom surface of the chip is facing upwards and the relative position of the camera and the chip is fixed (the center of the camera lens is aligned with the center of the chip, and the distance between the lens and the bottom surface of the chip is 50mm). The coaxial light source is turned on, and the light source power is adjusted to 10W and the exposure time is 50μs. The first grayscale image of the bottom surface of the chip is captured by the industrial camera (the image resolution is set to 1920×1080 pixels, the grayscale level is 8 bits, that is, the grayscale value range is 0-255). The grayscale histogram of the first grayscale image is obtained, and the brightness imbalance characterization value of the chip is obtained. Step S2: Determine the test sorting requirement state of the chip based on the brightness imbalance characterization value, wherein the test sorting requirement state includes a first-class test sorting requirement state and a second-class test sorting requirement state. Step S3: When the chip is in a test and sorting requirement state, first identify whether there is a candidate bright spot area in the first grayscale image of the chip; if there is no candidate bright spot area, sort the chip to the electrical testing compartment; if there is a candidate bright spot area, determine the polarization attenuation ratio based on the grayscale value of the candidate bright spot area in the first grayscale image and the grayscale value of the corresponding area in the second grayscale image, and determine the first sorting strategy based on the polarization attenuation ratio. Step S4: Determine whether the chip in the first-class test and sorting requirement state is in a suspected contamination state based on the polarization attenuation ratio determination result. Step S5: When the chip is in a state requiring secondary testing and sorting or in a state of suspected contamination, the bridging focal plane characterization value is determined based on the clarity of the bright spot area to be verified in the first focal plane image and the second focal plane image, and the second sorting strategy is determined based on the bridging focal plane characterization value. Step S6: For the chips sorted to the electrical testing compartment, perform electrical performance testing to complete the chip testing and sorting process.

[0024] Specifically, the chip's test and sorting requirements include a first type of test and sorting requirements and a second type of test and sorting requirements, wherein... If the brightness imbalance characterization value of the chip is less than the preset brightness imbalance characterization value of 0.18, the chip is determined to be in a first-class test and sorting requirement state. If the brightness imbalance characterization value is greater than or equal to the preset brightness imbalance characterization value, the chip is determined to be in the second-class test and sorting requirement state.

[0025] Specifically, the process of obtaining the brightness imbalance characterization value includes: The chip is illuminated using coaxial light, and a first grayscale image of the bottom surface of the chip is captured. The optimal global segmentation threshold is calculated using the Otsu's maximum inter-class variance method, and this global segmentation threshold is denoted as the first preset gray value 109. The Otsu's maximum inter-class variance method is a commonly used image adaptive global threshold segmentation algorithm in this field. Its core principle is to traverse the entire gray value range and calculate the gray value that maximizes the inter-class variance between foreground and background pixels, using this as the optimal global segmentation threshold. This enables unsupervised adaptive segmentation of the foreground and background of an image. Those skilled in the art can directly reproduce this threshold calculation process using standardized algorithm code. The gray-level histogram of the first gray-level image is statistically analyzed, dividing the pixels in the first gray-level image into a first pixel set and a second pixel set. The gray value of the first pixel set is less than the first preset gray value 109, and the gray value of the second pixel set is greater than or equal to the first preset gray value. The average gray value of the first pixel set is calculated as the first statistical gray value, and the average gray value of the second pixel set is calculated as the second statistical gray value. The ratio of the first statistical gray level to the second statistical gray level is used as the brightness imbalance characterization value.

[0026] Specifically, the brightness imbalance characterization value is the ratio of the average gray level of dark pixels to the average gray level of bright pixels, obtained by statistically analyzing the global gray level histogram of the coaxial light grayscale image. This ratio characterizes the overall optical contrast of the chip's bottom surface. When the brightness imbalance characterization value is small, it indicates a large gray level difference between dark and bright pixels and good overall contrast. This typically corresponds to chips with larger solder ball spacing or clean surfaces, and the risk of visual inspection misjudgment is low. Therefore, it is classified as a Class I test and sorting requirement state, employing rapid basic visual inspection. When the brightness imbalance characterization value is large, it indicates an increase in the average gray level of dark pixels and a decrease in overall contrast. Statistically, this reflects a trend of the solder ball gap area being "illuminated" by reflections. This usually occurs in fine-pitch packaging or scenarios with optical contamination, and the risk of visual inspection misjudgment is high. Therefore, it is classified as a Class II test and sorting requirement state, necessitating the initiation of a more refined visual inspection process.

[0027] In this embodiment, ten simple chips with known large solder ball spacing and clean surfaces were selected as the first sample group, and ten complex chips with known small solder ball spacing or slight oil film and particulate contamination on the surface were selected as the second sample group. Coaxial grayscale images of all samples were acquired, and the brightness imbalance characterization value of each chip was calculated according to the aforementioned method. Statistical results show that the brightness imbalance characterization value of the first sample group ranges from 0.05 to 0.15, while that of the second sample group ranges from 0.25 to 0.40. To ensure the tolerance of the judgment rule for low-risk chips and avoid missing high-risk chips, 1.2 times the maximum value of 0.15 in the first sample group was taken as the preset brightness imbalance characterization value, i.e., the preset brightness imbalance characterization value was 0.18.

[0028] Specifically, when the chip is in a state requiring a certain type of test and sorting... Identify whether candidate bright spot regions exist in the first grayscale image of the chip; If no candidate bright spot area is found, the chip is sorted to the electrical testing compartment. If candidate bright spot regions exist, the first sorting strategy for the chip is determined based on the polarization attenuation ratio of the chip, wherein: If the polarization attenuation ratio is less than the first preset polarization attenuation ratio of 0.3, the chip will be sorted into the defective product storage area. If the polarization attenuation ratio is greater than or equal to the first preset polarization attenuation ratio and less than the second preset polarization attenuation ratio of 0.6, the chip is marked as suspected contamination. If the polarization attenuation ratio is greater than or equal to the second preset polarization attenuation ratio, the chip will be sorted to the cleaning and rework compartment. The first preset polarization attenuation ratio is less than the second preset polarization attenuation ratio.

[0029] Specifically, the process of obtaining the polarization attenuation ratio includes: The chip is illuminated using coaxial light, and a first grayscale image of the bottom surface of the chip is captured. The chip is illuminated with orthogonally polarized light (a polarizer is installed in front of the light source and an analyzer is installed in front of the camera lens, and the polarization directions of the two are orthogonal to each other) and a second grayscale image of the bottom surface of the chip is captured. Under orthogonally polarized light, the specular reflection of the metal solder balls is greatly suppressed, while the diffuse reflection attenuation of contaminants (such as oil film and resin particles) is small. Identify candidate bright spot regions in the first grayscale image, wherein the candidate bright spot regions are connected regions in the first grayscale image whose grayscale value is greater than the second preset grayscale value 128 and whose area is greater than the preset area by 10 pixels; Calculate the average gray value of the candidate bright spot region in the first grayscale image, and record it as the gray value under coaxial light; Based on the centroid position of each candidate bright spot region, regions with the same coordinates are located in the second grayscale image, and the average grayscale value of the region in the second grayscale image is calculated and recorded as the grayscale under polarized light. The ratio of the gray level under polarized light to the gray level under coaxial light is denoted as the polarization attenuation ratio.

[0030] Specifically, the process of determining the second preset grayscale value includes: The first grayscale image is subjected to grayscale histogram statistics, and the optimal global segmentation threshold of the image is calculated using the Otsu maximum inter-class variance method. This threshold is recorded as the first preset grayscale value G1. The Otsu algorithm searches for the grayscale value that maximizes the inter-class variance between the foreground class and the background class by traversing the entire grayscale range. Since the candidate bright spot area physically corresponds to an abnormal area with stronger reflective properties than the surface of ordinary solder balls, it is represented in the grayscale image as a group of super bright pixels with a grayscale value higher than that of the normal bright area. Therefore, based on the first preset grayscale value, a preset bias coefficient k is introduced to adjust the first preset grayscale value upward to obtain the second preset grayscale value G2, that is: G2=G1×k. With the coaxial light source turned on at a power of 10W, the camera exposure time at 50μs, and the working distance between the lens and the bottom surface of the chip at 50mm, calibration tests were performed using chip samples known to contain oil film-particle composite contaminants and chip samples known to contain actual solder ball bridging defects. First grayscale images were acquired under coaxial light, and the ratio of the average grayscale value of the abnormal bright spot area in each type of sample to the first preset grayscale value G1 of their respective images was calculated. Statistical results showed that the average grayscale value of the contaminant bright spot area was 1.15-1.22 times G1, and the average grayscale value of the actual bridging defect bright spot area was 1.45-1.60 times G1. To ensure complete capture of both types of bright spots and differentiation by polarization attenuation ratio in subsequent steps, a coefficient value that covers the lower limit of the contaminant bright spot was selected. Preferably, the bias coefficient k is 1.17, i.e., G2 = G1 × 1.18. To prevent individual chips from deviating from the reasonable range in G2 calculation due to extreme surface conditions or abnormal lighting, upper and lower limits are imposed on G2: if the calculated G2 is less than 110, then 110 is forcibly taken as the second preset grayscale value; if the calculated G2 is greater than 180, then 180 is forcibly taken as the second preset grayscale value. In actual continuous operation, if the overall brightness of the captured image shifts due to natural decay of the light source, changes in ambient temperature, or differences in substrate material between chip batches, the first preset gray value G1 output by the Otsu algorithm will automatically shift accordingly. The second preset gray value G2, which is linked with G1 through a fixed proportional coefficient k, will also be automatically adjusted synchronously without the need for manual threshold reset, thus ensuring the stability and consistency of candidate bright spot region recognition under different test conditions. Under the conditions of this embodiment (light source power 10W, exposure time 50μs, lens distance from chip bottom surface 50mm), the first preset grayscale value G1 is obtained by performing the Otsu algorithm on the first grayscale image, which is 109. Substituting into the formula G2=109×1.17≈128, the second preset grayscale value in this embodiment is 128.

[0031] Specifically, the preset area is determined based on the following: In this embodiment, at a resolution of 1920×1080 and a magnification of 10x, the imaging area of ​​solder balls is 80-200 pixels, the imaging area of ​​isolated bright spots formed by oil film-particle composite contaminants is 8-30 pixels, and the area of ​​random noise points in the image is typically less than 3-5 pixels. Setting the preset area to 10 pixels can effectively filter out noise while completely preserving the bright spot area corresponding to the contaminant particles. However, the above value is not limited to this, and those skilled in the art can adjust the above value according to actual needs.

[0032] Specifically, the polarization attenuation ratio is essentially the average grayscale ratio of the same area under orthogonally polarized light and coaxial light. The polarization attenuation ratio reflects the reflective characteristics of the target bright spot. True solder ball bridging, composed of metal solder, has a smooth surface and primarily exhibits specular reflection. Under orthogonally polarized light, its brightness is significantly attenuated, resulting in a relatively small polarization attenuation. In contrast, contaminants such as oil films and resin particles primarily exhibit diffuse reflection, and their brightness attenuation is not significant under orthogonally polarized light, resulting in a relatively large polarization attenuation. When the polarization attenuation ratio is less than the first threshold, it is determined to be a genuine bridging defect and directly sorted to the defective product warehouse to prevent it from flowing into subsequent electrical testing and wasting resources. When the polarization attenuation ratio is between the two thresholds, it indicates that the reflective characteristics are blurred and uncertain, so it is marked as suspected contamination and upgraded to fine visual inspection. When the polarization attenuation ratio is greater than or equal to the second threshold, it is confirmed to be contaminant reflection rather than a genuine defect, and it is sorted to the cleaning and rework warehouse.

[0033] Specifically, the first preset polarization attenuation ratio has a value range of [0.2, 0.4], and the second preset polarization attenuation ratio has a value range of [0.5, 0.7]. Preferably, the first preset polarization attenuation ratio has a value of 0.3, and the second preset polarization attenuation ratio has a value of 0.6.

[0034] Specifically, the cleaning and rework compartment is used to temporarily store chips identified as having reflective surfaces due to surface contaminants. Operators remove the chips from the cleaning and rework compartment and send them to external cleaning equipment (such as a plasma cleaner or ultrasonic cleaner) for surface cleaning. After cleaning, the chips are reintroduced into the testing and sorting process. This embodiment does not involve specific cleaning processes and equipment; those skilled in the art can select conventional cleaning methods based on the type of contaminant.

[0035] Specifically, when the chip is in a Class II test sorting requirement state, or when the chip is marked as suspected contamination in the first test sorting requirement, the process of determining the second sorting strategy for the chip based on the bridging focal plane characterization value of the chip includes: If the bridging focal plane characterization value is less than the first preset bridging focal plane characterization value of 0.4, the chip will be sorted to the cleaning and rework compartment. If the bridging focal plane characterization value is greater than or equal to the first preset bridging focal plane characterization value and less than the second preset bridging focal plane characterization value of 0.8, then the chip is sorted to the electrical testing compartment. If the bridging focal plane characterization value is greater than or equal to the second preset bridging focal plane characterization value, the chip will be sorted into the defective product warehouse. The first preset bridging focal plane characterization value is less than the second preset bridging focal plane characterization value.

[0036] Specifically, the bridging focal plane characterization value reflects the ratio of the image sharpness of the bright spot to be verified on the solder ball gap plane to the chip substrate surface. Essentially, it is used to locate the actual physical height of the bright spot, thereby distinguishing between surface composite contaminants and actual solder ball bridging defects. When the bridging focal plane characterization value is less than a first preset threshold, the bright spot is mainly clearly imaged on the substrate surface, and is determined to be a surface composite contaminant, sent to the cleaning and rework compartment. When the bridging focal plane characterization value is between the two thresholds, the bright spot has no obvious height bias, mostly slight interference, and the chip has no substantial defects, sent to the electrical testing compartment. When the bridging focal plane characterization value is greater than or equal to a second preset threshold, the bright spot is clearly imaged on the solder ball gap plane, determined to be a real bridging defect, sent to the defective product compartment.

[0037] Specifically, the first preset bridging focal plane characterization value ranges from [0.3, 0.5], and the second preset bridging focal plane characterization value ranges from [0.7, 0.9]. Preferably, the first preset bridging focal plane characterization value is 0.4, and the second preset bridging focal plane characterization value is 0.8.

[0038] Specifically, the process of obtaining the bridging focal plane characterization value of the chip includes: Based on the centroid position of the candidate bright spot region, a magnified image is captured, switching to a high-magnification 10x objective lens to magnify and capture the candidate bright spot region, resulting in a magnified image (resolution 2560×1920 pixels, 8-bit grayscale, exposure time 80μs, coaxial light source power maintained at 20W). The centroid coordinates are calculated using the `moments` function from the OpenCV algorithm library. The OpenCV algorithm library, short for OpenSourceComputerVisionLibrary, is a widely used open-source computer vision and image processing algorithm library in this field. It includes standardized functions for image feature extraction, contour recognition, and geometric calculation, which can be directly installed and called by those skilled in the art. The `moments` function is a standardized function in the OpenCV library used to calculate image geometric moments. By inputting the pixel coordinates of the target region, it calculates the zeroth moment, first moment, and higher-order moments of that region. The centroid coordinates of the target region can be accurately calculated based on the ratio of the first moment to the zeroth moment. Those skilled in the art can directly call this function to calculate the centroid coordinates. Keep the relative position of the camera and the chip unchanged, and only change the focus height; The focus height is adjusted to the plane of the solder ball gap. In this embodiment, the focus height is adjusted to 8.23mm, and the first focal plane image is captured. The focus height is adjusted to the surface of the chip substrate. In this embodiment, the focus height is adjusted to 8.12mm to capture the second focal plane image. In the first focal plane image and the second focal plane image, the bright spot region to be verified is located respectively; For the bright spot region to be verified in the first focal plane, all pixels are traversed, and the variance of the Laplacian operator convolution result is calculated. This variance is denoted as the first sharpness. The Laplacian operator is a commonly used image edge detection operator based on second-order differentiation in the art. It has high sensitivity to regions with abrupt changes in image gray level. The sharper the image, the greater the edge gray level gradient, and the higher the variance value of the operator convolution result. Therefore, it is commonly used in the art for the quantitative evaluation of image sharpness. Those skilled in the art can calculate this operator by standardizing the convolution kernel. The same method was used to calculate the second sharpness for the bright spot area to be verified on the second focal plane; The ratio of the first sharpness to the second sharpness is denoted as the bridging focal plane characterization value of the chip. Specifically, the `findContours` function of OpenCV is used to identify intact, defect-free solder balls on the chip. The `findContours` function is a standardized function in the OpenCV library for image contour extraction. It can identify and output the contour coordinates and hierarchical relationships of all connected regions in a binary image as input. Those skilled in the art can directly call this function to achieve target contour recognition and extraction. The selection criteria are: intact solder ball contours, no damage, no offset, and no bright spots on the solder ball surface to exclude contamination. Four such solder balls are selected. The ball is used as the calibration reference. Then, the Z-axis focus height of the camera is adjusted. For every 0.005mm adjustment, an image of the corresponding solder ball is taken. For each solder ball image, the sharpness value of the solder ball image is calculated using a Laplacian operator with a 3×3 convolution kernel (the larger the sharpness value, the clearer the image, with a value range of 0-255). The sharpness value corresponding to each focus height is recorded. Finally, the focus height-sharpness curve is plotted. The focus height at which the sharpness value reaches its peak (and the peak sharpness value is greater than or equal to 200 to ensure that the image is clear and without blur) is found and recorded as the solder ball gap plane. Specifically, based on the overall chip image, a visual algorithm is used to identify exposed substrate areas on the chip that are free of solder balls and contaminants. The selection criteria are uniform grayscale (standard deviation of grayscale value less than 10) and no bright spots. Using the same method as the solder ball gap plane calibration, an image of the exposed substrate area is taken every time the focus height is adjusted by 0.005mm, and the sharpness value of each image is calculated. Then, a focus height-sharpness curve is plotted, and the focus height at which the sharpness value reaches its peak (and the peak sharpness value is greater than or equal to 180) is found and recorded as the chip substrate surface.

[0039] Specifically, the process of locating the bright spot region to be verified in the first focal plane image and the second focal plane image includes: Based on the centroid coordinates of the candidate bright spot regions identified in the first test sorting requirements, the points in the first focal plane image that have the same centroid coordinates are used as the search center. Using the search center as the center, the OpenCV findContours function is called to identify connected regions within a circular area with a preset radius of 15 pixels. These regions have a gray value greater than or equal to the second preset gray value and an area greater than or equal to the preset area, and are recorded as candidate regions. The gray values ​​of each candidate region are compared with the corresponding pixels in the candidate bright spot region. The pixels at the corresponding positions of the candidate regions and the candidate bright spot regions are traversed, and the gray value difference of each pixel is calculated. The reciprocal of the mean of the gray value differences is taken as the gray value similarity. The candidate region corresponding to the maximum gray value similarity is recorded as the bright spot region to be verified in the first focal plane. The outline of the bright spot region to be verified in the first focal plane is mapped to the same coordinate position in the second focal plane image; since the relative position of the camera and the chip is fixed during the two shots, the corresponding pixel region of the same coordinate region is taken and recorded as the bright spot region to be verified in the second focal plane.

[0040] On the other hand, embodiments of the present invention are applicable to chip testing and sorting equipment using the above-described method, including: A vision acquisition module is used to sequentially capture a first grayscale image, a second grayscale image, a first focal plane image focused on the solder ball gap plane, and a second focal plane image focused on the chip substrate surface. The vision acquisition module includes an industrial camera unit, a switchable light source unit, and an autofocus unit. The industrial camera unit uses an 8-bit grayscale industrial camera equipped with a conventional imaging lens and a switchable high-magnification microscope lens. The switchable light source unit integrates a coaxial light source and an orthogonally polarized light source, with the two light sources coaxially arranged below the camera's optical path and the light emission direction of the light source perpendicular to the chip's bottom surface. The autofocus unit uses a precision electric Z-axis slide, with the industrial camera fixed to the moving end of the Z-axis slide. The slide's positioning accuracy is not less than 0.001mm, used to adjust the focusing height to the solder ball gap plane or the chip substrate surface. An image processing module, connected to the vision acquisition module, is used to calculate the brightness imbalance characterization value based on the grayscale histogram; to calculate the polarization attenuation ratio based on the average grayscale in the first grayscale image and the second grayscale image; and to obtain the bridging focal plane characterization value based on the sharpness in the first focal plane image and the second focal plane image. The control module, connected to the image processing module, is used to determine the test sorting requirement state of the chip based on the brightness imbalance characterization value of the chip; to determine the first sorting strategy of the chip based on the polarization attenuation ratio of the chip; to determine the second sorting strategy of the chip based on the bridging focal plane characterization value of the chip; and to issue the final sorting instruction to the sorting execution module based on the electrical test results of the electrical test module. The sorting execution module, connected to the control module, is used to transfer the chips to the corresponding storage locations according to the first sorting strategy or the second sorting strategy. The storage locations include a defective product storage location, a cleaning and rework storage location, and an electrical testing storage location. The sorting execution module is also used to transfer qualified chips to the good product storage location and unqualified chips to the defective product storage location according to the final material distribution instruction from the control module after the electrical testing is completed. The electrical testing module is connected to both the sorting execution module and the control module to perform open / short circuit tests, DC parameter tests, and functional tests on the chips in the electrical testing compartment. After the electrical tests are completed, the test results (pass / fail) and the test completion status are uploaded to the control module in real time.

[0041] Specifically, the sorting execution module includes a loading unit and a unloading unit, which are responsible for the physical transfer of chips between various workstations and storage areas according to the instructions issued by the control module. The loading unit is used to transfer the chips to be tested from the tray to the vision inspection station, and completes the transfer of chips between the defective product storage area, the cleaning and rework storage area, and the electrical testing storage area according to the instructions of the control module. The control module issues the final sorting instruction to the unloading unit of the sorting execution module, and the unloading unit transfers qualified chips to the good product storage area and unqualified chips to the defective product storage area according to the final sorting instruction.

[0042] Specifically, the electrical testing module uses conventional automated test equipment (ATE) to sequentially perform the following tests: open / short circuit testing, detecting the connectivity between each pin of the chip and its internal circuitry to determine if an open or short circuit exists; DC parameter testing, measuring the chip's static DC characteristics, including but not limited to power supply current, leakage current, and output high / low level voltage; and functional testing, applying a preset input stimulus signal to the chip, acquiring the output response, and verifying whether its logic function meets the design specifications. During the testing process, the electrical testing module and the sorting execution module communicate in real time via an industrial bus (such as RS232) to transmit the test results (pass / fail) to the control module. Based on the test results, the unloading unit of the sorting execution module moves qualified chips to the good product bin and unqualified chips to the defective product bin. The specific test vectors, threshold parameters, and test sequence of the above electrical performance tests can be conventionally set by those skilled in the art according to the specifications of the chip under test and the operation manual of the ATE equipment, and will not be elaborated here.

[0043] Specifically, there are no restrictions on the specific structure of the image processing module and the control module. They themselves and their units can be composed of logic components, including field-programmable components, computers, or microprocessors in computers.

[0044] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A chip testing and sorting method, characterized in that, include: The chip to be tested is transferred to the vision inspection station, a first grayscale image of the bottom surface of the chip is captured, the grayscale histogram of the first grayscale image is obtained, and the brightness imbalance characterization value of the chip is obtained. The test sorting requirement state of the chip is determined based on the brightness imbalance characterization value, wherein the test sorting requirement state includes a first type of test sorting requirement state and a second type of test sorting requirement state. When the chip is in a state requiring a type of test and sorting, first identify whether there is a candidate bright spot area in the first grayscale image of the chip; if there is no candidate bright spot area, sort the chip to the electrical testing compartment; if there is a candidate bright spot area, determine the polarization attenuation ratio based on the grayscale value of the candidate bright spot area in the first grayscale image and the grayscale value of the corresponding area in the second grayscale image, and determine the first sorting strategy based on the polarization attenuation ratio. Based on the polarization attenuation ratio determination result, determine whether the chip in the first-class test and sorting requirement state is in a suspected contamination state; When the chip is in a state requiring secondary testing and sorting or in a state of suspected contamination, the bridging focal plane characterization value is determined based on the clarity of the bright spot area to be verified in the first focal plane image and the second focal plane image, and the second sorting strategy is determined based on the bridging focal plane characterization value. For chips sorted to the electrical testing compartment, electrical performance tests are performed to complete the chip testing and sorting process; When the chip is in a state requiring a certain type of test and sorting. Identify whether candidate bright spot regions exist in the first grayscale image of the chip; If no candidate bright spot area is found, the chip is sorted to the electrical testing compartment. If candidate bright spot regions exist, the first sorting strategy for the chip is determined based on the polarization attenuation ratio of the chip, wherein: If the polarization attenuation ratio is less than the first preset polarization attenuation ratio, the chip will be sorted into the defective product storage area. If the polarization attenuation ratio is greater than or equal to the first preset polarization attenuation ratio and less than the second preset polarization attenuation ratio, the chip is marked as suspected contamination. If the polarization attenuation ratio is greater than or equal to the second preset polarization attenuation ratio, the chip will be sorted to the cleaning and rework compartment. The first preset polarization attenuation ratio is less than the second preset polarization attenuation ratio; When the chip is in a Class II test and sorting requirement state, or when the chip is marked as suspected contamination in the first test and sorting requirement, the process of determining the second sorting strategy for the chip based on the bridging focal plane characterization value of the chip includes: If the bridging focal plane characterization value is less than the first preset bridging focal plane characterization value, the chip will be sorted to the cleaning and rework compartment. If the bridging focal plane characterization value is greater than or equal to the first preset bridging focal plane characterization value and less than the second preset bridging focal plane characterization value, then the chip is sorted to the electrical testing compartment. If the bridging focal plane characterization value is greater than or equal to the second preset bridging focal plane characterization value, the chip will be sorted into the defective product warehouse. The first preset bridging focal plane characterization value is less than the second preset bridging focal plane characterization value.

2. The chip testing and sorting method according to claim 1, characterized in that, The chip's test and sorting requirements include two types: a first type and a second type. If the brightness imbalance characterization value of the chip is less than the preset brightness imbalance characterization value, the chip is determined to be in a type of test and sorting requirement state. If the brightness imbalance characterization value is greater than or equal to the preset brightness imbalance characterization value, the chip is determined to be in the second-class test and sorting requirement state.

3. The chip testing and sorting method according to claim 2, characterized in that, The process of obtaining the brightness imbalance characterization value includes: The chip is illuminated using coaxial light, and a first grayscale image of the bottom surface of the chip is captured. The grayscale histogram of the first grayscale image is statistically analyzed, and the pixels in the first grayscale image are divided into a first pixel set and a second pixel set, wherein the grayscale value of the first pixel set is less than a first preset grayscale value, and the grayscale value of the second pixel set is greater than or equal to the first preset grayscale value. The average gray value of the first pixel set is calculated as the first statistical gray value, and the average gray value of the second pixel set is calculated as the second statistical gray value. The ratio of the first statistical gray level to the second statistical gray level is used as the brightness imbalance characterization value.

4. The chip testing and sorting method according to claim 3, characterized in that, The process of obtaining the polarization attenuation ratio includes: The chip is illuminated using coaxial light, and a first grayscale image of the bottom surface of the chip is captured. The chip is illuminated with orthogonally polarized light, and a second grayscale image of the bottom surface of the chip is captured. Identify candidate bright spot regions in the first grayscale image, wherein the candidate bright spot regions are connected regions in the first grayscale image whose grayscale value is greater than a second preset grayscale value and whose area is greater than a preset area; Calculate the average gray value of the candidate bright spot region in the first grayscale image, and record it as the gray value under coaxial light; Based on the centroid position of each candidate bright spot region, regions with the same coordinates are located in the second grayscale image, and the average grayscale value of the region in the second grayscale image is calculated and recorded as the grayscale under polarized light. The ratio of the gray level under polarized light to the gray level under coaxial light is denoted as the polarization attenuation ratio.

5. The chip testing and sorting method according to claim 4, characterized in that, The process of obtaining the bridging focal plane characterization value of the chip includes: Based on the centroid position of the candidate bright spot region, magnify the image and switch to a high-magnification lens to magnify the candidate bright spot region to obtain a locally magnified image; Keep the relative position of the camera and the chip unchanged, and only change the focus height; Adjust the focus height to the plane of the solder ball gap and take a picture of the first focal plane; Adjust the focus height to the surface of the chip substrate and capture the image of the second focal plane. In the first focal plane image and the second focal plane image, the bright spot region to be verified is located respectively; Calculate the sharpness of the bright spot region to be verified in the first focal plane image, and denote it as the first sharpness; Calculate the sharpness of the bright spot region to be verified in the second focal plane image, and denote it as the second sharpness; The ratio of the first sharpness to the second sharpness is denoted as the bridging focal plane characterization value of the chip.

6. The chip testing and sorting method according to claim 5, characterized in that, The solder ball gap plane is determined by focusing on several complete and defect-free solder balls on the chip until the solder ball imaging clarity reaches its peak. The focus position on the chip substrate surface is determined by focusing on the exposed area of ​​the substrate without solder balls or contaminants until the substrate image sharpness reaches its peak.

7. The chip testing and sorting method according to claim 6, characterized in that, The process of locating the bright spot region to be verified in the first focal plane image and the second focal plane image includes: Based on the centroid coordinates of the candidate bright spot regions identified in the first test sorting requirements, the points in the first focal plane image that have the same centroid coordinates are used as the search center. With the search center as the center, within a circular area of ​​a preset radius, connected regions whose pixel gray values ​​are greater than or equal to the second preset gray value and whose area is greater than or equal to the preset area are denoted as candidate regions; Each candidate region is compared with the gray value of a corresponding pixel in the candidate bright spot region to obtain a gray value similarity of several candidate regions; the candidate region corresponding to the maximum gray value similarity is recorded as the bright spot region to be verified in the first focal plane. The outline of the bright spot region to be verified in the first focal plane is mapped to the same coordinate position in the second focal plane image; since the relative position of the camera and the chip is fixed during the two shots, the corresponding pixel region of the same coordinate region is taken and recorded as the bright spot region to be verified in the second focal plane.

8. A chip testing and sorting device applicable to the method described in any one of claims 1-7, characterized in that, include: A vision acquisition module is used to sequentially capture a first grayscale image, a second grayscale image, a first focal plane image focused on the solder ball gap plane, and a second focal plane image focused on the chip substrate surface. It includes an industrial camera unit, a switchable light source unit, and an autofocus unit. The switchable light source unit includes a coaxial light source and an orthogonally polarized light source. The autofocus unit is used to adjust the focus height to the solder ball gap plane or the chip substrate surface. An image processing module, connected to the vision acquisition module, is used to calculate the brightness imbalance characterization value based on the grayscale histogram; to calculate the polarization attenuation ratio based on the average grayscale in the first grayscale image and the second grayscale image; and to obtain the bridging focal plane characterization value based on the sharpness in the first focal plane image and the second focal plane image. A control module, connected to the image processing module, is used to determine the test sorting requirement state of the chip based on the chip's brightness imbalance characterization value; to determine the first sorting strategy of the chip based on the chip's polarization attenuation ratio; and to determine the second sorting strategy of the chip based on the chip's bridging focal plane characterization value. The sorting execution module is connected to the control module and is used to transfer the chip to the corresponding compartment according to the first sorting strategy or the second sorting strategy. The compartment includes a defective product compartment, a cleaning and rework compartment, and an electrical testing compartment. An electrical testing module, which is connected to the sorting execution module and the control module respectively, is used to perform open circuit / short circuit tests, DC parameter tests and functional tests on the chips in the electrical testing compartment, and transfer qualified chips to the good product compartment and unqualified chips to the defective product compartment according to the test results.

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