Bonded wafer and method of processing the same

Abstract

This invention provides a bonding wafer and its processing method. First, a heat treatment process is performed to convert metal residues on the top surface of the top silicon layer and a portion of the top silicon layer thickness into an oxide layer. Then, an etching process is performed to remove the oxide layer and expose the remaining top surface of the top silicon layer. Next, the remaining top silicon layer undergoes in-situ repair processing. In this way, metal residues on the top surface of the top silicon layer can be removed, and the remaining top surface of the top silicon layer can be repaired through in-situ repair. This allows for in-situ repair and reconstruction of the top surface of the top silicon layer, resulting in an atomically smooth, low-defect, ultra-clean surface, making the metal element density on the top surface of the bonding wafer less than or equal to 0.001 × 10⁻⁶. 10 atoms / cm 2 .

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a bonding wafer and its processing method. Background Technology

[0002] Silicon-on-insulator (SOI) technology has brought significant advantages to semiconductor devices, such as effectively reducing parasitic capacitance, lowering power consumption, increasing operating speed, and enhancing radiation resistance. With the continuous evolution of advanced process nodes and the shrinking of device feature sizes, the cleanliness of the SOI wafer surface (especially its extremely thin top silicon layer) has become crucial. Even trace amounts of residual metal contamination on the top surface of an SOI wafer can significantly increase the interface state density, causing threshold voltage drift and increased leakage current, severely degrading device performance and reliability. This has become a key bottleneck restricting further miniaturization and yield improvement of integrated circuits. However, current SOI wafer manufacturing processes suffer from surface metal contamination, meaning that residual metal remains on the top surface of the SOI wafer. These residual metals mainly originate from process equipment and chemical reagents, and are difficult to completely remove using traditional cleaning methods. Summary of the Invention

[0003] The purpose of this invention is to provide a bonding wafer and a processing method thereof to remove metal residues from the surface of the top silicon layer.

[0004] To achieve the above objectives, the present invention provides a method for processing bonded wafers, comprising:

[0005] A bonding wafer is provided, the bonding wafer comprising a support substrate, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top;

[0006] A heat treatment process is performed to convert the metal residue on the top surface of the top silicon layer and a portion of the thickness of the top silicon layer into an oxide layer;

[0007] An etching process is performed to remove the oxide layer and expose the top surface of the remaining top silicon layer;

[0008] The remaining top silicon layer is then repaired in situ.

[0009] Optionally, in the bonding wafer processing method, the oxide layer comprises a metal oxide formed by the conversion of metal residues on the surface of the top silicon layer and silicon oxide formed by the conversion of a portion of the thickness of the top silicon layer.

[0010] Optionally, in the bonding wafer processing method, the temperature of the heat treatment process is 800°C-1200°C, and the oxidation time is 1 hour-5 hours.

[0011] Optionally, in the bonding wafer processing method, the gas used in the heat treatment process includes oxygen, and the oxygen flow rate is 1SLM-30SLM.

[0012] Optionally, in the bonding wafer processing method, the gases used in the heat treatment process include oxygen and water vapor, and the gas flow rates of the oxygen and the water vapor are both 1 SLM-30 SLM.

[0013] Optionally, in the bonding wafer processing method, the gas used in the heat treatment process includes a mixture of hydrogen and oxygen, wherein the flow rate of hydrogen and oxygen is 1 SLM-30 SLM, and the flow rate ratio of hydrogen to oxygen is 2:1 to 4:1.

[0014] Optionally, in the method for processing the bonded wafer, the etching process uses hydrofluoric acid with a concentration of 2%-15%, a temperature of 20℃-75℃, and a time of 100s-1000s.

[0015] Optionally, in the method for processing the bonded wafer, the temperature of the in-situ repair treatment is 1000 ℃-1200 ℃, and the time is 15s-35s.

[0016] Optionally, in the bonding wafer processing method, the atmosphere for the in-situ repair treatment is an inert gas atmosphere, or a mixed atmosphere in which the inert gas is doped with less than 5% hydrogen.

[0017] Based on the same inventive concept, the present invention also provides a bonding wafer, which is prepared by the bonding wafer processing method described above, wherein the metal element density on the top surface of the bonding wafer is less than or equal to 0.001 × 10⁻⁶. 10 atoms / cm 2 .

[0018] In the bonding wafer and its processing method provided by this invention, a heat treatment process is first performed to transform the metal residue on the top surface of the top silicon layer and a portion of the top silicon layer into an oxide layer. Then, an etching process is performed to remove the oxide layer and expose the remaining top surface of the top silicon layer. Next, the remaining top silicon layer undergoes in-situ repair processing. In this way, metal residue on the top surface of the top silicon layer can be removed, and the remaining top surface of the top silicon layer can be repaired through in-situ repair. This allows for in-situ repair and reconstruction of the top surface of the top silicon layer, resulting in an atomically smooth, low-defect, ultra-clean surface, making the metal element density on the top surface of the bonding wafer less than or equal to 0.001 × 10⁻⁶. 10 atoms / cm 2 . Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of the bonding wafer processing method provided in an embodiment of the present invention.

[0020] Figures 2 to 4 This is a schematic diagram of the structure formed in the bonding wafer processing method provided in the embodiments of the present invention.

[0021] Figure 5 This is an SEM surface scan image of the bonding wafer after the etching process is performed in the bonding wafer processing method provided in the embodiments of the present invention.

[0022] Figure 6 This is an SEM surface scan image of the bonding wafer in the bonding wafer processing method provided in this embodiment of the invention.

[0023] Figure 7 This is an SEM surface scan image of the bonding wafer in Comparative Example 1 of the bonding wafer processing method provided in this embodiment of the invention.

[0024] Figure 8 This is an SEM surface scan image of the bonding wafer in Comparative Example 2 of the bonding wafer processing method provided in this embodiment of the invention.

[0025] Figure 9 This is a SEM surface scan image of the bonding wafer in Comparative Example 3 of the bonding wafer processing method provided in this embodiment of the invention.

[0026] The reference numerals in the attached figures are explained as follows:

[0027] 100 - Bonded wafer; 110 - Supporting substrate; 120 - Buried oxide layer; 130 - Top silicon layer; 140 - Oxide layer; 141 - Metal oxide; 142 - Silicon oxide. Detailed Implementation

[0028] The bonding wafer and its processing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only used to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0029] Figure 1 This is a schematic flowchart of the bonding wafer processing method provided in an embodiment of the present invention. Figure 1 As shown, the bonding wafer processing method provided in this embodiment includes:

[0030] Step S1: Provide a bonding wafer, the bonding wafer comprising a support substrate, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top;

[0031] Step S2: Perform a heat treatment process to convert the metal residue on the top surface of the top silicon layer and a portion of the thickness of the top silicon layer into an oxide layer;

[0032] Step S3: Perform an etching process to remove the oxide layer and expose the top surface of the remaining top silicon layer;

[0033] Step S4: Perform in-situ repair treatment on the remaining top silicon layer.

[0034] Figures 2 to 4 This is a schematic diagram of the structure formed in the bonding wafer processing method provided in the embodiments of the present invention. The following will refer to the attached diagram. Figures 2 to 4 The bonding wafer processing method provided in the embodiments of the present invention will be described in more detail.

[0035] First, execute step S1, as follows: Figure 2 As shown, a bonding wafer 100 is provided, the bonding wafer 100 including a support substrate 110, a buried oxide layer 120 and a top silicon layer 130 stacked from bottom to top.

[0036] Specifically, the method for forming the bonding wafer 100 includes: first, providing a silicon ingot grown by the Czochralski method, with the crystal growth direction being... <100> or <110> or <111> The ingot is edge-rolled to the target diameter and cut into segments, in the direction of... <110> or <100> Then, the crystal segments are sliced ​​and subjected to grinding, polishing, and cleaning to obtain the final silicon wafer as a device substrate. The thickness of the device substrate can be 500 μm to 800 μm. Next, the device substrate is thermally oxidized to form a buried oxide layer 120 on its surface. The thickness of the buried oxide layer 120 can be 50 nm to 1000 nm. Then, hydrogen ion implantation is performed on the device substrate from the surface of the buried oxide layer 120 to form an ion implantation layer. The hydrogen ion implantation energy can be 50 to 70 keV, for example, 60 keV; the implantation dose can be 5E16 atom / cm. 2 ~6E16 atom / cm 2 For example, 5.5E16 atom / cm 2 .

[0037] Next, another crystal segment is provided and ground, polished and cleaned to form a support substrate 110 with a thickness of 500μm to 800μm.

[0038] Next, as Figure 2As shown, the support substrate 110 is bonded to the device substrate, and the buried oxide layer 120 is located between the device substrate and the support substrate 110. Then, a stripping process is performed to peel off a portion of the device substrate from the location of the ion implantation layer, and the remaining device substrate is used as the top silicon layer 130. The support substrate 110, the buried oxide layer 120 and the top silicon layer 130 constitute the bonding wafer 100.

[0039] Next, proceed to step S2, as follows: Figure 3 As shown, a heat treatment process is performed to convert the metal residue on the top surface of the top silicon layer 130, along with a portion of the thickness of the top silicon layer 130, into an oxide layer. The metal residue on the top surface of the top silicon layer 130 is metal contamination from the bonding wafer manufacturing process, such as that originating from process equipment and chemical reagents.

[0040] Specifically, the heat treatment process can be a furnace tube process, and the temperature of the heat treatment process can be 800℃-1200℃, for example 900℃, 1000℃ or 1100℃. The oxidation time can be 1 hour-5 hours, for example 1 hour, 3 hours or 4 hours.

[0041] In some embodiments, the gas used in the heat treatment process includes oxygen, and the oxygen flow rate can be 1 SLM-30 SLM, such as 5 SLM, 10 SLM or 20 SLM.

[0042] In some embodiments, the gases used in the heat treatment process include oxygen and water vapor, and the gas flow rates of the oxygen and the water vapor are both 1 SLM-30 SLM, such as 5 SLM, 10 SLM or 20 SLM.

[0043] In some embodiments, the heat treatment process uses a gas mixture of hydrogen and oxygen, i.e., water vapor is generated by burning the hydrogen-oxygen mixture (H2+O2) in a furnace, wherein the flow rates of the hydrogen and oxygen are both 1SLM-30SLM, and the flow rate ratio of the hydrogen to oxygen is 2:1 to 4:1.

[0044] During the heat treatment process, metal residues on the top surface of the top silicon layer 130 and a portion of the top silicon layer 130 are oxidized to form an oxide layer 140. Specifically, the oxide layer includes a metal oxide 141 formed from the metal residues on the surface of the top silicon layer 130 and a silicon oxide 142 formed from a portion of the top silicon layer, with the silicon oxide covering the metal oxide.

[0045] In this embodiment, the thickness of the oxide layer 140 can be 50 angstroms to 1000 angstroms, for example 60 angstroms, 100 angstroms, 200 angstroms, 300 angstroms, 500 angstroms, 600 angstroms, 700 angstroms or 800 angstroms.

[0046] It should be noted that the thickness of the oxide layer 140 cannot be too thick or too thin. If the oxide layer 140 is too thick, i.e., greater than 1000 angstroms, it will affect the thickness of the remaining top silicon layer 130, causing excessive top silicon layer 130 to be converted into silicon oxide. If the oxide layer 140 is too thin, i.e., less than 50 angstroms, the oxidized top silicon layer 130 will be too thin, making it easy for residual metal on the top surface of the top silicon layer 130 to not react completely. Based on this, in this embodiment, the thickness of the oxide layer 140 can be 50 angstroms to 1000 angstroms.

[0047] Next, proceed to step S3, as follows: Figure 4 As shown, an etching process is performed to remove the oxide layer 140 and expose the top surface of the remaining top silicon layer 130. In this way, the oxide layer 140 on the top surface of the top silicon layer can be removed, thereby completely removing the oxide layer 140 and the metal residue (or residual metal contamination) it traps.

[0048] In this embodiment, the etching process uses hydrofluoric acid with a concentration of 2%-15%. Specifically, the oxide layer 140 is removed by a wet etching process. The solution used in the wet etching process is hydrofluoric acid, and the concentration can be 2%-15%, for example, 3%, 5%, 10% or 12%; the temperature can be 20℃-75℃, for example, 30℃, 50℃ or 60℃; and the time can be 100s-1000s.

[0049] Next, step S4 is performed to perform in-situ repair treatment on the remaining top silicon layer 130. In this way, by repairing the top surface of the remaining top silicon layer 130 through in-situ repair treatment, the top surface of the top silicon layer 130 can be repaired and reconstructed in situ, thereby obtaining an atomically smooth, low-defect ultra-clean surface.

[0050] Figure 5 This is an SEM surface scan image of the bonding wafer after the etching process is performed in the bonding wafer processing method provided in this embodiment of the invention. For example... Figure 5 As shown, after the etching process, the top silicon layer 130 has lattice damage. Therefore, the top surface of the top silicon layer 130 can be repaired and reconstructed in situ through in-situ repair treatment, thereby obtaining an atomically flat, low-defect ultra-clean surface.

[0051] In this embodiment, the temperature of the in-situ repair process can be 1000℃-1200℃, such as 1050℃ or 1100℃, and the time can be 15s-35s. This can avoid insufficient repair effect caused by the in-situ repair temperature being too low or the time being too short, and avoid roughening or slip line problems in the top silicon layer caused by the temperature being too high or the time being too long.

[0052] In this embodiment, the gas used for in-situ remediation is an inert gas atmosphere or a mixed atmosphere of inert gas and less than 5% hydrogen.

[0053] In this embodiment, the in-situ repair treatment may include a rapid thermal annealing process.

[0054] The following provides an embodiment and three comparative examples to further illustrate the effect of the bonding wafer 100 processing method provided in this embodiment.

[0055] Example 1, as Figure 4 As shown, a bonding wafer 100 is provided, the bonding wafer 100 including a support substrate 110, a buried oxide layer 120 and a top silicon layer 130 stacked sequentially from bottom to top; a thermal processing process is performed to convert metal residues on the top surface of the top silicon layer 130 and a portion of the thickness of the top silicon layer 130 into an oxide layer 140, wherein the temperature of the thermal processing process is 1150°C; an etching process is performed to remove the oxide layer 140 and expose the remaining top surface of the top silicon layer 130; the remaining top silicon layer 130 is subjected to an in-situ repair process, wherein the in-situ repair process is performed at a temperature of 1150°C for a time of 30 seconds.

[0056] Figure 6 This is an SEM surface scan image of the bonding wafer in the bonding wafer processing method provided in this embodiment of the invention. Combined with... Figure 6 As shown, after in-situ repair, the metal element density on the top surface of the bonding wafer 100 is less than or equal to 0.001 × 10⁻⁶. 10 atoms / cm 2 Furthermore, the top surface of the bonded wafer is well repaired and free of slip lines.

[0057] In Comparative Example 1, two bare silicon wafers were selected as the device substrate and the support substrate, respectively, both with a thickness of 770µm-775µm. Then, the device substrate was sequentially cleaned and oxidized to form a buried oxide layer 120 with a thickness of 2000 angstroms. Subsequently, hydrogen ion implantation was performed on the device substrate at an implantation energy of 60 keV and an implantation dose of 5.5 × 10⁻⁶. 16 atom / cm 2Next, a bonding process is performed on the device substrate and the support substrate to bond the device substrate and the support substrate together, with the buried oxide layer 120 located between the device substrate and the support substrate; then, a stripping process is performed to strip a portion of the device substrate from the location of the ion implantation layer, and the remaining device substrate is used as the top silicon layer 130. The device substrate, the oxide layer 110 and the top silicon layer 130 constitute the bonding wafer 100; then, the bonding wafer 100 is subjected to a reinforcement process, a surface smoothing process and a thinning process in sequence.

[0058] Figure 7 This is an SEM surface scan image of the bonding wafer in Comparative Example 1 of the bonding wafer processing method provided in this embodiment of the invention. Combined with... Figure 7 As shown, the density of metal elements (e.g., Ni) on the top surface of the bonding wafer 100 is 0.2 × 10⁻⁶. 10 atoms / cm 2 .

[0059] Comparative Example 2: A bonding wafer 100 is provided, the bonding wafer 100 including a support substrate 110, a buried oxide layer 120 and a top silicon layer 130 stacked sequentially from bottom to top; a thermal processing process is performed to convert metal residues on the top surface of the top silicon layer 130 and a portion of the thickness of the top silicon layer 130 into an oxide layer 140, wherein the temperature of the thermal processing process is 900°C; an etching process is performed to remove the oxide layer 140 and expose the remaining top surface of the top silicon layer 130; the remaining top silicon layer 130 is subjected to an in-situ repair process, wherein the temperature of the in-situ repair process is 900°C and the time is 10s.

[0060] Figure 8 This is an SEM surface scan image of the bonding wafer in Comparative Example 2 of the bonding wafer processing method provided in this embodiment of the invention. Combined with... Figure 8 As shown, the density of metal elements (e.g., Ni) on the top surface of the bonding wafer 100 is 0.001 × 10⁻⁶. 10 atoms / cm 2 However, SEM results showed that the surface of the bonding wafer 100 (i.e. the top surface of the top silicon layer 130) was not repaired.

[0061] Comparative Example 3 provides a bonding wafer 100, which includes a support substrate 110, a buried oxide layer 120, and a top silicon layer 130 stacked sequentially from bottom to top; a thermal processing process is performed to convert metal residues on the top surface of the top silicon layer 130 and a portion of the thickness of the top silicon layer 130 into an oxide layer 140, wherein the temperature of the thermal processing process is 1200°C; an etching process is performed to remove the oxide layer 140 and expose the remaining top surface of the top silicon layer 130; the remaining top silicon layer 130 is subjected to an in-situ repair process, wherein the temperature of the in-situ repair process is 1250°C and the time is 40 seconds.

[0062] Figure 9 This is an SEM surface scan image of the bonding wafer in Comparative Example 3 of the bonding wafer processing method provided in this embodiment of the invention. Combined with... Figure 9 As shown, the density of metal elements (e.g., Ni) on the top surface of the bonding wafer 100 is 0.001 × 10⁻⁶. 10 atoms / cm 2 However, SEM results showed that there were 5 slip lines on the surface of the bonding wafer 100 (i.e. the top surface of the top silicon layer 130).

[0063] like Figure 4 As shown, this embodiment also provides a bonding wafer 100, which is prepared by the bonding wafer 100 processing method provided in this embodiment. The metal element density on the top surface of the bonding wafer 100 is less than or equal to 0.001 × 10⁻⁶. 10 atoms / cm 2 .

[0064] In summary, the bonding wafer and its processing method provided by this invention first perform a heat treatment process to transform the metal residue on the top surface of the top silicon layer and a portion of the top silicon layer into an oxide layer. Then, an etching process is performed to remove the oxide layer and expose the remaining top surface of the top silicon layer. Next, the remaining top silicon layer undergoes in-situ repair processing. This removes the metal residue on the top surface of the top silicon layer and repairs the remaining top surface through in-situ repair, enabling in-situ repair and reconstruction of the top surface. This results in an atomically smooth, low-defect, ultra-clean surface, with a metal element density on the top surface of the bonding wafer that is less than or equal to 0.001 × 10⁻⁶. 10 atoms / cm 2 .

[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0066] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for processing bonded wafers, characterized in that, include: A bonding wafer is provided, the bonding wafer comprising a support substrate, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top; A heat treatment process is performed to convert the metal residue on the top surface of the top silicon layer and a portion of the thickness of the top silicon layer into an oxide layer; An etching process is performed to remove the oxide layer and expose the top surface of the remaining top silicon layer; The remaining top silicon layer is then repaired in situ.

2. The method for processing bonded wafers as described in claim 1, characterized in that, The oxide layer comprises metal oxides formed from metal residues on the surface of the top silicon layer and silicon oxide formed from a portion of the thickness of the top silicon layer.

3. The method for processing bonded wafers as described in claim 1, characterized in that, The heat treatment process is carried out at a temperature of 800℃-1200℃ and an oxidation time of 1 hour-5 hours.

4. The method for processing bonded wafers as described in claim 3, characterized in that, The heat treatment process uses oxygen as the gas, and the oxygen flow rate is 1 SLM-30 SLM.

5. The method for processing bonded wafers as described in claim 3, characterized in that, The heat treatment process uses gases including oxygen and water vapor, with the gas flow rates of both oxygen and water vapor being 1 SLM-30 SLM.

6. The method for processing bonded wafers as described in claim 3, characterized in that, The heat treatment process uses a mixture of hydrogen and oxygen, with each hydrogen gas having a flow rate of 1 slm to 30 slm and a flow rate ratio of hydrogen to oxygen of 2:1 to 4:

1.

7. The method for processing bonded wafers as described in claim 1, characterized in that, The etching process uses hydrofluoric acid with a concentration of 2%-15%, a temperature of 20℃-75℃, and a time of 100s-1000s.

8. The method for processing bonded wafers as described in claim 1, characterized in that, The in-situ repair treatment is performed at a temperature of 1000℃-1200℃ for a time of 15s-35s.

9. The method for processing bonded wafers as described in claim 1, characterized in that, The atmosphere for the in-situ repair treatment is an inert gas atmosphere, or a mixed atmosphere in which an inert gas is doped with less than 5% hydrogen.

10. A bonding wafer, characterized in that, The bonding wafer is prepared using the bonding wafer processing method described in any one of claims 1-9, wherein the metal element density on the top surface of the bonding wafer is less than or equal to 0.001 × 10⁻⁶. 10 atoms / cm 2 .

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