Three-dimensional integrated packaging structure of glass core TGV panel with embedded heterogeneous chip and its fabrication method

Abstract

This invention discloses a three-dimensional integrated packaging structure and fabrication method of a glass core TGV panel with embedded heterogeneous chips. The upper and lower redistribution layers of the glass core are vertically interconnected through several metal vias. The glass core layer is provided with dry cavities, and several electronic components are embedded in the glass core layer along the Z-axis through these cavities. The electronic components are horizontally wired and transmit signals through the upper and lower redistribution layers, and are electrically connected to external circuits through the upper and lower redistribution layers and metal vias. This invention integrates the cost advantages of large-size glass panels, the performance advantages of glass materials, the vertical interconnection advantages of TGV, the density advantages of embedded packaging, and thermal management technology. It addresses the shortcomings of current packaging technologies in terms of high performance, high integration, low cost, and excellent heat dissipation, providing a system-level packaging solution with superior overall performance. This solution can improve system performance, heat dissipation performance, and integration, while reducing costs.

Description

Technical Field

[0001] This invention belongs to the field of electronic equipment technology, and specifically discloses a three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips and its preparation method. Background Technology

[0002] With the rapid development of chip technology, the demands for chip computing power, bandwidth, and energy efficiency are increasing exponentially. Traditional technologies, such as using Moore's Law to shrink transistor size to improve performance, are limited by physical constraints and economic costs. The industry is trending towards advanced packaging technologies, integrating multiple chips with different processes and functions into a single package to form "system-in-package" or "chip-level system," becoming the mainstream path for continuously improving system performance. However, existing advanced packaging technologies all have certain drawbacks; for example, 2.5D / 3D silicon interposer technology is very expensive, limited by the maximum diameter of silicon wafers being only 300µm. The interposer size is difficult to increase, limiting the number and area of ​​chips that can be integrated. Fan-out packaging technology has a relatively low interconnect density, and the RDL linewidth / spacing is usually wider than the 2.5D silicon interposer, making it difficult to support the extremely high bandwidth interconnection requirements between chips. Furthermore, on large-size panels, the mismatch of thermal expansion coefficients between the chip, molding compound, and panel carrier can lead to severe warping, affecting manufacturing yield. On the other hand, embedded packaging technology embeds the chip inside the printed circuit board (PCB), but the PCB linewidth / spacing cannot meet the interconnection requirements of advanced chips, and it is usually only suitable for power devices with low I / O counts or simple chips.

[0003] In the context of advanced packaging technology iteration in the post-Moore era, glass substrates and glass cores have become the mainstream development direction for 2.5D / 3D heterogeneous integrated packaging due to their advantages such as low dielectric loss, low coefficient of thermal expansion, and mass production capability for large-size panels. However, they can only mount chips on the surface and still suffer from problems such as high cost, low integration, large size, and insufficient heat dissipation. Therefore, this invention provides a three-dimensional integrated packaging structure for a glass core TGV panel with embedded heterogeneous chips that can improve system performance, heat dissipation performance, and integration while reducing costs, as well as its preparation method. Summary of the Invention

[0004] To address the aforementioned problems in existing technologies, this invention aims to provide a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips and its fabrication method. This structure fully leverages the cost advantages of large-size glass panels, the performance advantages of glass materials, the vertical interconnect advantages of TGV, the density advantages of embedded packaging, and innovative thermal management technologies. It optimizes and resolves the shortcomings of current advanced packaging technologies in terms of high performance, high integration, low cost, and excellent heat dissipation, providing a novel system-level packaging solution with superior overall performance. This solution improves system performance, heat dissipation, and integration while reducing costs.

[0005] The technical solution adopted in this invention is as follows: The first technical solution provides a three-dimensional integrated packaging structure for a glass core TGV panel with embedded heterogeneous chips, including a glass core plate layer, redistribution layers respectively disposed on the upper and lower surfaces of the glass core plate layer, and a plurality of glass through holes penetrating the glass core plate layer. Each of the glass vias is formed into a conductive metal via through a metallization process, and the redistribution layers on the upper and lower surfaces of the glass core layer are vertically interconnected through a number of the metal vias. The glass core layer is provided with cavities prepared by a combination of laser cutting for roughing and wet finishing. The cavities include at least one of single-depth cavities, stepped-depth cavities, or vertically opposed cavities. Several active and / or passive components are embedded in the glass core layer along the Z-axis through the cavities. The active and passive components achieve horizontal signal transmission and vertical interconnection through upper and lower redistribution layers and corresponding metal vias, respectively. Solder balls are implanted in the bottom redistribution layer of the glass core layer to achieve electrical interconnection and mechanical connection with external circuits. The glass core plate layer is divided into a cavity avoidance area and a cavity bottom area. Conventional signal metal through holes are arranged in the cavity avoidance area, and heat dissipation metal through holes are densely arranged in the cavity bottom area.

[0006] In some embodiments, each of the glass vias has a high aspect ratio, and each of the glass vias is fabricated using a glass via forming process, which may be laser-induced etching, laser ablation, or deep reactive ion etching; the metallization process is to achieve metallization by bottom-up superfill electroplating after depositing a seed layer through ion physical vapor deposition. The laser cutting process is either an ultrashort pulse laser cutting process or an ultraviolet laser cutting process.

[0007] In some embodiments, a single-depth cavity is provided on the top of the glass core layer, and all metal through holes are provided in the cavity clearance area; The single-depth cavity is used to embed the active element, and the passive element is attached to the upper surface of the glass core layer or the bottom of the glass core layer.

[0008] In some embodiments, the bottom area of ​​the cavity is provided with a plurality of metal through holes that are densely or evenly distributed, thereby enabling direct connection between the back side of the active element and the lower redistribution layer at the bottom of the glass core layer.

[0009] In some embodiments, a stepped cavity is provided on the top of the glass core layer, the stepped cavity having at least two stepped grooves with different inner groove depths; The stepped cavity is used to adapt and embed active components of different thicknesses through shallow and deep grooves of different depths; or, the stepped cavity is used to adapt and embed active and passive components of different thicknesses through shallow and deep grooves of different depths. All metal vias are located in the cavity clearance area; or, multiple metal vias are also densely or evenly distributed in the bottom area of ​​the cavity, thereby enabling direct connection between the back of the active element and the passive element and the lower redistribution layer at the bottom of the glass core layer.

[0010] In some embodiments, a top cavity is provided at the top of the glass core layer, and a bottom cavity is provided at the bottom of the glass core layer, thereby forming a cavity with cavities respectively provided in an upper and lower opposing manner; All metal through holes are located in the cavity clearance area; the upper and lower opposed cavities are used to embed active components, and the passive components are surface-mounted on the top of the glass core layer; Alternatively, a metal via is provided between the top cavity and the bottom cavity. The top cavity is used to embed an active component, and the bottom cavity is used to embed a passive component. The passive component is connected to the active component through the metal via, and the active component is connected to the lower redistribution layer through the metal via.

[0011] The second technical solution provides a method for fabricating a three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips, including the following steps: Obtain packaging design parameters, determine glass core board specifications, and preset the specifications, quantity, and location parameters of TGV, double-sided RDLs, cavity, electronic components, and each add-on layer; Prepare double-sided glass core panels and perform pre-treatment cleaning; TGV hole forming and metallization; Preparation of double-sided RDLs; Cavities are fabricated on glass core boards; Embedded active and / or passive components, encapsulated, surface-mount passive components; or embedded active and passive components, encapsulated. Solder balls are implanted at the bottom of the glass core board to complete the encapsulation.

[0012] In some embodiments, the pretreatment of the prepared double-sided glass core board includes the following operations: selecting a large-size glass panel according to the packaging design parameters, cleaning and drying the glass panel to remove surface impurities and contaminants; selecting silicon, silicon dioxide or silicon nitride materials, and depositing an adhesion layer on the surface of the glass core board sequentially through a magnetron sputtering process.

[0013] In some embodiments, the TGV hole formation and metallization includes the following operations: preparing a high aspect ratio TGV using laser-induced etching, laser ablation, or deep reactive ion etching processes; and achieving metallization by bottom-up superfill electroplating after depositing a seed layer through ion physical vapor deposition. The preparation of double-sided RDLs includes the following operations: a seed layer is sputtered onto the surface of a glass core plate using a metal conductive material via magnetron sputtering; or, Ti or Cr material is first selected, and an adhesion layer is sequentially deposited onto the surface of the glass core plate using magnetron sputtering, followed by sputtering a seed layer onto the surface of the glass core plate using a metal conductive material via magnetron sputtering; the thickness of the seed layer is ≤1µm; if the linewidth / spacing specification of the RDLs is greater than or equal to 10 / 10µm, a subtractive method is used for preparation; if the linewidth / spacing specification of the RDLs is less than 10 / 10µm, a semi-additive method is used for preparation. The process of fabricating the cavity on the glass core board includes the following operations: the cavity is prepared by a combination of laser cutting for roughing and wet finishing; the glass core board is vaporized layer by layer using an ultra-short pulse laser or ultraviolet laser until the depth meets the packaging design parameter requirements; and then the bottom of the cavity is finished and smoothed using a wet etching process.

[0014] In some embodiments, the embedded active and / or passive components are encapsulated, and the passive components are surface-mounted; or, the embedded active and passive components, and the encapsulation, include the following operations: Active components are embedded into the cavity of the glass core board through surface mount and layering processes. After encapsulation with molding compound, passive components are surface mounted onto the upper or lower surface of the glass core board. Alternatively, active and passive components can be embedded into the cavity of the glass core board through surface mount and layering processes.

[0015] The beneficial effects of this invention are as follows: This paper presents a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips and its fabrication method. Addressing the common shortcomings of current advanced packaging technologies in terms of high performance, high integration, low cost, and excellent heat dissipation, this paper creatively integrates the cost advantages of large-size glass panels, the performance advantages of glass materials, the vertical interconnect advantages of TGV, the density advantages of embedded packaging, and innovative thermal management technology to provide a novel, higher-performance system-level packaging solution. I. Performance Enhancement: The combination of high-density RDL and TGV provides ultra-fine linewidth / spacing interconnect capabilities comparable to silicon interposers, far exceeding the interconnect density of PCB embedded solutions, supporting high-bandwidth communication between HBM and GPU chips; the glass core material is a natural high-frequency insulator, with lower signal loss and less crosstalk, ensuring signal integrity in high-frequency applications such as 5G / millimeter wave; the innovative "TGV + back-integrated heat dissipation structure" forms a vertical and efficient heat dissipation path, directly dissipating the heat of the embedded high-power chip to the outside of the package.

[0016] II. Cost Advantages: The cost of large-size glass panels is far lower than that of semiconductor-grade silicon wafers; by using large-size glass panels (currently, the industry's mature size can reach 510mm x 515mm or larger), the number of chips that can be packaged at one time can be doubled, reducing the packaging cost of a single chip; it eliminates the physical limitation of silicon wafer diameter (such as 300mm) on the size of the interposer, and can package larger-size chips or integrate more wafers.

[0017] 3. High-density integration: The “chip embedded” structure embeds the chip inside the panel in the Z-axis direction, rather than simply placing it on the surface, achieving a thinner and more compact package that meets the stringent size requirements of mobile devices, wearable devices, etc. It supports the integration of chips with different process nodes (such as 7nm CPU, 28nm RF chip), different materials (Si, GaN, SiC), and IPD (integrated passive device) into the same glass panel.

[0018] IV. High Reliability: The coefficient of thermal expansion of glass can be adjusted through composition formulation to more closely resemble that of silicon chips. This better CTE matching significantly reduces stress caused by thermal expansion and contraction during temperature cycling, improving the long-term reliability of solder joints, TGV, and the chip itself. The rigidity and thermal stability of glass are superior to organic substrates and molding compounds, allowing for more effective control of overall warpage and improved manufacturing yield during large-size panel manufacturing. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating the process flow of the fabrication method for the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to the present invention. Figures 2-3A schematic diagram of the structure of Embodiment 1, which serves as the basic technical solution of this invention; Figures 4-5 This is a schematic diagram of the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to Embodiment 2 of the present invention. Figures 6-7 This is a schematic diagram of the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to Embodiment 3 of the present invention; Figures 8-9 This is a schematic diagram of the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to Embodiment 4 of the present invention. Figure 10 This is a schematic diagram of the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to Embodiment 5 of the present invention. Figures 11-12 This is a schematic diagram of the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to Embodiment 6 of the present invention; Figures 13-14 This is a schematic diagram of the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to Embodiment 7 of the present invention. Figures 15-16 This is a schematic diagram of the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips in Embodiment 8 of the present invention. Figures 17-18 This is a schematic diagram of the three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to Embodiment 9 of the present invention. Detailed Implementation

[0020] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "vertical," "horizontal," "left," "right," "inner," "outer," and similar expressions used in this specification are for illustrative purposes only. In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of indicated technical features. Thus, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0021] Furthermore, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections via an intermediate medium, or internal communication between two components. All technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0022] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] Please refer to Figures 1 to 18 As shown, this invention provides a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips and its fabrication method. The analysis of existing technical solutions is as follows: With the rapid development of chip technology, the demands on chip computing power, bandwidth, and energy efficiency are increasing exponentially. The traditional "Moore's Law," which improves performance by shrinking transistor size, is facing significant challenges due to physical limitations and economic costs. The industry is turning its attention to advanced packaging technologies, integrating multiple chips with different processes and functions into a single package to form "system-in-package" or "chip-level system," becoming the mainstream path for continuously improving system performance. Several mainstream advanced packaging technologies currently face key challenges. For example, 2.5D / 3D silicon interposer technology is very expensive, and due to the silicon wafer diameter (currently 300mm), the size of the interposer is difficult to increase, limiting the number and area of ​​chips that can be integrated. Fan-out packaging technology has a relatively low interconnect density, and the RDL linewidth / spacing is usually wider than that of 2.5D silicon interposers, making it difficult to support the extremely high bandwidth interconnection requirements between chips. Furthermore, on large-size panels, the mismatch in thermal expansion coefficients between the chip, molding compound, and panel carrier can lead to severe warping, affecting manufacturing yield. Traditional embedded packaging technology embeds the chip inside the printed circuit board (PCB), but the PCB linewidth / spacing is too large to meet the interconnection requirements of advanced chips, and it is usually only used for power devices with low I / O counts or simple chips. The "Heterogeneous Chip Embedded 3D Integration Based on Glass Core TGV Panel" proposed in this invention addresses the common shortcomings of current advanced packaging technologies in terms of high performance, high integration, low cost, and excellent heat dissipation. It creatively integrates the cost advantages of large-size glass panels, the performance advantages of glass materials, the vertical interconnection advantages of TGV, the density advantages of embedded packaging, and innovative thermal management technology, providing a brand-new system-level packaging solution with superior overall performance for further technological development.

[0024] To address the common shortcomings of current advanced packaging technologies in terms of high performance, high integration, low cost, and excellent heat dissipation, this invention proposes a "heterogeneous chip embedded three-dimensional integration based on glass core TGV panel" solution. This solution fully integrates the cost advantages of large-size glass panels, the performance advantages of glass materials, the vertical interconnect advantages of TGV, the density advantages of embedded packaging, and innovative thermal management technologies to provide a brand-new system-level packaging solution with superior overall performance.

[0025] Therefore, in order to solve the above-mentioned technical problems, the present invention has conceived and planned the following technical solution in the early stage: The first technical solution provides a three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips. The main structure is a glass core, redistribution layers (RDLs) respectively disposed on the upper and lower surfaces of the glass core, and a number of glass vias (TGVs) penetrating the glass core. The number of glass vias (TGVs) are formed into a number of conductive metal vias through a metallization process, and the upper and lower redistribution layers (RDLs) are vertically interconnected through the number of metal vias.

[0026] Each glass via has a high aspect ratio and is fabricated using a glass via forming process, which can be combined with laser-induced etching, laser ablation, or deep reactive ion etching. The metallization process can first be achieved by depositing a seed layer through ion physical vapor deposition, followed by bottom-up superfill electroplating.

[0027] Several cavities are arranged along the Z-axis on the glass core layer. The cavities include at least one of single-depth cavities, stepped-depth cavities, or vertically opposed cavities. Several electronic components, including active and / or passive components, are embedded in the glass core layer along the Z-axis through the cavities. The active and / or passive components achieve horizontal signal transmission and vertical interconnection through upper and lower redistribution layers and corresponding metal vias. Solder balls are planted in the redistribution layer at the bottom of the glass core layer, and electrical connection with external circuits is achieved through the placement of solder balls. The cavities are prepared using a combination of laser cutting for roughing grooves and wet finishing. The laser cutting process is either ultra-short pulse laser cutting or ultraviolet laser cutting. The glass core layer is divided into a cavity avoidance area and a cavity bottom area. Conventional signal metal vias are arranged in the cavity avoidance area, and heat dissipation metal vias are densely arranged in the cavity bottom area.

[0028] Specifically, a single-depth cavity can be set at the top of the glass core board layer. All metal vias are located outside the area of ​​the glass core board layer corresponding to the cavity, i.e., in the cavity clearance area. Electronic components are divided into active components and passive components. Chips and functional devices are active components, while resistors and capacitors are passive components. Active components can be embedded in the single-depth cavity, and passive components can be surface-mounted on the upper surface or bottom of the glass core board layer using conventional back-end packaging (SMT) technology. Solder balls are placed on the lower redistribution layer at the bottom of the glass core board layer, which enables electrical interconnection and mechanical connection with external circuit boards. Multiple metal vias can also be densely or evenly distributed in the area of ​​the glass core board layer corresponding to the bottom of the cavity, i.e., the bottom area of ​​the cavity, to achieve direct connection between the back of the active components and the lower redistribution layer at the bottom of the glass core board layer.

[0029] Alternatively, a stepped cavity can be provided at the top of the glass core layer, with at least two stepped grooves of different inner depths. The stepped cavity allows for the embedding of active components of different thicknesses using shallow and deep grooves of varying depths. Alternatively, the stepped cavity allows for the embedding of active and passive components of different thicknesses using shallow and deep grooves of varying depths. The metal vias are positioned such that all vias are located outside the area of ​​the glass core layer corresponding to the stepped cavity, i.e., the cavity clearance area. Alternatively, multiple metal vias can be densely or evenly distributed in the area of ​​the glass core layer corresponding to the bottom of the stepped cavity, i.e., the bottom area of ​​the cavity, thereby enabling direct connection between the back of the active and passive components and the lower redistribution layer at the bottom of the glass core layer. Similarly, solder balls are implanted on the lower redistribution layer at the bottom of the glass core layer, enabling electrical interconnection and mechanical connection with the external circuit board.

[0030] Alternatively, a top cavity can be provided at the top of the glass core layer, and bottom cavities can be provided at the bottom and bottom of the glass core layer, thus forming an upper and lower opposed cavity. Solder balls are implanted on the lower redistribution layer at the bottom of the glass core layer, which can also achieve electrical interconnection and mechanical connection with the external circuit board. All metal vias are located outside the area on the glass core layer corresponding to the stepped cavity, i.e., the cavity clearance area. Active components can be embedded in the upper and lower opposed cavities, and passive components can be mounted on the top surface of the glass core layer. The active components in the top and bottom cavities are connected to the upper and lower redistribution layers through metal vias, and the passive components are connected to the active components in the upper surface cavity through add-on wiring. Alternatively, metal vias can also be provided between the top and bottom cavities of the glass core layer. Active components can be embedded in the top cavity of the glass core layer, and passive components can be embedded in the bottom cavity of the glass core layer. The passive components are connected to the active components through metal vias, and the active components are connected to the lower redistribution layer through metal vias.

[0031] The second technical solution provides a method for fabricating a three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips, including the following steps: S101, obtain packaging design parameters, determine glass core board specifications, including preset specifications, quantity, and location parameters of TGV, double-sided RDLs, cavity, electronic components, and each add-on layer; specifically, follow the conventional design process and design technical requirements in the semiconductor packaging field.

[0032] S102, Double-sided glass core board preparation, pre-treatment and cleaning; Select a large-size glass panel according to the packaging design parameters. Clean and dry the glass panel to remove surface impurities and contaminants. To improve the adhesion between the metal layer and the glass, a glass surface activation / adhesive layer deposition step can be selected. A very thin adhesive layer can be deposited first, such as silicon, silicon dioxide, or silicon nitride. Using silicon, silicon dioxide, or silicon nitride, a very thin adhesive layer is sequentially deposited on the surface of the glass core board using a magnetron sputtering process.

[0033] S103, TGV pore forming and metallization; High aspect ratio TGVs are prepared by laser-induced etching and laser ablation. To further pursue vertical apertures, deep reactive ion etching can also be used to prepare high aspect ratio TGVs. After seeding with ion physical vapor deposition, metallization is achieved by bottom-up superfill electroplating.

[0034] That is, the high aspect ratio metal via TGV metallization technology can be achieved by using an iPVD seed layer combined with bottom-up super-fill electroplating technology.

[0035] S104, for preparing double-sided RDLs; A seed layer is sputtered onto the surface of a glass core substrate using a conductive metal material via magnetron sputtering; alternatively, Ti or Cr material is first used to deposit an adhesion layer onto the surface of the glass core substrate via magnetron sputtering, followed by sputtering a seed layer onto the surface of the glass core substrate using a conductive metal material via magnetron sputtering. Copper (Cu) is the preferred conductive material, and the thickness of the seed layer is ≤1µm. If the linewidth / spacing of the RDLs is greater than or equal to 10 / 10µm, a subtractive method is used, i.e., the process is executed in the following order: glass substrate preparation and cleaning → glass surface activation / adhesion layer deposition → seed layer deposition → photoresist coating and patterning → pattern electroplating → photoresist stripping → seed layer etching.

[0036] If the linewidth / spacing of RDLs is less than 10 / 10um, a semi-additive method is used for fabrication, which involves the following process sequence: glass substrate preparation and cleaning → seed layer deposition → photoresist coating and patterning → pattern electroplating → surface leveling → photoresist stripping.

[0037] To ensure a uniform, dense, and strongly adhered seed layer, a magnetron sputtering process can be used to sequentially deposit an adhesion layer (Ti, Cr, etc.) and a conductive seed layer (Cu, etc.) on the entire glass surface.

[0038] S105, machining cavities on glass core boards; The cavity is prepared using a combination of laser cutting for roughing and wet finishing. The glass core is vaporized layer by layer using an ultra-short pulse laser or ultraviolet laser until the depth meets the packaging design parameters. Then, the bottom of the cavity is finished and smoothed using a wet etching process.

[0039] This invention employs a combination of "laser roughing and wet finishing" processes. It uses short pulses (picosecond or femtosecond lasers) or ultraviolet lasers, and controls the laser energy, pulse number, and scanning path to vaporize the glass layer by layer until the designed target depth is reached. Finally, wet etching is used to perform the final finishing and smoothing of the bottom of the cavity.

[0040] S106, embedding active and / or passive components, encapsulating, surface mount passive components; or, embedding active and passive components, encapsulating; Active components are embedded into the cavity of a glass core board through surface mount and layer build-up processes. After encapsulation with molding compound, passive components are surface mounted onto the upper or lower surface of the glass core board. In other words, using industry-standard surface mount and layer build-up processes, active components are embedded inside the glass core board and encapsulated with molding compound (FR4, BT, ABF, etc.). After the circuit is completed, passive components (resistors, motors, etc.) are surface mounted using conventional back-end SMT.

[0041] Alternatively, active and passive components can be embedded into the cavity of the glass core board through surface mount and layering processes; that is, using industry-standard surface mount and layering processes, the active and passive components are embedded inside the glass core board, and then encapsulated with molding materials (such as FR4, BT, ABF, etc.).

[0042] S107, solder balls are implanted at the bottom of the glass core board to complete the encapsulation.

[0043] This invention provides a three-dimensional integrated packaging structure and fabrication method for a glass-core TGV panel with embedded heterogeneous chips. Addressing the common shortcomings of current advanced packaging technologies in terms of high performance, high integration, low cost, and excellent heat dissipation, this invention creatively integrates the cost advantages of large-size glass panels, the performance advantages of glass materials, the vertical interconnect advantages of TGV, the density advantages of embedded packaging, and innovative thermal management technology. This provides a novel, higher-performance system-in-package solution for further technological development. I. Performance Enhancement: The combination of high-density RDL and TGV provides ultra-fine linewidth / spacing interconnect capabilities comparable to silicon interposers, far exceeding the interconnect density of PCB embedded solutions, supporting high-bandwidth communication between HBM and GPU chips; the glass core material is a natural high-frequency insulator, with lower signal loss and less crosstalk, ensuring signal integrity in high-frequency applications such as 5G / millimeter wave; the innovative "TGV + back-integrated heat dissipation structure" forms a vertical and efficient heat dissipation path, directly dissipating the heat of the embedded high-power chip to the outside of the package.

[0044] II. Cost Advantages: The cost of large-size glass panels is far lower than that of semiconductor-grade silicon wafers; by using large-size glass panels (currently, the industry's mature size can reach 510mm x 515mm or larger), the number of chips that can be packaged at one time can be doubled, reducing the packaging cost of a single chip; it eliminates the physical limitation of silicon wafer diameter (such as 300mm) on the size of the interposer, and can package larger-size chips or integrate more wafers.

[0045] 3. High-density integration: The “chip embedded” structure embeds the chip inside the panel in the Z-axis direction, rather than simply placing it on the surface, achieving a thinner and more compact package that meets the stringent size requirements of mobile devices, wearable devices, etc. It supports the integration of chips with different process nodes (such as 7nm CPU, 28nm RF chip), different materials (Si, GaN, SiC), and IPD (integrated passive device) into the same glass panel.

[0046] IV. High Reliability: The coefficient of thermal expansion of glass can be adjusted through composition formulation to more closely resemble that of silicon chips. This better CTE matching significantly reduces stress caused by thermal expansion and contraction during temperature cycling, improving the long-term reliability of solder joints, TGV, and the chip itself. The rigidity and thermal stability of glass are superior to organic substrates and molding compounds, allowing for more effective control of overall warpage and improved manufacturing yield during large-size panel manufacturing.

[0047] Example 1: Example 1 Figures 2-3 As shown, the basic structure is provided according to the conventional glass core TGV substrate combined with surface mount technology; taking a simple double-sided glass substrate as the glass core layer as an example ( Figure 2 The specific structure consists of a glass core, upper and lower redistribution layers (RDLs), high aspect ratio glass vias (TGVs) penetrating the glass core, active components such as the main chip and functional devices, and passive components such as resistors and capacitors. Each glass via has a high aspect ratio, and several glass vias (TGVs) are metallized to form several conductive metal vias. The upper and lower redistribution layers (RDLs) are vertically interconnected through several metal vias. The active and passive components are surface-mounted on the upper surface of the glass core using conventional surface mount technology (SMT) and connected to the upper redistribution layer. The active and passive components are vertically interconnected through the upper redistribution layer and the conductive metal vias to the lower redistribution layer. Solder balls are implanted at the bottom of the glass core to achieve electrical interconnection and mechanical connection with the external circuit board.

[0048] The specific operation process of Example 1 is as follows: First, based on the chip function and system requirements of the packaged product, obtain the packaging design parameters, determine the glass core board specifications, and pre-set the specifications, quantity, and location parameters of the TGV, double-sided RDLs, and electronic components. Then, follow the standard design process and technical requirements in the semiconductor packaging field, as detailed below: 1. Determine the heterogeneous integration solution based on chip functions and system requirements. Based on the number, size, thickness, power consumption, and I / O distribution of the active chips to be integrated, as well as the type and layout requirements of the passive components, the chip arrangement, stacking relationship, and heterogeneous integration architecture are determined.

[0049] 2. Determine the structural parameters of the glass core board. Select the thickness, dimensions, and coefficient of thermal expansion of the glass core plate, determine the aperture, aspect ratio, arrangement density, and distribution area of ​​the TGV, and distinguish between the TGV for signal transmission and the TGV for heat dissipation enhancement.

[0050] 3. Design of upper and lower rewiring layers RDLs Based on the chip's I / O ports, TGV locations, and external solder ball layout, complete the design of the trace routing, trace width / spacing, and number of layers for the upper and lower surface RDLs, and determine whether to use a subtractive or semi-additive process.

[0051] 4. Interconnection and heat dissipation design Plan the interconnection between the chip and RDLs and TGV, and design the vertical heat dissipation path; 5. External Interface Design Determine the number, spacing, and arrangement of the bottom BGA solder balls to achieve electrical interface matching between the package and the external application system.

[0052] 6. Output complete design data Based on the above design results, a complete set of packaging design documents is output, including glass core board dimensions, TGV parameters, RDL graphics, chip coordinates, molding thickness, and solder ball parameters, serving as the basis for subsequent fabrication processes. The order of TGV followed by RDL is determined according to the respective performance requirements of TGV and RDL and the impact of the processing technology. Because glass drilling, electroplating, and CMP are all high-temperature / high-energy processes, after TGV copper plating, a copper ring will protrude from the glass surface, creating an uneven surface. CMP is needed to smooth the TGV surface after copper plating, making it mirror-like and preparing it for subsequent RDL wiring. If TGV is done later, the already fabricated RDL lines will be burned, damaged, or contaminated. RDL must be photolithographically applied to a flat surface; if RDL is applied first and then TGV is done, the drilling vibration and high temperature will cause the RDL to break, shift, or warp, resulting in extremely low yield. CMP is a critical prerequisite; after TGV, it must be CMP-flattened before photolithography can be applied for RDL. Therefore, the processing sequence was determined as follows: TGV hole forming → TGV metallization → double-sided RDL fabrication → surface mounting → solder ball placement.

[0053] Simultaneously, the specific processing technology is determined based on the linewidth / spacing of the upper and lower rewiring layers (RDLs). If the linewidth / spacing specification of the RDLs is greater than or equal to 10 / 10µm, a subtractive fabrication method is used, and the processing sequence is as follows: Glass substrate preparation and cleaning → Glass surface activation / adhesive layer deposition → Seed layer deposition → Photoresist coating and patterning → Pattern electroplating → Photoresist stripping → Seed layer etching; If the linewidth / spacing specification of RDLs is less than 10 / 10µm, then a semi-additive method is used for preparation, and the processing sequence is as follows: Glass substrate preparation and cleaning → Seed layer deposition → Photoresist coating and patterning → Pattern electroplating → Surface leveling → Photoresist stripping.

[0054] The second step is to prepare double-sided glass core boards and perform pre-treatment and cleaning. Select a large-size glass panel according to the packaging design parameters. Clean and dry the glass panel to remove surface impurities and contaminants. The glass surface activation / adhesion layer deposition step is to improve the adhesion between the metal layer and the glass. A very thin adhesion layer can be deposited first, such as silicon, silicon dioxide, or silicon nitride. Using silicon, silicon dioxide, or silicon nitride, a very thin adhesion layer is sequentially deposited on the surface of the glass core board through a magnetron sputtering process.

[0055] The third step is TGV hole formation and metallization; High aspect ratio vias (TGVs) are fabricated using laser-induced etching (LAI) and laser ablation. To further pursue vertical via shapes, deep reactive ion etching (DRIE) can also be used to fabricate high aspect ratio TGVs. After a seed layer is deposited by ion physical vapor deposition (IPV), metallization is achieved using bottom-up superfill electroplating. In other words, the metallization technology for high aspect ratio metal vias (TGVs) combines an iPVD seed layer with bottom-up superfill electroplating.

[0056] The fourth step is to prepare double-sided RDLs; The specific processing technology is determined based on the line width / spacing of the upper and lower rewiring layers (RDLs).

[0057] If the linewidth / spacing of RDLs is greater than or equal to 10 / 10um, then the subtractive method is used for fabrication, which is to follow the process sequence of glass substrate preparation and cleaning → glass surface activation / adhesive layer deposition → seed layer deposition → photoresist coating and patterning → pattern electroplating → photoresist stripping → seed layer etching.

[0058] If the linewidth / spacing of RDLs is less than 10 / 10um, a semi-additive method is used for fabrication, which involves the following process sequence: glass substrate preparation and cleaning → seed layer deposition → photoresist coating and patterning → pattern electroplating → surface leveling → photoresist stripping.

[0059] The glass surface activation / adhesion layer deposition step is to improve the adhesion between the metal layer and the glass by first depositing a very thin adhesion layer (such as silicon, silicon dioxide, or silicon nitride).

[0060] To ensure a uniform, dense, and strongly adhered seed layer, the seed layer deposition step can be performed by sequentially depositing an adhesion layer (Ti, Cr, etc.) and a conductive seed layer (Cu, etc.) on the entire glass surface using a magnetron sputtering process.

[0061] Alternatively, the seed layer deposition step can be performed by magnetron sputtering to deposit a conductive seed layer (such as Cu) on the entire glass surface, with a seed layer thickness ≤1µm.

[0062] Preferably, in the photoresist coating and patterning steps, the photoresist thickness is equal to the thickness of the target circuit; Preferably, in the pattern electroplating step, the electroplating thickness is greater than or equal to the target line thickness; Preferably, chemical mechanical polishing (CMP) technology can be used in the surface leveling step.

[0063] Next, in the fifth step, surface mount active and passive components; Traditional back-end SMT involves surface mounting active components (chips, functional devices, etc.) and passive components (resistors, motors, etc.).

[0064] The sixth step is to implant solder balls (ball grid array solder balls) on the bottom of the glass substrate to complete the encapsulation.

[0065] Example 1 uses a simple double-sided glass substrate ( Figure 2 Using a glass substrate as a carrier, active components (chips, functional devices, etc.) and passive components (resistors, motors, etc.) are surface-mounted according to conventional back-end SMT methods. Solder balls are placed on the bottom of the glass substrate. An example of a package is shown below. Figure 3 ).

[0066] Example 2: Example 2 Figures 4-5 As shown, addressing the urgent needs of current advanced packaging technologies in terms of high-density integration, reduced package size, and high heat dissipation, this paper creatively embeds heterogeneous chip components in a glass core board. It fully integrates and utilizes the cost advantages of large-size glass panels, the performance advantages of glass materials, the vertical interconnection advantages of TGV, the density advantages of embedded packaging, and innovative thermal management technologies to provide a new system-level packaging solution with superior overall performance. This results in a three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips and its fabrication method.

[0067] Example 2 is based on the glass core TGV substrate combined with surface mount technology provided in Example 1. It uses a large-area glass substrate as the glass core layer and embeds active components in a single cavity on the glass core layer. The specific steps are as follows: First, based on the chip function and system requirements of the packaged product, obtain the packaging design parameters, determine the glass core board specifications, and pre-set the specifications, quantity, and location parameters of TGV, double-sided RDLs, cavity, electronic components, and each add-on layer. Then, follow the standard design process and technical requirements in the semiconductor packaging field, as detailed below: 1. Determine the heterogeneous integration solution based on chip functions and system requirements. Based on the number, size, thickness, power consumption, and I / O distribution of the active chips to be integrated, as well as the type and layout requirements of the passive components, the chip arrangement, stacking relationship, and heterogeneous integration architecture are determined.

[0068] 2. Determine the structural parameters of the glass core board. Select the thickness, dimensions, and coefficient of thermal expansion of the glass core plate, determine the aperture, aspect ratio, arrangement density, and distribution area of ​​the TGV, and distinguish between the TGV for signal transmission and the TGV for heat dissipation enhancement.

[0069] 3. Cavity structure design Based on chip thickness, assembly gaps, and heat dissipation requirements, the number, location, depth, and outline dimensions of the cavities are designed. For stepped cavities, stacked cavities, or double-sided cavities (upper and lower opposed cavities) structures, the depth difference and relative position of each level of cavity are determined. In Example 2, the cavity structure design scheme involves setting a single-depth cavity on the top of the glass core layer.

[0070] 4. Rerouting Layer (RDL) Design Based on the chip I / O ports, TGV locations, and external solder ball layout, complete the design of the line routing, line width / spacing, and number of layers of the upper and lower surface RDLs, and determine whether to use a subtractive or semi-additive process.

[0071] 5. Interconnection and heat dissipation design Plan the interconnection relationship between the chip and RDLs and TGVs, and design a vertical heat dissipation path; for high-power chips, design an encrypted TGV array in the corresponding area at the bottom of the cavity to optimize heat dissipation efficiency.

[0072] 6. External Interface Design Determine the number, spacing, and arrangement of the bottom BGA solder balls to achieve electrical interface matching between the package and the external application system.

[0073] 7. Output complete design data Based on the above design results, a complete set of packaging design documents is output, including glass core board dimensions, TGV parameters, cavity processing coordinates and depth, RDL graphics, chip coordinates, molding thickness, and solder ball parameters, serving as the basis for subsequent fabrication processes. Similarly, the order of TGV followed by RDL is determined first, and then the cavity processing sequence is considered. RDL must be processed before the cavity. RDL requires a completely flat glass surface for photolithography and electroplating. If the cavity is cut first, there will be steps and grooves on the glass surface, making it impossible to fabricate the RDL, resulting in broken circuits and distorted patterns. The cavity process, on the other hand, simply involves "removing glass material," and the final processing will not damage the preceding TGV and RDL, while also precisely avoiding circuits and glass vias.

[0074] The second step is to prepare double-sided glass core boards and perform pre-treatment and cleaning. A large-size glass panel is selected as the glass core board according to the packaging design parameters. The glass panel is cleaned and dried to remove surface impurities and contaminants. Optionally, the glass surface activation / adhesion layer deposition step is to improve the adhesion between the metal layer and the glass. A very thin adhesion layer can be deposited first, such as silicon, silicon dioxide, or silicon nitride. Using silicon, silicon dioxide, or silicon nitride, a very thin adhesion layer is sequentially deposited on the surface of the glass core board through a magnetron sputtering process.

[0075] The third step is TGV hole formation and metallization; High aspect ratio vias (TGVs) are fabricated by laser-induced etching (LAI) and laser ablation through the glass core. To further pursue vertical via shapes, deep reactive ion etching (DRIE) can also be used to fabricate high aspect ratio TGVs. After a seed layer is deposited via ion physical vapor deposition (IPV), metallization is achieved using bottom-up superfill electroplating. In other words, the metallization technology for high aspect ratio metal vias (TGVs) combines an iPVD seed layer with bottom-up superfill electroplating. All metal vias are located outside the cavity area of ​​the glass core layer; that is, there are no TGVs in the cavity area.

[0076] The fourth step is to prepare double-sided RDLs; The specific manufacturing process is determined based on the line width / spacing of the upper and lower rewiring layers (RDLs).

[0077] If the linewidth / spacing of RDLs is greater than or equal to 10 / 10um, then the subtractive method is used for fabrication, which is to follow the process sequence of glass substrate preparation and cleaning → glass surface activation / adhesive layer deposition → seed layer deposition → photoresist coating and patterning → pattern electroplating → photoresist stripping → seed layer etching.

[0078] If the linewidth / spacing of RDLs is less than 10 / 10um, a semi-additive method is used for fabrication, which involves the following process sequence: glass substrate preparation and cleaning → seed layer deposition → photoresist coating and patterning → pattern electroplating → surface leveling → photoresist stripping.

[0079] The glass surface activation / adhesion layer deposition step is to improve the adhesion between the metal layer and the glass by first depositing a very thin adhesion layer (such as silicon, silicon dioxide, or silicon nitride).

[0080] To ensure a uniform, dense, and strongly adhered seed layer, the seed layer deposition step can be performed by sequentially depositing an adhesion layer (Ti, Cr, etc.) and a conductive seed layer (Cu, etc.) on the entire glass surface using a magnetron sputtering process.

[0081] Alternatively, the seed layer deposition step can be performed by magnetron sputtering to deposit a conductive seed layer (such as Cu) on the entire glass surface, with a seed layer thickness ≤1µm.

[0082] Preferably, in the photoresist coating and patterning steps, the photoresist thickness is equal to the thickness of the target circuit; Preferably, in the pattern electroplating step, the electroplating thickness is greater than or equal to the target line thickness; Preferably, chemical mechanical polishing (CMP) technology can be used in the surface leveling step.

[0083] Next, in the fifth step, the cavity is fabricated on the glass core board; Using the length and width of the glass core as the X and Y directions and the thickness of the glass core as the Z direction, a single-depth cavity is prepared on the upper surface of the glass core along the Z direction using a combination of laser cutting for roughing and wet finishing. First, the glass core is vaporized layer by layer using an ultra-short pulse laser or ultraviolet laser until the depth meets the packaging design parameters. Then, the bottom of the cavity is finished and smoothed using a wet etching process.

[0084] Example 2 employs a combination of "laser roughing and wet finishing" processes. Short pulses (picosecond or femtosecond lasers) or ultraviolet lasers are used. By controlling the laser energy, pulse number, and scanning path, the glass is vaporized layer by layer until the target depth is reached. The glass is vaporized and removed layer by layer according to the designed position and depth to form the rough outline of the cavity. Then, wet etching is used to perform the final finishing and smoothing of the bottom of the cavity. That is, the bottom and sidewalls of the cavity are finished and smoothed by wet etching.

[0085] Next, in the sixth step, embed and encapsulate the active components, and then surface mount the passive components. Active components are embedded into the cavity of a glass core board using industry-standard surface mount and layer-addition processes. The cavity and components are encapsulated using molding materials such as FR4, BT, or ABF. Electrical interconnection between the active components and TGV / RDLs is achieved through layer-addition RDLs. After the circuit is implemented, passive components are surface mounted onto the upper surface of the glass core board using conventional back-end SMT. In other words, active components are embedded inside the glass core board using industry-standard surface mount and layer-addition processes, encapsulated using molding materials (such as FR4, BT, or ABF), and passive components (resistors, motors, etc.) are surface mounted using conventional back-end SMT after the circuit is implemented. Short-path interconnection between passive components and active components is achieved through layer-addition RDLs.

[0086] The seventh step is to implant solder balls (ball grid array solder balls) at the bottom of the glass core board to complete the encapsulation and realize the electrical and mechanical connection between the encapsulation and the external circuit.

[0087] Example 2 specifically implements a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips, such as... Figure 4 As shown, a single-depth cavity is provided on the top of the glass core layer to embed active components, and passive components are surface-mounted on the upper surface of the glass core layer. An example of the package is... Figure 5 As shown, relative to Figure 3 The encapsulation structure, Figure 5 In the package structure, the interconnection paths between active and passive components are shorter. Figure 5 The volume of the package is further reduced in the X and Y directions.

[0088] Example 3: Example 3, based on Example 2, implements another three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips and its fabrication method. According to different task requirements, a second TGV is densely arranged at the bottom of a single-depth cavity. After metallization, it forms a second metal via. The specific applications of the second metal via are as follows: for signal transmission, for appropriate sparse distribution and heat dissipation, for dense and concentrated layout, etc., according to design requirements.

[0089] The first step also pre-determines the position, number, height, and size of the second metal via. In the third step, according to the pre-determined parameters, a second TGV is densely fabricated on the glass core plate at the position corresponding to the bottom of the single-depth cavity using laser-induced etching, laser ablation, or deep reactive ion etching, followed by metallization. In the fifth step, while processing the single-depth cavity on the glass core plate, the cavity processing depth is controlled to just expose the bottom TGV metal end face without damaging the TGV metal pillar, thus forming the second metal via. Figure 6As shown, the number and density of the second metal vias can be designed according to different task requirements; the second metal vias directly contact the back of the active component to form a vertical heat dissipation path, such as... Figure 7 As shown, multiple second metal vias are also densely arranged in the area of ​​the glass core layer corresponding to the bottom of the cavity, thereby realizing direct connection between the back of the active component and the lower rewiring layer at the bottom of the glass core layer.

[0090] Example 3 illustrates a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips. The package example is... Figure 7 As shown, relative to Figure 3 The encapsulation structure, Figure 7 In the package structure, the interconnection paths between active and passive components are shorter. Figure 7 The package size is further reduced in the X and Y directions; at the same time... Figure 7 It also achieves an efficient vertical heat dissipation path, further improving heat dissipation. Based on different task requirements, TGVs are densely arranged at the bottom of the cavity to form second metal vias. The number and density of these second metal vias are designed according to different task requirements, satisfying various task needs, such as signal transmission, appropriate sparse placement for heat conduction and dissipation, or dense centralized placement, etc.

[0091] Example 4: Example 4, based on Example 3, implements another three-dimensional integrated packaging structure for a glass core TGV panel with embedded heterogeneous chips and its fabrication method. To further improve heat dissipation, according to design requirements, TGVs are uniformly distributed at the bottom of the single-depth cavity, forming a second metal via after metallization. Figure 8 As shown, the second metal via directly contacts the back of the active component, forming a vertical heat dissipation path, as... Figure 9 As shown, multiple second metal vias are also evenly distributed in the area of ​​the glass core layer corresponding to the bottom of the cavity, thereby enabling direct connection between the back of the active component and the lower rewiring layer at the bottom of the glass core layer.

[0092] Example 4 illustrates a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips. The package example is... Figure 9 As shown, relative to Figure 3 The encapsulation structure, Figure 9 In the package structure, the interconnection paths between active and passive components are shorter. Figure 9 The package size is further reduced in the X and Y directions; at the same time... Figure 9This also achieves an efficient vertical heat dissipation path, further improving heat dissipation. Second metal vias are evenly distributed at the bottom of the cavity according to different task requirements, and the number of these vias is designed to meet various task needs, such as signal transmission, appropriate sparse placement for heat conduction and dissipation, or dense centralized placement, etc.

[0093] Example 5: Example 5, based on Example 4, implements another three-dimensional integrated packaging structure for a glass core TGV panel with embedded heterogeneous chips and its fabrication method. Matching the TGV conductivity at the bottom of the Cavity, passive components are mounted on the bottom of the glass core board structure. Simultaneously, solder balls (ball grid array solder balls) are also implanted on the bottom of the glass core board to complete the packaging, achieving electrical and mechanical connection between the package and external circuitry. Note that the height of the passive components protruding downwards from the bottom of the glass core board after mounting is less than the height of the solder balls (ball grid array solder balls) protruding downwards from the bottom of the glass core board.

[0094] Example 5 illustrates a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips. The package example is... Figure 10 As shown, relative to Figure 3 The encapsulation structure, Figure 10 In the package structure, the interconnection paths between active and passive components are shorter. Figure 10 The package size is further reduced in the X, Y, and Z directions; at the same time... Figure 10 This also achieves an efficient vertical heat dissipation path, further improving heat dissipation. TGVs are evenly distributed at the bottom of the cavity according to different task requirements, and the number of TGVs is designed according to different task requirements to meet various task needs, such as signal transmission, appropriate sparse and heat conduction for heat dissipation, and dense centralized layout, etc.

[0095] Example 6: Example 6, based on Example 2, implements another three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips and its fabrication method. A stepped cavity is fabricated on the top of the glass core layer using a combination of laser roughing and wet finishing processes. The stepped cavity has two stepped grooves with different inner groove depths. Active components of different thicknesses are embedded in the shallow and deep grooves of the stepped cavity. As an extension technology, active and passive components of different thicknesses can also be embedded in the shallow and deep grooves of the stepped cavity, respectively.

[0096] Based on the above embodiment two, in the fifth step, short pulses (picosecond or femtosecond lasers) or ultraviolet lasers are first used. By controlling the laser energy, pulse number, and scanning path, the glass is vaporized layer by layer until the designed target depth of the stepped cavity is reached. Then, wet etching is used for the final finishing and smoothing of the cavity bottom. The bottom and sidewalls of the cavity are refined and smoothed by wet etching, forming a stepped cavity with two stepped grooves of different inner groove depths, such as... Figure 11 As shown; through the stepped cavity, active components of different thicknesses can be embedded and installed through shallow and deep grooves of different depths; all metal through holes are located outside the area of ​​the glass core plate corresponding to the stepped cavity, that is, there is no TGV in the Cavity area.

[0097] In the sixth step, active components of different thicknesses are embedded into stepped grooves of varying depths within the stepped cavity of the glass core board using industry-standard surface mount and layering processes. The stepped cavity allows for the fitting of active components of different thicknesses through shallow and deep grooves. The stepped cavity and active components are encapsulated using molding materials such as FR4, BT, or ABF. Electrical interconnection between the active components and the TGV and RDLs is achieved through layering of RDLs. Figure 12 As shown; after the circuit is implemented, the passive components are surface-mounted onto the upper surface of the glass core board using conventional back-end SMT; that is, the active components are embedded inside the glass core board using industry-standard surface mount and layer-addition processes, and encapsulated with molding materials (such as FR4, BT, ABF, etc.). After the circuit is implemented, the passive components (resistors, motors, etc.) are surface-mounted using conventional back-end SMT, and short-path interconnection with the active components is achieved through layer-addition RDLs.

[0098] Solder balls (ball grid array solder balls) are implanted on the bottom rewiring layer at the bottom of the glass core board layer. Electrical interconnection and mechanical connection with external circuit boards can be achieved through the solder balls (ball grid array solder balls).

[0099] Example 6 illustrates a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips. The package example is... Figure 12 As shown, relative to Figure 3 The encapsulation structure, Figure 12 In the package structure, the interconnection paths between active and passive components are shorter. Figure 12 The volume of the package is further reduced in the X, Y, and Z directions.

[0100] Example 7: Example 7, based on Example 6, implements another three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips and its fabrication method. A stepped cavity is fabricated on the top of the glass core layer using a combination of laser roughing and wet finishing processes. The stepped cavity has two stepped grooves with different inner groove depths. Active components are embedded in the shallow grooves of the stepped cavity and passive components are embedded in the deep grooves of the stepped cavity. Multiple second and third metal through holes are also evenly distributed in the area of ​​the glass core layer corresponding to the bottom of the stepped cavity, thereby realizing direct connection between the back of the components embedded in the cavity and the lower redistribution layer at the bottom of the glass core layer.

[0101] The first step also pre-determines the position, quantity, height, and size of the second and third metal through holes. Specifically, the second metal through hole is set at the bottom of the shallow groove of the stepped cavity, and the third metal through hole is set at the bottom of the deep groove of the stepped cavity. In the third step, according to preset parameters, laser-induced etching, laser ablation, or deep reactive ion etching is used to densely fabricate the second and third TGVs at the positions corresponding to the bottom of the stepped cavity on the glass core plate, followed by metallization. In the fifth step, while processing the cavity on the glass core plate, the processing depth of the stepped cavity is controlled to just expose the metal end faces of the bottom second and third TGVs without damaging the TGV metal pillars, thereby forming the second and third metal vias. Figure 13 As shown, the number and density of the second metal vias can be designed according to different task requirements; the second and third metal vias directly contact the back of the active component to form a vertical heat dissipation path, such as... Figure 13 As shown. That is, multiple second and third metal vias are also densely arranged in the area of ​​the glass core layer corresponding to the bottom of the cavity, so as to realize the direct connection between the back of the component embedded in the cavity and the lower redistribution layer at the bottom of the glass core layer.

[0102] In step six, active components are embedded in shallow grooves of varying depths within the stepped cavities of the glass core board using industry-standard surface mount and layering processes. Passive components are embedded in deep grooves of varying depths within the stepped cavities of the glass core board. The stepped cavities and all components are encapsulated using molding materials such as FR4, BT, or ABF. Electrical interconnection between the active and passive components and the TGV and RDLs is achieved through layering RDLs. Figure 14 As shown, industry-standard surface mount and layer-addition processes are used to embed active and passive components inside the glass core board. These components are encapsulated using molding compounds (FR4, BT, ABF, etc.), and short-path interconnections are achieved with all components through layer-addition RDLs. After the circuitry is implemented, solder balls (ball grid array solder balls) are implanted on the bottom of the glass substrate.

[0103] Example 7 illustrates a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips. The package example is... Figure 14 As shown; relative to Figure 3 The encapsulation structure, Figure 14 In the package structure, the interconnection paths between active and passive components are shorter. Figure 14 The package size is further reduced in the X, Y, and Z directions; at the same time... Figure 14 This also achieves an efficient vertical heat dissipation path, further improving heat dissipation. The second and third TGVs are evenly distributed at the bottom of the cavity according to different task requirements, and the number of second and third TGVs is designed according to different task requirements to meet various task needs, such as signal transmission, appropriate sparse and heat-conducting layout, dense and concentrated layout, etc.

[0104] Example 8: Example 8, based on Example 2 above, implements another three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips and its fabrication method. A top cavity is set on the top of the glass core layer, and bottom cavities are set on the bottom of the glass core layer, thus forming an upper and lower opposed cavity. Solder balls (ball grid array solder balls) are implanted on the lower redistribution layer at the bottom of the glass core layer. Similarly, electrical interconnection and mechanical connection with the external circuit board can be achieved through the solder balls (ball grid array solder balls). All metal vias are set outside the areas on the glass core layer corresponding to the top cavity and bottom cavity. Active components can be embedded and mounted through the top cavity and bottom cavity. Passive components are mounted on the top surface of the glass core layer. The active components in the top cavity and bottom cavity are connected to the upper and lower redistribution layers through metal vias, respectively. The passive components are connected to the active components in the upper surface cavity through the added layer circuit.

[0105] Based on the above embodiment 2, the first step also includes pre-setting the specifications, quantity, and position parameters of cavities at the top and bottom of the glass core layer, respectively; In the fifth step, short-pulse lasers (picosecond or femtosecond lasers are optional) or ultraviolet lasers are first used. By controlling the laser energy, pulse number, and scanning path, the upper and lower surfaces of the glass are vaporized layer by layer until the designed target depths of the top and bottom cavities are reached. Then, wet etching is used to perform final finishing and smoothing of the bottom cavity of the top and bottom cavities. Wet etching is used to refine and smooth the bottom and sidewalls of the top and bottom cavities. The top and bottom cavities have the same inner groove depth, such as... Figure 15As shown; active components can be embedded through the top and bottom cavities; all metal vias are located outside the areas corresponding to the top and bottom cavities on the glass core layer, i.e., there is no TGV in the Cavity area.

[0106] In step six, active components are embedded into the top and bottom cavities of the glass core board using industry-standard surface mount and layering processes. The top and bottom cavities, as well as the active components, are encapsulated using molding materials such as FR4, BT, or ABF. Electrical interconnection between the active components in the top and bottom cavities and the TGV and RDLs is achieved through upper and lower layered RDLs, respectively. Figure 16 As shown; after the circuit is implemented, passive components are surface-mounted onto the upper surface of the glass core board using conventional back-end SMT. That is, using industry-standard surface mount and layer-addition processes, active components are embedded inside the top and bottom cavities of the glass core board, encapsulated with molding compounds (FR4, BT, ABF, etc.). After the circuit is implemented, passive components (resistors, motors, etc.) are surface-mounted using conventional back-end SMT, and short-path interconnection with active components is achieved through layer-addition RDLs. Solder balls (ball grid array solder balls) are implanted on the lower rewiring layer at the bottom of the glass core board layer. Electrical and mechanical connections with external circuit boards are achieved through these solder balls (ball grid array solder balls).

[0107] Example 8 illustrates a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips. The package example is... Figure 16 As shown, relative to Figure 3 The encapsulation structure, Figure 16 In the package structure, the interconnection paths between active and passive components are shorter. Figure 16 The package size has been further reduced in both the X and Y directions. Figure 16 The package has a higher integration density, enabling three-dimensional integration.

[0108] Example 9: Example 9, based on Example 8, implements another three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips and its fabrication method. A fourth metal via and a fifth metal via are also provided between the top cavity and the bottom cavity of the glass core layer. Active components can be embedded in the top cavity of the glass core layer, and passive components can be embedded in the bottom cavity of the glass core layer. The passive components are connected to the active components through the fifth metal via, and the active components are connected to the lower redistribution layer through the fourth metal via.

[0109] Example 9, based on Example 8, further specifies the position, number, height, and dimensions of the fourth and fifth metal vias in the first step, such as... Figure 17 As shown, Figure 17 The top cavity of the glass core layer is the active element cavity, and the bottom cavity is the passive element cavity. A fourth TGV (Transient Module Vault) is positioned near the left end of the top cavity, extending downwards from the bottom of the top cavity and penetrating the lower part of the glass core layer. Two TGVs located between the top and bottom cavities constitute the fifth TGV. In the third step, all TGVs, including the fourth and fifth TGVs, are fabricated on the glass core layer according to preset positions, quantities, heights, and dimensions. The fourth TGV is then metallized. In the fifth step, short-pulse lasers (picosecond or femtosecond lasers) or ultraviolet lasers are used to vaporize the upper and lower surfaces of the glass layer by layer until the designed target depths of the top and bottom cavities are reached, by controlling the laser energy, pulse number, and scanning path. Wet etching is then used to perform final finishing and smoothing of the bottom cavity of both the top and bottom cavities. Wet etching is also used to refine and smooth the bottom and sidewalls of both the top and bottom cavities. While fabricating the top cavity on the glass core layer, the fabrication depth is controlled to just expose the metal end face of the bottom fourth TGV, without damaging the TGV. Metal pillars, thus forming a fourth metal via, such as Figure 17 As shown, the upper surface of the fifth TGV is also exposed; while machining the bottom cavity on the glass core board, the machining depth of the bottom cavity is controlled so that the lower surface of the fifth TGV is just exposed. Through the machining process of the top cavity and the bottom cavity, the reserved hole section of the fifth TGV meets the preset parameter requirements.

[0110] In Example 9, after completing the fifth step and before executing the sixth step, an additional metallization process is added. This involves using an iPVD seed layer combined with bottom-up super-fill electroplating technology to metallize the fifth TGV, forming the fifth metal via. Then, in the sixth step, active components are embedded into the top cavity of the glass core board using industry-standard surface mount and layer-adding processes. The back of the active components is connected to the fourth and fifth metal vias via pads. Passive components are embedded into the bottom cavity of the glass core board using industry-standard surface mount and layer-adding processes. The passive components are connected to the fifth metal via via pads. The top and bottom cavities, as well as all components, are encapsulated using molding materials such as FR4, BT, or ABF. This allows direct connection between the back of the active components embedded in the top cavity and the lower redistribution layer at the bottom of the glass core board. Electrical interconnection between the components in the top and bottom cavities and the TGV and RDLs is achieved through upper and lower RDLs, respectively. Solder balls (ball grid array solder balls) are implanted on the lower rewiring layer at the bottom of the glass core board layer. These solder balls (ball grid array solder balls) enable electrical interconnection and mechanical connection with external circuit boards. Figure 18 As shown.

[0111] Example 9 illustrates a three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips. The package example is... Figure 18 As shown; relative to Figure 3 The encapsulation structure, Figure 18 In the package structure, the interconnection paths between active and passive components are shorter. Figure 18 The package size is further reduced in the X, Y, and Z directions; at the same time... Figure 18 It also achieves an efficient vertical heat dissipation path, further improving heat dissipation. The fourth and fifth TGVs are evenly distributed at the bottom of the cavity according to different task requirements, and the number of fourth and fifth TGVs is designed according to different task requirements to meet various task needs, such as signal transmission, appropriate sparse heat conduction and heat dissipation, and dense centralized layout, etc., resulting in higher packaging integration density and achieving three-dimensional integration.

[0112] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensional integrated packaging structure for a glass-core TGV panel with embedded heterogeneous chips, characterized in that: It includes a glass core layer, redistribution layers respectively disposed on the upper and lower surfaces of the glass core layer, and a plurality of glass through holes penetrating the glass core layer; Each of the glass vias is formed into a conductive metal via through a metallization process, and the redistribution layers on the upper and lower surfaces of the glass core layer are vertically interconnected through a number of the metal vias. The glass core layer is provided with cavities prepared by a combination of laser cutting for roughing and wet finishing. The cavities include at least one of single-depth cavities, stepped cavities, or vertically opposed cavities. Several active and / or passive components are embedded in the glass core layer along the Z-axis through the cavities. The active and passive components achieve horizontal signal transmission and vertical interconnection through upper and lower redistribution layers and corresponding metal vias, respectively. Solder balls are implanted in the bottom redistribution layer of the glass core layer to achieve electrical interconnection and mechanical connection with external circuits. The glass core plate layer is divided into a cavity avoidance area and a cavity bottom area. Conventional signal metal through holes are arranged in the cavity avoidance area, and heat dissipation metal through holes are densely arranged in the cavity bottom area. Each of the glass vias has a high aspect ratio, and each of the glass vias is prepared using a glass via forming process, which is laser-induced etching, laser ablation, or deep reactive ion etching; the metallization process is to achieve metallization by bottom-up super-fill electroplating after depositing a seed layer through ion physical vapor deposition; the laser cutting process is an ultra-short pulse laser cutting process or an ultraviolet laser cutting process.

2. The three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to claim 1, characterized in that: The top of the glass core layer is provided with a single-depth cavity, and all metal through holes are located in the cavity clearance area. The single-depth cavity is used to embed the active element, and the passive element is attached to the upper surface of the glass core layer or the bottom of the glass core layer.

3. The three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to claim 2, characterized in that: The bottom area of ​​the cavity is provided with a number of metal through holes that are concentrated or evenly distributed, thereby enabling direct connection between the back of the active element and the lower redistribution layer at the bottom of the glass core layer.

4. The three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to claim 1, characterized in that: The top of the glass core layer is provided with a stepped cavity, and the stepped cavity has at least two stepped grooves with different inner groove depths. The stepped cavity is used to adapt and embed active components of different thicknesses through shallow and deep grooves of different depths; or, the stepped cavity is used to adapt and embed active and passive components of different thicknesses through shallow and deep grooves of different depths. All metal vias are located in the cavity clearance area; or, multiple metal vias are also densely or evenly distributed in the bottom area of ​​the cavity, thereby enabling direct connection between the back of the active element and the passive element and the lower redistribution layer at the bottom of the glass core layer.

5. The three-dimensional integrated packaging structure of a glass core TGV panel with embedded heterogeneous chips according to claim 1, characterized in that: The top of the glass core layer is provided with a top cavity, and the bottom of the glass core layer is provided with a bottom cavity, thereby forming an upper and lower opposing cavity. All metal through holes are located in the cavity clearance area; the upper and lower opposed cavities are used to embed active components, and the passive components are surface-mounted on the top of the glass core layer; Alternatively, a metal via is provided between the top cavity and the bottom cavity. The top cavity is used to embed an active component, and the bottom cavity is used to embed a passive component. The passive component is connected to the active component through the metal via, and the active component is connected to the lower redistribution layer through the metal via.

6. A method for fabricating a three-dimensional integrated packaging structure of a glass-core TGV panel with embedded heterogeneous chips, used to fabricate the three-dimensional integrated packaging structure of a glass-core TGV panel with embedded heterogeneous chips according to any one of claims 1 to 5, characterized in that: The following steps are included: Obtain packaging design parameters, determine glass core layer specifications, and preset the specifications, quantity, and location parameters of TGV, double-sided RDLs, cavity, electronic components, and each add-on layer; Prepare double-sided glass core panels and perform pre-treatment cleaning; TGV hole forming and metallization; Preparation of double-sided RDLs; Cavities are fabricated on glass core boards; Embedded active and / or passive components, encapsulated, surface-mount passive components; or embedded active and passive components, encapsulated. Solder balls are implanted at the bottom of the glass core board to complete the encapsulation.

7. The method for fabricating a three-dimensional integrated packaging structure of a glass-core TGV panel with embedded heterogeneous chips according to claim 6, characterized in that: The pretreatment of the prepared double-sided glass core board includes the following operations: selecting a large-size glass panel according to the packaging design parameters, cleaning and drying the glass panel, and removing surface impurities and contaminants; Silicon, silicon dioxide, or silicon nitride materials are selected, and an adhesion layer is sequentially deposited on the surface of the glass core board through a magnetron sputtering process.

8. The method for fabricating a three-dimensional integrated packaging structure of a glass-core TGV panel with embedded heterogeneous chips according to claim 6, characterized in that: The TGV hole formation and metallization includes the following operations: high aspect ratio TGV is prepared by laser-induced etching, laser ablation or deep reactive ion etching processes; After the seed layer is deposited by ion physical vapor deposition, metallization is achieved by bottom-up superfill electroplating. The preparation of bifacial RDLs includes the following operations: a seed layer is sputtered onto the surface of a glass core plate using a magnetic sputtering process with a conductive metal material; or, Ti or Cr material is first selected, and an adhesion layer is sequentially deposited onto the surface of the glass core plate using a magnetic sputtering process, followed by sputtering a seed layer onto the surface of the glass core plate using a conductive metal material using a magnetic sputtering process; if the linewidth / spacing specification of the RDLs is greater than or equal to 10 / 10 μm, a subtractive method is used for preparation; if the linewidth / spacing specification of the RDLs is less than 10 / 10 μm, a semi-additive method is used for preparation. The process of fabricating the cavity on the glass core board includes the following operations: the cavity is prepared by a combination of laser cutting for roughing and wet finishing; the glass core board is vaporized layer by layer using an ultra-short pulse laser or ultraviolet laser until the depth meets the packaging design parameter requirements; and then the bottom of the cavity is finished and smoothed using a wet etching process.

9. The method for fabricating a three-dimensional integrated packaging structure of a glass-core TGV panel with embedded heterogeneous chips according to claim 6, characterized in that: The embedded active and / or passive components, encapsulation, and surface mount passive components; or, the embedded active and passive components, encapsulation, include the following operations: Active components are embedded into the cavity of the glass core board through surface mount and layering processes. After encapsulation with molding compound, passive components are surface mounted onto the upper or lower surface of the glass core board. Alternatively, active and passive components can be embedded into the cavity of the glass core board through surface mount and layering processes.

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