Method for manufacturing a heterogeneous package structure and heterogeneous package structure

Abstract

This invention provides a method for fabricating a heterogeneous packaging structure and the heterogeneous packaging structure itself, relating to the field of chip packaging technology. First, a separation trench is formed by half-cutting a diced area on the front side of a substrate wafer. Then, a first carrier is mounted on the front side of the substrate wafer, and the back side of the substrate wafer is thinned to expose the back side of multiple main chips. Next, the main chips in a predetermined area are removed, and substitute chips are attached, wherein the substitute chips can be arranged opposite to the main chips. Then, a first molding compound is formed to cover the sidewalls of the main chips and substitute chips, and a substitute redistribution layer is formed on the front side of the substitute chips. Finally, after removing the first carrier, a main redistribution layer is formed on the front side of the main chips. Compared to existing technologies, this invention significantly improves fabrication efficiency and reduces mounting misalignment. It also reduces wiring layer density, thereby mitigating leakage, short circuits, and overheating caused by inductive effects.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and more specifically, to a method for preparing a heterogeneous packaging structure and the heterogeneous packaging structure itself. Background Technology

[0002] Traditional reconfigurable wafer-level packaging (RDBMS) technology typically involves cutting individual chips from a wafer, mounting them onto a carrier wafer for reconfiguration, and then performing wiring. Its main advantages include high-density integration, small package size, superior product performance, and high signal transmission frequency. However, because it uses individual chip mounting, its mounting efficiency is too low, and issues such as process misalignment during mounting can lead to misalignment of subsequent wiring layers and pad designs, affecting conductivity.

[0003] Furthermore, conventional technologies require multiple carriers to reconstruct the wafer, and when multiple chips are integrated together, the wiring layer density also increases. If the signal transmission is in the ultra-high frequency signal transmission path of 100GHz-300GHz, there is an inductive effect between the wiring layers, which can lead to parasitic inductance and leakage, resulting in short circuits and overheating between the wiring layers. Summary of the Invention

[0004] The purpose of this invention is to provide a method for preparing a heterogeneous packaging structure and a heterogeneous packaging structure, which can improve preparation efficiency, reduce mounting misalignment, and simultaneously reduce wiring layer density while enabling direct integration of multiple chips, thereby mitigating leakage, short circuits, overheating and other phenomena caused by inductance effects.

[0005] In a first aspect, the present invention provides a method for preparing a heterogeneous packaging structure, comprising: Provide a substrate wafer; Separation trenches are formed by half-cutting the dicing area on the front side of the substrate wafer to form multiple main chips; A first carrier is mounted on the front side of the substrate wafer; Thin the back side of the substrate wafer to expose the separation trench and the back side of the multiple main chips; Remove the main chip from a preset area on the first vehicle and attach a replacement chip to the preset area, wherein the back of the replacement chip is attached to the first vehicle; A first molding compound is formed on the first carrier to cover the main chip and the substitute chip, wherein the first molding compound fills the separation trench, and the back side of the main chip and the front side of the substitute chip are exposed to the first molding compound. A replacement redistribution layer is formed on the replacement chip, wherein the replacement redistribution layer is electrically connected to the replacement chip; Remove the first carrier to expose the front of the main chip; A main redistribution layer is formed on the main chip, wherein the main redistribution layer is electrically connected to the main chip; The first molding layer is cut along the center or edge of at least a portion of the dividing groove.

[0006] In an optional implementation, prior to the step of cutting the first molding compound along the center or edge of the separating groove, the method further includes: A first solder ball is formed on the main redistribution layer; A second solder ball is formed on the replacement redistribution layer.

[0007] In an optional implementation, prior to the step of removing the first vehicle, the method further includes: A second carrier is mounted on the replacement rewiring layer.

[0008] In an optional implementation, prior to the step of forming a replacement redistribution layer on the replacement chip, the method further includes: Conductive pillars are formed in the first molding compound layer between the main chip and the substitute chip; The conductive post penetrates the first molding layer and is used to electrically connect to the substitute redistribution layer and the main redistribution layer, so that the substitute redistribution layer and the main redistribution layer are electrically connected through the conductive post.

[0009] In an optional implementation, after the step of forming a main redistribution layer on the main chip, the method further includes: A stacked chip is mounted on the main redistribution layer, wherein the stacked chip is electrically connected to the main redistribution layer.

[0010] In an optional implementation, after the step of mounting the stacked chips on the main redistribution layer, the method further includes: A second molding compound is formed on the main redistribution layer to cover the stacked chips.

[0011] In an optional embodiment, the step of forming a separation trench by half-cutting the dicing region on the front side of the substrate wafer includes: Separation trenches are formed by half-cutting the two sides of the dicing area on the front side of the substrate wafer, so that the central area of ​​the dicing area is retained to form a support layer, wherein the support layer is separated from the main chip by the separation trenches.

[0012] In an optional implementation, prior to the step of forming a replacement redistribution layer on the replacement chip, the method further includes: Conductive pillars are formed in the support layer; The conductive post penetrates the support layer and is used to electrically connect to the substitute redistribution layer and the main redistribution layer, so that the substitute redistribution layer and the main redistribution layer are electrically connected through the conductive post.

[0013] In an optional implementation, the step of forming a replacement redistribution layer on the replacement chip includes: A replacement dielectric layer is formed on the front side of the replacement chip; A substitute metal layer is formed in the substitute dielectric layer; The substitute dielectric layer covers the front side of the substitute chip and the surface of the first molding layer, and the substitute metal layer covers at least the front side of the substitute chip.

[0014] In an optional implementation, the step of forming a main redistribution layer on the main chip includes: A main dielectric layer is formed on the front side of the main chip; A main metal layer is formed in the main dielectric layer; The main dielectric layer covers the front side of the main chip and the surface of the first molding compound, and the main metal layer covers at least the front side of the main chip.

[0015] Secondly, the present invention provides a heterogeneous packaging structure, which is prepared by the method for preparing a heterogeneous packaging structure as described in the foregoing embodiments, wherein the heterogeneous packaging structure includes: Main chip; A first molding compound covering the main chip, wherein both the front and back sides of the main chip are exposed outside the first molding compound; The main body redistribution layer is disposed on the front side of the main body chip, and the main body redistribution layer is electrically connected to the main body chip; A replacement dielectric layer disposed on the back of the main chip.

[0016] Thirdly, the present invention provides a heterogeneous packaging structure, which is prepared by the method for preparing a heterogeneous packaging structure as described in the foregoing embodiments, wherein the heterogeneous packaging structure includes: Main chip; The main body redistribution layer is disposed on the front side of the main body chip, and the main body redistribution layer is electrically connected to the main body chip; A replacement dielectric layer disposed on the back of the main chip.

[0017] Fourthly, the present invention provides a heterogeneous packaging structure, which is prepared using the heterogeneous packaging structure preparation method described in the foregoing embodiments, wherein the heterogeneous packaging structure includes: A main chip and a substitute chip are spaced apart, wherein the front faces of the main chip and the front faces of the substitute chip face opposite directions; A first molding compound layer covering the main chip and the substitute chip; The main body redistribution layer is disposed on the front side of the main body chip, and the main body redistribution layer is electrically connected to the main body chip; A replacement redistribution layer is disposed on the front side of the replacement chip, and the replacement redistribution layer is electrically connected to the replacement chip.

[0018] In an optional embodiment, the heterogeneous packaging structure further includes a stacked chip disposed on the main redistribution layer and electrically connected to the main redistribution layer.

[0019] In an optional embodiment, the heterogeneous packaging structure further includes a second molding layer disposed on the main redistribution layer and covering the stacked chips.

[0020] In an optional embodiment, a conductive post is provided in the first molding compound. The conductive post is disposed between the main chip and the substitute chip and penetrates the first molding compound. The conductive post is electrically connected to the substitute redistribution layer and the main redistribution layer, so that the substitute redistribution layer and the main redistribution layer are electrically connected through the conductive post.

[0021] In an optional embodiment, a sensing area is provided on the front side of the main chip, the main redistribution layer avoids the sensing area, and an optical component is provided on the main redistribution layer. The optical component extends to the sensing area, and a sensing cavity is provided between the sensing area and the optical component.

[0022] In an optional embodiment, a sensing area is provided on the front side of the main chip, a sensing glass sheet is provided in the main redistribution layer, and an optical component is provided on the main redistribution layer. The two sides of the sensing glass sheet are in contact with the sensing area and the optical component, respectively.

[0023] In an optional embodiment, a support layer is provided in the first molding layer, the support layer being spaced apart from both the main chip and the substitute chip, and a conductive post is provided in the support layer, the conductive post penetrating the support layer and electrically connected to both the substitute redistribution layer and the main redistribution layer, so that the substitute redistribution layer and the main redistribution layer are electrically connected through the conductive post.

[0024] The beneficial effects of the embodiments of the present invention include: The method for fabricating a heterogeneous packaging structure and the heterogeneous packaging structure provided in this invention firstly involves half-cutting a dicing area on the front side of a substrate wafer to form a separation trench, thereby forming multiple main chips. Then, a first carrier is mounted on the front side of the substrate wafer, and the multiple main chips are separated after thinning the back side of the substrate wafer. Next, according to the design, the main chips in a predetermined area are removed, and substitute chips are added and mounted. The back side of the substitute chips is attached to the first carrier, while the front side of the main chips is attached to the first carrier, thus allowing the substitute chips and main chips to be arranged in opposite directions. Then, a first molding compound is formed to cover the sidewalls of the main chips and substitute chips, and a substitute redistribution layer is formed on the front side of the substitute chips. Finally, after removing the first carrier, a main redistribution layer is formed on the front side of the main chips.

[0025] Compared to existing technologies, the heterogeneous packaging structure fabrication method provided in this invention can utilize a half-cut process to achieve the reconfiguration and mounting of multiple chips, eliminating the need for alignment and bonding of each chip, thus significantly improving fabrication efficiency and mitigating mounting misalignment. Simultaneously, it allows for the partial removal of the main chip followed by the bonding of a substitute chip, enabling the direct integration of multiple different chips. Since the main chip and substitute chip are oriented in opposite directions, wiring can be performed on both sides of the first molding layer. For single-sided wiring, this reduces the wiring layer density, thereby mitigating leakage, short circuits, and overheating caused by inductive effects. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A flowchart illustrating the process steps of the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the structure corresponding to step S1 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention. Figure 3 This is a schematic diagram of the structure corresponding to step S2 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 5 This is a schematic diagram of the structure corresponding to step S4 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 6This is a schematic diagram of the structure corresponding to step S5 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 7 This is a schematic diagram of the structure corresponding to step S6 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention. Figure 8 This is a schematic diagram of the structure corresponding to step S7 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 9 This is a schematic diagram of the structure corresponding to step S8 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention. Figure 10 This is a schematic diagram of the structure corresponding to step S9 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 11 This is a schematic diagram of the structure corresponding to step S10 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention. Figure 12 This is a schematic diagram of the structure corresponding to step S11 in the method for preparing the heterogeneous packaging structure provided in the first embodiment of the present invention. Figure 13 This is a schematic diagram of a first heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 14 This is a schematic diagram of the second heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 15 This is a schematic diagram of the third heterogeneous packaging structure provided in the first embodiment of the present invention; Figure 16 This is a schematic diagram of the structure corresponding to step S7 in the method for preparing the heterogeneous packaging structure provided in the second embodiment of the present invention; Figure 17 This is a schematic diagram of the structure corresponding to step S8 in the method for preparing the heterogeneous packaging structure provided in the second embodiment of the present invention; Figure 18 This is a schematic diagram of the structure corresponding to step S11 in the method for preparing the heterogeneous packaging structure provided in the second embodiment of the present invention. Figure 19 This is a schematic diagram of the structure corresponding to step S12 in the method for preparing the heterogeneous packaging structure provided in the second embodiment of the present invention; Figure 20 This is a schematic diagram of the structure corresponding to step S13 in the method for preparing the heterogeneous packaging structure provided in the second embodiment of the present invention. Figure 21 This is a schematic diagram of the heterogeneous packaging structure provided in the second embodiment of the present invention; Figure 22 This is a schematic diagram of a heterogeneous packaging structure provided in the third embodiment of the present invention; Figure 23 This is a schematic diagram of the structure corresponding to step S2 in the method for preparing the heterogeneous packaging structure provided in the fourth embodiment of the present invention; Figure 24 This is a schematic diagram of the structure corresponding to step S7 in the method for preparing the heterogeneous packaging structure provided in the fourth embodiment of the present invention; Figure 25 This is a schematic diagram of the heterogeneous packaging structure provided in the fourth embodiment of the present invention; Figure 26 This is a schematic diagram of the heterogeneous packaging structure provided in the fifth embodiment of the present invention; Figure 27 This is a schematic diagram of a heterogeneous packaging structure provided in the sixth embodiment of the present invention.

[0028] Icons: 100 - Heterogeneous packaging structure; 110 - Main chip; 110a - Acceptable chip; 110b - Defective chip; 111 - Sensing area; 113 - Sensing glass sheet; 120 - Replacement chip; 130 - First molding compound layer; 140 - Replacement redistribution layer; 141 - Replacement dielectric layer; 142 - Replacement metal layer; 143 - Replacement wiring area; 144 - Replacement thermal conductive area; 150 - Main redistribution layer; 151 - Main dielectric layer; 152 - Main metal layer; 153 - Main wiring area; 154 - Main thermal conductive area; 160 - Stacked chips; 170 - Second molding compound layer; 180 - Support layer; 190 - Conductive pillar; 200 - Substrate wafer; 210 - Separator trench; 300 - First carrier; 400 - Second carrier; 500 - Optical component. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0032] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0033] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0034] As disclosed in the background section, traditional reconfigurable wafer packaging technology typically requires cutting individual chips from a wafer, mounting them on a carrier for reconfiguration, and then routing. This method requires mounting each chip individually, resulting in low mounting efficiency and potential process misalignment issues during mounting, which can easily lead to misalignment in subsequent routing and pad design, affecting conductivity.

[0035] Furthermore, conventional reconfigurable wafer packaging technology, due to the requirements of reconfigurable wafers, integrates multiple chips together. Since the multiple chips are oriented in the same direction, wiring can only be performed on one side. This leads to an increase in wiring layer density. If the signal is transmitted in the transmission path of ultra-high frequency signals in the range of 100GHz-300GHz, there is an inductive effect between the wiring layers, which can cause parasitic inductance and leakage, resulting in short circuits, overheating, and other phenomena between the wiring layers.

[0036] To address the aforementioned problems, embodiments of the present invention provide a novel method for preparing a heterogeneous packaging structure and a heterogeneous packaging structure. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0037] The method for fabricating heterogeneous packaging structures provided in this invention can improve fabrication efficiency, reduce mounting misalignment, and simultaneously reduce wiring layer density while enabling direct integration of multiple chips, thereby mitigating leakage, short circuits, and overheating caused by inductance effects.

[0038] First Embodiment See Figure 1 The method for preparing a heterogeneous packaging structure provided in this embodiment of the invention is used to prepare a heterogeneous packaging structure 100. The method includes the following steps: S1: Provide a substrate wafer 200.

[0039] See also Figure 2Specifically, the substrate wafer 200 has multiple main chips 110, and there are diced areas between the main chips 110. The thickness of the substrate wafer 200 is 600-800μm.

[0040] S2: A separation trench 210 is formed by half-cutting the dicing area on the front side of the substrate wafer 200 to form multiple main chips 110.

[0041] See also Figure 3 Specifically, a diamond cutting tool can be used to cut the substrate wafer 200 in half along a predetermined cutting tool, with a cutting depth H1 of 80-300μm, thereby forming multiple separating trenches 210 with a depth of 80-300μm.

[0042] S3: Mount the first carrier 300 on the front side of the substrate wafer 200.

[0043] See also Figure 4 Specifically, a substrate or carrier can be taken, and a liquid adhesive layer can be applied to the first carrier 300 by spin coating using a coating machine. Then, the substrate wafer 200 is soft-baked and shaped into a film by a hot plate. Then, the half-cut substrate wafer 200 is flipped and applied to the adhesive film. The adhesive film can be a UV adhesive, such as epoxy resin, polyimide, benzocyclobutene and other polymer composite materials. The first carrier 300 can be made of materials such as glass, silicon oxide, metal and so on.

[0044] S4: Thin the back side of the substrate wafer 200 to expose the back side of the separation trench 210 and multiple host chips 110.

[0045] See also Figure 5 Specifically, the back side of the substrate wafer 200 can be thinned through a grinding process until the separation trench 210 is exposed, thereby exposing the back side of multiple main chips 110 and separating the multiple main chips 110. In the actual grinding process, the separation trench 210 can also serve as a cleaning trench to drain the cleaning solution in a timely manner and avoid particle residue.

[0046] S5: Remove the main chip 110 from the preset area on the first vehicle 300 and attach a replacement chip 120 in the preset area.

[0047] See also Figure 6 The back side of the substitute chip 120 is attached to the first carrier 300. Specifically, the adhesive film in the preset area is first debonded by irradiating it with UV light, thereby removing part of the main chip 110. Then, the substitute chip 120 is mounted in reverse in the preset area with its back side facing down, which reduces the difficulty of the process.

[0048] It is worth noting that in some embodiments, the main chip 110 is divided into a qualified chip 110a and a defective chip 110b. The defective chip 110b can be removed in step S5, that is, the bad chip is removed, and a new qualified chip (KGD, known good die) is added. The positions of the defective chip 110b and the qualified chip 110a can be determined according to the test pattern provided by the wafer testing plant, and the position of the defective chip 110b is set as a preset area. Debonding is then performed on the preset area to achieve rapid screening, thereby improving the chip reconstruction wafer efficiency and improving the coplanarity of the overall chip.

[0049] It should be noted that the substitute chip 120 and the main chip 110 can be the same size, or the substitute chip 120 can be smaller than the main chip 110. The substitute chip 120 and the main chip 110 can be the same type of chip or different types of chips. Furthermore, the substitute chip 120 is mounted with its pads facing upwards, allowing it to be reversed from the main chip 110, thus achieving heterogeneous packaging. This reversed mounting of the substitute chip 120 and the main chip 110 allows for customized packaging structures, enabling different packaging designs. Additionally, it allows for double-sided wiring during the subsequent redistribution layer formation, reducing wiring density. Moreover, the metal ratio of the wiring on both sides of the first molding layer 130 is more balanced, thereby suppressing warpage of the overall packaging structure and achieving warpage balance.

[0050] In some other preferred embodiments, smaller supplementary chips can also be attached to the edge of the wafer to meet different customization requirements.

[0051] S6: A first molding layer 130 is formed on the first carrier 300, covering the main chip 110 and the substitute chip 120.

[0052] See Figure 7 The first molding layer 130, after molding, can fill the partition trench 210, and through grinding, the back side of the main chip 110 and the front side of the substitute chip 120 are exposed to the first molding layer 130. Specifically, a molding process can be performed, in which liquid molding material is used to fill the partition trench 210, and after baking, a molded structure is formed.

[0053] S7: Form a substitute redistribution layer 140 on the substitute chip 120.

[0054] See Figure 8The substitute redistribution layer 140 is electrically connected to the substitute chip 120. Specifically, a substitute dielectric layer 141 can be formed first on the front side of the substitute chip 120; then a substitute metal layer 142 can be formed in the substitute dielectric layer 141; wherein the substitute dielectric layer 141 covers the front side of the substitute chip 120 and the surface of the first molding compound 130, and the substitute metal layer 142 at least covers the front side of the substitute chip 120. Preferably, the substitute metal layer 142 can cover the entire surface of the first molding compound 130, the front side of the substitute chip 120, and the back side of the main chip 110. Specifically, the substitute metal layer 142 can be divided into a substitute wiring area 143 and a substitute heat-conducting area 144, which are independently separated. The substitute heat-conducting area 144 can extend to the back side of the main chip 110 and contact the back side of the main chip 110. It does not serve as an electrical connection, but rather as a structural support and heat dissipation function in the cut product package structure.

[0055] In actual fabrication, a dielectric material can be formed on the surface of the first molding layer 130 by spin coating. The dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. Then, a photomask is placed on the dielectric layer, and an exposure and development process is used to form a patterned layer opening layer. Then, an electroplating process is used to form an electroplated metal layer on the patterned layer opening, thereby forming a wiring layer. Then, a spin coating process is used again to form a second dielectric layer. Then, a dry etching process is used to form an opening on the second dielectric layer to expose the bottom wiring layer. Then, an electroplating process is used to form conductive metal pillars in the openings and a metal layer on the surface of the metal pillars. The metal layer improves its solderability, forming a replacement redistribution layer 140.

[0056] S8: Mount the second vehicle 400 on the substitute rewiring layer 140.

[0057] See Figure 9 Specifically, a second vehicle 400 can be mounted on the replacement redistribution layer 140. The material and mounting method of the second vehicle 400 can be referenced from the first vehicle 300.

[0058] S9: Remove the first vehicle 300 to expose the front of the main chip 110.

[0059] See Figure 10 Specifically, the packaging structure can be flipped over, and the first carrier 300 can be removed by overall debonding to expose the front of the main chip 110, while the back of the substitute chip 120 can also be exposed at the same time.

[0060] S10: A main redistribution layer 150 is formed on the main chip 110.

[0061] See Figure 11The main redistribution layer 150 is electrically connected to the main chip 110. Specifically, a main dielectric layer 151 can be formed on the front side of the main chip 110, and then a main metal layer 152 can be formed in the main dielectric layer 151; wherein, the main dielectric layer 151 covers the front side of the main chip 110 and the surface of the first molding compound 130, and the main metal layer 152 covers at least the front side of the main chip 110. Preferably, the main metal layer 152 can cover the entire surface of the first molding compound 130, the back side of the substitute chip 120, and the front side of the main chip 110. Specifically, the main metal layer 152 can be divided into a main wiring area 153 and a main heat-conducting area 154 that are independently separated from each other, wherein the main heat-conducting area 154 can extend to the back side of the substitute chip 120, and it does not play an electrical connection role, but plays a structural support and heat dissipation role in the product package structure. By expanding the distribution range of the main redistribution layer 150 and the alternative redistribution layer 140, the proportion of wiring metal on both sides of the first molding layer 130 is made more balanced, thereby suppressing the warping of the overall packaging structure and achieving warping balance.

[0062] In actual fabrication, a dielectric material can be formed on the surface of the first molding layer 130 by spin coating. The dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. Then, a photomask is placed on the dielectric layer, and an exposure and development process is used to form a patterned layer opening layer. Then, an electroplating process is used to form an electroplated metal layer on the patterned layer opening, thereby forming a wiring layer. Then, a spin coating process is used again to form a second dielectric layer. Then, a dry etching process is used to form an opening on the second dielectric layer to expose the bottom wiring layer. Then, an electroplating process is used to form conductive metal pillars in the openings and a metal layer on the surface of the metal pillars. The metal layer improves its solderability, forming the main redistribution layer 150.

[0063] S11: Remove the second vehicle 400.

[0064] See Figure 12 Specifically, the second carrier 400 is removed again using a debonding process, a first solder ball is formed on the main redistribution layer 150, and a second solder ball is formed on the substitute redistribution layer 140. Both the first and second solder balls can be formed by stencil printing or electroplating, for example, by forming solder balls, the material of which can be SnAg, SnAgCu, etc.

[0065] S12: Cut the first sealing layer 130 along the center or edge of at least part of the dividing groove 210.

[0066] See Figures 13 to 15Specifically, a cutting process can be used to form the final product. Different products can be obtained by choosing different cutting path positions. The final product may contain at least one of the main chip 110 and the substitute chip 120.

[0067] See Figure 13 This invention also provides a first heterogeneous packaging structure 100, which is fabricated using the aforementioned heterogeneous packaging structure fabrication method. The heterogeneous packaging structure 100 includes a main chip 110, a first molding compound 130, a main redistribution layer 150, and a substitute dielectric layer 141. The first molding compound 130 covers the main chip 110, with both the front and back sides of the main chip 110 exposed. The main redistribution layer 150 is disposed on the front side of the main chip 110 and is electrically connected to the main chip 110. The substitute dielectric layer 141 is disposed on the back side of the main chip 110.

[0068] Furthermore, a substitute metal layer 142 is also provided in the substitute dielectric layer 141. The substitute metal layer 142 is a substitute heat conduction area 144, which can play a role in structural support and heat dissipation, improve the strength and heat dissipation effect of the overall packaging structure, and achieve the back protection of the main chip 110 through the substitute dielectric layer 141.

[0069] It should be noted that the first heterogeneous packaging structure 100 here can be achieved by cutting the first molding layer 130 along the center of the separating groove 210 during cutting (step S12), thereby retaining the first molding layer 130.

[0070] See Figure 14 This invention also provides a second heterogeneous packaging structure 100, which is fabricated using the aforementioned heterogeneous packaging structure fabrication method. The heterogeneous packaging structure 100 includes a main chip 110, a main redistribution layer 150, and a substitute dielectric layer 141. The main redistribution layer 150 is disposed on the front side of the main chip 110 and is electrically connected to the main chip 110; the substitute dielectric layer 141 is disposed on the back side of the main chip 110. Furthermore, the substitute dielectric layer 141 also includes a substitute metal layer 142. This substitute metal layer 142 is an ineffective area and can provide structural support and heat dissipation, improving the overall strength and heat dissipation effect of the packaging structure.

[0071] It should be noted that the second heterogeneous packaging structure 100 here can be achieved by cutting the first molding layer 130 along the edge of the separating groove 210 during the cutting process (step S12), thereby removing the first molding layer 130 and exposing the sidewall of the main chip 110.

[0072] See Figure 15This invention also provides a third heterogeneous packaging structure 100, which is fabricated using the aforementioned heterogeneous packaging structure fabrication method. This heterogeneous packaging structure 100 includes a main chip 110, a substitute chip 120, a first molding compound 130, a main redistribution layer 150, and a substitute redistribution layer 140. The main chip 110 and the substitute chip 120 are spaced apart, with the front faces of the main chip 110 and the substitute chip 120 facing opposite directions. The first molding compound 130 covers the main chip 110 and the substitute chip 120. The main redistribution layer 150 is disposed on the front face of the main chip 110 and is electrically connected to the main chip 110. The substitute redistribution layer 140 is disposed on the front face of the substitute chip 120 and is electrically connected to the substitute chip 120.

[0073] It should be noted that by properly setting the cutting path during actual cutting (step S12), the main chip 110 and the substitute chip 120 can be packaged together, and the main redistribution layer 150 and the substitute redistribution layer 140 can be retained, achieving double-sided wiring. In addition, the substitute wiring area 143 of the substitute redistribution layer 140 can extend to the back of the main chip 110, and the main wiring area 153 of the main redistribution layer 150 can extend to the back of the substitute chip 120. Therefore, the wiring range can be expanded, the wiring density can be further reduced, and by expanding the distribution range of the main redistribution layer 150 and the substitute redistribution layer 140, the proportion of wiring metal on both sides of the first molding layer 130 is relatively more balanced, thereby suppressing the warping of the overall packaging structure and achieving warping balance.

[0074] In summary, the method for fabricating a heterogeneous packaging structure and the heterogeneous packaging structure 100 provided in this embodiment of the invention firstly involves half-cutting a dicing area on the front side of a substrate wafer 200 to form a separation trench 210, thereby forming multiple main chips 110. Then, a first carrier 300 is mounted on the front side of the substrate wafer 200, and the multiple main chips 110 are separated after thinning the back side of the substrate wafer 200. Next, according to the design, a predetermined area of ​​the main chips 110 is removed, and a substitute chip 120 is added and mounted. The back side of the substitute chip 120 is attached to the first carrier 300, while the front side of the main chips 110 is attached to the first carrier 300; therefore, the substitute chip 120 and the main chips 110 can be arranged oppositely. Then, a first molding compound 130 is formed to cover the sidewalls of the main chips 110 and the substitute chips 120, and a substitute redistribution layer 140 is formed on the front side of the substitute chip 120. Finally, after removing the first carrier 300, a main redistribution layer 150 is formed on the front side of the main chips 110. Compared to existing technologies, the heterogeneous packaging structure fabrication method provided in this invention can utilize a half-cut process to achieve the reconfiguration and mounting of multiple chips, eliminating the need for alignment and bonding of each chip, thus significantly improving fabrication efficiency and mitigating mounting misalignment. Simultaneously, it can partially remove the main chip 110 and then bond a substitute chip 120, enabling direct integration of multiple different chips. Since the main chip 110 and the substitute chip 120 are oriented in opposite directions, wiring can be performed on both sides of the first molding layer 130. For single-sided wiring, this reduces the wiring layer density, thereby mitigating leakage, short circuits, and overheating caused by inductive effects.

[0075] Second Embodiment This invention provides a method for preparing a heterogeneous packaging structure. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0076] The method for preparing a heterogeneous packaging structure provided in this embodiment of the invention includes the following steps: S1: Provide a substrate wafer 200.

[0077] S2: A separation trench 210 is formed by half-cutting the dicing area on the front side of the substrate wafer 200 to form multiple main chips 110.

[0078] S3: Mount the first carrier 300 on the front side of the substrate wafer 200.

[0079] S4: Thin the back side of the substrate wafer 200 to expose the back side of the separation trench 210 and multiple host chips 110.

[0080] S5: Remove the main chip 110 from the preset area on the first vehicle 300, and attach a substitute chip 120 to the preset area, wherein the back of the substitute chip 120 is attached to the first vehicle 300.

[0081] Specifically, the size of the substitute chip 120 is smaller than that of the main chip 110. Different types of chips can be used to achieve chip customization and double-sided wiring.

[0082] S6: A first molding layer 130 is formed on the first carrier 300, covering the main chip 110 and the substitute chip 120.

[0083] Steps S1 to S6 can be referred to in the first embodiment.

[0084] S7: Conductive pillars 190 are formed in the first molding layer 130 between the main chip 110 and the substitute chip 120.

[0085] See Figure 16 The conductive post 190 penetrates the first molding compound 130 and is electrically connected to the substitute redistribution layer 140 and the main redistribution layer 150, thereby electrically connecting the substitute redistribution layer 140 and the main redistribution layer 150 through the conductive post 190. Specifically, an etching process or a laser aperture-opening process can be used to form apertures around the substitute chip 120, and then electroplating is used to form the conductive post 190. It should be noted that the fabrication of the conductive post 190 facilitates the implementation of the wiring process and improves the wiring accuracy.

[0086] S8: Form a substitute redistribution layer 140 on the substitute chip 120.

[0087] See Figure 17 Specifically, the replacement redistribution layer 140 is electrically connected to one end of the conductive post 190. After the replacement redistribution layer 140 is formed, a second solder ball can be formed on the replacement redistribution layer 140 by a ball-planting process.

[0088] S9: Mount the second vehicle 400 on the substitute rewiring layer 140.

[0089] S10: Remove the first vehicle 300 to expose the front of the main chip 110.

[0090] S11: A main redistribution layer 150 is formed on the main chip 110.

[0091] See Figure 18 Specifically, the main redistribution layer 150 is electrically connected to the other end of the conductive post 190, thereby enabling the main redistribution layer 150 and the substitute redistribution layer 140 to be electrically connected through the conductive post 190.

[0092] S12: Attach stacked chips 160 on the main redistribution layer 150.

[0093] See Figure 19 The stacked chip 160 is electrically connected to the main redistribution layer 150. Specifically, a surface mount technology (SMT) process can be used to mount the stacked chip 160 onto the main redistribution layer 150. The stacked chip 160 can be a flip chip, which is fixed to the pads of the main redistribution layer 150 by a reflow soldering process. By setting up the stacked chip 160, stacked packaging can be achieved, increasing the chip packaging density.

[0094] S13: A second molding layer 170 is formed on the main redistribution layer 150 to cover the stacked chip 160.

[0095] See Figure 20 Specifically, a second molding layer 170 can be formed on the main redistribution layer 150 through a molding process to effectively protect the stacked structure.

[0096] S14: Remove the second vehicle 400.

[0097] S15: Cut the first sealing layer 130 along the center or edge of at least part of the dividing groove 210.

[0098] See Figure 21 This invention also provides a heterogeneous packaging structure 100, which is fabricated using the aforementioned method for preparing a heterogeneous packaging structure. The heterogeneous packaging structure 100 includes a main chip 110, a substitute chip 120, a first molding compound 130, a main redistribution layer 150, a substitute redistribution layer 140, a stacked chip 160, and a second molding compound 170. The main chip 110 and the substitute chip 120 are spaced apart, with the front faces of the main chip 110 and the substitute chip 120 facing opposite directions. The first molding compound 130 covers the main chip 110 and the substitute chip 120. The main redistribution layer 150 is disposed on the front face of the main chip 110 and is electrically connected to the main chip 110. The substitute redistribution layer 140 is disposed on the front face of the substitute chip 120 and is electrically connected to the substitute chip 120. The stacked chip 160 is disposed on the main redistribution layer 150 and is electrically connected to the main redistribution layer 150. The second molding layer 170 is disposed on the main redistribution layer 150 and covers the stacked chip 160.

[0099] In this embodiment, a conductive post 190 is provided in the first molding compound 130. The conductive post 190 is disposed between the main chip 110 and the substitute chip 120 and penetrates the first molding compound 130. The conductive post 190 is electrically connected to the substitute redistribution layer 140 and the main redistribution layer 150, so that the substitute redistribution layer 140 and the main redistribution layer 150 are electrically connected through the conductive post 190.

[0100] It should be noted that the main chip 110 and the substitute chip 120 are different types of chips, and the main chip 110 and the substitute chip 120 are designed on opposite sides. The substitute chip 120 is smaller than the main chip 110, achieving heterogeneous integration. The reverse design enables double-sided wiring and balances electrical performance, avoiding the capacitive and inductive effects caused by excessively dense single-sided wiring layers. The main redistribution layer 150 and the substitute redistribution layer 140 are widely distributed, which can significantly improve the overall package structure strength and heat dissipation performance. At the same time, the conductive pillars 190 enable double-sided wiring conductivity, which helps to improve wiring accuracy.

[0101] Third Embodiment This invention provides a method for preparing a heterogeneous packaging structure. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0102] The method for preparing a heterogeneous packaging structure provided in this embodiment of the invention includes the following steps: S1: Provide a substrate wafer 200.

[0103] S2: A separation trench 210 is formed by half-cutting the dicing area on the front side of the substrate wafer 200 to form multiple main chips 110.

[0104] S3: Mount the first carrier 300 on the front side of the substrate wafer 200.

[0105] S4: Thin the back side of the substrate wafer 200 to expose the back side of the separation trench 210 and multiple host chips 110.

[0106] S5: Remove the main chip 110 from the preset area on the first vehicle 300, and attach a substitute chip 120 to the preset area, wherein the back of the substitute chip 120 is attached to the first vehicle 300.

[0107] S6: A first molding layer 130 is formed on the first carrier 300, covering the main chip 110 and the substitute chip 120.

[0108] S7: Form a substitute redistribution layer 140 on the substitute chip 120.

[0109] S8: Mount the second vehicle 400 on the substitute rewiring layer 140.

[0110] S9: Remove the first vehicle 300 to expose the front of the main chip 110.

[0111] S10: A main redistribution layer 150 is formed on the main chip 110.

[0112] Steps S1 to S10 can be referred to in the first embodiment.

[0113] S11: Attach stacked chips 160 on the main redistribution layer 150.

[0114] The stacked chip 160 is electrically connected to the main redistribution layer 150. Specifically, a surface mount technology (SMT) process can be used to mount the stacked chip 160 onto the main redistribution layer 150. The stacked chip 160 can be a flip chip, which is fixed to the pads of the main redistribution layer 150 by a reflow soldering process. By setting up the stacked chip 160, stacked packaging can be achieved, increasing the chip packaging density.

[0115] S12: A second molding layer 170 is formed on the main redistribution layer 150 to cover the stacked chip 160.

[0116] S13: Remove the second vehicle 400.

[0117] S14: Cut the first sealing layer 130 along the center or edge of at least part of the dividing groove 210.

[0118] See Figure 22 This invention provides a heterogeneous packaging structure 100, which is fabricated using the aforementioned heterogeneous packaging structure fabrication method. The heterogeneous packaging structure 100 includes a main chip 110, a substitute chip 120, a first molding compound 130, a main redistribution layer 150, a substitute redistribution layer 140, a stacked chip 160, and a second molding compound 170. The main chip 110 and the substitute chip 120 are spaced apart, with the front faces of the main chip 110 and the substitute chip 120 facing opposite directions. The first molding compound 130 covers the main chip 110 and the substitute chip 120. The main redistribution layer 150 is disposed on the front face of the main chip 110 and is electrically connected to the main chip 110. The substitute redistribution layer 140 is disposed on the front face of the substitute chip 120 and is electrically connected to the substitute chip 120. The stacked chip 160 is disposed on the main redistribution layer 150 and is electrically connected to the main redistribution layer 150. The second molding layer 170 is disposed on the main redistribution layer 150 and covers the stacked chip 160. By setting the stacked chip 160, the chip packaging density is improved and a heterogeneous chip integration structure can be realized.

[0119] It is worth noting that the main chip 110 and the substitute chip 120 are different types of chips, and the main chip 110 and the substitute chip 120 are designed on opposite sides. The substitute chip 120 is smaller than the main chip 110, achieving heterogeneous integration. The reverse design enables double-sided wiring and balances electrical performance, avoiding the capacitive and inductive effects caused by excessively dense single-sided wiring layers. Furthermore, the main redistribution layer 150 and the substitute redistribution layer 140 are widely distributed, significantly improving the overall package structure strength and heat dissipation performance.

[0120] Fourth embodiment This invention provides a method for preparing a heterogeneous packaging structure. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0121] S1: Provide a substrate wafer 200.

[0122] S2: A separation trench 210 is formed by half-cutting the dicing area on the front side of the substrate wafer 200 to form multiple main chips 110.

[0123] See Figure 23 Specifically, separation trenches 210 can be formed by half-cutting the two edges of the dicing area on the front side of the substrate wafer 200, so that the central region of the dicing area is retained to form a support layer 180, wherein the support layer 180 is separated from the main chip 110 by the separation trenches 210. In actual fabrication, the width of the separation trenches 210 can be shortened so that the silicon layer in the center of the dicing area can be retained to form the support layer 180.

[0124] S3: Mount the first carrier 300 on the front side of the substrate wafer 200.

[0125] S4: Thin the back side of the substrate wafer 200 to expose the back side of the separation trench 210 and multiple host chips 110.

[0126] Specifically, after thinning the substrate wafer by 200, the support layer 180 can be exposed at the same time.

[0127] S5: Remove the main chip 110 from the preset area on the first vehicle 300, and attach a substitute chip 120 to the preset area, wherein the back of the substitute chip 120 is attached to the first vehicle 300.

[0128] S6: A first molding layer 130 is formed on the first carrier 300, covering the main chip 110 and the substitute chip 120.

[0129] Specifically, the first molding layer 130 may also encapsulate the support layer 180.

[0130] S7: Conductive pillars 190 are formed in the support layer 180.

[0131] See Figure 24 Specifically, the conductive pillar 190 penetrates the support layer 180 and is used to electrically connect with the substitute redistribution layer 140 and the main redistribution layer 150, so that the substitute redistribution layer 140 and the main redistribution layer 150 are electrically connected through the conductive pillar 190. In actual fabrication, TSV (Through-Screen Via) technology can be used to form openings around the substitute chip 120 and electroplating to form the conductive pillar 190. It should be noted that the fabrication of the conductive pillar 190 here facilitates the implementation of the wiring process and can improve the wiring accuracy. Furthermore, openings in the support layer 180 can also avoid the formation of thermal stress in the molding layer and achieve higher opening accuracy.

[0132] It should be noted that the support layer 180 here is a silicon layer, which protects the conductive pillars 190 and prevents warping of the molding compound. Furthermore, it can be fabricated using a dry etching process, replacing conventional laser grooving and avoiding thermal stress issues. In addition, the silicon layer has a lower dielectric constant, higher conductivity, and higher transmission efficiency compared to the molding compound layer.

[0133] S8: Form a substitute redistribution layer 140 on the substitute chip 120.

[0134] S9: Mount the second vehicle 400 on the substitute rewiring layer 140.

[0135] S10: Remove the first vehicle 300 to expose the front of the main chip 110.

[0136] S11: A main redistribution layer 150 is formed on the main chip 110.

[0137] S12: Attach stacked chips 160 on the main redistribution layer 150.

[0138] S13: A second molding layer 170 is formed on the main redistribution layer 150 to cover the stacked chip 160.

[0139] S14: Remove the second vehicle 400.

[0140] S15: Cut the first sealing layer 130 along the center or edge of at least part of the dividing groove 210.

[0141] See Figure 25This invention also provides a heterogeneous packaging structure 100, which is fabricated using the aforementioned method for preparing a heterogeneous packaging structure. The heterogeneous packaging structure 100 includes a main chip 110, a substitute chip 120, a first molding compound 130, a main redistribution layer 150, a substitute redistribution layer 140, a stacked chip 160, and a second molding compound 170. The main chip 110 and the substitute chip 120 are spaced apart, with the front faces of the main chip 110 and the substitute chip 120 facing opposite directions. The first molding compound 130 covers the main chip 110 and the substitute chip 120. The main redistribution layer 150 is disposed on the front face of the main chip 110 and is electrically connected to the main chip 110. The substitute redistribution layer 140 is disposed on the front face of the substitute chip 120 and is electrically connected to the substitute chip 120. The stacked chip 160 is disposed on the main redistribution layer 150 and is electrically connected to the main redistribution layer 150. The second molding layer 170 is disposed on the main redistribution layer 150 and covers the stacked chip 160.

[0142] In this embodiment, a support layer 180 is provided in the first molding layer 130. The support layer 180 is spaced apart from both the main chip 110 and the substitute chip 120. A conductive post 190 is provided in the support layer 180. The conductive post 190 penetrates the support layer 180 and is electrically connected to the substitute redistribution layer 140 and the main redistribution layer 150, so that the substitute redistribution layer 140 and the main redistribution layer 150 are electrically connected through the conductive post 190.

[0143] In summary, the method for preparing the heterogeneous packaging structure and the heterogeneous packaging structure 100 provided in the embodiments of the present invention, by setting the support layer 180 and the conductive pillars 190, can realize the electrical connection of double-sided wiring on the one hand, and can improve the overall packaging structure strength by using the support layer 180, and also help to reduce the warping of the molding layer.

[0144] Fifth embodiment This invention provides a heterogeneous packaging structure, whose basic structure, principle, and technical effects are the same as those of the first or second embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first or second embodiment.

[0145] See Figure 26This invention also provides a heterogeneous packaging structure 100, which is fabricated using the aforementioned method for preparing a heterogeneous packaging structure. The heterogeneous packaging structure 100 includes a main chip 110, a substitute chip 120, a first molding compound 130, a main redistribution layer 150, a substitute redistribution layer 140, a stacked chip 160, and a second molding compound 170. The main chip 110 and the substitute chip 120 are spaced apart, with the front faces of the main chip 110 and the substitute chip 120 facing opposite directions. The first molding compound 130 covers the main chip 110 and the substitute chip 120. The main redistribution layer 150 is disposed on the front face of the main chip 110 and is electrically connected to the main chip 110. The substitute redistribution layer 140 is disposed on the front face of the substitute chip 120 and is electrically connected to the substitute chip 120. The stacked chip 160 is disposed on the main redistribution layer 150 and is electrically connected to the main redistribution layer 150. The second molding layer 170 is disposed on the main redistribution layer 150 and covers the stacked chip 160.

[0146] In this embodiment, a conductive post 190 is provided in the first molding compound 130. The conductive post 190 is disposed between the main chip 110 and the substitute chip 120 and penetrates the first molding compound 130. The conductive post 190 is electrically connected to the substitute redistribution layer 140 and the main redistribution layer 150, so that the substitute redistribution layer 140 and the main redistribution layer 150 are electrically connected through the conductive post 190.

[0147] In this embodiment, a sensing area 111 is provided on the front side of the main chip 110. The main redistribution layer 150 avoids the sensing area 111, and an optical component 500 is provided on the main redistribution layer 150. The optical component 500 extends to correspond to the sensing area 111, and a sensing cavity is provided between the sensing area 111 and the optical component 500. Specifically, the edge of the main redistribution layer 150 forms a stepped structure, and the optical component 500 corresponds to the sensing area 111. The optical component 500 can be a fiber optic array unit (FAU), an optical engine (OE), a waveguide, a beam splitter, a microring resonator, a modulator, a photodetector, a microlens array, an optical waveguide, an acoustic waveguide, an electromagnetic waveguide, or the like. In addition, the main chip 110 can be a silicon photonics chip, a photonic integrated circuit chip (PIC), or other sensor chips, while the substitute chip 120 and the stacked chip 160 can be electronic integrated circuit chips (EIC), system-on-a-chip (SOC), central processing unit (CPU), graphics processing unit (GPU), high-bandwidth memory (HBM), or other types of chips.

[0148] It should be noted that by setting up the optical component 500 and avoiding the sensing area 111 with the main redistribution layer 150, the main redistribution layer 150 can support the optical component 500 while avoiding interference with the sensor, and at the same time ensure that the formed sensing cavity is unobstructed, thus ensuring the light transmission effect.

[0149] In some other preferred embodiments, the optical component 500 can also be directly attached to the front of the main chip 110 and cover the sensing area 111, avoiding the formation of a sensing cavity. Furthermore, the direct bonding of the optical component 500 to the sensing area 111 reduces the overall package height while further ensuring effective light transmission.

[0150] Sixth Embodiment This invention provides a heterogeneous packaging structure, whose basic structure, principle, and technical effects are the same as those of the first or second embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first or second embodiment.

[0151] See Figure 27 This invention also provides a heterogeneous packaging structure 100, which is fabricated using the aforementioned method for preparing a heterogeneous packaging structure. The heterogeneous packaging structure 100 includes a main chip 110, a substitute chip 120, a first molding compound 130, a main redistribution layer 150, a substitute redistribution layer 140, a stacked chip 160, and a second molding compound 170. The main chip 110 and the substitute chip 120 are spaced apart, with the front faces of the main chip 110 and the substitute chip 120 facing opposite directions. The first molding compound 130 covers the main chip 110 and the substitute chip 120. The main redistribution layer 150 is disposed on the front face of the main chip 110 and is electrically connected to the main chip 110. The substitute redistribution layer 140 is disposed on the front face of the substitute chip 120 and is electrically connected to the substitute chip 120. The stacked chip 160 is disposed on the main redistribution layer 150 and is electrically connected to the main redistribution layer 150. The second molding layer 170 is disposed on the main redistribution layer 150 and covers the stacked chip 160.

[0152] In this embodiment, a conductive post 190 is provided in the first molding compound 130. The conductive post 190 is disposed between the main chip 110 and the substitute chip 120 and penetrates the first molding compound 130. The conductive post 190 is electrically connected to the substitute redistribution layer 140 and the main redistribution layer 150, so that the substitute redistribution layer 140 and the main redistribution layer 150 are electrically connected through the conductive post 190.

[0153] In this embodiment, a sensing area 111 is provided on the front side of the main chip 110, a sensing glass plate 113 is provided in the main redistribution layer 150, and an optical component 500 is provided on the main redistribution layer 150. The two sides of the sensing glass plate 113 are in contact with the sensing area 111 and the optical component 500, respectively. It should be noted that the main redistribution layer 150 surrounds the sensing glass plate 113, and the sensing glass plate 113 corresponds to the sensing area 111, so that the optical component 500 and the sensing area 111 are optically transmitted through the sensing glass plate 113. The optical component 500 can be a fiber optic array unit (FAU), an optical engine (OE), a waveguide, a beam splitter, a microring resonator, a modulator, a photodetector, a microlens array, an optical waveguide, an acoustic waveguide, an electromagnetic waveguide, or the like. In addition, the main chip 110 can be a silicon photonics chip, a photonic integrated circuit chip (PIC), or other sensor chips, while the substitute chip 120 and the stacked chip 160 can be electronic integrated circuit chips (EIC), system-on-a-chip (SOC), central processing unit (CPU), graphics processing unit (GPU), high-bandwidth memory (HBM), or other types of chips.

[0154] It should be noted that by setting up the optical component 500 and avoiding the sensing area 111 with the main redistribution layer 150, the main redistribution layer 150 can support the optical component 500 while avoiding interference with the sensor. At the same time, optical transmission is achieved through the sensing glass plate 113, ensuring both structural support and light transmission effect.

[0155] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for preparing a heterogeneous packaging structure, characterized in that, include: Provide a substrate wafer; Separation trenches are formed by half-cutting the dicing area on the front side of the substrate wafer to form multiple main chips; A first carrier is mounted on the front side of the substrate wafer; Thin the back side of the substrate wafer to expose the separation trench and the back side of the multiple main chips; Remove the main chip from a preset area on the first vehicle and attach a replacement chip to the preset area, wherein the back of the replacement chip is attached to the first vehicle; A first molding compound is formed on the first carrier to cover the main chip and the substitute chip, wherein the first molding compound fills the separation trench, and the back side of the main chip and the front side of the substitute chip are exposed to the first molding compound. A replacement redistribution layer is formed on the replacement chip, wherein the replacement redistribution layer is electrically connected to the replacement chip; Remove the first carrier to expose the front of the main chip; A main redistribution layer is formed on the main chip, wherein the main redistribution layer is electrically connected to the main chip; Cut the first molding layer along the center or edge of at least a portion of the separating groove; The step of forming a separation trench by half-cutting the dicing region on the front side of the substrate wafer includes: Separation trenches are formed by half-cutting the two sides of the dicing area on the front side of the substrate wafer, so that the silicon layer in the central region of the dicing area is retained to form a support layer, wherein the support layer is separated from the main chip by the separation trenches; Prior to the step of forming a substitute redistribution layer on the substitute chip, the method further includes: Conductive pillars are formed in the support layer; The conductive post penetrates the support layer and is used to electrically connect to the alternative redistribution layer and the main redistribution layer, so that the alternative redistribution layer and the main redistribution layer are electrically connected through the conductive post.

2. The method for preparing the heterogeneous packaging structure according to claim 1, characterized in that, Prior to the step of cutting the first molding compound along the center or edge of the separating groove, the method further includes: A first solder ball is formed on the main redistribution layer; A second solder ball is formed on the replacement redistribution layer.

3. The method for preparing the heterogeneous packaging structure according to claim 1, characterized in that, Prior to the step of removing the first vehicle, the method further includes: A second carrier is mounted on the replacement rewiring layer.

4. The method for preparing the heterogeneous packaging structure according to claim 1, characterized in that, Prior to the step of forming a substitute redistribution layer on the substitute chip, the method further includes: Conductive pillars are formed in the first molding compound layer between the main chip and the substitute chip; The conductive post penetrates the first molding layer and is used to electrically connect to the substitute redistribution layer and the main redistribution layer, so that the substitute redistribution layer and the main redistribution layer are electrically connected through the conductive post.

5. The method for preparing the heterogeneous packaging structure according to claim 1 or 4, characterized in that, After the step of forming a main redistribution layer on the main chip, the method further includes: A stacked chip is mounted on the main redistribution layer, wherein the stacked chip is electrically connected to the main redistribution layer.

6. The method for preparing the heterogeneous packaging structure according to claim 5, characterized in that, After the step of mounting stacked chips on the main redistribution layer, the method further includes: A second molding compound is formed on the main redistribution layer to cover the stacked chips.

7. The method for preparing a heterogeneous packaging structure according to claim 1, characterized in that, The step of forming a replacement redistribution layer on the replacement chip includes: A replacement dielectric layer is formed on the front side of the replacement chip; A substitute metal layer is formed in the substitute dielectric layer; The substitute dielectric layer covers the front side of the substitute chip and the surface of the first molding layer, and the substitute metal layer covers at least the front side of the substitute chip.

8. The method for preparing a heterogeneous packaging structure according to claim 1, characterized in that, The step of forming a main redistribution layer on the main chip includes: A main dielectric layer is formed on the front side of the main chip; A main metal layer is formed in the main dielectric layer; The main dielectric layer covers the front side of the main chip and the surface of the first molding compound, and the main metal layer covers at least the front side of the main chip.

9. A heterogeneous packaging structure, prepared by the method for preparing a heterogeneous packaging structure as described in claim 1, characterized in that, The heterogeneous packaging structure includes: Main chip; A first molding compound covering the main chip, wherein both the front and back sides of the main chip are exposed outside the first molding compound; The main body redistribution layer is disposed on the front side of the main body chip, and the main body redistribution layer is electrically connected to the main body chip; A replacement dielectric layer disposed on the back of the main chip.

10. A heterogeneous packaging structure, prepared by the method for preparing a heterogeneous packaging structure as described in claim 1, characterized in that, The heterogeneous packaging structure includes: Main chip; The main body redistribution layer is disposed on the front side of the main body chip, and the main body redistribution layer is electrically connected to the main body chip; A replacement dielectric layer disposed on the back of the main chip.

11. A heterogeneous packaging structure, prepared by the method for preparing a heterogeneous packaging structure as described in claim 1, characterized in that, The heterogeneous packaging structure includes: A main chip and a substitute chip are spaced apart, wherein the front faces of the main chip and the front faces of the substitute chip face opposite directions; A first molding compound layer covering the main chip and the substitute chip; The main body redistribution layer is disposed on the front side of the main body chip, and the main body redistribution layer is electrically connected to the main body chip; A replacement redistribution layer is disposed on the front side of the replacement chip, and the replacement redistribution layer is electrically connected to the replacement chip.

12. The heterogeneous packaging structure according to claim 11, characterized in that, The heterogeneous packaging structure also includes stacked chips, which are disposed on the main redistribution layer and electrically connected to the main redistribution layer.

13. The heterogeneous packaging structure according to claim 12, characterized in that, The heterogeneous packaging structure further includes a second molding layer, which is disposed on the main redistribution layer and covers the stacked chips.

14. The heterogeneous packaging structure according to any one of claims 11-13, characterized in that, The first molding compound has conductive pillars disposed between the main chip and the substitute chip, and penetrate the first molding compound. The conductive pillars are electrically connected to the substitute redistribution layer and the main redistribution layer, so that the substitute redistribution layer and the main redistribution layer are electrically connected through the conductive pillars.

15. The heterogeneous packaging structure according to claim 14, characterized in that, The front side of the main chip has a sensing area, the main redistribution layer avoids the sensing area, and an optical component is disposed on the main redistribution layer. The optical component extends to the sensing area, and a sensing cavity is disposed between the sensing area and the optical component.

16. The heterogeneous packaging structure according to claim 14, characterized in that, The front side of the main chip is provided with a sensing area, the main redistribution layer is provided with a sensing glass sheet, and the main redistribution layer is provided with an optical component. The two sides of the sensing glass sheet are in contact with the sensing area and the optical component, respectively.

17. The heterogeneous packaging structure according to any one of claims 11-13, characterized in that, The first molding compound has a support layer that is spaced apart from both the main chip and the substitute chip. The support layer has conductive pillars that penetrate the support layer and are electrically connected to both the substitute redistribution layer and the main redistribution layer, so that the substitute redistribution layer and the main redistribution layer are electrically connected through the conductive pillars.

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