Semiconductor device

Abstract

Improve the surge energy tolerance of a semiconductor device. The semiconductor device (1) includes: a semiconductor element (3); and a plurality of wires (44) connected to electrodes (302) exposed on the surface of the semiconductor element. The plurality of wires includes wires (44A) of a first wire diameter, spaced 1 mm apart from the electrodes of the semiconductor element. 2 In this process, the sum of the contact areas between the electrode and multiple wires of the first wire diameter is 0.123 mm. 2 above.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] In semiconductor devices used for power conversion devices, there are semiconductor devices in which the electrodes of semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor) elements are connected to conductor patterns such as wiring boards by wires (e.g., Patent Documents 1 and 2).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2005-166854

[0006] Patent Document 2: Japanese Patent Application Publication No. 2008-186957 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] The aforementioned semiconductor devices are required to improve surge energy tolerance to prevent damage to semiconductor components caused by sudden high currents.

[0009] One of the objectives of this invention is to improve the surge energy tolerance of semiconductor devices.

[0010] Solution for solving the problem

[0011] One type of semiconductor device includes: a semiconductor element; and a plurality of wires, said plurality of wires being coupled to electrodes exposed on the surface of said semiconductor element. The plurality of wires comprises wires of a first wire diameter, per 1 mm of the electrodes of said semiconductor element. 2 In this configuration, the sum of the contact areas between the electrode and the plurality of wires is 0.123 mm. 2 above.

[0012] The effects of the invention

[0013] The surge energy tolerance of semiconductor devices can be improved by the above method. Attached Figure Description

[0014] [ Figure 1 ] Figure 1 This is a top view of a semiconductor device according to an embodiment.

[0015] [ Figure 2 ] Figure 2 This is an explanation Figure 1A cross-sectional view of an example structure within the housing of a semiconductor device.

[0016] [ Figure 3 ] Figure 3 It was formed in Figure 1 The circuit diagram of the inverter circuit of the semiconductor device.

[0017] [ Figure 4 ] Figure 4 A and Figure 4 B is a top view illustrating the relationship between the wire diameter and the joint point.

[0018] [ Figure 5 ] Figure 5 A and Figure 5 B is a side view illustrating the relationship between the wire diameter and the joint point.

[0019] [ Figure 6 ] Figure 6 It is a table illustrating the relationship between the number of joints and the joint area for each wire diameter.

[0020] [ Figure 7 ] Figure 7 It is a graph illustrating the relationship between the number of wires for each wire diameter and the surge energy tolerance.

[0021] [ Figure 8 ] Figure 8 It is a graph illustrating the relationship between the number of joints for each wire diameter and surge energy tolerance.

[0022] [ Figure 9 ] Figure 9 This is a graph illustrating the relationship between the bonding area and surge energy tolerance for each wire diameter.

[0023] [ Figure 10 ] Figure 10 It is a graph illustrating the relationship between the number of wires per unit area for each wire diameter and the surge energy tolerance.

[0024] [ Figure 11 ] Figure 11 It is a graph illustrating the relationship between the number of joints per unit area and surge energy tolerance for each wire diameter.

[0025] [ Figure 12 ] Figure 12 This is a graph illustrating the relationship between the bonding area per unit area and surge energy tolerance for each wire diameter. Detailed Implementation

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The X-axis, Y-axis, and Z-axis in the accompanying drawings are shown to define the planes and directions in the illustrated semiconductor device. The X-axis, Y-axis, and Z-axis are orthogonal to each other, forming a right-handed system. In the following description, the direction parallel to the X-axis will be referred to as the X-direction, the direction parallel to the Y-axis will be referred to as the Y-direction, and the direction parallel to the Z-axis will be referred to as the Z-direction. Furthermore, when the X-direction, Y-direction, and Z-direction are associated with the direction of the arrows (positive and negative) on the illustrated X-axis, Y-axis, and Z-axis, they will be labeled "positive side" or "negative side".

[0027] In this specification, the Z-direction is sometimes referred to as the up-down direction. In this specification, "up" or "above" refers to the side of the reference surface, component, or position that is on the positive side of the Z-direction, while "below" or "below" refers to the side of the reference surface, component, or position that is on the negative side of the Z-direction. For example, when described as "component B is placed on component A," from the perspective of component A, component B is placed on the positive side of the Z-direction. Furthermore, when described as "the upper surface of component A," this surface is located at the positive side of component A in the Z-direction, including the surface facing the positive side of the Z-direction. These directions and the surfaces associated with them are terms used for ease of explanation, and their correspondence with the X-axis, Y-axis, and Z-axis may change depending on the mounting posture of the semiconductor device. For example, in this specification, the surface of the semiconductor element facing the circuit board is called the lower surface, and the surface opposite to the lower surface is called the upper surface; however, this is not limited to this, and the surface facing the circuit board may also be called the upper surface, and the surface opposite to it may be called the lower surface.

[0028] The aspect ratios and relative sizes of the components in the figures are schematic representations and may not correspond to those in actual manufactured semiconductor devices. For ease of explanation, exaggerated representations of the relative sizes of components and depictions differing from the shapes of actual components used in semiconductor devices are also included. Furthermore, for illustrative purposes, several cross-sectional views show the cross-sectional structure of a semiconductor device cut by imaginary cutting lines, which cannot be accurately shown in top-view diagrams.

[0029] In this specification, terms such as "not shown," "not illustrated," and "not illustrated" refer to reference numerals and leader lines that indicate the constituent elements or explicitly represent those constituent elements, which are not shown in the drawings. For example, "first main electrode not shown" means that the portion representing the first main electrode (e.g., a graphic or line) is not shown in the drawing, and that the symbol and leader lines explicitly representing the portion of the first main electrode that conforms to the drawing are not shown in the drawing. Furthermore, underlined symbols in the drawings indicate a constituent element comprising multiple parts distinguished by multiple symbols.

[0030] The semiconductor devices illustrated in the following description are, for example, power conversion devices such as inverters that can be applied to industrial or electrical applications (e.g., automotive motors). Therefore, detailed descriptions of structures, functions, operations, manufacturing methods, etc., that are the same as or similar to known semiconductor devices are omitted in the following description. The term "semiconductor device" in this specification refers to a semiconductor element, sometimes called a semiconductor chip, bare chip, etc., sealed with an insulating material, and may also be referred to as a "semiconductor module," etc. Furthermore, the "surge energy withstand capability" in this invention can be expressed as the product of the surge current withstand capability IFSM and the voltage VFSM. The surge current withstand capability IFSM is the maximum value of the non-repeating forward surge current in a half-cycle of a sinusoidal wave at a commercial frequency (pulse width tp = 10 ms), and the voltage VFSM is the value of the forward voltage Vf of the diode element when the surge current withstand capability IFSM is measured.

[0031] Figure 1 This is a top view of a semiconductor device according to an embodiment. Figure 2 This is an explanation Figure 1 A cross-sectional view of an example structure within the housing of a semiconductor device. Figure 3 It was formed in Figure 1 The circuit diagram of the inverter circuit of the semiconductor device. Figure 2 The cross-sectional view can be Figure 1 An example of the cross-sectional structure of a semiconductor device 1 when cut along a single-dotted line A-A'.

[0032] The semiconductor device 1 according to this embodiment includes circuit boards 2A and 2B, semiconductor elements 3A to 3D, wires 40 to 49, a housing 5, a sealing material (not shown), and a heat sink 6. In this specification, when referring to constituent elements based on a combination of numbers and letters following those numbers, the numbers and letters are described when constituent elements with the same numbers are distinguished; otherwise, only the numbers are described. For example, when referring to a specific semiconductor element among multiple semiconductor elements 3A to 3D, ... Figure 1 The symbol assigned to the specific semiconductor element is recorded (e.g., "semiconductor element 3A"), and otherwise simply "semiconductor element 3". Furthermore, when referring to multiple components with the same name, modifiers such as "first" or "second" are sometimes added. For example, circuit board 2A and circuit board 2B are sometimes recorded as "first circuit board 2A" and "second circuit board 2B". Moreover, modifiers such as "first" and "second" are used only to distinguish multiple identical components and are not intended to determine the order of these components.

[0033] Circuit board 2 is a component mounting device that mounts a semiconductor element 3, sometimes referred to as a semiconductor chip, bare chip, etc. The semiconductor element 3 can be, for example, an RC (Reverse Conducting)-IGBT element that combines the functions of a switching element such as an IGBT (Insulated Gate Bipolar Transistor) element and a diode element such as an FWD (Free Wheeling Diode). Circuit board 2 and semiconductor element 3 are used to form... Figure 3 The circuit components of the illustrated half-bridge inverter circuit 10.

[0034] The first circuit board 2A includes an insulating substrate 200, conductor patterns 201-207 disposed on the upper surface of the insulating substrate 200, and a heat dissipation pattern disposed on the lower surface of the insulating substrate 200. The second circuit board 2B includes an insulating substrate 200, conductor patterns 201, 202, 204-207 disposed on the upper surface of the insulating substrate 200, and a heat dissipation pattern 208 disposed on the lower surface of the insulating substrate 200. The circuit board 2 can be a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate, but is not limited to such substrates. The first circuit board 2A and the second circuit board 2B can also be integrated.

[0035] The insulating substrate 200 can be, for example, a ceramic substrate formed from ceramic materials such as alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or a composite material of alumina (Al2O3) and zirconium oxide (ZrO2). The insulating substrate 200 can also be a substrate obtained by molding an insulating resin such as epoxy resin into a sheet shape, a substrate obtained by impregnating an insulating resin into a substrate such as glass fiber, or a substrate obtained by coating the surface of a flat metal core with an insulating resin.

[0036] The conductor patterns 201-207 disposed on the upper surface of the insulating substrate 200 are used as wiring in electronic circuits such as inverter circuits formed within the semiconductor device 1. The heat dissipation pattern 208 disposed on the lower surface of the insulating substrate 200 is used as a heat dissipation component to conduct heat emitted by the semiconductor element 3 to the heat sink 6 when the semiconductor device 1 is operating. The conductor patterns 201-207 and the heat dissipation pattern 208 are formed, for example, from metal foils such as copper or aluminum.

[0037] Circuit board 2 is disposed on the upper surface of heat sink 6. The heat dissipation pattern 208 of circuit board 2 is connected to the upper surface of heat sink 6 in a tight manner through a bonding material such as solder (not shown), thermal grease, or thermally conductive compound. Heat sink 6 may be, for example, a metal plate such as copper or aluminum. Heat sink 6 may also have multiple fins on its lower surface. Heat sink 6 may be part of cooler 7 or a component connected to cooler 7. That is, cooler 7 is any component in semiconductor device 1 of this embodiment. Cooler 7 is not limited to a specific cooling method or a specific structure.

[0038] Figure 1 and Figure 2 The illustrated semiconductor device 1 has a housing 5 disposed on the upper surface of a heat sink 6. The housing 5 includes a frame-shaped insulating member 500 having open ends on its upper and lower surfaces, and a plurality of terminals 501-507 integrated with the insulating member 500. The insulating member 500 of the housing 5 can be shaped to accommodate the circuit board 2, semiconductor element 3, wires 40-49, etc., when disposed on the upper surface of the heat sink 6, and is divided into spaces that can be filled with a sealing material to seal them. The open ends on the upper surface side of the insulating member 500 can also be covered, for example, by a cover (not shown) formed of insulating material.

[0039] The terminals 501-507 of the housing 5 are roughly divided into main terminals 501-503 and control terminals 504-507. The main terminals 501-503 are connected to electrodes that allow the main current to flow through switching elements such as the IGBT element in the semiconductor element 3. [The last sentence appears to be incomplete and possibly refers to a separate process.] Figure 3 In the case of the semiconductor device 1 of the illustrated half-bridge inverter circuit 10, the first main terminal 501 can be a P terminal connected to the positive terminal of the DC power supply and connected to the collector of the IGBT element 310 in the semiconductor elements 3A and 3B disposed on the upper surface of the first circuit board 2A. The second main terminal 502 can be an N terminal connected to the negative terminal of the DC power supply and connected to the emitter electrode of the IGBT element 310 in the semiconductor elements 3C and 3D disposed on the upper surface of the second circuit board 2B. The third main terminal 503 is an intermediate terminal (M terminal) connected to the load and connected to the emitter electrode of the IGBT element 310 in the semiconductor elements 3A and 3B disposed on the upper surface of the first circuit board 2A and the collector electrode of the semiconductor elements 3C and 3D disposed on the upper surface of the second circuit board 2B. The semiconductor element 3, which is the RC-IGBT element described above, includes the IGBT element 310 and a diode element 311 connected in reverse parallel with the IGBT element 310. Figure 1 and Figure 2 The semiconductor element 3 in the illustrated semiconductor device 1 is arranged on the circuit board 2 with a collector electrode disposed on the lower surface and an emitter electrode 302 and a gate electrode 303 disposed on the upper surface.

[0040] The collector electrodes of semiconductor elements 3A and 3B on the first circuit board 2A are bonded to the first conductor pattern 201 of the circuit board 2A via solder or other bonding materials. The first conductor pattern 201 of the first circuit board 2A is electrically connected to the first main terminal 501 via line 40. The emitter electrodes 302 of semiconductor elements 3A and 3B on the first circuit board 2A are electrically connected to the second conductor pattern 202 of the first circuit board 2A via line 41. The second conductor pattern 202 of the first circuit board 2A is electrically connected to the first conductor pattern 201 of the second circuit board 2B via line 42. The first conductor pattern 201 of the second circuit board 2B is bonded to the collector electrodes of semiconductor elements 3C and 3D, and is electrically connected to the third main terminal 503 via line 43. The emitter electrodes 302 of semiconductor elements 3C and 3D are electrically connected to the second conductor pattern 202 of the second circuit board 2B via line 44. The second conductor pattern 202 of the second circuit board 2B is electrically connected to the third conductor pattern 203 of the first circuit board 2A via line 45, and the third conductor pattern 203 of the first circuit board 2A is electrically connected to the second main terminal 502 via line 46.

[0041] The gate electrodes 303 of semiconductor devices 3A and 3B are electrically connected to the fourth conductor pattern 204 of the first circuit board 2A via line 47. The fourth conductor pattern 204 of the first circuit board 2A is electrically connected to the first control terminal 504 via line and the sixth conductor pattern 206 of the second circuit board 2B. The gate electrodes 303 of semiconductor devices 3C and 3D are electrically connected to the fourth conductor pattern 204 of the second circuit board 2B via line 48. The fourth conductor pattern 204 of the second circuit board 2B is electrically connected to the second control terminal 505 via line and the sixth conductor pattern 206 of the first circuit board 2A.

[0042] in addition, Figure 3The illustrated half-bridge inverter circuit 10 has auxiliary control terminals 506 and 507, referred to as auxiliary emitter terminal, sensing emitter terminal, emitter sensing terminal, etc. The first auxiliary control terminal 506 is electrically connected to the emitter electrodes 302 of semiconductor elements 3A and 3B, and is connected to a control circuit (not shown) that generates control signals applied to the gate electrodes 303 of semiconductor elements 3A and 3B. The second auxiliary control terminal 507 is electrically connected to the emitter electrodes 302 of semiconductor elements 3C and 3D, and is connected to a control circuit (not shown) that generates control signals applied to the gate electrodes 303 of semiconductor elements 3C and 3D. In the case of the semiconductor device 1 with auxiliary emitter terminals, the second conductor pattern 202 of the first circuit board 2A is electrically connected to the first auxiliary control terminal 506 via a line, the fifth conductor pattern 205 of the first circuit board 2A, and the seventh conductor pattern 207 of the second circuit board 2B, etc. Similarly, the second conductor pattern 202 of the second circuit board 2B is electrically connected to the second auxiliary control terminal 507 via line 49, the fifth conductor pattern 205 of the second circuit board 2B, and the seventh conductor pattern 207 of the first circuit board 2A.

[0043] In addition, refer to Figures 1-3 The semiconductor device 1 and the half-bridge inverter circuit 10 described herein are merely examples of semiconductor devices to which the present invention can be applied. The circuit board 2, semiconductor element 3, housing 5, etc., in the semiconductor device 1 are not limited to a specific structure. The electronic circuits formed in the semiconductor device 1 to which the present invention can be applied are not limited to the aforementioned half-bridge inverter circuit 10.

[0044] In the semiconductor device 1 of this embodiment, the emitter electrode 302 of a semiconductor element 3 is electrically connected to the conductor pattern 202 of the circuit board 2 via a plurality of lines 41 or 44. By making such a connection, the contact area between the emitter electrode 302 and the lines 41 or 44 can be increased, thereby increasing the surge energy tolerance of the semiconductor element 3. However, the contact area between the emitter electrode 302 of the semiconductor element 3 and the lines 41 or 44 is constrained by the combination of the size of the area of ​​the emitter electrode 302 exposed on the upper surface of the semiconductor element 3 and the wire diameter of the lines 41 or 44. Furthermore, the lines 41 and 44 can be made of aluminum, aluminum alloy, etc., but are not limited to specific materials. In addition, in this specification, the lines 41 and 44 connected to the emitter electrode 302 of the semiconductor element 3 are described as having a circular cross-section, but the cross-sectional shape of the lines 41 and 44 is not limited to a circle.

[0045] Figure 4 A and Figure 4 B is a top view illustrating the relationship between the wire diameter and the joint point. Figure 5 A and Figure 5B is a side view illustrating the relationship between the wire diameter and the joint point. Figure 6 It is a table illustrating the relationship between the number of joints and the joint area for each wire diameter. Figure 5 A's side view could be Figure 4 Left side view of A Figure 5 The side view of B can be Figure 4 The left-side view of B. Furthermore... Figure 4 A and Figure 4 The emitter electrode 302 of the semiconductor element 3 illustrated in B is divided into two parts in the extension direction (Y direction) of line 44, but the emitter electrode 302 can also be a single electrode that is not divided, or it can be divided by other dividing patterns.

[0046] Figure 4 A and Figure 5 A shows an example of the line spacing D2 and the number of connection points with the emitter electrode 302 of the semiconductor element 3 to the conductor pattern 202 of the circuit board 2 when the emitter electrode 302 of the semiconductor element 3 is connected by a line 44B with a diameter R2 of 400 μm (hereinafter referred to as "the second diameter line 44B"). In the line bonding using the second diameter line 44B, the spacing L2 between the connection points when two portions of one line 44B are bonded to the conductor in such a way that a line arc is formed therebetween can be, for example, about 3.3 mm. Therefore, for example, if the dimension ERy in the extension direction (Y direction) of the line 44B in the area ER where the emitter electrode 302 is exposed on the upper surface of the semiconductor element 3 is about 5.0 mm, then the number of connection points with the emitter electrode 302 in one second diameter line 44B is 2. Therefore, when the emitter electrode 302 of the semiconductor element 3 with a region ER of 5.0 mm is electrically connected to the conductor pattern 202 of the circuit board 2 via a wire 44B of the second wire diameter, the relationship between the number of wires, the number of junction points, and the junction area is as follows: Figure 6 The relationship illustrated. Figure 6 The example of the second wire diameter (R2 = 400 μm) wire 44B, with its joint area, derives the joint area of ​​a single joint point to the joint area of ​​0.323 mm when joined using a standard joining tool. 2 Furthermore, in practice, the wire and electrode are connected by interlocking over a defined, finite area when viewed from above. The term "junction point" used in this specification corresponds to the central portion of the area where the wire and electrode are connected by interlocking. For example, in the junction of a wire and electrode having a near-elliptical junction area, the intersection of the major and minor axes of the ellipse is the junction point. The distances between these junction points are specified in this specification.

[0047] Furthermore, when the emitter electrode 302 of the semiconductor element 3 is bonded with multiple lines 44B of second wire diameter in a direction orthogonal to the extension direction (Y direction) of the lines (X direction), the minimum value of the spacing D2 of the lines in the X direction (minimum spacing D2min) depends on the dimension of the bonding tool in the X direction (in other words, Figure 4 The gap G2 between the joints of adjacent lines 44B as illustrated in example A). The minimum spacing D2min of the second diameter lines 44B can be 0.8mm, therefore in Figure 4 When the dimension ECx in the X direction of the region ER illustrated in A is 5.0 mm, the maximum number of the second wire diameter wires 44B that can be used for bonding with the emitter electrode 302 of the semiconductor element 3 is 6 to 7.

[0048] Figure 4 B and Figure 5 B illustrates an example of the line spacing D1 and the number of bonding points with the emitter electrode 302 of the semiconductor element 3 when the emitter electrode 302 is connected to the conductor pattern 202 of the circuit board 2 using a line 44A with a diameter R1 of 200 μm (hereinafter referred to as "the first diameter line 44A"). In the line bonding using the first diameter line 44A, the spacing L1 between the bonding points when two portions of one line 44A are bonded to the conductor in such a way that a line arc is formed therebetween can be set to approximately 1.1 mm, for example. Therefore, for example, if the dimension ERy in the extension direction (Y direction) of the line 44A in the area ER where the emitter electrode 302 is exposed on the upper surface of the semiconductor element 3 is approximately 5.0 mm, then the number of bonding points with the emitter electrode 302 in one first diameter line 44A is 4. Furthermore, depending on the performance of the bonding tool and the performance of the device, the spacing L1 can also be set to 1.0 mm or 0.9 mm. Furthermore, when the emitter electrode 302 of the semiconductor element 3 is coupled with a plurality of first-diameter wires 44A in a direction orthogonal to the extension direction (Y direction) of the wire 44A (X direction), the minimum value (minimum spacing D1min) of the spacing D1 of the first-diameter wires 44A depending on the gap G1 between adjacent bonding points in the X direction can be 0.4 mm. Therefore, in Figure 4 The region ER illustrated in B has a dimension ECx of 5.0 mm in the X direction (i.e., compared to...). Figure 4 When the size of the region ER (as illustrated in A) is the same, the maximum number of first-diameter wires 44A that can be used for bonding with the emitter electrode 302 of the semiconductor element 3 is 12 to 13. Therefore, when electrically connecting the emitter electrode 302 of the semiconductor element 3 with the aforementioned region ER to the conductor pattern 202 of the circuit board 2 via first-diameter wires 44A, the relationship between the number of wires 44A and the bonding area is as follows: Figure 6 The relationship illustrated therein. Furthermore... Figure 6The example of the first wire diameter (R1 = 200 μm) of wire 44A derives the joint area of ​​a single joint point to the joint area of ​​0.085 mm when joined using a standard joining tool. 2 .

[0049] As described above, the minimum spacing D1min (=0.4mm) of the first wire diameter (200μm) wire 44A can be half the minimum spacing D2min (=0.8mm) of the second wire diameter (400μm) wire 44B. Therefore, for example, by changing the wire bonded to the emitter electrode 302 of the semiconductor element 3 from the 400μm wire 44B to the 200μm wire 44A, and doubling the number of wires, the bonding area can be increased. However, as referred to Figures 7-9 As explained below, if only a smaller wire diameter is selected to increase the junction area, the surge energy tolerance of semiconductor element 3 may not increase.

[0050] Figure 7 It is a graph illustrating the relationship between the number of wires for each wire diameter and the surge energy tolerance. Figure 8 It is a graph illustrating the relationship between the number of joints for each wire diameter and surge energy tolerance. Figure 9 This is a graph illustrating the relationship between the bonding area and surge energy tolerance for each wire diameter. Figures 7-9 The surge energy tolerance in each chart is set as the product of the surge current tolerance IFSM and the voltage VFSM. Furthermore, as mentioned above, the surge current tolerance IFSM is the maximum value of the non-repeating forward surge current in a half-cycle of a sinusoidal wave at a commercial frequency (pulse width tp = 10 ms), and the voltage VFSM is the value of the forward voltage Vf of the diode element when the surge current tolerance IFSM is measured.

[0051] according to Figures 7-9 As can be seen from the chart, whether the first wire diameter (200μm) wire 44A is bonded to the emitter electrode 302 of the semiconductor element 3, or the second wire diameter (400μm) wire 44B is bonded to the emitter electrode 302 of the semiconductor element 3, the surge energy tolerance increases with the increase of the number of wires, the number of bonding points, and the bonding area.

[0052] However, for example, the surge energy withstand capability when eight first-diameter wires 44A are bonded to the emitter electrode 302 of the semiconductor element 3 is smaller than that when four first-diameter wires 44A are bonded to the emitter electrode 302 of the semiconductor element 3. The bonding area when eight first-diameter wires 44A are bonded to the emitter electrode 302 of the semiconductor element 3 is 2.74 mm². 2 This is greater than the bonding area (2.584 mm²) when four wires of the second diameter 44B are bonded to the emitter electrode 302 of the semiconductor element 3.2 However, in Figure 9 In the chart, the bonding area of ​​the 200μm diameter wire is 2.74mm². 2 In this case, the surge energy tolerance is less than that of a wire with a diameter of 400 μm and a bonding area of ​​2.584 mm². 2 Surge energy tolerance under certain conditions. When 10 wires of the first diameter 44A are bonded to the emitter electrode 302 of the semiconductor element 3, compared to bonding 5 wires of the second diameter 44B to the emitter electrode 302 of the semiconductor element 3, although the bonding area in the emitter electrode 302 is larger, the surge energy tolerance remains approximately the same. Conversely, if 12 wires of the first diameter 44A are bonded to the emitter electrode 302 of the semiconductor element 3, compared to bonding 6 wires of the second diameter 44B to the emitter electrode 302 of the semiconductor element 3, the bonding area in the emitter electrode 302 increases from 3.876 mm². 2 Increased to 4.08mm 2 Furthermore, the surge energy tolerance is increased. Therefore, the size (Y direction × X direction) of the area ER exposed by the emitter electrode 302 of semiconductor element 3 is 5.0 × 5.0 mm. 2 In this case, by connecting 12 wires 44A of the first wire diameter to the emitter electrode 302, compared to connecting the wires 44B of the second wire diameter, the surge energy tolerance can be increased. Figures 7-9 In the illustrated diagram, the surge energy tolerance when 12 wires of the first diameter 44A are joined to the emitter electrode 302 is approximately 10% greater than the surge energy tolerance when 6 wires of the second diameter 44B are joined. Specifically, as... Figure 9 As illustrated, the maximum surge energy tolerance when the second diameter (400 μm) wire 44B is joined is approximately 6.0 kW, while the maximum surge energy tolerance when the first diameter (200 μm) wire 44A is joined is approximately 6.6 kW.

[0053] Furthermore, the dimensions (Y direction × X direction) of the area ER exposed by the emitter electrode 302 are 5.0 × 5.0 mm. 2 In this case, the number of 400μm diameter wires 44B that can be coupled to the emitter electrode 302 can be a maximum of 6 to 7, as described above. Figure 7 In the chart, the surge energy tolerance ratio is higher when seven 400μm diameter wires (44B) are joined together, while the number of 200μm diameter wires (44A) with higher surge energy tolerance can be 11 or more. The dimensions (Y direction × X direction) of region ER are 5.0 × 5.0 mm. 2 When 11 wires 44A with a diameter of 200 μm are bonded to the emitter electrode 302, such as Figure 8As illustrated, with 44 bonding points, the surge energy tolerance is greater compared to when there are 7 bonding points (44B) with a diameter of 400 μm (14 bonding points). The dimensions (Y direction × X direction) of region ER are 5.0 × 5.0 mm. 2 When the emitter electrode 302 is coupled with wires 44A with a diameter of 200μm, if there are more than 12 wires, the surge energy tolerance can be further increased. If there are 11 wires, the increase in the time required for wire coupling (production cycle time) can be suppressed.

[0054] Additionally, the dimensions (Y direction × X direction) of the area ER exposed by the emitter electrode 302 are 5.0 × 5.0 mm. 2 In such cases, Figure 6 As illustrated, nine wires with a diameter of 300 μm can be bonded to the emitter electrode 302. In this example, each wire can be bonded to the emitter electrode 302 at three bonding points, resulting in 27 bonding points and a bonding area of ​​4.077 mm². 2 An example of surge energy withstand capability when nine 300μm diameter wires are coupled to the emitter electrode 302 of semiconductor element 3 is shown below. Figure 7 as well as Figure 9 The value shown in the black diamond is less than the surge energy tolerance of joining 12 wires of diameter 44A with a diameter of 200μm, but greater than the surge energy tolerance of joining 6 wires of diameter 400μm of 44B.

[0055] Based on the above points, in the semiconductor device 1 of this embodiment, the number of wires is selected such that the sum of the bonding areas when bonding 200μm wires 44A to the emitter electrode 302 of the semiconductor element 3 is greater than the sum of the bonding areas that maximize surge energy tolerance when bonding wires with a diameter larger than these wires 44A (e.g., wires with a diameter of 400μm or 300μm) to the emitter electrode 302. This increases the surge energy tolerance of the semiconductor element 3. Similarly, when bonding 300μm wires to the emitter electrode 302 of the semiconductor element 3, the number of wires is selected such that the sum of the bonding areas is greater than the sum of the bonding areas that maximize surge energy tolerance when bonding wires with a diameter larger than these wires (e.g., wires 44B with a diameter of 400μm) to the emitter electrode 302. This also increases the surge energy tolerance of the semiconductor element 3. That is, in the semiconductor device 1 of this embodiment, the plurality of lines connected to the emitter electrode 302 of the semiconductor element 3 include lines of a first wire diameter, and the method is selected such that the sum of the bonding areas of the emitter electrode 302 is greater than the sum of the bonding areas that maximize the surge energy tolerance when a line of a second wire diameter that is thicker than the first wire diameter is bonded to the emitter electrode.

[0056] Reference Figure 6as well as Figures 7-9 The relationship between the wire diameter and surge energy tolerance for each of the above-mentioned wire diameters is related to the size (Y direction × X direction) of the exposed area ER of the emitter electrode 302, which is 5.0 × 5.0 mm. 2 The above relationship can be rewritten as a relationship independent of the size of the exposed area ER of the emitter electrode 302 by converting it into the number of junction points and the junction area per unit area of ​​the emitter electrode 302.

[0057] Figure 10 It is a graph illustrating the relationship between the number of wires per unit area for each wire diameter and the surge energy tolerance. Figure 11 It is a graph illustrating the relationship between the number of joints per unit area and surge energy tolerance for each wire diameter. Figure 12 This is a graph illustrating the relationship between the bonding area per unit area and surge energy tolerance for each wire diameter. Figure 10 , Figure 11 as well as Figure 12 The horizontal axis in the chart can be... Figure 7 , Figure 8 as well as Figure 9 The value on the horizontal axis of the graph is divided by the size of the area ER exposed by the emitter electrode 302 (5.0 × 5.0 mm). 2 The value obtained is that the unit area can be 1 mm². 2 . Figure 10 as well as Figure 11 The "6 sticks" mentioned at the top of the chart refer to the use of 6 sticks. Figure 7 as well as Figure 8 The value corresponds to line 44B with a diameter of 400μm in the chart.

[0058] Figure 10 The illustrated graph shows a straight line Q1 representing the relationship between the number of wires per unit area and surge energy tolerance when using 200μm wire 44A. This line suggests that setting the number of wires per unit area to 0.380 or more results in a surge energy tolerance greater than that of using 6 wires of 400μm diameter 44B (approximately 6.0kW). Furthermore, Figure 11 The illustrated graph shows a straight line Q2 representing the relationship between the number of junctions per unit area and surge energy tolerance when using wire 44A with a wire diameter of 200 μm. This line suggests that if the number of junctions per unit area is set to 0.153 or higher, the surge energy tolerance is greater than that when using 6 wires 44B with a wire diameter of 400 μm (approximately 6.0 kW).

[0059] In addition, in the Figure 12 The illustrated charts and Figure 10In comparison with the chart, when six 400μm diameter wires 44B are joined to the electrode 302 of semiconductor element 3 with a surge energy tolerance of the maximum (e.g., approximately 6.0kW), the electrode is 1mm per... 2 Compared to the bonding area, when 12 wires 44A with a diameter of 200 μm are bonded to the electrode 302 of semiconductor element 3, the electrode area per 1 mm is significantly smaller. 2 The joint area is large.

[0060] and, Figure 12 The illustrated graph shows a straight line Q3 representing the relationship between the bonding area per unit area and surge energy tolerance when using a 200 μm wire. If the bonding area per unit area (1 mm²) is... 2 The bonding area is greater than approximately 0.123 mm. 2 This is greater than the surge energy tolerance when using a 400μm wire, as represented by the straight line Q4. Additionally, as... Figure 12 As shown, the joint area per unit area is set to approximately 0.150 mm. 2 The surge energy withstand capability is greater when the wire diameter is 200 μm and when the wire diameter is 300 μm, and the surge energy withstand capability is greater when the wire diameter is 200 μm. That is, when a wire with a diameter of 200 μm or more but less than 400 μm is bonded to the emitter electrode 302 of the semiconductor element 3, when the electrode is made to be 1 mm thicker, the surge energy withstand capability is greater. 2 The bonding area is 0.123 mm. 2 Above and 0.18mm 2 When setting the wire diameter, number of wires, and number of joints in the following manner, it indicates that each 1mm of electrode is used for... 2 The point showing the relationship between the bonding area and surge energy is within region S1. Compared to bonding a wire with a diameter of 400 μm or more to the emitter electrode 302 of the semiconductor element 3, the surge energy tolerance can be increased. Furthermore, Figure 12 Region S1 in the middle can also be the electrode every 1 mm 2 The upper limit of the bonding area is set to be less than 0.18 mm. 2 Any value or 0.18mm 2 The region containing any of the above values. Additionally, the electrode is per 1mm. 2 The minimum value of the joint area can also be Figure 12 The value in straight line Q3 that is larger than the maximum measured surge energy withstand capability (approximately 6.0 kW) when using a 400 μm wire (e.g., 0.13 mm) is larger. 2 ).

[0061] in addition, Figure 12The graph suggests that the relationship between the bonding area per unit area and the surge energy when using wire with a diameter less than 200 μm is a straight line, Q5. That is, when the bonding area per unit area is set to 0.123 mm... 2 For the same values ​​mentioned above, using a finer wire diameter increases surge energy tolerance. However, when the wire diameter is reduced and the number of bonding points is increased, the manufacturing cost of the semiconductor device 1 may rise due to the increased time (production cycle time) required to connect the emitter electrode 302 of the semiconductor element 3 to the wire, and the increased energy required for bonding. Therefore, the wire diameter and bonding area per unit area are preferably set based on the surge energy tolerance required by the semiconductor device 1. Figure 12 The decision is made within the range of region S1 and region S2.

[0062] In the semiconductor device 1 used in a power conversion device, the switching operation of the switching elements such as the IGBT element in the semiconductor element 3 is high-speed, thus sometimes suddenly (e.g., at the start of operation) generating high inrush currents and inrush voltages. If the suddenly generated inrush current or inrush voltage exceeds the assumed value (rated), the semiconductor element 3 is damaged, and power cannot be supplied to the load connected to the power conversion device (e.g., a motor in a vehicle, elevator, etc.). Therefore, the semiconductor device 1 requires maximizing the surge energy tolerance of the semiconductor element 3.

[0063] In the semiconductor device described in Patent Document 1, the surge current withstand capability is increased by reducing the wiring length (resistance value) of the portion between the two junctions of a single wire along the surface of the emitter electrode of the semiconductor element 3. However, the semiconductor device in Patent Document 1 does not determine the optimal wire diameter by comparing the relationship between the junction area derived for each wire diameter and the surge current withstand capability. Therefore, as referred to... Figures 7-9 As described above, reducing the wire diameter may decrease the surge current withstand capability. Furthermore, the semiconductor device described in Patent Document 2 involves distributing multiple wires in an uneven configuration to the electrodes of the semiconductor element, making it difficult to increase the connection area to increase the surge current withstand capability. In contrast, in the semiconductor device 1 of this embodiment, by comparing the relationship between the connection area derived for each wire diameter and the surge energy withstand capability, the optimal wire diameter for maximizing surge energy withstand capability can be determined.

[0064] In the semiconductor device 1 of this embodiment, the wire diameter of the wire bonded to the emitter electrode 302 of the semiconductor element 3 is not limited to the aforementioned 200 μm or 300 μm. For example, the wire diameter can also be 100 μm, 150 μm, 250 μm, etc. The number of bonding points between a single wire and the emitter electrode 302 of the semiconductor element 3 can be varied depending on the combination of the size of the exposed area ER of the emitter electrode 302 and the wire diameter. For example, a wire 44B with a wire diameter of 400 μm can have three or more bonding points with the emitter electrode 302. Furthermore, the bonding points of adjacent wires can also be connected to each other... Figure 4 A and Figure 4 The lines illustrated in example B are arranged in different directions (X direction). For example, the junctions of adjacent lines can also be staggered in the direction of line extension (Y direction) by the interval between the junctions of one line (e.g., Figure 4 The distance B is a non-integer multiple (e.g., 1 / 2) of the spacing L1. Furthermore, the plurality of lines bonded to the emitter electrode 302 of a semiconductor element 3 are not limited to having the same wire diameter. For example, lines with a diameter of 200 μm and lines with a diameter of 400 μm may also be included. Additionally, the wire diameters of the lines bonded to the emitter electrode 302 and the lines bonded to the third electrode (gate electrode) in a semiconductor element 3 may be different.

[0065] In the semiconductor device 1 of this embodiment, semiconductor elements having switching elements such as IGBTs and semiconductor elements having diode elements such as FWDs can be connected in parallel via conductor patterns and bonding wires on a circuit board. The switching element of the semiconductor element is not limited to IGBTs; for example, it can be a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), or the like. When the switching element is a power MOSFET, the collector and emitter of the aforementioned IGBT element are read as drain and source, and the auxiliary emitter is read as auxiliary source. Furthermore, the diode element connected in reverse parallel with the switching element can be, for example, an SBD (Schottky Barrier Diode), a JBS (Junction Barrier Schottky) diode, an MPS (Merged PN Schottky) diode, or a PN diode. Semiconductor elements are not limited to those formed using silicon (Si), but can also be formed using wide-bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and diamond. Semiconductor device 1 may also include semiconductor elements other than switching elements and diode elements.

[0066] Furthermore, in the above embodiment, the emitter electrode 302 of the switching element (IGBT element) of the semiconductor element 3 is connected to multiple lines, but the electrodes of the semiconductor element 3 connected to the multiple lines are not limited to this. For example, the semiconductor element 3 may also be configured such that the surface on which the emitter electrode 302 and the gate electrode 303 are formed faces the circuit board 2. In this case, the electrodes of the semiconductor element 3 connected to the multiple lines can be the collector electrodes of the IGBT element. Additionally, if the semiconductor element with the switching element and the semiconductor element with the diode element are separate semiconductor elements, the aforementioned multiple lines may, for example, be connected to the electrodes of the semiconductor element with the diode element. Furthermore, if the switching element of the semiconductor element 3 is a power MOSFET element, and the lines 41 or 44 (see reference...) Figure 1 The electrode 302 of the connected semiconductor element 3 can also be the source electrode.

[0067] The semiconductor device 1 described in the above embodiments is not limited to a specific application. For example, it can be used in industrial power conversion devices such as inverter devices that drive motors in elevators, escalators, and building air conditioning systems, as well as in high-output power conversion devices such as power conversion devices for vehicles. Vehicles can be, for example, electric vehicles that use motors to drive their wheels, or hybrid vehicles that use an internal combustion engine in addition to a motor. Vehicles are not limited to four-wheeled vehicles; they can also be two-wheeled vehicles, railway vehicles, etc.

[0068] Below, we summarize the feature points of the above-described implementation methods.

[0069] The semiconductor device according to the above embodiments includes: a semiconductor element; and a plurality of lines, the plurality of lines being coupled to electrodes exposed on the surface of the semiconductor element, wherein the plurality of lines include lines of a first wire diameter, per 1 mm of the electrodes of the semiconductor element. 2 In this configuration, the sum of the contact areas between the electrode and the plurality of wires is 0.123 mm. 2 above.

[0070] In the semiconductor device according to the above embodiments, the spacing between the junctions of one wire in the first wire diameter is 1.1 mm or less.

[0071] In the semiconductor device according to the above embodiments, the wire of the first wire diameter is joined to the electrode at a plurality of junction points, and a wire arc separated from the electrode is formed between the junction points.

[0072] In the semiconductor device according to the above embodiments, every 1 mm of the electrode of the semiconductor element 2 In this configuration, the sum of the contact areas between the electrode and the plurality of wires is 0.13 mm. 2 above.

[0073] In the semiconductor device described in the above embodiments, the first wire diameter is 200 μm or 300 μm.

[0074] In the semiconductor device described in the above embodiments, the semiconductor element is formed from a semiconductor substrate of silicon, silicon carbide, or gallium nitride, and the electrode of the semiconductor element is the emitter electrode of an IGBT (Insulated Gate Bipolar Transistor) element or the source electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) element.

[0075] In the semiconductor device according to the above embodiments, every 1 mm of the electrode 2In the first sum, the sum is greater than the second sum, where the first sum is the sum of the bonding areas of the electrode with the plurality of wires of the first wire diameter, and the second sum is the sum of the bonding areas of the electrode with the plurality of wires of the second wire diameter that maximizes the surge energy tolerance.

[0076] In the semiconductor device according to the above embodiments, every 1 mm of the electrode 2 In the case where the sum of the bonding areas of the electrode with the plurality of wires of the first wire diameter, i.e., the first bonding area, and the sum of the bonding areas of the electrode with the plurality of wires of the second wire diameter, i.e., the second bonding area, are the same, the surge energy tolerance of a semiconductor element having the electrode bonded by the plurality of wires of the first wire diameter is greater than that of a semiconductor element having the electrode bonded by the plurality of wires of the second wire diameter.

[0077] Furthermore, the present invention is not limited to the embodiments described above, and various modifications, substitutions, and variations can be made without departing from the spirit of the technical concept. Moreover, if the technical concept can be realized in other ways due to technological advancements or derived technologies, this method can also be used for implementation. Therefore, the claims cover all embodiments that can be included within the scope of the technical concept.

[0078] Industrial availability

[0079] As explained above, the present invention has the effect of improving the surge energy tolerance of semiconductor elements in semiconductor devices and preventing damage to semiconductor elements caused by sudden high currents, and is particularly useful for industrial or vehicle semiconductor devices used as power conversion devices.

[0080] This application is based on Japanese Special Application 2024-091877, filed on June 6, 2024. The entire contents of that application are contained herein.

Claims

1. A semiconductor device comprising: Semiconductor components; and Multiple lines, said multiple lines being coupled to electrodes exposed on the surface of the semiconductor element, in, The plurality of lines includes lines with a first wire diameter. Every 1 mm of the electrode in the semiconductor element 2 In this configuration, the sum of the contact areas between the electrode and the plurality of wires is 0.123 mm. 2 above.

2. The semiconductor device according to claim 1, wherein, The spacing between the joints of one wire in the first wire diameter is less than 1.1 mm.

3. The semiconductor device according to claim 2, wherein, The first wire diameter is joined to the electrode at multiple joints, and an arc of wire separated from the electrode is formed between the joints.

4. The semiconductor device according to claim 3, wherein, Every 1 mm of the electrode in the semiconductor element 2 In this configuration, the sum of the contact areas between the electrode and the plurality of wires is 0.13 mm. 2 above.

5. The semiconductor device according to claim 4, wherein, The first wire diameter is 200μm or 300μm.

6. The semiconductor device according to claim 5, wherein, The semiconductor element is formed from a semiconductor substrate of any one of silicon, silicon carbide, and gallium nitride. The electrode of the semiconductor element is the emitter electrode of an insulated gate bipolar transistor (IGBT) or the source electrode of a metal-oxide-semiconductor field-effect transistor (MOSFET).

7. The semiconductor device according to claim 6, wherein, Every 1 mm of the electrode 2 In the first sum, the sum is greater than the second sum, wherein the first sum is the sum of the bonding areas of the electrode with the plurality of wires of the first wire diameter, and the second sum is the sum of the bonding areas of the electrode with the plurality of wires of the second wire diameter that maximize the surge energy tolerance.

8. The semiconductor device according to claim 7, wherein, Every 1 mm of the electrode 2 In the case where the sum of the bonding areas of the electrode with the plurality of wires of the first wire diameter, i.e., the first bonding area, is the same as the sum of the bonding areas of the electrode with the plurality of wires of the second wire diameter, i.e., the second bonding area, the semiconductor element having the electrode bonded through the plurality of wires of the first wire diameter has a greater surge energy tolerance than the semiconductor element having the electrode bonded through the plurality of wires of the second wire diameter.

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