A high-volume real-time data fault recording system based on time slicing

Abstract

This invention discloses a high-volume real-time fault recording system based on time slicing, relating to the field of power system technology. It includes a computing board, a management board, a differential data bus, and a synchronization bus. Under the control of the time-slicing signal on the synchronization bus, the fault recording data calculated by the CPU chip on the computing board is transmitted from the FPGA chip on the computing board to the FPGA chip on the management board via the differential data bus and cached in a DDR chip. The FPGA chip on the management board reads the cached data based on the fault recording start flag and fault recording time stamp, sends it to the CPU chip on the management board, and generates a recording file which is written to an SSD chip. This invention features a unified hardware architecture for the management board and computing board, high reliability, large internal communication bandwidth, high CPU program execution efficiency, high system flexibility, and strong scalability, showing promising application prospects.

Description

Technical Field

[0001] This invention relates to a high-volume real-time data fault recording system based on time slicing, belonging to the field of power system technology. Background Technology

[0002] As a core technology for power system fault detection, analysis and diagnosis, fault recording can capture various electrical quantity data in real time during normal operation, abnormal fluctuations and fault occurrence of the power system, including the instantaneous changes and dynamic evolution of key parameters such as voltage, current, power and frequency. It provides accurate, complete and irreplaceable raw data support for the rapid location of power system faults, cause analysis and responsibility identification.

[0003] When faults such as short circuits, grounding faults, overcurrent faults, and overvoltage faults occur in a power system, the fault recording system can quickly start recording waveforms, completely recording electrical quantity waveforms and related switch status information for a certain period before and after the fault. This effectively solves the problems of difficulty in capturing data at the moment of a fault and difficulty in tracing the cause of the fault. At the same time, it provides a reliable basis for verifying the correctness of power system protection device operation, optimizing system operation modes, and formulating fault prevention measures. It plays an indispensable role in improving the safety, stability, and reliability of power system operation, reducing economic losses caused by faults, and ensuring the continuous and efficient operation of the power system.

[0004] As power systems become increasingly complex, new types of faults are emerging, posing significant challenges to post-fault analysis. This is especially true for high-performance power equipment, such as flexible DC control and protection devices, which often have large system architectures, high real-time requirements, and large volumes of internal communication data, placing even higher demands on the performance of fault recording systems.

[0005] The new generation of independently controllable power equipment includes computing boards and management boards, both of which use embedded general-purpose processors (CPUs) and field-programmable gate arrays (FPGAs) as their core architecture, and employ high-speed communication interfaces to achieve internal data interaction. The CPU chip, as the main control chip, undertakes key tasks such as protection and control logic processing, real-time data calculation, and system scheduling and management; the FPGA chip, with its high parallelism and flexibility, realizes functions such as interface expansion and high-speed data transmission.

[0006] The existing fault recording system is implemented independently by a CPU chip. After triggering fault recording, the CPU on the computing board generates a recording file based on the calculated waveform data and sends it to the CPU on the management board for storage via the device's internal bus. The computing board CPU has a high workload and it is difficult to flexibly adjust the data frequency and duration of the fault recording system. The internal bus bandwidth is also relatively small, which may cause problems such as packet loss and data congestion when multiple computing boards transmit fault recording data simultaneously.

[0007] In view of this, the existing fault recording system has problems such as poor flexibility, slow operation efficiency and small data flow, which urgently need to be solved. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-flow-rate real-time data fault recording system based on time slicing, which solves the problems of poor flexibility, slow operation efficiency, and small data flow of fault recording systems, and cannot effectively meet the needs of high-performance power equipment such as flexible DC control and protection devices.

[0009] To achieve the above objectives, the present invention is implemented using the following technical solution: This invention provides a high-volume real-time data fault recording system based on time slicing, including a computing board, a management board, a differential data bus, and a synchronization bus. The computing board and the management board are each provided with at least one, and are connected to the differential data bus and the synchronization bus respectively. The computing board is used to calculate the fault waveform data from the input sampled data, and the fault waveform data is sent to the management board via the differential data bus. The management board is used to receive fault waveform data transmitted via the differential data bus, and to parse and cache the fault waveform data. The management board is also used to send time slice control signals to the computing board via a synchronization bus to control the timing of the computing board sending fault waveform data, thereby achieving time slice alignment between the computing board and the management board.

[0010] Furthermore, the computing board includes a first CPU chip and a first FPGA chip. The first CPU chip is used to calculate fault waveform data based on the input sampling data and transmit it to the first FPGA chip. The first FPGA chip is used to send the fault waveform data to the management board through the differential data bus and receive the time slice control signal of the synchronization bus, and control the transmission rhythm of the fault waveform data according to the time slice control signal.

[0011] Furthermore, the first CPU chip includes a protection control logic module and a first Ethernet controller module, and the first FPGA chip includes a first Ethernet message receiving module, a synchronization receiving module, and a data sending module. The protection control logic module is used to calculate fault waveform data from the input sampled data; The first Ethernet controller module is used to organize the fault recording data into Ethernet packets and send them to the first Ethernet packet receiving module, and then send them to the management board via the differential data bus through the data sending module; The synchronization receiving module is used to receive the time slice control signal transmitted by the synchronization bus, and to control the data sending module to send fault recording data within a given time slice according to the time slice control signal.

[0012] Furthermore, the management board includes a second CPU chip, a second FPGA chip, an SSD chip, and a DDR chip; The second FPGA chip is used to receive and parse fault waveform data, and write the parsed fault waveform data into the DDR chip; it is also used to determine whether fault waveform recording is triggered based on the parsed fault waveform data. When the parsed fault waveform data triggers fault waveform recording, the fault waveform recording start flag and fault waveform recording time stamp are extracted, the fault waveform data is read from the DDR chip based on the fault waveform recording time stamp, and the fault waveform data, fault waveform recording start flag and fault waveform recording time stamp are sent together to the second CPU chip. The second CPU chip is used to adjust the format of the fault recording data according to the fault recording start mark and fault recording time stamp before writing it into the SSD chip.

[0013] Furthermore, the second CPU chip includes a waveform data processing module and a second Ethernet controller module, and the second FPGA chip includes a second Ethernet message receiving module, a DDR read / write control module, and a message parsing module; The message parsing module is used to receive and parse the fault recording data transmitted by the differential data bus, and determine whether the parsed fault recording data triggers fault recording. If fault recording is triggered, the fault recording start flag, fault recording timestamp and parsed fault recording data are sent to the DDR read and write control module together. If fault recording is not triggered, only the parsed fault recording data is sent to the DDR read and write control module. The DDR read / write control module is used to write the parsed fault waveform data into the DDR chip, and when it receives the fault waveform start flag and the fault waveform time stamp, it reads the fault waveform data from the DDR chip according to the fault waveform time stamp, and sends the fault waveform data, the fault waveform start flag, and the fault waveform time stamp together to the waveform data processing module through the second Ethernet message receiving module and the second Ethernet controller module. The waveform data processing module is used to adjust the format of the fault waveform data according to the fault waveform start flag and the fault waveform time stamp, and write it into the SSD chip.

[0014] Furthermore, the second FPGA chip also includes a synchronization management module, which is used to send time slice control signals to the computing board via a synchronization bus.

[0015] Furthermore, the DDR read / write control module is connected to the DDR chip via the HPIO high-performance IO pin of the second FPGA chip to realize the buffered read / write of fault recording data.

[0016] Furthermore, the waveform recording data processing module is connected to the SSD chip via a SATA interface to store fault waveform recording data.

[0017] Furthermore, the fault recording start marker and fault recording time stamp are both obtained from the fault recording data.

[0018] Furthermore, the first Ethernet controller module and the first Ethernet message receiving module, the second Ethernet controller module and the second Ethernet message receiving module transmit data through the SGMII Gigabit Ethernet interface.

[0019] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: The fault recording data provided by this invention is transmitted in a time-division manner according to the time slice signal of the synchronous bus, which will not cause data transmission and reception conflicts on the differential bus, thus improving the reliability of the entire fault recording system. The large-volume recording data buffer is read and written by the FPGA chip on the management board. The CPU chip on the management board only needs to complete the recording data reception and recording file format adjustment, which greatly simplifies the processing operation of the CPU program and improves the running efficiency of the CPU program. The system of this invention features isolated internal data and control loops, simple communication connections between the computing board and management board, and the ability to dynamically adjust the number of computing and management boards according to requirements, thus improving system flexibility and scalability. The management board and computing board adopt a unified CPU+FPGA core chip architecture, and the SSD and DDR chips on the management board are compatible through optional matching, reducing hardware design and manufacturing costs. The entire system communication link, including the differential data bus, SGMII gigabit Ethernet interface, HPIO high-performance interface, and SSD interface, are all high-speed data interfaces, significantly improving the internal transmission bandwidth of fault recording data. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the architecture of a high-volume real-time data fault recording system based on time slicing in one embodiment of the present invention; Figure 2 This is a schematic diagram of time-slice division for a high-volume real-time data fault recording system based on time slices in one embodiment of the present invention. Figure 3 This is a schematic diagram of a high-volume real-time data fault recording system based on time slicing in one embodiment of the present invention. Figure 4This is a schematic diagram of the processing method of a high-volume real-time data fault recording system based on time slicing in one embodiment of the present invention. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0022] Example 1

[0023] This invention provides a high-volume real-time data fault recording system based on time slicing, comprising a computing board, a management board, a differential data bus, and a synchronization bus. At least one computing board and one management board are included, and the actual number can be dynamically adjusted and increased according to requirements. Both the computing board and the management board are connected to the differential data bus and the synchronization bus.

[0024] The arithmetic board is used to calculate the fault waveform data from the input sampled data, and the fault waveform data is sent to the management board via the differential data bus. In this embodiment, the differential data bus uses 4B5B encoding, with a line rate of 1000Mbps and a data rate of 800Mbps.

[0025] The management board is used to receive fault waveform data transmitted from the differential data bus, parse and buffer the fault waveform data, and simultaneously send time slice control signals through the synchronization bus to control the timing of fault waveform data sent by the computing board while receiving the clock signal of the fault waveform data. This ensures that the time slice signals generated by each computing board are fully aligned and avoids signal conflicts on the differential data bus.

[0026] like Figure 1 As shown, the system architecture of this embodiment includes multiple computing boards and multiple management boards (up to 8 computing boards).

[0027] The system architecture supports multiple management boards simultaneously receiving fault waveform data from different computing boards. To avoid conflicts in the synchronization bus time slice control signals, management board 1 uniformly sends the time slice control signal to the synchronization bus, and all other boards synchronize with management board 1 via the time slice control signal of the synchronization bus. Each computing board sends fault waveform data to the differential data bus in a time-division manner according to its allocated time slice, ensuring that the transmitted fault waveform data does not have signal conflicts. Each management board receives and buffers the fault waveform data for its corresponding time slice according to the configuration information.

[0028] like Figure 2 As shown, the system time slice is divided into 100µs cycles. Each cycle is further divided into 10 equal-length time slices with 10µs intervals, and the start time of each cycle is aligned with the synchronization pulse signal of the synchronization bus.

[0029] Of the 10 time slices in each cycle, 8 time slices are used to transmit waveform data recorded by the computing board, and 2 time slices are used to transmit other data within the system. The differential data bus can transmit up to 1000 bytes of data within each time slice.

[0030] Example 2

[0031] like Figure 3 As shown, based on Embodiment 1, the computing board of this embodiment includes a first CPU chip and a first FPGA chip.

[0032] The first CPU chip includes a protection control logic module and a first Ethernet controller module. The protection control logic module implements the relevant code logic for relay protection functions, performs real-time data calculation and processing on the input sampled data, and periodically generates fault waveform data for external transmission. The first Ethernet controller module is a dedicated hardware interface for the CPU chip, supporting Ethernet data transmission and reception at a maximum rate of 1000Mbps. It is used to organize the fault waveform data into Ethernet packets and send them to the first FPGA chip.

[0033] The first FPGA chip includes a first Ethernet message receiving module, a synchronization receiving module, and a data sending module. The first Ethernet message receiving module receives Ethernet messages sent by the first Ethernet controller module and parses them to obtain fault waveform data. The data sending module reassembles the fault waveform data according to the differential data bus message format and sends it to the management board via the differential data bus. The synchronization receiving module receives the time switching control signal of the synchronization bus and generates message sending pulses according to the pre-configured differential data bus time slice number to control the data sending module to transmit within a given time slice.

[0034] The management board includes a second CPU chip, a second FPGA chip, an SSD chip, and a DDR chip. The second CPU chip includes a waveform data processing module and a second Ethernet controller module. The second FPGA chip includes a second Ethernet packet receiving module, a DDR read / write control module, a synchronization management module, and a packet parsing module.

[0035] The message parsing module receives and processes the fault waveform data sent from the differential data bus, parses the fault waveform data, and transmits it to the DDR controller module. The DDR controller module periodically writes the fault waveform data into the DDR chip for buffering. In this embodiment, the DDR chip is connected to the second FPGA chip via HPIO high-performance pins. The DDR chip port data rate is greater than or equal to 1600Mbps, and the total capacity of the DDR chip is greater than 1Gbit, capable of buffering fault waveform data for more than 100 seconds. The buffered fault waveform data is written cyclically.

[0036] The message parsing module also needs to determine whether the protection control logic module has triggered fault recording. If the protection control logic module has triggered fault recording, the message parsing module sends a fault recording start flag and a fault recording timestamp to the DDR read / write control module. (The fault recording start flag and fault recording timestamp are calculated by the protection control logic module from the input sampled data and then sent along with the fault recording data.)

[0037] After receiving the fault recording start flag and fault recording timestamp, the DDR read / write control module calculates the DDR chip data readback address based on the fault recording timestamp, reads the fault recording data starting from the readback address, and sends it up via the second Ethernet message receiving module. The DDR read / write control module supports a maximum of 10 seconds of forward and 10 seconds of backward fault recording data readback and upload.

[0038] The fault waveform data sent up is received by the second Ethernet controller module, which is a dedicated hardware interface for the second CPU chip and supports Ethernet data transmission and reception at a maximum rate of 1000Mbps.

[0039] The second Ethernet controller module sends the parsed fault waveform data, fault waveform start flag, and fault waveform timestamp to the waveform data processing module. The waveform data processing module adjusts the format of the fault waveform data according to the fault waveform start flag and fault waveform timestamp and writes it to the SSD chip. The SSD chip is connected to the second CPU chip via a SATA interface to store the fault waveform file.

[0040] The synchronization management module sends a time slice control signal to the synchronization bus every 100µs to ensure that the time slices inside the computing board and the management board are aligned.

[0041] In this embodiment, the first Ethernet controller module and the first Ethernet message receiving module, the second Ethernet controller module and the second Ethernet message receiving module transmit data through the SGMII Gigabit Ethernet interface.

[0042] Combination Figure 4 The processing method of the high-volume real-time data fault recording system based on time slicing in this embodiment includes: (1) After the system starts normally, the first CPU chip completes the protection control logic processing and sends fault waveform data to the first FPGA chip through the gigabit Ethernet interface.

[0043] (2) The first FPGA chip waits for the configured data transmission time slice, and then transmits the fault recording data through the differential data bus.

[0044] (3) The second FPGA chip receives the fault recording data, parses the data, and determines whether fault recording should be started. If recording is not started, the management board normally writes the fault recording data into the DDR chip cache.

[0045] (4) If the second FPGA chip determines that the waveform recording has started based on the fault waveform recording start flag, after writing the waveform recording data into the DDR chip cache, it calculates the waveform recording data readback address in the DDR chip based on the fault waveform recording time stamp, and reads the fault waveform recording data from the readback address.

[0046] (5) The second FPGA chip packages the fault waveform readback data and sends it to the second CPU chip through the gigabit Ethernet interface.

[0047] (6) The second CPU chip verifies the fault waveform data. If the fault waveform data is incorrectly verified, the management board CPU chip sends a verification error alarm message to the management board FPGA chip, and the management board FPGA chip resends the current waveform data.

[0048] (7) The second CPU chip verifies that the fault waveform data is correct, generates a fault waveform file, and writes it to the SSD chip for storage.

[0049] The fault recording system of this invention has a simple architecture and low hardware design and manufacturing costs. The internal data communication adopts a time-division multiplexing mode based on time slicing, which ensures high data transmission reliability. All communication interfaces involved in the system are high-speed data interfaces, with large bandwidth and fast communication speed for fault recording data transmission. The fault recording data buffer is implemented by an FPGA chip, and the CPU chip processing operation is simple and efficient. The internal data loop and control loop are isolated, supporting multiple computing boards or management boards to process fault recording data simultaneously. It is flexible and scalable, and has good application prospects.

[0050] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0051] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0052] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0053] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0054] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A high-volume real-time data fault recording system based on time slicing, characterized in that, It includes a computing board, a management board, a differential data bus, and a synchronization bus. Each computing board and management board is provided with at least one, and each is connected to the differential data bus and the synchronization bus respectively. The computing board is used to calculate the fault waveform data from the input sampled data, and the fault waveform data is sent to the management board via the differential data bus. The management board is used to receive fault waveform data transmitted via the differential data bus, and to parse and cache the fault waveform data. The management board is also used to send time slice control signals to the computing board via a synchronization bus to control the timing of the computing board sending fault waveform data, thereby achieving time slice alignment between the computing board and the management board.

2. The high-volume real-time data fault recording system based on time slicing according to claim 1, characterized in that, The computing board includes a first CPU chip and a first FPGA chip. The first CPU chip is used to calculate fault waveform data based on input sampling data and transmit it to the first FPGA chip. The first FPGA chip is used to send the fault waveform data to the management board through the differential data bus and receive the time slice control signal of the synchronization bus, and control the transmission cycle of the fault waveform data according to the time slice control signal.

3. The high-volume real-time data fault recording system based on time slicing according to claim 2, characterized in that, The first CPU chip includes a protection control logic module and a first Ethernet controller module, and the first FPGA chip includes a first Ethernet message receiving module, a synchronization receiving module, and a data sending module. The protection control logic module is used to calculate fault waveform data from the input sampled data; The first Ethernet controller module is used to organize the fault recording data into Ethernet packets and send them to the first Ethernet packet receiving module, and then send them to the management board via the differential data bus through the data sending module; The synchronization receiving module is used to receive the time slice control signal transmitted by the synchronization bus, and to control the data sending module to send fault recording data within a given time slice according to the time slice control signal.

4. The high-volume real-time data fault recording system based on time slicing according to claim 1, characterized in that, The management board includes a second CPU chip, a second FPGA chip, an SSD chip, and a DDR chip; The second FPGA chip is used to receive and parse fault waveform data, and write the parsed fault waveform data into the DDR chip; it is also used to determine whether fault waveform recording is triggered based on the parsed fault waveform data. When the parsed fault waveform data triggers fault waveform recording, the fault waveform recording start flag and fault waveform recording time stamp are extracted, the fault waveform data is read from the DDR chip based on the fault waveform recording time stamp, and the fault waveform data, fault waveform recording start flag and fault waveform recording time stamp are sent together to the second CPU chip. The second CPU chip is used to adjust the format of the fault recording data according to the fault recording start mark and the fault recording time stamp before writing it into the SSD chip.

5. The high-volume real-time data fault recording system based on time slicing according to claim 4, characterized in that, The second CPU chip includes a waveform data processing module and a second Ethernet controller module, and the second FPGA chip includes a second Ethernet message receiving module, a DDR read / write control module, and a message parsing module. The message parsing module is used to receive and parse the fault recording data transmitted by the differential data bus, and determine whether the parsed fault recording data triggers fault recording. If fault recording is triggered, the fault recording start flag, fault recording timestamp and parsed fault recording data are sent to the DDR read and write control module together. If fault recording is not triggered, only the parsed fault recording data is sent to the DDR read and write control module. The DDR read / write control module is used to write the parsed fault waveform data into the DDR chip, and when it receives the fault waveform start flag and the fault waveform time stamp, it reads the fault waveform data from the DDR chip according to the fault waveform time stamp, and sends the fault waveform data, the fault waveform start flag, and the fault waveform time stamp together to the waveform data processing module through the second Ethernet message receiving module and the second Ethernet controller module. The waveform data processing module is used to adjust the format of the fault waveform data according to the fault waveform start mark and the fault waveform time stamp, and write it into the SSD chip.

6. The high-volume real-time data fault recording system based on time slicing according to claim 5, characterized in that, The second FPGA chip also includes a synchronization management module, which is used to send time slice control signals to the computing board via a synchronization bus.

7. The high-volume real-time data fault recording system based on time slicing according to claim 5, characterized in that, The DDR read / write control module is connected to the DDR chip through the HPIO high-performance IO pin of the second FPGA chip to realize the buffer read / write of fault recording data.

8. The high-volume real-time data fault recording system based on time slicing according to claim 5, characterized in that, The waveform recording data processing module is connected to the SSD chip via a SATA interface to store fault waveform recording data.

9. The high-volume real-time data fault recording system based on time slicing according to claim 5, characterized in that, The fault recording start marker and fault recording time stamp are both obtained from the fault recording data.

10. The high-volume real-time data fault recording system based on time slicing according to claim 3 or 5, characterized in that, The first Ethernet controller module and the first Ethernet message receiving module, the second Ethernet controller module and the second Ethernet message receiving module transmit data through the SGMII Gigabit Ethernet interface.

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