A method and system for testing impedance matching and signal integrity of circuit boards

Abstract

This invention discloses a method and system for testing impedance matching and signal integrity of circuit boards, relating to the field of circuit board testing and inspection technology. Instead of directly calculating the straight-line distance, this invention extracts the topological test path from the test sensor to each grid point along the actual wiring topology of the raw test signal data collected by the test sensor on the circuit board. It then generates grid test feature values ​​by inversely weighting the path length, avoiding blind interpolation across wiring areas. This improves the authenticity of the test data, the accuracy of defect location, and the accuracy of the test results. It solves the problem of amplified test errors and inaccurate defect location caused by ignoring wiring paths when using pure geometric spatial distance for grid interpolation in existing technologies. This solution can achieve automated testing of circuit board impedance and signal integrity, accurate defect location, and test report output, and is suitable for high-speed circuit board factory inspection and quality verification scenarios.

Description

Technical Field

[0001] This invention relates to the field of circuit board testing and inspection technology, and in particular to a method and system for testing circuit board impedance matching and signal integrity. Background Technology

[0002] As high-speed digital circuit boards evolve towards higher density and higher frequency, reflection problems caused by impedance discontinuities such as vias, abrupt linewidth changes, and interlayer transitions are becoming increasingly prominent during signal propagation on transmission lines. These reflections lead to signal distortion, eye diagram closure, and increased timing jitter, directly affecting the signal integrity of the circuit board and the reliability of the system. To locate impedance mismatch defects, verify signal integrity, and complete factory / quality inspection tests of the circuit board, sensors are typically deployed on the circuit board to collect signal data. Then, spatial interpolation methods are used to expand the discrete sensor data into a signal strength distribution map of the entire circuit board plane. Finally, the defect area is identified and the test pass / fail status is determined based on the distribution map.

[0003] In related technologies, spatial interpolation often directly calculates the Euclidean or Manhattan distance between the sensor and the target grid point, and uses this geometric distance as a weight for inverse distance weighted interpolation. For example, the voltage value collected by the sensor is divided by a power of the geometric distance and then summed to obtain the estimated feature value of the grid point. However, this method ignores the fact that the actual propagation of signals on the circuit board must follow the metal traces. When the geometric distance passes through non-trace areas or crosses traces of different signal layers, the calculated "distance" does not correspond to the actual signal transmission path, leading to distorted test data, defect location misalignment, and incorrect test result judgment. Therefore, how to make the generation process of grid test feature values ​​closely match the actual signal propagation path, and improve the accuracy of circuit board impedance and signal integrity testing and defect location precision, has become an urgent problem to be solved in current circuit board signal integrity optimization. Summary of the Invention

[0004] This application provides a circuit board impedance matching and signal integrity testing method and system, which solves the problems of amplified test errors and inaccurate defect location caused by ignoring the trace path when performing grid interpolation based on pure geometric spatial distance in the prior art. It realizes that the grid test characteristic value of each grid point strictly follows the actual propagation law of the signal on the trace, avoids blind interpolation across trace areas, and improves the authenticity of test data, defect location accuracy and spatial distribution accuracy.

[0005] This application provides a method for testing circuit board impedance matching and signal integrity. This method is applied to a circuit board impedance matching and signal integrity testing system, and includes:

[0006] The wiring topology and impedance discontinuity boundaries of the circuit board are obtained, and raw test signal data of the test sensors deployed on the circuit board are acquired.

[0007] The planar area of ​​the circuit board is divided into grids. The topology test path from each test sensor to each grid point is extracted according to the wiring topology. The test reflection attenuation on the topology test path is calculated in combination with the impedance discontinuity boundary.

[0008] Based on the topology test path and the test reflection attenuation, the original test signal data is tested and mapped to generate grid test feature values ​​for each grid point;

[0009] Cluster adjacent grid points whose test feature values ​​exceed the test pass threshold into test anomaly analysis regions, and summarize the grid test feature values ​​in the test anomaly analysis regions to generate region test feature vectors.

[0010] The test judgment parameters and defect location coordinates are calculated based on the regional test feature vector, and the test report and defect marking results are output.

[0011] Furthermore, obtaining the wiring topology and impedance discontinuity boundaries of the circuit board includes:

[0012] Read the layout file of the circuit board and extract the signal trace coordinate set from the layout file as the wiring topology;

[0013] Locate the via position coordinates and the linewidth abrupt change position coordinates in the signal trace coordinate set, and mark the via position coordinates and the linewidth abrupt change position coordinates as the impedance discontinuity boundary.

[0014] Furthermore, the step of extracting the topology test path from each test sensor to each grid point based on the wiring topology includes:

[0015] Each of the grid points is mapped to the nearest set of coordinates of the signal trace to obtain the projection anchor point;

[0016] Along the set of signal trace coordinates, trace the connected trajectory from the coordinates of the test sensor to the projection anchor point;

[0017] The connected trajectory is recorded as the topology test path.

[0018] Furthermore, the calculation of the test reflection attenuation on the topology test path in conjunction with the impedance discontinuity boundary includes:

[0019] Determine whether the topology test path crosses the impedance discontinuity boundary;

[0020] Extract the wire diameter ratio on both sides of the impedance discontinuity boundary, and calculate the test reflection coefficient based on the wire diameter ratio;

[0021] The test reflection attenuation is obtained by multiplying the test reflection coefficients of all impedance discontinuities on the topology test path.

[0022] Furthermore, the step of performing test mapping on the original test signal data based on the topology test path and the test reflection attenuation to generate grid test feature values ​​for each grid point includes:

[0023] Calculate the trajectory length of the topology test path;

[0024] The test mapping reference value is obtained by dividing the original test signal data using the test reflection attenuation amount.

[0025] The test feature value of the grid is obtained by performing an inverse distance calculation on the test mapping benchmark value using the trajectory length.

[0026] Furthermore, the step of clustering adjacent grid points whose test feature values ​​exceed the test pass threshold into test anomaly analysis regions includes:

[0027] Extract the numerical difference of the grid test feature values ​​of two adjacent grid points;

[0028] Merge adjacent grid points whose numerical difference exceeds the test pass threshold to generate abnormal merged connected components.

[0029] The area defined by the outer contour of the merged abnormal connected block is set as the test abnormality analysis area.

[0030] Furthermore, the step of summarizing the grid test feature values ​​within the test anomaly analysis region to generate a region test feature vector includes:

[0031] Extract all the grid test feature values ​​contained within the test anomaly analysis area;

[0032] The region test feature vector is constructed by arranging and concatenating all the grid test feature values ​​into a matrix.

[0033] Furthermore, the step of calculating the test judgment parameters and defect location coordinates based on the regional test feature vector includes:

[0034] Analyze the regional test feature vector and calculate the arithmetic mean of all grid test feature values ​​within the test anomaly analysis region;

[0035] Extract the test reflection attenuation of all grid points in the test anomaly analysis area corresponding to the constructed regional test feature vector, and calculate the total regional test attenuation;

[0036] The test judgment parameter is obtained by multiplying the mean of the test features by the sum of the test attenuation in the region.

[0037] Furthermore, the output test report and defect marking results include:

[0038] Establish a communication connection with the test host computer / test terminal;

[0039] The test judgment parameters, defect location coordinates, and boundary coordinate set of the test anomaly analysis area are converted into a standardized test data format.

[0040] Standardized test data is written into a test report file to generate a circuit board defect marking map.

[0041] This application provides a circuit board impedance matching and signal integrity testing system to implement a circuit board impedance matching and signal integrity testing method, including: a test data acquisition module, a test path analysis module, a test feature mapping module, a test anomaly clustering module, and a test evaluation output module;

[0042] The test data acquisition module is used to acquire the wiring topology and impedance discontinuity boundaries of the circuit board, and to acquire the raw test signal data of the test sensors deployed on the circuit board.

[0043] The test path analysis module is used to divide the planar area of ​​the circuit board into a grid, extract the topological test path from each test sensor to each grid point according to the wiring topology, and calculate the test reflection attenuation on the topological test path in combination with the impedance discontinuity boundary.

[0044] The test feature mapping module is used to perform test mapping on the original test signal data based on the topology test path and the test reflection attenuation, and generate grid test feature values ​​for each grid point;

[0045] The test anomaly clustering module is used to cluster adjacent grid points whose test feature values ​​exceed the test pass threshold into test anomaly analysis regions, and to summarize the grid test feature values ​​in the test anomaly analysis regions to generate a region test feature vector.

[0046] The test evaluation output module is used to calculate test judgment parameters and defect location coordinates based on the regional test feature vector, and output test reports and defect marking results.

[0047] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0048] The circuit board impedance matching and signal integrity testing method provided in this application obtains the wiring topology and impedance discontinuity boundaries of the circuit board, and collects the raw test signal data of the test sensors deployed on the circuit board; divides the planar area of ​​the circuit board into a grid, extracts the topology test path from each test sensor to each grid point according to the wiring topology, and calculates the test reflection attenuation on the topology test path in combination with the impedance discontinuity boundaries.

[0049] Based on the topology test path and test reflection attenuation, the original test signal data is tested and mapped to generate grid test feature values ​​for each grid point. Adjacent grid points with abnormal test feature values ​​are clustered into test anomaly analysis regions, and the grid test feature values ​​within these regions are aggregated to generate regional test feature vectors. Test judgment parameters and defect location coordinates are calculated based on these regional test feature vectors, and test reports and defect marking results are output. In this process, the actual circuit board wiring topology is used instead of pure geometric distance as the basis for signal test propagation, ensuring that the calculation of grid test feature values ​​is based on connected trajectories and reducing test interpolation deviations caused by crossing different traces or blank areas.

[0050] Furthermore, the test reflection coefficient calculation at impedance discontinuity boundaries is introduced on the topology test path, using the electromagnetic wave reflection law as a constraint in data deduction, so that the test reflection attenuation directly reflects the actual test loss of the signal on the transmission path. Going further, the accumulated test reflection attenuation is used as a multiplier factor directly in the calculation of test judgment parameters, making test judgment and defect location driven by the actual degree of signal damage. This eliminates the complex step of manually setting test thresholds, improving the accuracy of circuit board testing, the precision of defect location, and the reproducibility of test results. Attached Figure Description

[0051] Figure 1 A flowchart of a circuit board impedance matching and signal integrity testing method provided in this application embodiment;

[0052] Figure 2 This is a schematic diagram of a circuit board impedance matching and signal integrity testing system provided in an embodiment of this application. Detailed Implementation

[0053] This application provides a circuit board impedance matching and signal integrity testing method and system, which solves the problems of amplified test errors and inaccurate defect location caused by ignoring the trace path when performing grid interpolation based on pure geometric spatial distance in the prior art. Instead of directly calculating the straight-line distance, the method extracts the topological test path from the test sensor to each grid point by taking the original test signal data collected by the test sensor on the circuit board along the actual wiring topology. On the topological test path, impedance discontinuity boundaries are identified and the test reflection coefficient is calculated. The test reflection attenuation is obtained by accumulating and multiplying all the test reflection coefficients on the path. The test reflection attenuation is then used to compensate the original test signal data, and the grid test feature value is generated by inverse distance weighting with the path length. This ensures that the grid test feature value of each grid point strictly follows the actual propagation law of the signal on the trace, avoids blind interpolation across trace areas, and improves the authenticity of test data, defect location accuracy, and spatial distribution accuracy.

[0054] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0055] like Figure 1 As shown, this application provides a circuit board impedance matching and signal integrity testing method, which is applied to a circuit board impedance matching and signal integrity testing system, including:

[0056] S1: Obtain the wiring topology of the circuit board. and impedance discontinuity boundary set and collect data deployed on the circuit board. A voltage sensor or time domain reflectometer sensor At any moment raw signal data ,in For sensor indexing, , The time variable is in seconds; the original signal data This is a voltage value, measured in volts.

[0057] S2: In the planar area of ​​the circuit board Above, according to the preset grid spacing The unit is meters, divided into grid points According to the wiring topology Extract each sensor using the shortest path algorithm. Reach each grid point topological propagation path And in conjunction with the aforementioned impedance discontinuity boundary set Calculate each of the topology test paths Reflection attenuation ,in ;

[0058] S3: Based on the aforementioned topology test path and the reflection attenuation amount For the original signal data Perform propagation mapping to generate each grid point Mesh test eigenvalues This spatializes the discrete sensor data, forming a signal strength distribution map of the entire circuit board plane;

[0059] S4: Connect adjacent grid points whose test feature values ​​exceed the test pass threshold (i.e., feature values ​​are abnormal). Clustering into one or more test anomaly analysis regions , And summarize each of the test anomaly analysis areas. All grid test features Generate the region test feature vector for this area. This enables the digital representation of signal integrity characteristics in different areas of the circuit board.

[0060] S5: Based on the region test feature vector Calculate the test judgment parameters and defect location coordinates, and output the test report and defect marking results.

[0061] Furthermore, the wiring topology of the circuit board is obtained in S1. and impedance discontinuity boundary set Specifically, it includes:

[0062] S11: Read the layout file of the circuit board, which is in ODB++ or Gerber format; use the API of the computer-aided design software to parse the layout file, extract the set of centerline coordinates of all signal traces, and record it as the wiring topology. Each line segment is defined by the coordinates of its starting point. and endpoint coordinates Definition, unit is meter;

[0063] S12: In the signal trace coordinate set, the via position coordinate set is located by numerical comparison. and the set of coordinates of the abrupt changes in linewidth Line width mutation is defined as the absolute value of the rate of change of the width of adjacent line segments exceeding [a certain threshold]. Location; set the coordinates of the via position and the set of coordinates of the linewidth abrupt change position The union of these is denoted as the set of impedance discontinuities. .

[0064] Furthermore, in S2, according to the wiring topology... Extract each sensor Reach each grid point topological propagation path Specifically, it includes:

[0065] S21: For each grid point coordinates Calculate its connection to the wiring topology. The shortest Euclidean distance between all line segments is used, with the coordinates of the perpendicular point on the nearest line segment as the projection anchor point. If the foot of the perpendicular falls on the extension of the line segment, then the nearest endpoint of the line segment is taken as the projection anchor point.

[0066] S22: The wiring topology The model is an undirected weighted graph, where the intersections of line segments are nodes, and the lengths of the line segments are the weights of the edges; Dijkstra's algorithm is used to calculate the weights from the sensors. From the node to the projection anchor point The shortest weighted path to the given node, which consists of several line segments connected end to end. Composition, in which This represents the number of line segments that make up the path.

[0067] S23: Record the shortest weighted path as the topology test path. It stores the sequence of line segments it traverses and the length of each line segment. (Unit: meters) .

[0068] Furthermore, in S2, the aforementioned impedance discontinuity boundary set is incorporated. Calculate each of the topology test paths Reflection attenuation Specifically, it includes:

[0069] S24: Traverse the topology test path For each point on the impedance discontinuity boundary set, determine whether the coordinates of that point belong to the set of impedance discontinuities. If it belongs to the category, mark the point as a reflection point; according to the sensor... To grid point The order in which the reflection points are arranged into a sequence ,in This represents the total number of reflection points;

[0070] S25: For each reflection point ( Extract the line diameter (i.e., signal line width) on both sides of the reflection point from the layout file. and The unit is meters; calculate the reflection coefficient at this reflection point using the reflection coefficient formula in transmission line theory. for:

[0071] ;

[0072] in It is a dimensionless real number, with a range of values. ;

[0073] S26: The topology test path Substitute the reflection coefficients of all reflection points into the cascade formula for signal transmission to calculate the reflection attenuation. :

[0074] ;

[0075] in It is a dimensionless real number representing the voltage attenuation ratio of the signal after passing through all discontinuities, with a range of values. ;like ,but .

[0076] Furthermore, in S3, the test path is based on the aforementioned topology. and the reflection attenuation amount For the original signal data Perform propagation mapping to generate each grid point Mesh test eigenvalues Specifically, it includes:

[0077] S31: Calculate the topology test path Total trajectory length The unit is meters:

[0078] ;

[0079] in For path The number of line segments included. For the first The length of the line segment;

[0080] S32: Utilizing the aforementioned reflection attenuation For the raw signal data Perform attenuation compensation calculations to obtain the test mapping baseline value. :

[0081] ;

[0082] in The unit is volt. Dimensionless The unit is volt;

[0083] S33: Utilizing the total trajectory length As a distance weight, the mapping reference value Perform inverse distance weighted fusion to obtain the mesh test feature values. :

[0084] ;

[0085] in The unit is volt; used to reflect the effect of each sensor on the grid points. The signal contribution is inversely proportional to its propagation distance and is compensated for by reflection attenuation.

[0086] Furthermore, in S4, adjacent grid points whose test feature values ​​exceed the test pass threshold will be included. Clustering for test anomaly analysis regions Specifically, it includes:

[0087] S41: For any two adjacent grid points and ( ,and and (sharing a single edge on the mesh), calculate the absolute difference of their mesh test eigenvalues. ,in The unit is volt;

[0088] S42: Set a connectivity threshold The unit is volts. The value is taken as 0.1 times the variance of all grid test eigenvalues ​​of the circuit board, i.e. The variance This refers to the sample variance in statistics; if Then and Marked as connected;

[0089] S43: Using either the flood fill algorithm or the disjoint-set data structure algorithm, test outliers are merged into anomaly merged connected components, and the area defined by the outer contour of the anomaly merged connected components is set as the test anomaly analysis region. Record each area The set of boundary grid point coordinates is used for subsequent impedance compensation positioning.

[0090] Furthermore, in S4, each of the aforementioned test anomaly analysis areas is summarized. All grid test features Generate the region test feature vector for this area. Specifically, it includes:

[0091] S44: Extract the test anomaly analysis region The set of indices of all grid points contained within And extract the corresponding grid test feature values. ;

[0092] S45: [The area is...] Grid points within coordinate ascending order Sort the coordinates lexicographically in ascending order to form a one-dimensional sequence; then, sort all the feature values ​​in this sequence. By concatenating these elements sequentially, a column vector is constructed, which is the test feature vector of the aforementioned region. :

[0093] ;

[0094] in Indicates the area The total number of internal grid points, Indicates transpose; The dimension is This vector fully preserves the spatial distribution information of signal strength within the region.

[0095] Furthermore, in S5, the feature vector of the region is tested. Calculate each of the test anomaly analysis regions Required test judgment parameters Specifically, it includes:

[0096] S51: Analyze the test feature vector of the region Calculate the test anomaly analysis region The arithmetic mean of all grid test feature values ​​(test feature mean) :

[0097] ;

[0098] in The unit is volt, which represents the average signal strength in that area;

[0099] S52: Extract and construct the test feature vector of the region The corresponding test anomaly analysis area Historical test reflection attenuation of all grid points within the system Calculate the total attenuation of the test area. :

[0100] ;

[0101] in It is a dimensionless real number, representing the cumulative sum of the test reflection attenuation along all sensor-grid point paths within the region;

[0102] S53: Average the test features The sum of the test attenuation in the region Multiply by a preset scaling factor. The value is set to 0.5 to obtain the test judgment parameter. :

[0103] ;

[0104] in The unit is volt; the test judgment parameters It is used to compensate for reflections and attenuation on the transmission path, and the transmitter needs to add an extra amount of signal amplitude pre-compensation.

[0105] Simultaneously, the arithmetic mean of the coordinates of all grid points within the test anomaly analysis area is calculated to generate defect location coordinates.

[0106] Furthermore, S5 outputs test reports and defect marking results, specifically including:

[0107] S54: Establish a communication connection with the test host computer / test terminal. The communication connection adopts standard communication interface protocols such as USB, Ethernet or RS-232, and the communication rate meets the requirements for real-time transmission of test data. It is used to upload the test results to the test management system or display terminal.

[0108] S55: Convert the set of test judgment parameters, defect location coordinates and boundary coordinates of the test anomaly analysis area into a standardized test data format (such as JSON or XML format). The standardized test data format includes fields such as defect number, defect location coordinates, test judgment parameter value and test timestamp, which facilitates the interface with the test management system.

[0109] S56: Write standardized test data into a test report file. The test report includes basic information about the circuit board, test judgment parameters for each test anomaly analysis area, defect location coordinates, and defect severity level. Mark the defect location on the circuit board plan view according to the defect location coordinates to generate a circuit board defect marking map. The defect marking map distinguishes the severity of defects with different colors or symbols, and intuitively presents the signal integrity test results of the circuit board.

[0110] like Figure 2As shown in the figure, this application provides a circuit board impedance matching and signal integrity testing system for implementing the circuit board impedance matching and signal integrity testing method, including: a test data acquisition module, a test path analysis module, a test feature mapping module, a test anomaly clustering module, and a test evaluation output module;

[0111] The test data acquisition module is used to acquire the wiring topology and impedance discontinuity boundaries of the circuit board, and to acquire the raw test signal data of the test sensors deployed on the circuit board.

[0112] The test path analysis module is used to divide the planar area of ​​the circuit board into a grid, extract the topological test path from each test sensor to each grid point according to the wiring topology, and calculate the test reflection attenuation on the topological test path in combination with the impedance discontinuity boundary.

[0113] The test feature mapping module is used to perform test mapping on the original test signal data based on the topology test path and the test reflection attenuation, and generate grid test feature values ​​for each grid point;

[0114] The test anomaly clustering module is used to cluster adjacent grid points whose test feature values ​​exceed the test pass threshold into test anomaly analysis regions, and to summarize the grid test feature values ​​in the test anomaly analysis regions to generate a region test feature vector.

[0115] The test evaluation output module is used to calculate test judgment parameters and defect location coordinates based on the regional test feature vector, and output test reports and defect marking results.

[0116] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0117] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0118] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0119] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist independently, or two or more modules can be integrated into one module.

[0120] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0121] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for testing impedance matching and signal integrity of a circuit board, the method comprising: The method comprises the following steps: obtaining the wiring topology and impedance discontinuous boundary of a circuit board, collecting original test signal data of test sensors arranged on the circuit board; dividing a grid in a planar region of the circuit board, extracting a topological test path of each test sensor to each grid point according to the wiring topology, and calculating a test reflection attenuation on the topological test path in combination with the impedance discontinuous boundary; based on the topological test path and the test reflection attenuation, performing test mapping on the original test signal data to generate a grid test characteristic value of each grid point; clustering adjacent grid points with test characteristic values exceeding a test qualified threshold into a test abnormality analysis region, and generating a region test characteristic vector by summarizing the grid test characteristic values in the test abnormality analysis region; calculating a test decision parameter and a defect positioning coordinate according to the region test characteristic vector, and outputting a test report and a defect marking result.

2. The method of claim 1, wherein the step of measuring the impedance of the circuit board is performed by a network analyzer. The method of obtaining the wiring topology and impedance discontinuous boundary of a circuit board comprises: reading a layout file of the circuit board, and extracting a signal trace coordinate set from the layout file as the wiring topology; positioning via hole position coordinates and line width mutation position coordinates in the signal trace coordinate set, and marking the via hole position coordinates and the line width mutation position coordinates as the impedance discontinuous boundary.

3. The method of claim 2, wherein the step of applying a signal to the circuit board under test is performed by a signal generator. The method of extracting a topological test path of each test sensor to each grid point according to the wiring topology comprises: mapping each grid point to a projection anchor point on the signal trace coordinate set closest to the grid point; tracking a connected track of a coordinate where the test sensor is located to the projection anchor point along the signal trace coordinate set; recording the connected track as the topological test path.

4. The circuit board impedance matching and signal integrity testing method as described in claim 1, characterized in that, The method of calculating a test reflection attenuation on the topological test path in combination with the impedance discontinuous boundary comprises: judging whether the topological test path passes through the impedance discontinuous boundary; extracting a line diameter ratio on both sides of the impedance discontinuous boundary passed through, and calculating a test reflection coefficient according to the line diameter ratio; multiplying test reflection coefficients of all the impedance discontinuous boundaries on the topological test path to obtain the test reflection attenuation.

5. The circuit board impedance matching and signal integrity testing method as described in claim 1, characterized in that, The method of performing test mapping on the original test signal data to generate a grid test characteristic value of each grid point based on the topological test path and the test reflection attenuation comprises: calculating a total track length of the topological test path; performing attenuation compensation operation on the original test signal data by using the test reflection attenuation to obtain a test mapping reference value; performing inverse distance weighted fusion on the test mapping reference value by using the total track length to obtain the grid test characteristic value.

6. The circuit board impedance matching and signal integrity testing method as described in claim 1, characterized in that, The method of clustering adjacent grid points with test characteristic values exceeding a test qualified threshold into a test abnormality analysis region comprises: extracting an absolute difference of grid test characteristic values of two adjacent grid points; performing a merging operation on the two adjacent grid points with the absolute difference exceeding the test qualified threshold to generate an abnormal merged connected block; setting a range circled by an outer contour of the abnormal merged connected block as the test abnormality analysis region.

7. The circuit board impedance matching and signal integrity testing method as described in claim 1, characterized in that, The process of summarizing the grid test feature values ​​within the test anomaly analysis area to generate a region test feature vector includes: Extract all the grid test feature values ​​contained within the test anomaly analysis area; The region test feature vector is constructed by arranging and concatenating all the grid test feature values ​​into a matrix.

8. The circuit board impedance matching and signal integrity testing method as described in claim 1, characterized in that, The step of calculating the test judgment parameters and defect location coordinates based on the regional test feature vector includes: Analyze the regional test feature vector and calculate the arithmetic mean of all grid test feature values ​​within the test anomaly analysis region; Extract the test reflection attenuation of all grid points in the test anomaly analysis area corresponding to the constructed regional test feature vector, and calculate the total regional test attenuation; The test judgment parameter is obtained by multiplying the mean of the test features by the sum of the test attenuation in the region.

9. The circuit board impedance matching and signal integrity testing method as described in claim 1, characterized in that, The output test report and defect marking results include: Establish communication connections with the host computer and test terminal; The test judgment parameters, defect location coordinates, and boundary coordinate set of the test anomaly analysis area are converted into a standardized test data format. Standardized test data is written into a test report file to generate a circuit board defect marking map.

10. A system for performing a method for testing impedance matching and signal integrity of a circuit board according to any one of claims 1 to 9, wherein include: Test data acquisition module, test path analysis module, test feature mapping module, test anomaly clustering module, and test evaluation output module; The test data acquisition module is used to acquire the wiring topology and impedance discontinuity boundaries of the circuit board, and to acquire the raw test signal data of the test sensors deployed on the circuit board. The test path analysis module is used to divide the planar area of ​​the circuit board into a grid, extract the topological test path from each test sensor to each grid point according to the wiring topology, and calculate the test reflection attenuation on the topological test path in combination with the impedance discontinuity boundary. The test feature mapping module is used to perform test mapping on the original test signal data based on the topology test path and the test reflection attenuation, and generate grid test feature values ​​for each grid point; The test anomaly clustering module is used to cluster adjacent grid points whose test feature values ​​exceed the test pass threshold into test anomaly analysis regions, and to summarize the grid test feature values ​​in the test anomaly analysis regions to generate region test feature vectors. The test evaluation output module is used to calculate test judgment parameters and defect location coordinates based on the regional test feature vector, and output test reports and defect marking results.

Images