A test circuit for a chip signal function module
By designing a test circuit for the chip signal function module, the problem of inconvenience in simulating chip sensor signals in existing technologies is solved, enabling the testing of the sensitivity and detection rate of the chip signal function module, thus improving the convenience and accuracy of the test.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINA AERONAUTICAL CONTROL SYST RES INST
- Filing Date
- 2026-06-01
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies lack convenient methods to simulate debris of different sizes and properties from debris sensor signals, making it impossible to effectively test the sensitivity and detection rate of debris signal functional modules.
A test circuit for a chip signal functional module was designed, including a chip signal excitation generation circuit, a resonant circuit, a comparator circuit, a Schmitt trigger circuit, a digital logic unit, a direct digital frequency synthesis circuit, a digital-to-analog conversion circuit, a proportional circuit, and a filter circuit. These circuits form a closed-loop system to simulate and test chip sensor signals.
The sensitivity and detection rate of the chip signal function module were tested, and it was able to simulate chip signals of different sizes and properties, thus improving the convenience and accuracy of the test.
Smart Images
Figure CN122307316A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of lubricating oil system testing technology, and in particular to a test circuit for a chip signal function module. Background Technology
[0002] The size and distribution of debris in the lubricating oil of aviation power equipment can characterize the wear degree of rotating mechanical components. It can also be used to predict and diagnose early failures of rotating components based on debris growth trends, enabling proactive maintenance measures. The aviation power equipment lubricating oil debris signal module allows for real-time quantitative analysis of debris size distribution and growth trends, which is of great significance for reducing aviation power equipment failures, improving uptime, and even extending service life.
[0003] Currently, in the development of the lubricating oil debris signal function module for aviation power equipment, testing is mainly conducted by injecting debris particles into the oil circuit or manually pulling out debris particles. The preparation work is cumbersome and cannot guarantee the consistency of the signal. There is a lack of a relatively convenient way to simulate the sensor signal of debris of different sizes and properties in order to test the sensitivity, detection rate and other indicators of the debris signal function module. Summary of the Invention
[0004] In view of the defects and deficiencies in the existing technology, the present invention provides a test circuit for the chip signal function module, so as to solve the technical problem that the lack of a relatively convenient way to simulate chip sensor signals of different sizes and properties of chips makes it impossible to test the sensitivity, detection rate and other indicators of the chip signal function module.
[0005] As a first aspect of the present invention, a test circuit for a chip signal functional module is provided. The chip signal functional module includes a chip signal excitation generation circuit and a chip signal feedback processing circuit. The test circuit for the chip signal functional module includes a resonant circuit, a first comparator circuit, a first Schmitt trigger circuit, a digital logic unit, a second Schmitt trigger circuit, a second comparator circuit, a direct digital frequency synthesis circuit, a digital-to-analog converter circuit, a proportional circuit, and a filter circuit. One end of the resonant circuit is connected to the chip signal excitation generation circuit. The other end of the resonant circuit is connected to the digital logic unit sequentially through the first comparator circuit and the first Schmitt trigger circuit. The digital logic unit is also connected to the direct digital frequency synthesis circuit, the second Schmitt trigger circuit, and the digital-to-analog converter circuit. The direct digital frequency synthesis circuit is also connected to the second comparator circuit and the digital-to-analog converter circuit. The second comparator circuit is connected to the second Schmitt trigger circuit. The digital-to-analog converter circuit is also connected to one end of the filter circuit through the proportional circuit. The other end of the filter circuit is connected to the chip signal feedback processing circuit.
[0006] Furthermore, the chip signal excitation generation circuit is used to generate an excitation signal; The resonant circuit is used to generate a reference sine wave signal according to the excitation signal; The first comparator circuit is used to process the reference sine wave signal into a reference square wave signal; The first Schmitt trigger circuit is used to shape the reference square wave signal to output the shaped reference square wave signal; The digital logic unit is used to control the direct digital frequency synthesis circuit to generate a carrier signal that meets the requirements according to the shaped reference square wave signal, and output the carrier signal that meets the requirements to the digital-to-analog conversion circuit. When the digital-to-analog converter receives the carrier signal that meets the requirements, the digital logic unit is used to control the amplitude of the carrier signal in the digital-to-analog converter, so that the digital-to-analog converter outputs an amplitude-modulated wave signal to the proportional circuit. The scaling circuit is used to scale the amplitude-modulated wave signal to output the scaled amplitude-modulated wave signal to the filter circuit. The filter circuit is used to filter the scaled amplitude-modulated wave signal to output the chip signal to be tested to the chip signal feedback processing circuit, thereby realizing the testing of the chip signal functional module.
[0007] Furthermore, when the digital-to-analog conversion circuit receives the carrier signal that meets the requirements, the digital logic unit controls the digital-to-analog conversion circuit to generate a modulated signal; the digital-to-analog conversion circuit generates an amplitude-modulated wave signal based on the modulated signal and the carrier signal that meets the requirements, and outputs the amplitude-modulated wave signal to the proportional circuit.
[0008] Furthermore, the carrier signal generated by the direct digital frequency synthesis circuit is processed into a target square wave signal by the second comparator circuit; the target square wave signal is shaped by the second Schmitt trigger circuit to output the shaped target square wave signal to the digital logic unit. The digital logic unit is used to extract the frequency and phase information of the shaped target square wave signal, and simultaneously extract the frequency and phase information of the shaped reference square wave signal. Then, it compares the frequency and phase information of the shaped target square wave signal with the frequency and phase information of the shaped reference square wave signal, and uses PID control to eliminate frequency and phase errors, thereby controlling the carrier signal generated by the direct digital frequency synthesis circuit to have the same frequency as the reference sine wave signal, with the phase difference set within the range of 0 to 360°. That is, the digital logic unit controls the direct digital frequency synthesis circuit to generate the carrier signal that meets the requirements.
[0009] Furthermore, the digital logic unit is used to detect the rising edge of the shaped reference square wave signal and the rising edge of the shaped target square wave signal in real time, and uses a counter to record the time difference between the two rising edges to calculate the phase error of the two current square wave signals; then, based on the phase error of the two current square wave signals, the frequency adjustment amount is calculated through PID control to obtain the latest frequency; and based on the latest frequency, the carrier signal generated by the direct digital frequency synthesis circuit is controlled to have the same frequency as the reference sine wave signal; finally, the host computer controls the direct digital frequency synthesis circuit through the digital logic unit so that the phase of the carrier signal generated by the direct digital frequency synthesis circuit meets the requirements.
[0010] Furthermore, both the first comparator circuit and the second comparator circuit include first resistors R1 to sixteenth resistors R16, a first capacitor C2, a second capacitor C3, an operational amplifier U1, and a comparator U2, wherein... One end of the first resistor R1 and one end of the third resistor R3 are both connected to the reference sine wave signal or the carrier signal. The other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the other end of the third resistor R3. The first resistor R1, the second resistor R2, and the third resistor R3 form a resistor divider network. One end of the first capacitor C2 is connected to the other end of the first resistor R1 and the second resistor R2, respectively. The other end of the first capacitor C2 is connected to one end of the fourth resistor R4 and the sixth resistor R6, respectively. The first capacitor C2 and the fourth resistor R4 form a first high-pass filter. One end of the second capacitor C3 is connected to the other end of the third resistor R3 and the second resistor R2, respectively. The other end of the second capacitor C3 is connected to one end of the fifth resistor R5 and the seventh resistor R7, respectively. The second capacitor C3 and the fifth resistor R5 form a second high-pass filter. The other ends of the fourth resistor R4 and the fifth resistor R5 are both grounded. The other end of the sixth resistor R6 is connected to the eighth resistor R7, respectively. One end of resistor R8 is connected to the negative input terminal IN- of operational amplifier U1. The other end of resistor R8 is connected to the output terminal OUT of operational amplifier U1. The other end of resistor R7 is connected to one end of resistor R9 and the positive input terminal IN+ of operational amplifier U1. The other end of resistor R9 is grounded. The output terminal OUT of operational amplifier U1 is connected in series with resistor R11 and to the negative input terminal IN- of comparator U2. One end of resistor R10 is grounded. The other end of resistor R10 is connected to one end of resistor R12 and the positive input terminal IN+ of comparator U2. The other end of resistor R12 is connected to the output terminal OUT of comparator U2 and one end of resistor R13. The other end of resistor R13 is connected to one end of resistor R14 and one end of resistor R15. The other end of resistor R14 is connected to +12V. The other end of resistor R15 is grounded through resistor R16 and outputs the reference square wave signal or the target square wave signal after voltage division.
[0011] Furthermore, the resonant circuit is composed of an inductor and a capacitor connected in parallel to simulate the excitation coil of the chip sensor.
[0012] Furthermore, the first Schmitt trigger circuit and the second Schmitt trigger circuit are both of model number SNJ54LVC14AW; the digital logic unit is of model number XC7A200T; the direct digital frequency synthesis circuit is of model number AD9958; and the digital-to-analog conversion circuit is of model number AD5543.
[0013] Furthermore, the proportional circuit includes an operational amplifier of model OP249.
[0014] Furthermore, the filter circuit employs a cascaded fourth-order Butterworth low-pass filter and a fourth-order Butterworth high-pass filter.
[0015] The test circuit for the chip signal function module provided by this invention has the following advantages: it can simulate the chip signal to be tested generated by chip particles passing through the chip sensor, and can simulate chip signals of different sizes and properties through the matching host computer, replacing the conventional method of injecting chip particles into the oil circuit or manually pulling out chip particles, and is used for various functional performance tests of the chip signal function module in research and development, production and testing. Attached Figure Description
[0016] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.
[0017] Figure 1 This is a schematic block diagram of the test circuit for the chip signal function module provided by the present invention.
[0018] Figure 2 This is a schematic block diagram of an embodiment of the test circuit for the chip signal function module provided by the present invention.
[0019] Figure 3 The comparator circuit provided by this invention is shown in the schematic diagram.
[0020] Figure 4 The block diagram of the digital phase-locked loop (PLL) technology used in the digital logic unit provided by this invention.
[0021] Figure 5 This is a schematic diagram illustrating the interaction between the digital logic unit, the direct digital frequency synthesis circuit, and the digital-to-analog conversion circuit provided by the present invention.
[0022] Figure 6 This is a schematic diagram of the amplitude-modulated wave signal provided by the present invention.
[0023] Figure 7 This is a schematic diagram of the demodulated chip signal provided by the present invention. Detailed Implementation
[0024] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0027] This embodiment provides a test circuit for the chip signal function module, such as... Figure 1-2 As shown, the chip signal functional module includes a chip signal excitation generation circuit and a chip signal feedback processing circuit. The test circuit for the chip signal functional module includes a resonant circuit 1, a first comparator circuit 2, a first Schmitt trigger circuit 3, a digital logic unit 4, a second Schmitt trigger circuit 5, a second comparator circuit 6, a direct digital frequency synthesis circuit 7, a digital-to-analog converter circuit 8, a proportional circuit 9, and a filter circuit 10. One end of the resonant circuit 1 is connected to the chip signal excitation generation circuit, and the other end of the resonant circuit 1 is sequentially connected to the first comparator circuit 2 and the first... The Schmitt trigger circuit 3 is connected to the digital logic unit 4. The digital logic unit 4 is also connected to the direct digital frequency synthesis circuit 7, the second Schmitt trigger circuit 5, and the digital-to-analog converter circuit 8. The direct digital frequency synthesis circuit 7 is also connected to the second comparator circuit 6 and the digital-to-analog converter circuit 8. The second comparator circuit 6 is connected to the second Schmitt trigger circuit 5. The digital-to-analog converter circuit 8 is also connected to one end of the filter circuit 10 through the proportional circuit 9. The other end of the filter circuit 10 is connected to the chip signal feedback processing circuit.
[0028] Preferably, such as Figure 2 As shown, the chip signal excitation generation circuit is used to generate an excitation signal; The resonant circuit 1 is used to generate a reference sine wave signal according to the excitation signal; The first comparator circuit 2 is used to process the reference sine wave signal into a reference square wave signal of 0 to 3.3V; The first Schmitt trigger circuit 3 is used to shape the reference square wave signal to output the shaped reference square wave signal; The digital logic unit 4 is used to control the direct digital frequency synthesis circuit 7 to generate a carrier signal that meets the requirements according to the shaped reference square wave signal, and output the carrier signal that meets the requirements to the digital-to-analog conversion circuit 8; wherein, the digital logic unit 4 extracts frequency and phase information from the shaped reference square wave signal, and controls the direct digital frequency synthesis circuit 7 to generate a carrier signal with the required frequency and phase according to the frequency and phase of the shaped reference square wave signal; When the digital-to-analog converter circuit 8 receives the carrier signal that meets the requirements, the digital logic unit 4 is used to control the amplitude of the carrier signal in the digital-to-analog converter circuit 8, so that the digital-to-analog converter circuit 8 outputs an amplitude-modulated wave signal to the proportional circuit 9. The proportional circuit 9 is used to scale the amplitude-modulated wave signal to output the scaled amplitude-modulated wave signal to the filter circuit 10. The filter circuit 10 is used to filter the scaled amplitude-modulated wave signal to output the chip signal to be tested to the chip signal feedback processing circuit, thereby realizing the testing of the chip signal functional module.
[0029] It should be noted that, Figure 2 In this context, SjsEXC+ and SjsEXC- represent the excitation signal, while Sjs+ and Sjs- represent the chip signal to be measured.
[0030] Preferably, the carrier signal (which is a sine wave) generated by the direct digital frequency synthesis circuit 7 is processed into a target square wave signal by the second comparator circuit 6; the target square wave signal is shaped by the second Schmitt trigger circuit 5 to output the shaped target square wave signal to the digital logic unit 4. The digital logic unit 4 is used to extract the frequency and phase information of the shaped target square wave signal, and simultaneously extract the frequency and phase information of the shaped reference square wave signal. Then, it compares the frequency and phase information of the shaped target square wave signal with the frequency and phase information of the shaped reference square wave signal, and uses PID control to eliminate frequency and phase errors, thereby controlling the carrier signal generated by the direct digital frequency synthesis circuit 7 to have the same frequency as the reference sine wave signal, with the phase difference set within the range of 0 to 360°. That is, the digital logic unit 4 controls the direct digital frequency synthesis circuit 7 to generate the carrier signal that meets the requirements.
[0031] Preferably, such as Figure 3 As shown, both the first comparator circuit 2 and the second comparator circuit 6 include first resistors R1 to sixteenth resistors R16, first capacitor C2, second capacitor C3, operational amplifier U1, and comparator U2. One end of the first resistor R1 and one end of the third resistor R3 are both connected to the reference sine wave signal or the carrier signal. The other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the other end of the third resistor R3. The first resistor R1, the second resistor R2, and the third resistor R3 form a resistor divider network. One end of the first capacitor C2 is connected to the other end of the first resistor R1 and the second resistor R2, respectively. The other end of the first capacitor C2 is connected to one end of the fourth resistor R4 and the sixth resistor R6, respectively. The first capacitor C2 and the fourth resistor R4 form a first high-pass filter. One end of the second capacitor C3 is connected to the other end of the third resistor R3 and the second resistor R2, respectively. The other end of the second capacitor C3 is connected to one end of the fifth resistor R5 and the seventh resistor R7, respectively. The second capacitor C3 and the fifth resistor R5 form a second high-pass filter. The other ends of the fourth resistor R4 and the fifth resistor R5 are both grounded. The other end of the sixth resistor R6 is connected to the eighth resistor R7, respectively. One end of resistor R8 is connected to the negative input terminal IN- of operational amplifier U1. The other end of resistor R8 is connected to the output terminal OUT of operational amplifier U1. The other end of resistor R7 is connected to one end of resistor R9 and the positive input terminal IN+ of operational amplifier U1. The other end of resistor R9 is grounded. The output terminal OUT of operational amplifier U1 is connected in series with resistor R11 and to the negative input terminal IN- of comparator U2. One end of resistor R10 is grounded. The other end of resistor R10 is connected to one end of resistor R12 and the positive input terminal IN+ of comparator U2. The other end of resistor R12 is connected to the output terminal OUT of comparator U2 and one end of resistor R13. The other end of resistor R13 is connected to one end of resistor R14 and one end of resistor R15. The other end of resistor R14 is connected to +12V. The other end of resistor R15 is grounded through resistor R16 and outputs the reference square wave signal or the target square wave signal after voltage division.
[0032] Specifically, such as Figure 3As shown, the excitation signal is amplified by the resonant circuit to generate a reference sine wave signal of approximately 60Vpp. This reference sine wave signal is input to the first comparator circuit, attenuated to 1 / 20 by a resistor divider network, filtered by a high-pass filter, and then converted into a single-ended signal by the input differential proportional operational circuit constructed by operational amplifier U1. This signal is then compared with the threshold voltage of comparator U2 to process the 60Vpp reference sine wave signal into a reference square wave signal of 0–3.3V. This square wave signal is then shaped by the first Schmitt trigger circuit and provided to the digital logic unit for acquisition to extract frequency and phase information. Similarly, the carrier signal generated by the direct digital frequency synthesis circuit is processed by the second comparator circuit into a target square wave signal of 0–3.3V, and then shaped by the second Schmitt trigger circuit before being provided to the digital logic unit for acquisition to extract frequency and phase information.
[0033] It should be noted that, Figure 3 In this context, SIN+ and SIN- represent the reference sine wave signal or the carrier signal; SQR represents the reference square wave signal or the target square wave signal.
[0034] Specifically, the operational amplifier U1 is model OP249, and the comparator U2 is model LM193.
[0035] Specifically, such as Figure 4 As shown, digital phase-locked loop (PLL) technology is implemented in digital logic unit 4. Digital logic unit 4 is used to detect the rising edge of the shaped reference square wave signal and the rising edge of the shaped target square wave signal in real time, and uses a counter to record the time difference between the two rising edges to calculate the phase error between the two square wave signals. Then, based on the phase error between the two square wave signals, a frequency adjustment amount is calculated through PID control to obtain the latest frequency. The carrier signal generated by the direct digital frequency synthesis circuit 7 is controlled to have the same frequency as the reference sine wave signal based on the latest frequency. Finally, the host computer controls the direct digital frequency synthesis circuit 7 through digital logic unit 4 to ensure that the phase of the carrier signal generated by the direct digital frequency synthesis circuit 7 meets the requirements.
[0036] Preferably, when the digital-to-analog converter 8 receives the carrier signal that meets the requirements, the digital logic unit 4 controls the digital-to-analog converter 8 to generate a modulated signal; the digital-to-analog converter 8 generates an amplitude-modulated wave signal according to the modulated signal and the carrier signal that meets the requirements, and outputs the amplitude-modulated wave signal to the proportional circuit 9.
[0037] In embodiments of the present invention, such as Figure 5As shown, the digital logic unit obtains the frequency and phase information of the excitation signal and the carrier signal, respectively. The digital logic unit calculates the phase difference between the frequency and carrier signals to control the direct digital frequency synthesizer (DDS) to output the carrier signal. The carrier signal output by the DDS serves as the reference input to the digital-to-analog converter (DAC). Simultaneously, the digital logic unit can control the amplitude variation of the DAC output signal via the bus, thereby generating an amplitude-modulated (AM) signal. The generated AM signal is then proportionally downscaled and bandpass filtered before being input to the chip signal feedback processing circuit.
[0038] Specifically, the digital logic unit controls the direct digital frequency synthesis circuit to output a carrier signal with the same frequency as the reference sine wave signal through digital phase-locked loop technology. Its mathematical definition is: ; in, The amplitude is adjustable, ranging from 0.05V to 0.5V. The frequency is the same as that of the reference sine wave signal, approximately 107kHz. Phase, adjustable from 0 to 360°, resolution 1°; Specifically, the digital logic unit controls the digital-to-analog converter circuit to generate the modulated signal. Its mathematical definition is: ; in, The amplitude is adjustable from 2mV to 2V. The frequency is adjustable from 10Hz to 2kHz, with a resolution of 1Hz. Specifically, the carrier signal output by the direct digital frequency synthesis circuit As the reference input of the digital-to-analog conversion circuit, when the carrier signal... When the requirements are met, the digital-to-analog conversion circuit uses the carrier signal. and the modulated signal Generate amplitude-modulated wave signal And output an amplitude-modulated wave signal. like Figure 6 As shown, its mathematical definition is: .
[0039] like Figure 7 As shown, different phase settings are used to simulate the chip signal generated when iron chips and non-iron chips pass through the chip sensor. The chip signal is demodulated by the chip signal function module to obtain the waveform of the chip. The waveform of iron chips (Fe) is shown as a solid blue line, while the waveform of non-iron chips (NFe) is shown as a short red horizontal line.
[0040] In this embodiment of the invention, the amplitude is set by the host computer that is compatible with the test circuit of the invention to simulate the chip particles of different sizes, the phase is set to simulate the chip particles of different properties (iron chips, non-iron chips), the amplitude change time width is set to simulate the chip signal morphology under different lubricating oil flow rates, and the amplitude change period can also be set to simulate the frequency of chip signal occurrence within a certain period of time, so as to test the detection rate index of the chip signal function module.
[0041] The present invention provides a test circuit for a chip signal function module, which reflects the size of chip particles through voltage amplitude (the larger the amplitude, the larger the particle size) and distinguishes between ferromagnetic and non-ferromagnetic materials through phase difference, thereby realizing multi-dimensional signal simulation.
[0042] Preferably, the resonant circuit 1 is composed of an inductor and a capacitor connected in parallel to simulate the excitation coil of the chip sensor.
[0043] Preferably, the first Schmitt trigger circuit 3 and the second Schmitt trigger circuit 5 are both of model SNJ54LVC14AW; the digital logic unit 4 is of model XC7A200T; the direct digital frequency synthesis circuit 7 is of model AD9958; and the digital-to-analog conversion circuit 8 is of model AD5543.
[0044] Preferably, the proportional circuit 9 includes an operational amplifier of model OP249.
[0045] Preferably, the filter circuit 10 uses a fourth-order Butterworth low-pass filter and a fourth-order Butterworth high-pass filter cascaded together to filter the scaled amplitude-modulated wave signal, thereby achieving μV-level amplitude modulation and a high signal-to-noise ratio for the chip signal under test.
[0046] It should be noted that the chip signal excitation generation circuit refers to the "metal chip excitation generation circuit" in the invention patent application number 202011590812.8, and will not be described again here.
[0047] It should be noted that the chip signal feedback processing circuit uses the MetalSCAN online oil metal chip monitoring system from Gastops, Canada.
[0048] This invention provides a test circuit for a chip signal function module. The test object is the chip signal function module, and the function of the test circuit is to simulate the input and output of a chip sensor, i.e., input an excitation signal and output the chip signal to be tested. The input of this invention is the excitation signal of the chip signal excitation generation circuit. The resonant circuit simulates the resonance phenomenon of the chip sensor. After processing by the first comparator circuit and the first Schmitt trigger circuit, it is provided to the digital logic unit to identify the frequency and phase. The digital logic unit controls the direct digital frequency synthesis circuit to generate a carrier signal that meets the requirements, and controls the digital-to-analog conversion circuit to generate the amplitude of the carrier signal. After passing through the proportional circuit and the filter circuit, it is output to the chip signal feedback processing circuit. At the same time, the digital logic unit, the direct digital frequency synthesis circuit, the second comparator circuit, and the second Schmitt trigger circuit form a closed loop to track the accurate phase of the excitation signal.
[0049] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. A test circuit for a chip signal functional module, the chip signal functional module comprising a chip signal excitation generation circuit and a chip signal feedback processing circuit, characterized in that, The test circuit for the chip signal function module includes a resonant circuit (1), a first comparator circuit (2), a first Schmitt trigger circuit (3), a digital logic unit (4), a second Schmitt trigger circuit (5), a second comparator circuit (6), a direct digital frequency synthesis circuit (7), a digital-to-analog conversion circuit (8), a proportional circuit (9), and a filter circuit (10). One end of the resonant circuit (1) is connected to the chip signal excitation generation circuit, and the other end of the resonant circuit (1) is connected to the digital logic unit via the first comparator circuit (2) and the first Schmitt trigger circuit (3) in sequence. (4) Connection, the digital logic unit (4) is also connected to the direct digital frequency synthesis circuit (7), the second Schmitt trigger circuit (5) and the digital-to-analog conversion circuit (8) respectively. The direct digital frequency synthesis circuit (7) is also connected to the second comparator circuit (6) and the digital-to-analog conversion circuit (8) respectively. The second comparator circuit (6) is connected to the second Schmitt trigger circuit (5). The digital-to-analog conversion circuit (8) is also connected to one end of the filter circuit (10) through the proportional circuit (9). The other end of the filter circuit (10) is connected to the chip signal feedback processing circuit.
2. The test circuit for the chip signal function module according to claim 1, characterized in that, The chip signal excitation generation circuit is used to generate an excitation signal; The resonant circuit (1) is used to generate a reference sine wave signal according to the excitation signal; The first comparator circuit (2) is used to process the reference sine wave signal into a reference square wave signal; The first Schmitt trigger circuit (3) is used to shape the reference square wave signal to output the shaped reference square wave signal; The digital logic unit (4) is used to control the direct digital frequency synthesis circuit (7) to generate a carrier signal that meets the requirements according to the shaped reference square wave signal, and output the carrier signal that meets the requirements to the digital-to-analog conversion circuit (8). When the digital-to-analog converter (8) receives the carrier signal that meets the requirements, the digital logic unit (4) is used to control the amplitude of the carrier signal in the digital-to-analog converter (8), so that the digital-to-analog converter (8) outputs an amplitude-modulated wave signal to the proportional circuit (9). The scaling circuit (9) is used to scale the amplitude-modulated wave signal to output the scaled amplitude-modulated wave signal to the filter circuit (10). The filter circuit (10) is used to filter the scaled amplitude-modulated wave signal to output the chip signal to be tested to the chip signal feedback processing circuit, thereby realizing the test of the chip signal functional module.
3. The test circuit for the chip signal function module according to claim 2, characterized in that, When the digital-to-analog converter (8) receives the carrier signal that meets the requirements, the digital logic unit (4) controls the digital-to-analog converter (8) to generate a modulated signal; the digital-to-analog converter (8) generates an amplitude-modulated wave signal according to the modulated signal and the carrier signal that meets the requirements, and outputs the amplitude-modulated wave signal to the proportional circuit (9).
4. The test circuit for the chip signal function module according to claim 2, characterized in that, The carrier signal generated by the direct digital frequency synthesis circuit (7) is processed into a target square wave signal by the second comparator circuit (6); the target square wave signal is shaped by the second Schmitt trigger circuit (5) to output the shaped target square wave signal to the digital logic unit (4); The digital logic unit (4) is used to extract the frequency and phase information of the shaped target square wave signal and the frequency and phase information of the shaped reference square wave signal. Then, the frequency and phase information of the shaped target square wave signal are compared with the frequency and phase information of the shaped reference square wave signal. The frequency and phase error is eliminated by PID adjustment, so as to control the carrier signal generated by the direct digital frequency synthesis circuit (7) to have the same frequency as the reference sine wave signal and the phase difference is set within the range of 0 to 360°. That is, the digital logic unit (4) controls the direct digital frequency synthesis circuit (7) to generate the carrier signal that meets the requirements.
5. The test circuit for the chip signal function module according to claim 4, characterized in that, The digital logic unit (4) is used to detect the rising edge of the shaped reference square wave signal and the rising edge of the shaped target square wave signal in real time, and to record the time difference between the two rising edges using a counter to calculate the phase error of the two current square wave signals; then, based on the phase error of the two current square wave signals, the frequency adjustment amount is calculated by PID control to obtain the latest frequency; and based on the latest frequency, the carrier signal generated by the direct digital frequency synthesis circuit (7) is controlled to have the same frequency as the reference sine wave signal; finally, the host computer controls the direct digital frequency synthesis circuit (7) through the digital logic unit (4) so that the phase of the carrier signal generated by the direct digital frequency synthesis circuit (7) meets the requirements.
6. The test circuit for the chip signal function module according to claim 4, characterized in that, The first comparator circuit (2) and the second comparator circuit (6) both include first resistors R1 to sixteenth resistors R16, first capacitor C2, second capacitor C3, operational amplifier U1, and comparator U2, wherein, One end of the first resistor R1 and one end of the third resistor R3 are both connected to the reference sine wave signal or the carrier signal. The other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the other end of the third resistor R3. The first resistor R1, the second resistor R2, and the third resistor R3 form a resistor divider network. One end of the first capacitor C2 is connected to the other end of the first resistor R1 and the second resistor R2, respectively. The other end of the first capacitor C2 is connected to one end of the fourth resistor R4 and the sixth resistor R6, respectively. The first capacitor C2 and the fourth resistor R4 form a first high-pass filter. One end of the second capacitor C3 is connected to the other end of the third resistor R3 and the second resistor R2, respectively. The other end of the second capacitor C3 is connected to one end of the fifth resistor R5 and the seventh resistor R7, respectively. The second capacitor C3 and the fifth resistor R5 form a second high-pass filter. The other ends of the fourth resistor R4 and the fifth resistor R5 are both grounded. The other end of the sixth resistor R6 is connected to the eighth resistor R7, respectively. One end of resistor R8 is connected to the negative input terminal IN- of operational amplifier U1. The other end of resistor R8 is connected to the output terminal OUT of operational amplifier U1. The other end of resistor R7 is connected to one end of resistor R9 and the positive input terminal IN+ of operational amplifier U1. The other end of resistor R9 is grounded. The output terminal OUT of operational amplifier U1 is connected in series with resistor R11 and to the negative input terminal IN- of comparator U2. One end of resistor R10 is grounded. The other end of resistor R10 is connected to one end of resistor R12 and the positive input terminal IN+ of comparator U2. The other end of resistor R12 is connected to the output terminal OUT of comparator U2 and one end of resistor R13. The other end of resistor R13 is connected to one end of resistor R14 and one end of resistor R15. The other end of resistor R14 is connected to +12V. The other end of resistor R15 is grounded through resistor R16 and outputs the reference square wave signal or the target square wave signal after voltage division.
7. The test circuit for the chip signal function module according to claim 1, characterized in that, The resonant circuit (1) is composed of an inductor and a capacitor connected in parallel to simulate the excitation coil of the chip sensor.
8. The test circuit for the chip signal function module according to claim 1, characterized in that, The first Schmitt trigger circuit (3) and the second Schmitt trigger circuit (5) are both of model number SNJ54LVC14AW; the digital logic unit (4) is of model number XC7A200T; the direct digital frequency synthesis circuit (7) is of model number AD9958; and the digital-to-analog conversion circuit (8) is of model number AD5543.
9. The test circuit for the chip signal function module according to claim 1, characterized in that, The proportional circuit (9) includes an operational amplifier of model OP249.
10. The test circuit for the chip signal function module according to claim 1, characterized in that, The filter circuit (10) uses a fourth-order Butterworth low-pass filter cascaded with a fourth-order Butterworth high-pass filter.