A server clock topology switching system and method

Abstract

This application provides a server clock topology switching system and method, including a backplane and N motherboards. The backplane has a first controller, and each motherboard has a clock generator, a clock selector, a second controller, and a CPU. When the first controller receives a command to switch to N-channel operating mode and confirms that all motherboards are in place, the first controller sends a local strobe signal to the second controller of the i-th motherboard, causing the CPU of the i-th motherboard to use the clock signal provided by its own clock generator; and sends a common strobe signal to the second controllers of the remaining motherboards, causing the CPUs of the remaining motherboards to use the clock signal provided by the clock generator of the i-th motherboard. When the first controller receives a command to switch to single-channel operating mode, the first controller sends a local strobe signal to the second controller of each in-place motherboard, causing the CPUs of each motherboard to use the clock signal provided by the clock generator of their respective motherboard, thereby achieving flexible configuration.

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