Storage device for determining whether to reconstruct a mapping unit and method of operating the same

Abstract

This disclosure relates to a storage device and a method of operating the same for determining whether to rebuild a mapping unit. The storage device may include: a memory storing a plurality of mapping units, the plurality of mapping units being included in a mapping table indicating mapping relationships between a plurality of logical addresses and a plurality of physical addresses, each of the plurality of mapping units indicating a mapping relationship between one or more logical addresses and one or more physical addresses; and a controller configured to load a target mapping unit among the plurality of mapping units into a host memory buffer located outside the storage device, and, when performing a target operation, determine whether to rebuild the target mapping unit by comparing the tag information of the target mapping unit with the tag information of the target data corresponding to the target mapping unit in the memory.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0197845, filed with the Korean Intellectual Property Office on December 27, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a storage device for determining whether to rebuild a mapped cell in a host memory buffer and a method for operating the storage device. Background Technology

[0004] A storage device is a means for storing data in response to requests from external devices such as computers, mobile terminals (e.g., smartphones or tablets).

[0005] The storage device may include memory for storing data therein and a controller for controlling the memory. The memory may be volatile or non-volatile. The controller may receive commands from an external device (i.e., a host) and execute or control operations according to the received commands to read, erase, or write data to the memory included in the storage device.

[0006] Storage devices can store mapping tables in memory, which indicate the mapping relationships between multiple logical addresses and multiple physical addresses. The mapping table can be used to look up the physical address of data corresponding to a specific logical address during a read operation, and to record the physical address where data corresponding to a specific logical address is written during a write operation. Summary of the Invention

[0007] Embodiments of this disclosure may provide a storage device and a method of operating the storage device, the storage device being able to prevent errors that occur when a mapped cell loaded into the host memory buffer is rolled back, and to enhance the reliability of the mapped cell loaded into the host memory buffer.

[0008] The purposes of the embodiments disclosed herein are not limited to those described herein, and other purposes not mentioned will be readily apparent to those skilled in the art from the following description.

[0009] Embodiments of this disclosure may provide a storage device, including: a memory storing a plurality of mapping units, the plurality of mapping units including a mapping table indicating mapping relationships between a plurality of logical addresses and a plurality of physical addresses, each of the plurality of mapping units indicating a mapping relationship between one or more logical addresses and one or more physical addresses; and a controller configured to load a target mapping unit among the plurality of mapping units into a host memory buffer located outside the storage device, and, when performing a target operation, determine whether to reconstruct the target mapping unit by comparing tag information of the target mapping unit with tag information of target data corresponding to the target mapping unit in the memory.

[0010] Embodiments of this disclosure may provide a method for operating a storage device, including: loading a target mapping unit among a plurality of mapping units from memory to a host memory buffer located outside the storage device, the plurality of mapping units including a mapping table indicating mapping relationships between a plurality of logical addresses and a plurality of physical addresses, the memory storing the mapping table; comparing tag information of the target mapping unit with tag information of target data corresponding to the target mapping unit during target operation; and determining whether to reconstruct the target mapping unit based on the comparison result.

[0011] According to embodiments of the present disclosure, a storage device and a method of operating the storage device can be provided, the storage device being able to prevent errors that occur when a mapping unit loaded into a host memory buffer is rolled back, and to enhance the reliability of the mapping unit loaded into the host memory buffer.

[0012] The effects of the embodiments disclosed herein are not limited to those described above, and other effects not mentioned will be clearly understood by those skilled in the art based on the description of the claims. Attached Figure Description

[0013] This disclosure will be more fully understood from the detailed description and accompanying drawings provided below, which are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0014] Figure 1 This is a schematic configuration diagram of a storage device according to an embodiment of the present disclosure.

[0015] Figure 2 It is shown schematically. Figure 1 A block diagram of the memory.

[0016] Figure 3 A schematic structure of a storage device according to an embodiment of the present disclosure is shown.

[0017] Figure 4 This is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0018] Figure 5 The illustration shows the tag information of the target mapping unit and the tag information of the target data according to an embodiment of the present disclosure.

[0019] Figure 6 An example of an operation for determining tag information of target data according to an embodiment of the present disclosure is shown.

[0020] Figure 7 This illustrates another example of the operation of determining tag information for target data according to embodiments of the present disclosure.

[0021] Figure 8 This illustrates another example of the operation of determining tag information for target data according to embodiments of the present disclosure.

[0022] Figure 9 This is a flowchart illustrating the operation of determining whether the storage device should rebuild the target mapping unit according to an embodiment of the present disclosure.

[0023] Figure 10 This is a flowchart illustrating the operation of a storage device reconstructing a target mapping unit according to an embodiment of the present disclosure.

[0024] Figure 11 A method of operating a storage device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0025] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that may be implemented, and in which even if the same reference numerals and symbols are shown in different drawings, these reference numerals and symbols may be used to denote the same or similar components. Further, in the following description of examples or embodiments of the invention, a detailed description of well-known functions and components incorporated herein will be omitted where it is determined that such a detailed description might obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “including,” “constituting,” “forming,” “comprise,” and “form” as used herein are generally intended to allow for the addition of additional components unless used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0026] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of the invention. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0027] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be explained that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or joined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., with each other.

[0028] When time-relative terms such as “after,” “following,” “next,” “before,” etc., are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may also be used to describe discontinuous or non-sequential processes or operations, unless used with the terms “directly” or “immediately.”

[0029] Furthermore, when referring to any size, relative dimensions, etc., even without a specific description, the numerical values ​​or corresponding information of the component or feature (e.g., grade, range, etc.) should be taken into account, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Further, the term "can" fully encompasses all the meanings of the term "able to".

[0030] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic configuration diagram of a storage device according to an embodiment of the present disclosure.

[0032] Reference Figure 1 The storage device 100 may include a memory 110 for storing data and a controller 120 for controlling the memory 110.

[0033] The memory 110 includes multiple memory blocks and operates in response to control by the controller 120. Operations of the memory 110 may include, for example, read operations, programming operations (also referred to as "write operations"), and erase operations.

[0034] The memory 110 may include a memory cell array, which includes a plurality of memory cells (also simply referred to as "cells") for storing data.

[0035] For example, memory 110 can be implemented in various types of memory such as: DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Fourth Generation Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin-transfer torque random access memory (STT-RAM).

[0036] The memory 110 can be implemented as a three-dimensional array structure. For example, embodiments of this disclosure can be applied to charge-fetch flash memory (CTF) where the charge storage layer is configured by a dielectric layer and to flash memory where the charge storage layer is configured by a conductive floating gate.

[0037] The memory 110 can receive commands and addresses from the controller 120 and can access the region in the memory cell array selected by the address. In other words, the memory 110 can perform operations instructed by commands on the region selected by the address.

[0038] The memory 110 can perform programming, reading, or erasing operations. For example, when performing a programming operation, the memory 110 can program data into an address-selected region. When performing a reading operation, the memory 110 can read data from the address-selected region. In an erasing operation, the memory 110 can erase data stored in the address-selected region.

[0039] The controller 120 can control write operations (programming operations), read operations, erase operations, and background operations on the memory 110. For example, background operations may include at least one of garbage collection (GC) operations, wear leveling (WL) operations, read reclamation (RR) operations, and bad block management (BBM) operations.

[0040] The controller 120 can control the operation of the memory 110 based on a request from a device located outside the storage device 100 (e.g., a host). However, the controller 120 can also control the operation of the memory 110 without a request from the host.

[0041] As a non-limiting example, the host can be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device configured for a data center, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, an RFID (Radio Frequency Identification) device, and a mobile device capable of driving or driving autonomously under human control (e.g., a vehicle, robot, or drone). Optionally, the host can be a virtual reality (VR) device that provides 2D or 3D virtual reality images or an augmented reality (AR) device that provides augmented reality images. The host can be any of various electronic devices that require storage device 100 to store data.

[0042] The host may include at least one operating system (OS). The operating system typically manages and controls the host's functions and operations, and controls the interoperability between the host and storage device 100. Based on the host's mobility, operating systems can be categorized into general-purpose operating systems and mobile operating systems.

[0043] The controller 120 and the host can be separate devices, or they can be integrated into a single device. For ease of explanation, the controller 120 and the host will be described below as separate devices.

[0044] Reference Figure 1 The controller 120 may include a memory interface 122 and a control circuit 123, and may further include a host interface 121.

[0045] Host interface 121 provides an interface for communicating with a host. For example, host interface 121 provides an interface using at least one of the following interface protocols: USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI (Peripheral Component Interconnect) protocol, PCI-E (High-Speed ​​PCI) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, IDE (Integrated Drive Electronics) protocol, and proprietary protocols.

[0046] When receiving a command from the host, the control circuit 123 can receive the command through the host interface 121 and can perform operations to process the received command.

[0047] Memory interface 122 can be coupled to memory 110 to provide an interface for communicating with memory 110. That is, memory interface 122 can be configured to provide an interface between memory 110 and controller 120 in response to control of control circuitry 123.

[0048] Control circuit 123 performs general control operations of controller 120 to control the operation of memory 110. For this purpose, for example, control circuit 123 may include at least one of processor 124 and working memory 125, and may optionally include error detection and correction circuitry (ECC circuitry) 126.

[0049] The processor 124 can control the general operation of the controller 120 and can perform logical calculations. The processor 124 can communicate with the host through the host interface 121 and with the memory 110 through the memory interface 122.

[0050] Processor 124 can perform the logical operations required to execute the functions of the Flash Translation Layer (FTL). Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) through the Flash Translation Layer. The Flash Translation Layer can receive logical block addresses and translate them into physical block addresses using a mapping table.

[0051] Depending on the mapping unit, there are various address mapping methods in the flash translation layer. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0052] Processor 124 can randomize data received from the host. For example, processor 124 can randomize data received from the host by using a set randomization seed. The randomized data can be provided to memory 110 and can be programmed into the memory cell array of memory 110.

[0053] During a read operation, processor 124 can derandomize data received from memory 110. For example, processor 124 can derandomize data received from memory 110 using a derandomization seed. The derandomized data can then be output to the host.

[0054] Processor 124 can run firmware to control the operation of controller 120. That is, in order to control the general operation of controller 120 and perform logical calculations, processor 124 can run or drive firmware loaded into working memory 125 at startup. Hereinafter, the operation of storage device 100 according to embodiments of the present disclosure will be described as processor 124 implementing and running firmware that defines the corresponding operations.

[0055] As a program to be run in storage device 100 to drive storage device 100, firmware may include various functional layers. For example, firmware may include binary data in which code is defined for running the functional layers respectively.

[0056] For example, the firmware may include at least one of a flash translation layer, a host interface layer (HIL), and a flash interface layer (FIL). The flash translation layer performs the function of translating the logical address requested by the host to the storage device 100 and the physical address of the memory 110. The host interface layer (HIL) is used to analyze the command requested by the host to the storage device 100, which is a storage device, and transmit the command to the flash translation layer. The flash interface layer (FIL) transmits the command indicated by the flash translation layer to the memory 110.

[0057] This firmware can be loaded into working memory 125 from, for example, memory 110 or a separate non-volatile memory (e.g., ROM or NOR flash memory) located outside memory 110. When processor 124 performs a boot operation after power-on, it may first load all or part of the firmware into working memory 125.

[0058] Processor 124 can execute logical calculations defined in firmware loaded into working memory 125 to control the general operation of controller 120. Processor 124 can store the results of executing the logical calculations defined in firmware in working memory 125. Processor 124 can control controller 120 based on the results of executing the logical calculations defined in firmware, causing controller 120 to generate commands or signals. When a portion of the firmware defining the logical calculation to be executed is stored in memory 110 but not loaded into working memory 125, processor 124 can generate an event (e.g., an interrupt) to load the corresponding portion of the firmware from memory 110 into working memory 125.

[0059] The processor 124 can load the metadata required for the driver firmware from the memory 110. The metadata used to manage the data in the memory 110 may include, for example, management information about the user data stored in the memory 110.

[0060] Firmware can be updated during the manufacture of storage device 100 or during operation of storage device 100. Controller 120 can download new firmware from outside storage device 100 and update existing firmware using the new firmware.

[0061] To drive the controller 120, the working memory 125 can store necessary firmware, program code, commands, and data. The working memory 125 can be volatile memory, including at least one of, for example, SRAM (static RAM), DRAM (dynamic RAM), and SDRAM (synchronous DRAM). Alternatively, in addition to the working memory 125, the controller 120 can also use a separate volatile memory (e.g., SRAM, DRAM) located outside the controller 120.

[0062] The error detection and correction circuit 126 can detect and correct error bits in the target data using an error correction code. The target data may be, for example, data stored in the working memory 125 or data read from the memory 110.

[0063] The error detection and correction circuit 126 can decode data using an error correction code. The error detection and correction circuit 126 can be implemented using various code decoders. For example, a decoder that performs non-system code decoding or a decoder that performs system code decoding can be used.

[0064] For example, when each read data consists of multiple sectors, the error detection and correction circuit 126 can detect error bits in each of the read data on a sector-by-sector basis. A sector can refer to a data unit smaller than a page, which is the read unit of flash memory. The sectors that make up each read data can be matched with each other using addresses.

[0065] The error detection and correction circuit 126 can calculate the bit error rate (BER) on a sector-by-sector basis and determine whether an error is correctable. For example, when the bit error rate is higher than a reference value, the error detection and correction circuit 126 can determine that the corresponding sector is uncorrectable or has failed. On the other hand, when the bit error rate is lower than the reference value, the error detection and correction circuit 126 can determine that the corresponding sector is correctable or has passed.

[0066] Error detection and correction circuit 126 can sequentially perform error detection and correction operations on all read data. If a sector included in the read data is correctable, error detection and correction circuit 126 can omit the error detection and correction operation for the corresponding sector for the next read data. If all error detection and correction operations for read data end in this manner, error detection and correction circuit 126 can detect the last uncorrectable sector in the read data. One or more sectors may be determined to be uncorrectable. Error detection and correction circuit 126 can transmit information about the sectors determined to be uncorrectable (e.g., address information) to processor 124.

[0067] Bus 127 can be configured to provide a channel between components 121, 122, 124, 125, and 126 of controller 120. Bus 127 may include, for example, a control bus for transmitting various control signals, commands, etc., a data bus for transmitting various data, etc.

[0068] Some of the components 121, 122, 124, 125, and 126 of the controller 120 may be omitted, or some of the components 121, 122, 124, 125, and 126 of the controller 120 may be integrated into a single component. In addition to the components 121, 122, 124, 125, and 126 of the controller 120, one or more other components may be added.

[0069] In the following text, reference will be made to Figure 2 The memory 110 is described in more detail.

[0070] Figure 2 It is shown schematically. Figure 1 Block diagram of memory 110.

[0071] Reference Figure 2 According to embodiments of the present disclosure, the memory 110 may include a memory cell array 210, an address decoder 220, a read and write circuit 230, control logic 240, and a voltage generation circuit 250.

[0072] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz (where z is a natural number of 2 or greater).

[0073] Multiple word lines (WL) and bit lines (BL) can be set in multiple memory blocks BLK1 to BLKz, and multiple memory cells can be arranged.

[0074] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read and write circuitry 230 via multiple bit lines BL.

[0075] Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. For example, the multiple memory cells may be non-volatile memory cells and may be configured with non-volatile memory cells having a vertical channel structure.

[0076] The memory cell array 210 can be configured as a two-dimensional memory cell array or as a three-dimensional memory cell array.

[0077] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) storing 1 bit of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) storing 2 bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) storing 3 bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) storing 4 bits of data. In yet another example, the memory cell array 210 may include a plurality of memory cells, each of which stores 5 or more bits of data.

[0078] The number of bits of data stored in each of multiple memory cells can be dynamically determined. For example, a single-level cell storing 1 bit of data can be changed to a three-level cell storing 3 bits of data.

[0079] Reference Figure 2 The address decoder 220, read and write circuit 230, control logic 240 and voltage generation circuit 250 can operate as peripheral circuits to drive the memory cell array 210.

[0080] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0081] Address decoder 220 can be configured to operate in response to control of control logic 240.

[0082] Address decoder 220 can receive addresses through input / output buffers in memory 110. Address decoder 220 can be configured to decode block addresses in the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0083] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0084] The address decoder 220 can apply a read voltage Vread to a selected word line WL in a selected memory block during a read operation, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0085] The address decoder 220 can apply the verification voltage generated by the voltage generation circuit 250 to the selected word line WL in the selected memory block during the programming verification operation, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0086] Address decoder 220 can be configured to decode the column address in the received address. Address decoder 220 can send the decoded column address to read and write circuitry 230.

[0087] Read and programming operations on memory 110 can be performed on a page-by-page basis. The address received when requesting a read or programming operation may include at least one of a block address, a row address, and a column address.

[0088] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read and write circuits 230.

[0089] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0090] The read and write circuitry 230 may include multiple page buffers PB. The read and write circuitry 230 may operate as a read circuit in the read operation of the memory cell array 210 and as a write circuit in the write operation of the memory cell array 210.

[0091] The aforementioned read and write circuit 230 can also be referred to as a page buffer circuit or a data register circuit that includes multiple page buffers PB. The read and write circuit 230 may include a data buffer responsible for data processing functions, and may further include a cache buffer responsible for caching functions.

[0092] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. During read and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cells to sense the threshold voltage (Vth) of the memory cells, and can latch the sensed data by sensing the current changes generated according to the programming state of the corresponding memory cells through sensing nodes.

[0093] The read and write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0094] During a read operation, the read and write circuit 230 temporarily stores the read data by sensing data in the memory cell, and then outputs the data DATA to the input / output buffer of the memory 110. As an exemplary embodiment, in addition to the page buffer PB or the page register, the read and write circuit 230 may also include column select circuitry.

[0095] Control logic 240 can be connected to address decoder 220, read and write circuit 230, and voltage generation circuit 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory 110.

[0096] Control logic 240 can be configured to control the general operation of memory 110 in response to control signal CTRL. Control logic 240 can output control signals for adjusting the precharge potential level of the sensing nodes of multiple page buffers PB.

[0097] Control logic 240 can control read and write circuit 230 to perform read operations on memory cell array 210. Voltage generation circuit 250 can generate read voltage Vread and pass voltage Vpass used in the read operation in response to voltage generation circuit control signals output from control logic 240.

[0098] Each memory block of the aforementioned memory 110 can be configured with multiple pages corresponding to multiple word lines WL and multiple strings corresponding to multiple bit lines BL.

[0099] Within a memory block BLK, multiple word lines (WL) and multiple bit lines (BL) can be configured to intersect each other. For example, each of the multiple word lines (WL) can be configured along the row direction, and each of the multiple bit lines (BL) can be configured along the column direction. In another example, each of the multiple word lines (WL) can be configured along the column direction, and each of the multiple bit lines (BL) can be configured along the row direction.

[0100] A memory cell can be connected to one of multiple word lines (WL) and one of multiple bit lines (BL). A transistor can be placed in each memory cell.

[0101] For example, a transistor disposed in each memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be connected directly or via another transistor TR to the corresponding bit line BL. The source (or drain) of the transistor may be connected directly or via another transistor to the source line (which may be ground). The gate of the transistor may include a floating gate surrounded by a dielectric and a control gate from which a gate voltage is applied from the word line WL.

[0102] In each memory block, a first select line (also referred to as a source select line or drain select line) may be additionally located outside the first outermost word line of the two outermost word lines, closer to the first outermost word line of the read and write circuit 230, and a second select line (also referred to as a drain select line or source select line) may be additionally located outside the second outermost word line of the two outermost word lines.

[0103] At least one additional dummy character line can be set between the first outermost character line and the first selection line. At least one additional dummy character line can also be set between the second outermost character line and the second selection line.

[0104] Read and programming operations (e.g., write operations) of the above storage blocks can be performed on a page-by-page basis, and erase operations can be performed on a block-by-block basis.

[0105] Figure 3 A schematic structure of a storage device according to an embodiment of the present disclosure is shown.

[0106] Reference Figure 3 The storage device 100 may include a memory 110 and a controller 120.

[0107] The memory 110 can store a mapping table MAP_TBL, which indicates the mapping relationship between multiple logical addresses and multiple physical addresses.

[0108] The mapping table MAP_TBL can include multiple mapping units MAP_UNIT. Each of the multiple mapping units MAP_UNIT can indicate the mapping relationship between one or more logical addresses LA and one or more physical addresses PA.

[0109] A logical address can correspond to the starting address of a logical address region of a fixed size (e.g., page size), and a physical address can correspond to the starting address of a physical address region of a fixed size.

[0110] Mapping units can be called mapping slices, mapping chunks, etc.

[0111] Controller 120 can load the target mapping unit TGT_MAP_UNIT from among multiple mapping units MAP_UNIT into the host memory buffer HMB.

[0112] The host memory buffer (HMB) may be included in the external device 10, and the external device 10 may be a host. The external device 10 may allocate a portion of its memory region to the storage device 100, and the allocated memory region may be referred to as the host memory buffer (HMB).

[0113] Storage device 100 can store data in an allocated host memory buffer (HMB) and read data stored in the host memory buffer (HMB).

[0114] As an example, storage device 100 may store one or more of a plurality of mapping units (MAP_UNIT) in the host memory buffer (HMB). As another example, storage device 100 may store management data used for managing or controlling storage device 100. As yet another example, storage device 100 may temporarily store user data to be written to memory 110.

[0115] The host memory buffer (HMB) can be located in volatile or non-volatile memory included in the external device 10.

[0116] In embodiments of this disclosure, when the controller 120 does not have sufficient internal memory to store multiple mapping units MAP_UNIT (e.g., if the controller 120 does not include DRAM), the host memory buffer HMB can be used to perform the functions of the flash translation layer (FTL). That is, the controller 120 can load one or more of the multiple mapping units MAP_UNIT into the host memory buffer HMB and obtain information about the physical address corresponding to the logical address by using the mapping units loaded into the host memory buffer HMB.

[0117] When executing the set target operation, the controller 120 can determine whether to rebuild the target mapping unit TGT_MAP_UNIT by comparing the tag information of the target mapping unit TGT_MAP_UNIT with the tag information of the target data corresponding to the target mapping unit TGT_MAP_UNIT. When rebuilding the target mapping unit TGT_MAP_UNIT, the controller 120 can use other information stored in the memory 110 to update the target mapping unit TGT_MAP_UNIT.

[0118] In this case, the logical address corresponding to the target data can be included in the target mapping unit TGT_MAP_UNIT.

[0119] This will be discussed below. Figure 4 Detailed description is provided.

[0120] Figure 4 This is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0121] Reference Figure 4 The controller 120 of the storage device 100 can detect the operation of the target operation (S410).

[0122] For example, the target operation could be an operation to read the target mapping unit TGT_MAP_UNIT from the host memory buffer HMB, an operation to clear the target mapping unit TGT_MAP_UNIT from the host memory buffer HMB to memory 110, or an operation to scan the validity of the target mapping unit TGT_MAP_UNIT.

[0123] When the host sends a read command to the controller 120, the controller 120 can perform an operation to read the target mapping unit TGT_MAP_UNIT from the host memory buffer HMB to process the read command.

[0124] The operation of clearing the target mapping unit TGT_MAP_UNIT can represent the operation of writing the target mapping unit TGT_MAP_UNIT loaded into the host memory buffer HMB to the mapping table MAP_TBL stored in memory 110.

[0125] Additionally, the operation of scanning the validity of the target mapping unit TGT_MAP_UNIT can represent the operation of detecting errors in the target mapping unit TGT_MAP_UNIT. The scan operation can be performed periodically before the target mapping unit TGT_MAP_UNIT is cleared to memory 110 or when the host is in an idle state.

[0126] Additionally, when performing a target operation, the controller 120 can compare the tag information of the target mapping unit TGT_MAP_UNIT with the tag information of the target data (S420). The tag information can also refer to information such as age and time.

[0127] Therefore, the controller 120 can read the tag information of the target mapping unit TGT_MAP_UNIT from the host memory buffer HMB, and can read the target data and the tag information of the target data from the memory 110 using the mapping relationship indicated by the target mapping unit TGT_MAP_UNIT.

[0128] Additionally, the controller 120 may determine whether to rebuild the target mapping unit TGT_MAP_UNIT (S430) based on the comparison result performed in step S420.

[0129] Figure 5 The illustration shows the tag information of the target mapping unit and the tag information of the target data according to an embodiment of the present disclosure.

[0130] Reference Figure 5 The target mapping unit TGT_MAP_UNIT and its tag information (TAG) can be stored in the host memory buffer HMB.

[0131] Additionally, the tag information (TAG) of the target data TGT_DATA can be stored in memory 110. For example, the tag information of the target data TGT_DATA can be stored in a spare area of ​​the page storing the target data TGT_DATA. The metadata of the target data TGT_DATA can be stored in the spare area, and the tag information can also be stored together with the metadata.

[0132] The controller 120 of the storage device 100 can read the target mapping unit TGT_MAP_UNIT and the tag information of the target mapping unit TGT_MAP_UNIT from the host memory buffer HMB, and can read the target data TGT_DATA and the tag information of the target data TGT_DATA from the memory 110, so as to compare the tag information of the target mapping unit TGT_MAP_UNIT and the tag information of the target data TGT_DATA.

[0133] The tag information for the aforementioned target data TGT_DATA can be determined in several ways. This will be discussed below. Figures 6 to 8 Detailed description is provided.

[0134] Figure 6 An example of an operation for determining tag information of target data according to an embodiment of the present disclosure is shown.

[0135] Reference Figure 6 The tag information (TAG) of the target data TGT_DATA can indicate the time point at which the target data TGT_DATA was last programmed into memory 110.

[0136] If no update or migration operation is performed on the target data TGT_DATA after it has been programmed into memory 110, the tag information of the target data TGT_DATA can indicate the point in time when the target data TGT_DATA was programmed into memory 110.

[0137] On the other hand, if the target data TGT_DATA is programmed into the memory 110 and an update operation or migration operation (e.g., wear leveling operation, garbage collection operation) is subsequently performed on the target data TGT_DATA, the tag information of the target data TGT_DATA can indicate the time point at which the last update operation or migration operation was performed on the target data TGT_DATA.

[0138] exist Figure 6 If the target data TGT_DATA is programmed into memory 110 at time point A, then the tag information of the target data TGT_DATA can be determined as A.

[0139] Subsequently, if the target data TGT_DATA is updated or migrated at time point B, the tag information of the target data TGT_DATA can be determined as B.

[0140] Then, when the target data TGT_DATA is updated or migrated at time point C, the tag information of the target data TGT_DATA can be determined as C.

[0141] When determining the tag information of the target data TGT_DATA, the tag information of the mapping unit corresponding to the target data TGT_DATA can also be determined from the mapping table MAP_TBL.

[0142] Figure 7 This illustrates another example of the operation of determining tag information for target data according to embodiments of the present disclosure.

[0143] Reference Figure 7 The value of the tag information (TAG) of the target data TGT_DATA can be the difference between the reference time point REF_TP and the time point when the target data TGT_DATA was last programmed into memory 110.

[0144] The reference time point REF_TP can be any time point. For example, the reference time point REF_TP could be the time when the target data TGT_DATA is first programmed into memory 110. As another example, the reference time point REF_TP could be the time when the startup operation of storage device 100 is completed. Figure 7 In this context, the value at the reference time point is R.

[0145] Then, when the target data TGT_DATA is programmed into memory 110 at time point A, the tag information of the target data TGT_DATA can be determined as (AR).

[0146] Subsequently, if the target data TGT_DATA is updated or migrated at time point B, the tag information of the target data TGT_DATA can be determined as (BR).

[0147] If the target data TGT_DATA is updated or migrated at time point C, the tag information of the target data TGT_DATA can be determined as (CR).

[0148] Similar to Figure 6 When the tag information of the target data TGT_DATA is determined, the tag information of the mapping unit corresponding to the target data TGT_DATA can also be determined from the mapping table MAP_TBL.

[0149] Figure 8This illustrates another example of the operation of determining tag information for target data according to embodiments of the present disclosure.

[0150] Reference Figure 8 The value of the tag information (TAG) of the target data TGT_DATA can indicate the total number of times the target data TGT_DATA has been programmed, updated, or migrated.

[0151] exist Figure 8 If the target data TGT_DATA is programmed into memory 110 at time point A, the tag information of the target data TGT_DATA can be determined as 1.

[0152] Then, when the target data TGT_DATA is updated or migrated at time point B, the tag information of the target data TGT_DATA can be determined as 2.

[0153] Subsequently, if the target data TGT_DATA is updated or migrated at time point C, the tag information of the target data TGT_DATA can be determined as 3.

[0154] Similar to Figure 6 When determining the tag information of the target data TGT_DATA, the tag information of the mapping unit corresponding to the target data TGT_DATA in the mapping table MAP_TBL can also be determined.

[0155] Figure 9 This is a flowchart illustrating the operation of determining whether the storage device should rebuild the target mapping unit according to an embodiment of the present disclosure.

[0156] Reference Figure 9 The controller 120 of the storage device 100 can determine whether the tag information of the target mapping unit TGT_MAP_UNIT is inconsistent or mismatched with the tag information of the corresponding target data TGT_DATA (S910).

[0157] If the tag information of the target mapping unit TGT_MAP_UNIT is inconsistent with the tag information of the target data TGT_DATA (in S910, it is), then the controller 120 can reconstruct the target mapping unit TGT_MAP_UNIT (S920).

[0158] When the tag information of the target mapping unit TGT_MAP_UNIT does not match the tag information of the target data TGT_DATA, it can be indicated that the target mapping unit TGT_MAP_UNIT loaded into the host memory buffer HMB by the host has been rolled back to a previous version after the target mapping unit TGT_MAP_UNIT was loaded into the host memory buffer HMB.

[0159] If the target mapping unit TGT_MAP_UNIT rolls back to a previous version, the controller 120 cannot detect whether the target mapping unit has rolled back using techniques such as ECC or CRC, because the rollback is not a detectable internal error of the target mapping unit TGT_MAP_UNIT.

[0160] If the controller 120 does not detect that the target mapping unit TGT_MAP_UNIT loaded into the host memory buffer HMB has been rolled back to a previous version, the controller 120 may access the wrong physical address during a read or write operation, which could lead to a serious error.

[0161] Therefore, the controller 120 can use the tag information to detect this situation and prevent errors caused by rollback by rebuilding the target mapping unit TGT_MAP_UNIT.

[0162] If the tag information of the target mapping unit TGT_MAP_UNIT is consistent with the tag information of the target data TGT_DATA (not in S910), then the controller 120 can maintain the target mapping unit TGT_MAP_UNIT without rebuilding it (S930).

[0163] Figure 10 This is a flowchart illustrating the operation of a storage device reconstructing a target mapping unit according to an embodiment of the present disclosure.

[0164] Reference Figure 10 The controller 120 of the storage device 100 can search for the log corresponding to the target mapping unit TGT_MAP_UNIT among multiple logs (S1010).

[0165] The memory 110 of storage device 100 can store multiple logs that indicate the change history of the mapping table MAP_TBL. For example, each log may include information about a specific logical address and the new mapped physical address of that specific logical address.

[0166] Additionally, the controller 120 can determine whether a log corresponding to the target mapping unit TGT_MAP_UNIT exists among multiple logs (S1020). The logical address included in the log corresponding to the target mapping unit TGT_MAP_UNIT is also included in the target mapping unit TGT_MAP_UNIT.

[0167] If a log corresponding to the target mapping unit TGT_MAP_UNIT exists (in S1020), the controller 120 can reconstruct the target mapping unit TGT_MAP_UNIT based on the log corresponding to the target mapping unit TGT_MAP_UNIT (S1030). In this case, the controller 120 can perform an operation that reflects the mapping relationship between the physical address and the logical address included in the log corresponding to the target mapping unit TGT_MAP_UNIT to the target mapping unit TGT_MAP_UNIT (i.e., a replay operation).

[0168] If no log exists corresponding to the target mapping unit TGT_MAP_UNIT (no in S1020), the controller 120 can reconstruct the target unit TGT_MAP_UNIT based on the original mapping unit for the target mapping unit TGT_MAP_UNIT among the multiple mapping units MAP_UNIT included in the mapping table MAP_TBL (S1040). In this case, the controller 120 can replace the target mapping unit TGT_MAP_UNIT with the original mapping unit.

[0169] Figure 11 A method of operating a storage device according to an embodiment of the present disclosure is shown.

[0170] Reference Figure 11 The operation method of the storage device 100 may include the step (S1110): loading the target mapping unit TGT_MAP_UNIT among the multiple mapping units MAP_UNIT included in the mapping table MAP_TBL in the memory 110 into the host memory buffer HMB located outside the storage device 100.

[0171] Additionally, the operation method of the storage device 100 may include the step (S1120): when a set target operation is performed, the tag information of the target mapping unit TGT_MAP_UNIT is compared with the tag information of the target data TGT_DATA corresponding to the target mapping unit TGT_MAP_UNIT.

[0172] For example, the target operation could be an operation to read the target mapping unit TGT_MAP_UNIT from the host memory buffer HMB, an operation to clear the target mapping unit TGT_MAP_UNIT from the host memory buffer HMB to memory 110, or an operation to scan the validity of the target mapping unit TGT_MAP_UNIT.

[0173] For example, the tag information could indicate the time point at which the target data TGT_DATA was last programmed into memory 110. In this case, the value of the tag information could be the difference between the reference time point and the time point at which the target data TGT_DATA was last programmed into memory 110.

[0174] In another example, the tag information can indicate the total number of times the target data TGT_DATA has been programmed, updated, or migrated.

[0175] In addition, the operation method of the storage device 100 may also include the step (S1130): determining whether to rebuild the target mapping unit TGT_MAP_UNIT based on the comparison result of step S1120.

[0176] In addition, the operation method of the storage device 100 may further include the following steps: if the tag information of the target mapping unit TGT_MAP_UNIT does not match the tag information of the target data TGT_DATA, then the target mapping unit TGT_MAP_UNIT is reconstructed.

[0177] As an example, the steps of rebuilding the target mapping unit TGT_MAP_UNIT may include the following steps: rebuilding the target mapping unit TGT_MAP_UNIT based on the log corresponding to the target mapping unit TGT_MAP_UNIT among multiple logs indicating the change history of the mapping table MAP_TBL.

[0178] As another example, the step of rebuilding the target mapping unit TGT_MAP_UNIT may include the following steps: if there is no log corresponding to the target mapping unit TGT_MAP_UNIT, then rebuild the target mapping unit TGT_MAP_UNIT based on the original mapping unit for the target mapping unit TGT_MAP_UNIT among the multiple mapping units MAP_UNIT included in the mapping table MAP_TBL.

[0179] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions may be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered descriptive only and not limiting of the scope of the technology. The technical scope of this disclosure is not limited to the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted in conjunction with the appended claims and cover all equivalent solutions falling within the scope of the appended claims.

Claims

1. A storage device, comprising: A memory that stores a plurality of mapping units, the plurality of mapping units being included in a mapping table indicating a mapping relationship between a plurality of logical addresses and a plurality of physical addresses, each of the plurality of mapping units indicating a mapping relationship between one or more logical addresses and one or more physical addresses; as well as The controller loads the target mapping unit among the plurality of mapping units into a host memory buffer located outside the storage device, and when a target operation is performed, determines whether to rebuild the target mapping unit by comparing the tag information of the target mapping unit with the tag information of the target data corresponding to the target mapping unit in the memory.

2. The memory device of claim 1, wherein, The target operation includes reading the target mapping unit from the host memory buffer, clearing the target mapping unit from the host memory buffer to the memory, or scanning the validity of the target mapping unit.

3. The memory device of claim 1, wherein, The tag information of the target data indicates the time point at which the target data was last programmed into the memory.

4. The memory device of claim 3, wherein, The value of the tag information of the target data is the difference between the reference time point and the time point when the target data was last programmed into the memory.

5. The memory device of claim 1, wherein, The tag information of the target data indicates the total number of times the target data has been programmed, updated, or migrated.

6. The memory device of claim 1, wherein, If the label information of the target mapping unit does not match the label information of the target data, the controller reconstructs the target mapping unit.

7. The memory device of claim 6, wherein, The memory stores multiple logs indicating the change history of the mapping table. The controller reconstructs the target mapping unit based on the logs corresponding to the target mapping unit among the plurality of logs.

8. The memory device of claim 6, wherein, When no log corresponding to the target mapping unit exists, the controller reconstructs the target mapping unit based on the original mapping unit for the target mapping unit among the multiple mapping units included in the mapping table.

9. A method of operating a storage device, comprising: The target mapping unit among a plurality of mapping units is loaded from memory into a host memory buffer located outside the storage device, the plurality of mapping units being included in a mapping table indicating the mapping relationship between a plurality of logical addresses and a plurality of physical addresses, the memory storing the mapping table; When performing a target operation, the label information of the target mapping unit is compared with the label information of the target data corresponding to the target mapping unit; as well as The determination of whether to reconstruct the target mapping unit is based on the comparison results.

10. The operating method according to claim 9, wherein, The target operation includes reading the target mapping unit from the host memory buffer, clearing the target mapping unit from the host memory buffer to the memory, or scanning the validity of the target mapping unit.

11. The operating method according to claim 9, wherein, The tag information of the target data indicates the time point at which the target data was last programmed into the memory.

12. The operating method according to claim 11, wherein, The value of the tag information of the target data is the difference between the reference time point and the time point when the target data was last programmed into the memory.

13. The operating method according to claim 9, wherein, The tag information of the target data indicates the total number of times the target data has been programmed, updated, or migrated.

14. The operating method according to claim 9, further comprising: If the label information of the target mapping unit does not match the label information of the target data, then the target mapping unit is reconstructed.

15. The operating method according to claim 14, wherein, Reconstructing the target mapping unit includes: reconstructing the target mapping unit based on a log corresponding to the target mapping unit among multiple logs indicating the change history of the mapping table.

16. The operating method according to claim 14, wherein, Reconstructing the target mapping unit includes: if there is no log corresponding to the target mapping unit, then reconstructing the target mapping unit based on the original mapping unit for the target mapping unit among the multiple mapping units included in the mapping table.

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